2 * This file implements the DMA operations for NVLink devices. The NPU
3 * devices all point to the same iommu table as the parent PCI device.
5 * Copyright Alistair Popple, IBM Corporation 2015.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of version 2 of the GNU General Public
9 * License as published by the Free Software Foundation.
12 #include <linux/slab.h>
13 #include <linux/mmu_notifier.h>
14 #include <linux/mmu_context.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/memblock.h>
19 #include <linux/iommu.h>
22 #include <asm/powernv.h>
26 #include <asm/iommu.h>
27 #include <asm/pnv-pci.h>
28 #include <asm/msi_bitmap.h>
34 #define npu_to_phb(x) container_of(x, struct pnv_phb, npu)
37 * Other types of TCE cache invalidation are not functional in the
40 static struct pci_dev *get_pci_dev(struct device_node *dn)
42 struct pci_dn *pdn = PCI_DN(dn);
44 return pci_get_domain_bus_and_slot(pci_domain_nr(pdn->phb->bus),
45 pdn->busno, pdn->devfn);
48 /* Given a NPU device get the associated PCI device. */
49 struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev)
51 struct device_node *dn;
52 struct pci_dev *gpdev;
57 if (WARN_ON(!npdev->dev.of_node))
60 /* Get assoicated PCI device */
61 dn = of_parse_phandle(npdev->dev.of_node, "ibm,gpu", 0);
65 gpdev = get_pci_dev(dn);
70 EXPORT_SYMBOL(pnv_pci_get_gpu_dev);
72 /* Given the real PCI device get a linked NPU device. */
73 struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index)
75 struct device_node *dn;
76 struct pci_dev *npdev;
81 /* Not all PCI devices have device-tree nodes */
82 if (!gpdev->dev.of_node)
85 /* Get assoicated PCI device */
86 dn = of_parse_phandle(gpdev->dev.of_node, "ibm,npu", index);
90 npdev = get_pci_dev(dn);
95 EXPORT_SYMBOL(pnv_pci_get_npu_dev);
97 #define NPU_DMA_OP_UNSUPPORTED() \
98 dev_err_once(dev, "%s operation unsupported for NVLink devices\n", \
101 static void *dma_npu_alloc(struct device *dev, size_t size,
102 dma_addr_t *dma_handle, gfp_t flag,
105 NPU_DMA_OP_UNSUPPORTED();
109 static void dma_npu_free(struct device *dev, size_t size,
110 void *vaddr, dma_addr_t dma_handle,
113 NPU_DMA_OP_UNSUPPORTED();
116 static dma_addr_t dma_npu_map_page(struct device *dev, struct page *page,
117 unsigned long offset, size_t size,
118 enum dma_data_direction direction,
121 NPU_DMA_OP_UNSUPPORTED();
125 static int dma_npu_map_sg(struct device *dev, struct scatterlist *sglist,
126 int nelems, enum dma_data_direction direction,
129 NPU_DMA_OP_UNSUPPORTED();
133 static int dma_npu_dma_supported(struct device *dev, u64 mask)
135 NPU_DMA_OP_UNSUPPORTED();
139 static u64 dma_npu_get_required_mask(struct device *dev)
141 NPU_DMA_OP_UNSUPPORTED();
145 static const struct dma_map_ops dma_npu_ops = {
146 .map_page = dma_npu_map_page,
147 .map_sg = dma_npu_map_sg,
148 .alloc = dma_npu_alloc,
149 .free = dma_npu_free,
150 .dma_supported = dma_npu_dma_supported,
151 .get_required_mask = dma_npu_get_required_mask,
155 * Returns the PE assoicated with the PCI device of the given
156 * NPU. Returns the linked pci device if pci_dev != NULL.
158 static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
159 struct pci_dev **gpdev)
162 struct pci_controller *hose;
163 struct pci_dev *pdev;
164 struct pnv_ioda_pe *pe;
167 pdev = pnv_pci_get_gpu_dev(npe->pdev);
171 pdn = pci_get_pdn(pdev);
172 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
175 hose = pci_bus_to_host(pdev->bus);
176 phb = hose->private_data;
177 pe = &phb->ioda.pe_array[pdn->pe_number];
185 long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
186 struct iommu_table *tbl)
188 struct pnv_phb *phb = npe->phb;
190 const unsigned long size = tbl->it_indirect_levels ?
191 tbl->it_level_size : tbl->it_size;
192 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
193 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
195 pe_info(npe, "Setting up window %llx..%llx pg=%lx\n",
196 start_addr, start_addr + win_size - 1,
197 IOMMU_PAGE_SIZE(tbl));
199 rc = opal_pci_map_pe_dma_window(phb->opal_id,
202 tbl->it_indirect_levels + 1,
205 IOMMU_PAGE_SIZE(tbl));
207 pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
210 pnv_pci_ioda2_tce_invalidate_entire(phb, false);
212 /* Add the table to the list so its TCE cache will get invalidated */
213 pnv_pci_link_table_and_group(phb->hose->node, num,
214 tbl, &npe->table_group);
219 long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
221 struct pnv_phb *phb = npe->phb;
224 pe_info(npe, "Removing DMA window\n");
226 rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
228 0/* levels */, 0/* table address */,
229 0/* table size */, 0/* page size */);
231 pe_err(npe, "Unmapping failed, ret = %lld\n", rc);
234 pnv_pci_ioda2_tce_invalidate_entire(phb, false);
236 pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
243 * Enables 32 bit DMA on NPU.
245 static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
247 struct pci_dev *gpdev;
248 struct pnv_ioda_pe *gpe;
252 * Find the assoicated PCI devices and get the dma window
253 * information from there.
255 if (!npe->pdev || !(npe->flags & PNV_IODA_PE_DEV))
258 gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
262 rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
265 * We don't initialise npu_pe->tce32_table as we always use
266 * dma_npu_ops which are nops.
268 set_dma_ops(&npe->pdev->dev, &dma_npu_ops);
272 * Enables bypass mode on the NPU. The NPU only supports one
273 * window per link, so bypass needs to be explicitly enabled or
274 * disabled. Unlike for a PHB3 bypass and non-bypass modes can't be
275 * active at the same time.
277 static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
279 struct pnv_phb *phb = npe->phb;
281 phys_addr_t top = memblock_end_of_DRAM();
283 if (phb->type != PNV_PHB_NPU_NVLINK || !npe->pdev)
286 rc = pnv_npu_unset_window(npe, 0);
287 if (rc != OPAL_SUCCESS)
290 /* Enable the bypass window */
292 top = roundup_pow_of_two(top);
293 dev_info(&npe->pdev->dev, "Enabling bypass for PE %x\n",
295 rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
296 npe->pe_number, npe->pe_number,
297 0 /* bypass base */, top);
299 if (rc == OPAL_SUCCESS)
300 pnv_pci_ioda2_tce_invalidate_entire(phb, false);
305 void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
310 struct pnv_ioda_pe *npe;
311 struct pci_dev *npdev;
314 npdev = pnv_pci_get_npu_dev(gpdev, i);
319 pdn = pci_get_pdn(npdev);
320 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
323 phb = pci_bus_to_host(npdev->bus)->private_data;
325 /* We only do bypass if it's enabled on the linked device */
326 npe = &phb->ioda.pe_array[pdn->pe_number];
329 dev_info(&npdev->dev,
330 "Using 64-bit DMA iommu bypass\n");
331 pnv_npu_dma_set_bypass(npe);
333 dev_info(&npdev->dev, "Using 32-bit DMA via iommu\n");
334 pnv_npu_dma_set_32(npe);
339 /* Switch ownership from platform code to external user (e.g. VFIO) */
340 void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
342 struct pnv_phb *phb = npe->phb;
346 * Note: NPU has just a single TVE in the hardware which means that
347 * while used by the kernel, it can have either 32bit window or
348 * DMA bypass but never both. So we deconfigure 32bit window only
349 * if it was enabled at the moment of ownership change.
351 if (npe->table_group.tables[0]) {
352 pnv_npu_unset_window(npe, 0);
357 rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
358 npe->pe_number, npe->pe_number,
359 0 /* bypass base */, 0);
361 pe_err(npe, "Failed to disable bypass, err %lld\n", rc);
364 pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
367 struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
369 struct pnv_phb *phb = npe->phb;
370 struct pci_bus *pbus = phb->hose->bus;
371 struct pci_dev *npdev, *gpdev = NULL, *gptmp;
372 struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
377 list_for_each_entry(npdev, &pbus->devices, bus_list) {
378 gptmp = pnv_pci_get_gpu_dev(npdev);
383 pe_info(gpe, "Attached NPU %s\n", dev_name(&npdev->dev));
384 iommu_group_add_device(gpe->table_group.group, &npdev->dev);
390 /* Maximum number of nvlinks per npu */
391 #define NV_MAX_LINKS 6
393 /* Maximum index of npu2 hosts in the system. Always < NV_MAX_NPUS */
394 static int max_npu2_index;
397 struct mm_struct *mm;
398 struct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];
399 struct mmu_notifier mn;
403 /* Callback to stop translation requests on a given GPU */
404 struct npu_context *(*release_cb)(struct npu_context *, void *);
407 * Private pointer passed to the above callback for usage by
413 struct mmio_atsd_reg {
419 * Find a free MMIO ATSD register and mark it in use. Return -ENOSPC
420 * if none are available.
422 static int get_mmio_atsd_reg(struct npu *npu)
426 for (i = 0; i < npu->mmio_atsd_count; i++) {
427 if (!test_and_set_bit_lock(i, &npu->mmio_atsd_usage))
434 static void put_mmio_atsd_reg(struct npu *npu, int reg)
436 clear_bit_unlock(reg, &npu->mmio_atsd_usage);
439 /* MMIO ATSD register offsets */
440 #define XTS_ATSD_AVA 1
441 #define XTS_ATSD_STAT 2
443 static void mmio_launch_invalidate(struct mmio_atsd_reg *mmio_atsd_reg,
444 unsigned long launch, unsigned long va)
446 struct npu *npu = mmio_atsd_reg->npu;
447 int reg = mmio_atsd_reg->reg;
449 __raw_writeq(cpu_to_be64(va),
450 npu->mmio_atsd_regs[reg] + XTS_ATSD_AVA);
452 __raw_writeq(cpu_to_be64(launch), npu->mmio_atsd_regs[reg]);
455 static void mmio_invalidate_pid(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
456 unsigned long pid, bool flush)
459 unsigned long launch;
461 for (i = 0; i <= max_npu2_index; i++) {
462 if (mmio_atsd_reg[i].reg < 0)
465 /* IS set to invalidate matching PID */
466 launch = PPC_BIT(12);
468 /* PRS set to process-scoped */
469 launch |= PPC_BIT(13);
473 mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
476 launch |= pid << PPC_BITLSHIFT(38);
479 launch |= !flush << PPC_BITLSHIFT(39);
481 /* Invalidating the entire process doesn't use a va */
482 mmio_launch_invalidate(&mmio_atsd_reg[i], launch, 0);
486 static void mmio_invalidate_va(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
487 unsigned long va, unsigned long pid, bool flush)
490 unsigned long launch;
492 for (i = 0; i <= max_npu2_index; i++) {
493 if (mmio_atsd_reg[i].reg < 0)
496 /* IS set to invalidate target VA */
499 /* PRS set to process scoped */
500 launch |= PPC_BIT(13);
504 mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
507 launch |= pid << PPC_BITLSHIFT(38);
510 launch |= !flush << PPC_BITLSHIFT(39);
512 mmio_launch_invalidate(&mmio_atsd_reg[i], launch, va);
516 #define mn_to_npu_context(x) container_of(x, struct npu_context, mn)
518 static void mmio_invalidate_wait(
519 struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
524 /* Wait for all invalidations to complete */
525 for (i = 0; i <= max_npu2_index; i++) {
526 if (mmio_atsd_reg[i].reg < 0)
529 /* Wait for completion */
530 npu = mmio_atsd_reg[i].npu;
531 reg = mmio_atsd_reg[i].reg;
532 while (__raw_readq(npu->mmio_atsd_regs[reg] + XTS_ATSD_STAT))
538 * Acquires all the address translation shootdown (ATSD) registers required to
539 * launch an ATSD on all links this npu_context is active on.
541 static void acquire_atsd_reg(struct npu_context *npu_context,
542 struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
546 struct pci_dev *npdev;
547 struct pnv_phb *nphb;
549 for (i = 0; i <= max_npu2_index; i++) {
550 mmio_atsd_reg[i].reg = -1;
551 for (j = 0; j < NV_MAX_LINKS; j++) {
553 * There are no ordering requirements with respect to
554 * the setup of struct npu_context, but to ensure
555 * consistent behaviour we need to ensure npdev[][] is
558 npdev = READ_ONCE(npu_context->npdev[i][j]);
562 nphb = pci_bus_to_host(npdev->bus)->private_data;
564 mmio_atsd_reg[i].npu = npu;
565 mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
566 while (mmio_atsd_reg[i].reg < 0) {
567 mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
576 * Release previously acquired ATSD registers. To avoid deadlocks the registers
577 * must be released in the same order they were acquired above in
580 static void release_atsd_reg(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
584 for (i = 0; i <= max_npu2_index; i++) {
586 * We can't rely on npu_context->npdev[][] being the same here
587 * as when acquire_atsd_reg() was called, hence we use the
588 * values stored in mmio_atsd_reg during the acquire phase
589 * rather than re-reading npdev[][].
591 if (mmio_atsd_reg[i].reg < 0)
594 put_mmio_atsd_reg(mmio_atsd_reg[i].npu, mmio_atsd_reg[i].reg);
599 * Invalidate either a single address or an entire PID depending on
602 static void mmio_invalidate(struct npu_context *npu_context, int va,
603 unsigned long address, bool flush)
605 struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
606 unsigned long pid = npu_context->mm->context.id;
608 if (npu_context->nmmu_flush)
610 * Unfortunately the nest mmu does not support flushing specific
611 * addresses so we have to flush the whole mm once before
612 * shooting down the GPU translation.
614 flush_all_mm(npu_context->mm);
617 * Loop over all the NPUs this process is active on and launch
620 acquire_atsd_reg(npu_context, mmio_atsd_reg);
622 mmio_invalidate_va(mmio_atsd_reg, address, pid, flush);
624 mmio_invalidate_pid(mmio_atsd_reg, pid, flush);
626 mmio_invalidate_wait(mmio_atsd_reg);
629 * The GPU requires two flush ATSDs to ensure all entries have
630 * been flushed. We use PID 0 as it will never be used for a
631 * process on the GPU.
633 mmio_invalidate_pid(mmio_atsd_reg, 0, true);
634 mmio_invalidate_wait(mmio_atsd_reg);
635 mmio_invalidate_pid(mmio_atsd_reg, 0, true);
636 mmio_invalidate_wait(mmio_atsd_reg);
638 release_atsd_reg(mmio_atsd_reg);
641 static void pnv_npu2_mn_release(struct mmu_notifier *mn,
642 struct mm_struct *mm)
644 struct npu_context *npu_context = mn_to_npu_context(mn);
646 /* Call into device driver to stop requests to the NMMU */
647 if (npu_context->release_cb)
648 npu_context->release_cb(npu_context, npu_context->priv);
651 * There should be no more translation requests for this PID, but we
652 * need to ensure any entries for it are removed from the TLB.
654 mmio_invalidate(npu_context, 0, 0, true);
657 static void pnv_npu2_mn_change_pte(struct mmu_notifier *mn,
658 struct mm_struct *mm,
659 unsigned long address,
662 struct npu_context *npu_context = mn_to_npu_context(mn);
664 mmio_invalidate(npu_context, 1, address, true);
667 static void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,
668 struct mm_struct *mm,
669 unsigned long start, unsigned long end)
671 struct npu_context *npu_context = mn_to_npu_context(mn);
672 unsigned long address;
674 for (address = start; address < end; address += PAGE_SIZE)
675 mmio_invalidate(npu_context, 1, address, false);
677 /* Do the flush only on the final addess == end */
678 mmio_invalidate(npu_context, 1, address, true);
681 static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
682 .release = pnv_npu2_mn_release,
683 .change_pte = pnv_npu2_mn_change_pte,
684 .invalidate_range = pnv_npu2_mn_invalidate_range,
688 * Call into OPAL to setup the nmmu context for the current task in
689 * the NPU. This must be called to setup the context tables before the
690 * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
692 * A release callback should be registered to allow a device driver to
693 * be notified that it should not launch any new translation requests
694 * as the final TLB invalidate is about to occur.
696 * Returns an error if there no contexts are currently available or a
697 * npu_context which should be passed to pnv_npu2_handle_fault().
699 * mmap_sem must be held in write mode.
701 struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
703 struct npu_context *(*cb)(struct npu_context *, void *),
708 struct device_node *nvlink_dn;
709 struct mm_struct *mm = current->mm;
710 struct pnv_phb *nphb;
712 struct npu_context *npu_context;
715 * At present we don't support GPUs connected to multiple NPUs and I'm
716 * not sure the hardware does either.
718 struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
720 if (!firmware_has_feature(FW_FEATURE_OPAL))
721 return ERR_PTR(-ENODEV);
724 /* No nvlink associated with this GPU device */
725 return ERR_PTR(-ENODEV);
727 nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
728 if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
730 return ERR_PTR(-ENODEV);
732 if (!mm || mm->context.id == 0) {
734 * Kernel thread contexts are not supported and context id 0 is
735 * reserved on the GPU.
737 return ERR_PTR(-EINVAL);
740 nphb = pci_bus_to_host(npdev->bus)->private_data;
744 * Setup the NPU context table for a particular GPU. These need to be
745 * per-GPU as we need the tables to filter ATSDs when there are no
746 * active contexts on a particular GPU.
748 rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
749 PCI_DEVID(gpdev->bus->number, gpdev->devfn));
751 return ERR_PTR(-ENOSPC);
754 * We store the npu pci device so we can more easily get at the
757 npu_context = mm->context.npu_context;
760 npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
762 kref_init(&npu_context->kref);
763 npu_context->mm = mm;
764 npu_context->mn.ops = &nv_nmmu_notifier_ops;
765 rc = __mmu_notifier_register(&npu_context->mn, mm);
770 opal_npu_destroy_context(nphb->opal_id, mm->context.id,
771 PCI_DEVID(gpdev->bus->number,
776 mm->context.npu_context = npu_context;
778 WARN_ON(!kref_get_unless_zero(&npu_context->kref));
781 npu_context->release_cb = cb;
782 npu_context->priv = priv;
785 * npdev is a pci_dev pointer setup by the PCI code. We assign it to
786 * npdev[][] to indicate to the mmu notifiers that an invalidation
787 * should also be sent over this nvlink. The notifiers don't use any
788 * other fields in npu_context, so we just need to ensure that when they
789 * deference npu_context->npdev[][] it is either a valid pointer or
792 WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
794 if (!nphb->npu.nmmu_flush) {
796 * If we're not explicitly flushing ourselves we need to mark
797 * the thread for global flushes
799 npu_context->nmmu_flush = false;
800 mm_context_add_copro(mm);
802 npu_context->nmmu_flush = true;
806 EXPORT_SYMBOL(pnv_npu2_init_context);
808 static void pnv_npu2_release_context(struct kref *kref)
810 struct npu_context *npu_context =
811 container_of(kref, struct npu_context, kref);
813 if (!npu_context->nmmu_flush)
814 mm_context_remove_copro(npu_context->mm);
816 npu_context->mm->context.npu_context = NULL;
817 mmu_notifier_unregister(&npu_context->mn,
823 void pnv_npu2_destroy_context(struct npu_context *npu_context,
824 struct pci_dev *gpdev)
826 struct pnv_phb *nphb;
828 struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
829 struct device_node *nvlink_dn;
835 if (!firmware_has_feature(FW_FEATURE_OPAL))
838 nphb = pci_bus_to_host(npdev->bus)->private_data;
840 nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
841 if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
844 WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], NULL);
845 opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id,
846 PCI_DEVID(gpdev->bus->number, gpdev->devfn));
847 kref_put(&npu_context->kref, pnv_npu2_release_context);
849 EXPORT_SYMBOL(pnv_npu2_destroy_context);
852 * Assumes mmap_sem is held for the contexts associated mm.
854 int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
855 unsigned long *flags, unsigned long *status, int count)
857 u64 rc = 0, result = 0;
859 struct page *page[1];
861 /* mmap_sem should be held so the struct_mm must be present */
862 struct mm_struct *mm = context->mm;
864 if (!firmware_has_feature(FW_FEATURE_OPAL))
867 WARN_ON(!rwsem_is_locked(&mm->mmap_sem));
869 for (i = 0; i < count; i++) {
870 is_write = flags[i] & NPU2_WRITE;
871 rc = get_user_pages_remote(NULL, mm, ea[i], 1,
872 is_write ? FOLL_WRITE : 0,
876 * To support virtualised environments we will have to do an
877 * access to the page to ensure it gets faulted into the
878 * hypervisor. For the moment virtualisation is not supported in
879 * other areas so leave the access out.
893 EXPORT_SYMBOL(pnv_npu2_handle_fault);
895 int pnv_npu2_init(struct pnv_phb *phb)
899 struct device_node *dn;
900 struct pci_dev *gpdev;
901 static int npu_index;
904 phb->npu.nmmu_flush =
905 of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
906 for_each_child_of_node(phb->hose->dn, dn) {
907 gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
909 rc = opal_npu_map_lpar(phb->opal_id,
910 PCI_DEVID(gpdev->bus->number, gpdev->devfn),
914 "Error %lld mapping device to LPAR\n",
919 for (i = 0; !of_property_read_u64_index(phb->hose->dn, "ibm,mmio-atsd",
921 phb->npu.mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
923 pr_info("NPU%lld: Found %d MMIO ATSD registers", phb->opal_id, i);
924 phb->npu.mmio_atsd_count = i;
925 phb->npu.mmio_atsd_usage = 0;
927 if (WARN_ON(npu_index >= NV_MAX_NPUS))
929 max_npu2_index = npu_index;
930 phb->npu.index = npu_index;