arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/memblock.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24 #include <linux/iommu.h>
  25 #include <linux/rculist.h>
  26 #include <linux/sizes.h>
  27
  28 #include <asm/sections.h>
  29 #include <asm/io.h>
  30 #include <asm/prom.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/machdep.h>
  33 #include <asm/msi_bitmap.h>
  34 #include <asm/ppc-pci.h>
  35 #include <asm/opal.h>
  36 #include <asm/iommu.h>
  37 #include <asm/tce.h>
  38 #include <asm/xics.h>
  39 #include <asm/debugfs.h>
  40 #include <asm/firmware.h>
  41 #include <asm/pnv-pci.h>
  42 #include <asm/mmzone.h>
  43
  44 #include <misc/cxl-base.h>
  45
  46 #include "powernv.h"
  47 #include "pci.h"
  48 #include "../../../../drivers/pci/pci.h"
  49
  50 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  51 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  53
  54 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
  55                                               "NPU_OCAPI" };
  56
  57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  58                             const char *fmt, ...)
  59 {
  60         struct va_format vaf;
  61         va_list args;
  62         char pfix[32];
  63
  64         va_start(args, fmt);
  65
  66         vaf.fmt = fmt;
  67         vaf.va = &args;
  68
  69         if (pe->flags & PNV_IODA_PE_DEV)
  70                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  71         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  72                 sprintf(pfix, "%04x:%02x     ",
  73                         pci_domain_nr(pe->pbus), pe->pbus->number);
  74 #ifdef CONFIG_PCI_IOV
  75         else if (pe->flags & PNV_IODA_PE_VF)
  76                 sprintf(pfix, "%04x:%02x:%2x.%d",
  77                         pci_domain_nr(pe->parent_dev->bus),
  78                         (pe->rid & 0xff00) >> 8,
  79                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  80 #endif /* CONFIG_PCI_IOV*/
  81
  82         printk("%spci %s: [PE# %.2x] %pV",
  83                level, pfix, pe->pe_number, &vaf);
  84
  85         va_end(args);
  86 }
  87
  88 static bool pnv_iommu_bypass_disabled __read_mostly;
  89 static bool pci_reset_phbs __read_mostly;
  90
  91 static int __init iommu_setup(char *str)
  92 {
  93         if (!str)
  94                 return -EINVAL;
  95
  96         while (*str) {
  97                 if (!strncmp(str, "nobypass", 8)) {
  98                         pnv_iommu_bypass_disabled = true;
  99                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 100                         break;
 101                 }
 102                 str += strcspn(str, ",");
 103                 if (*str == ',')
 104                         str++;
 105         }
 106
 107         return 0;
 108 }
 109 early_param("iommu", iommu_setup);
 110
 111 static int __init pci_reset_phbs_setup(char *str)
 112 {
 113         pci_reset_phbs = true;
 114         return 0;
 115 }
 116
 117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
 118
 119 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 120 {
 121         /*
 122          * WARNING: We cannot rely on the resource flags. The Linux PCI
 123          * allocation code sometimes decides to put a 64-bit prefetchable
 124          * BAR in the 32-bit window, so we have to compare the addresses.
 125          *
 126          * For simplicity we only test resource start.
 127          */
 128         return (r->start >= phb->ioda.m64_base &&
 129                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 130 }
 131
 132 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 133 {
 134         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 135
 136         return (resource_flags & flags) == flags;
 137 }
 138
 139 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 140 {
 141         s64 rc;
 142
 143         phb->ioda.pe_array[pe_no].phb = phb;
 144         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 145
 146         /*
 147          * Clear the PE frozen state as it might be put into frozen state
 148          * in the last PCI remove path. It's not harmful to do so when the
 149          * PE is already in unfrozen state.
 150          */
 151         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 152                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 153         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 154                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 155                         __func__, rc, phb->hose->global_number, pe_no);
 156
 157         return &phb->ioda.pe_array[pe_no];
 158 }
 159
 160 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 161 {
 162         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 163                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 164                         __func__, pe_no, phb->hose->global_number);
 165                 return;
 166         }
 167
 168         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 169                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 170                          __func__, pe_no, phb->hose->global_number);
 171
 172         pnv_ioda_init_pe(phb, pe_no);
 173 }
 174
 175 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 176 {
 177         long pe;
 178
 179         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 180                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 181                         return pnv_ioda_init_pe(phb, pe);
 182         }
 183
 184         return NULL;
 185 }
 186
 187 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 188 {
 189         struct pnv_phb *phb = pe->phb;
 190         unsigned int pe_num = pe->pe_number;
 191
 192         WARN_ON(pe->pdev);
 193         WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
 194         kfree(pe->npucomp);
 195         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 196         clear_bit(pe_num, phb->ioda.pe_alloc);
 197 }
 198
 199 /* The default M64 BAR is shared by all PEs */
 200 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 201 {
 202         const char *desc;
 203         struct resource *r;
 204         s64 rc;
 205
 206         /* Configure the default M64 BAR */
 207         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 208                                          OPAL_M64_WINDOW_TYPE,
 209                                          phb->ioda.m64_bar_idx,
 210                                          phb->ioda.m64_base,
 211                                          0, /* unused */
 212                                          phb->ioda.m64_size);
 213         if (rc != OPAL_SUCCESS) {
 214                 desc = "configuring";
 215                 goto fail;
 216         }
 217
 218         /* Enable the default M64 BAR */
 219         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 220                                       OPAL_M64_WINDOW_TYPE,
 221                                       phb->ioda.m64_bar_idx,
 222                                       OPAL_ENABLE_M64_SPLIT);
 223         if (rc != OPAL_SUCCESS) {
 224                 desc = "enabling";
 225                 goto fail;
 226         }
 227
 228         /*
 229          * Exclude the segments for reserved and root bus PE, which
 230          * are first or last two PEs.
 231          */
 232         r = &phb->hose->mem_resources[1];
 233         if (phb->ioda.reserved_pe_idx == 0)
 234                 r->start += (2 * phb->ioda.m64_segsize);
 235         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 236                 r->end -= (2 * phb->ioda.m64_segsize);
 237         else
 238                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 239                         phb->ioda.reserved_pe_idx);
 240
 241         return 0;
 242
 243 fail:
 244         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 245                 rc, desc, phb->ioda.m64_bar_idx);
 246         opal_pci_phb_mmio_enable(phb->opal_id,
 247                                  OPAL_M64_WINDOW_TYPE,
 248                                  phb->ioda.m64_bar_idx,
 249                                  OPAL_DISABLE_M64);
 250         return -EIO;
 251 }
 252
 253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 254                                          unsigned long *pe_bitmap)
 255 {
 256         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 257         struct pnv_phb *phb = hose->private_data;
 258         struct resource *r;
 259         resource_size_t base, sgsz, start, end;
 260         int segno, i;
 261
 262         base = phb->ioda.m64_base;
 263         sgsz = phb->ioda.m64_segsize;
 264         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 265                 r = &pdev->resource[i];
 266                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 267                         continue;
 268
 269                 start = _ALIGN_DOWN(r->start - base, sgsz);
 270                 end = _ALIGN_UP(r->end - base, sgsz);
 271                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 272                         if (pe_bitmap)
 273                                 set_bit(segno, pe_bitmap);
 274                         else
 275                                 pnv_ioda_reserve_pe(phb, segno);
 276                 }
 277         }
 278 }
 279
 280 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 281 {
 282         struct resource *r;
 283         int index;
 284
 285         /*
 286          * There are 16 M64 BARs, each of which has 8 segments. So
 287          * there are as many M64 segments as the maximum number of
 288          * PEs, which is 128.
 289          */
 290         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 291                 unsigned long base, segsz = phb->ioda.m64_segsize;
 292                 int64_t rc;
 293
 294                 base = phb->ioda.m64_base +
 295                        index * PNV_IODA1_M64_SEGS * segsz;
 296                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 297                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 298                                 PNV_IODA1_M64_SEGS * segsz);
 299                 if (rc != OPAL_SUCCESS) {
 300                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 301                                 rc, phb->hose->global_number, index);
 302                         goto fail;
 303                 }
 304
 305                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 306                                 OPAL_M64_WINDOW_TYPE, index,
 307                                 OPAL_ENABLE_M64_SPLIT);
 308                 if (rc != OPAL_SUCCESS) {
 309                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 310                                 rc, phb->hose->global_number, index);
 311                         goto fail;
 312                 }
 313         }
 314
 315         /*
 316          * Exclude the segments for reserved and root bus PE, which
 317          * are first or last two PEs.
 318          */
 319         r = &phb->hose->mem_resources[1];
 320         if (phb->ioda.reserved_pe_idx == 0)
 321                 r->start += (2 * phb->ioda.m64_segsize);
 322         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 323                 r->end -= (2 * phb->ioda.m64_segsize);
 324         else
 325                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 326                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 327
 328         return 0;
 329
 330 fail:
 331         for ( ; index >= 0; index--)
 332                 opal_pci_phb_mmio_enable(phb->opal_id,
 333                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 334
 335         return -EIO;
 336 }
 337
 338 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 339                                     unsigned long *pe_bitmap,
 340                                     bool all)
 341 {
 342         struct pci_dev *pdev;
 343
 344         list_for_each_entry(pdev, &bus->devices, bus_list) {
 345                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 346
 347                 if (all && pdev->subordinate)
 348                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 349                                                 pe_bitmap, all);
 350         }
 351 }
 352
 353 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 354 {
 355         struct pci_controller *hose = pci_bus_to_host(bus);
 356         struct pnv_phb *phb = hose->private_data;
 357         struct pnv_ioda_pe *master_pe, *pe;
 358         unsigned long size, *pe_alloc;
 359         int i;
 360
 361         /* Root bus shouldn't use M64 */
 362         if (pci_is_root_bus(bus))
 363                 return NULL;
 364
 365         /* Allocate bitmap */
 366         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 367         pe_alloc = kzalloc(size, GFP_KERNEL);
 368         if (!pe_alloc) {
 369                 pr_warn("%s: Out of memory !\n",
 370                         __func__);
 371                 return NULL;
 372         }
 373
 374         /* Figure out reserved PE numbers by the PE */
 375         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 376
 377         /*
 378          * the current bus might not own M64 window and that's all
 379          * contributed by its child buses. For the case, we needn't
 380          * pick M64 dependent PE#.
 381          */
 382         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 383                 kfree(pe_alloc);
 384                 return NULL;
 385         }
 386
 387         /*
 388          * Figure out the master PE and put all slave PEs to master
 389          * PE's list to form compound PE.
 390          */
 391         master_pe = NULL;
 392         i = -1;
 393         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 394                 phb->ioda.total_pe_num) {
 395                 pe = &phb->ioda.pe_array[i];
 396
 397                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 398                 if (!master_pe) {
 399                         pe->flags |= PNV_IODA_PE_MASTER;
 400                         INIT_LIST_HEAD(&pe->slaves);
 401                         master_pe = pe;
 402                 } else {
 403                         pe->flags |= PNV_IODA_PE_SLAVE;
 404                         pe->master = master_pe;
 405                         list_add_tail(&pe->list, &master_pe->slaves);
 406                 }
 407
 408                 /*
 409                  * P7IOC supports M64DT, which helps mapping M64 segment
 410                  * to one particular PE#. However, PHB3 has fixed mapping
 411                  * between M64 segment and PE#. In order to have same logic
 412                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 413                  * segment and PE# on P7IOC.
 414                  */
 415                 if (phb->type == PNV_PHB_IODA1) {
 416                         int64_t rc;
 417
 418                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 419                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 420                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 421                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 422                         if (rc != OPAL_SUCCESS)
 423                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 424                                         __func__, rc, phb->hose->global_number,
 425                                         pe->pe_number);
 426                 }
 427         }
 428
 429         kfree(pe_alloc);
 430         return master_pe;
 431 }
 432
 433 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 434 {
 435         struct pci_controller *hose = phb->hose;
 436         struct device_node *dn = hose->dn;
 437         struct resource *res;
 438         u32 m64_range[2], i;
 439         const __be32 *r;
 440         u64 pci_addr;
 441
 442         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 443                 pr_info("  Not support M64 window\n");
 444                 return;
 445         }
 446
 447         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 448                 pr_info("  Firmware too old to support M64 window\n");
 449                 return;
 450         }
 451
 452         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 453         if (!r) {
 454                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 455                         dn);
 456                 return;
 457         }
 458
 459         /*
 460          * Find the available M64 BAR range and pickup the last one for
 461          * covering the whole 64-bits space. We support only one range.
 462          */
 463         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 464                                        m64_range, 2)) {
 465                 /* In absence of the property, assume 0..15 */
 466                 m64_range[0] = 0;
 467                 m64_range[1] = 16;
 468         }
 469         /* We only support 64 bits in our allocator */
 470         if (m64_range[1] > 63) {
 471                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 472                         __func__, m64_range[1], phb->hose->global_number);
 473                 m64_range[1] = 63;
 474         }
 475         /* Empty range, no m64 */
 476         if (m64_range[1] <= m64_range[0]) {
 477                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 478                         __func__, phb->hose->global_number);
 479                 return;
 480         }
 481
 482         /* Configure M64 informations */
 483         res = &hose->mem_resources[1];
 484         res->name = dn->full_name;
 485         res->start = of_translate_address(dn, r + 2);
 486         res->end = res->start + of_read_number(r + 4, 2) - 1;
 487         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 488         pci_addr = of_read_number(r, 2);
 489         hose->mem_offset[1] = res->start - pci_addr;
 490
 491         phb->ioda.m64_size = resource_size(res);
 492         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 493         phb->ioda.m64_base = pci_addr;
 494
 495         /* This lines up nicely with the display from processing OF ranges */
 496         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 497                 res->start, res->end, pci_addr, m64_range[0],
 498                 m64_range[0] + m64_range[1] - 1);
 499
 500         /* Mark all M64 used up by default */
 501         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 502
 503         /* Use last M64 BAR to cover M64 window */
 504         m64_range[1]--;
 505         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 506
 507         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 508
 509         /* Mark remaining ones free */
 510         for (i = m64_range[0]; i < m64_range[1]; i++)
 511                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 512
 513         /*
 514          * Setup init functions for M64 based on IODA version, IODA3 uses
 515          * the IODA2 code.
 516          */
 517         if (phb->type == PNV_PHB_IODA1)
 518                 phb->init_m64 = pnv_ioda1_init_m64;
 519         else
 520                 phb->init_m64 = pnv_ioda2_init_m64;
 521 }
 522
 523 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 524 {
 525         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 526         struct pnv_ioda_pe *slave;
 527         s64 rc;
 528
 529         /* Fetch master PE */
 530         if (pe->flags & PNV_IODA_PE_SLAVE) {
 531                 pe = pe->master;
 532                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 533                         return;
 534
 535                 pe_no = pe->pe_number;
 536         }
 537
 538         /* Freeze master PE */
 539         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 540                                      pe_no,
 541                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 542         if (rc != OPAL_SUCCESS) {
 543                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 544                         __func__, rc, phb->hose->global_number, pe_no);
 545                 return;
 546         }
 547
 548         /* Freeze slave PEs */
 549         if (!(pe->flags & PNV_IODA_PE_MASTER))
 550                 return;
 551
 552         list_for_each_entry(slave, &pe->slaves, list) {
 553                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 554                                              slave->pe_number,
 555                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 556                 if (rc != OPAL_SUCCESS)
 557                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 558                                 __func__, rc, phb->hose->global_number,
 559                                 slave->pe_number);
 560         }
 561 }
 562
 563 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 564 {
 565         struct pnv_ioda_pe *pe, *slave;
 566         s64 rc;
 567
 568         /* Find master PE */
 569         pe = &phb->ioda.pe_array[pe_no];
 570         if (pe->flags & PNV_IODA_PE_SLAVE) {
 571                 pe = pe->master;
 572                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 573                 pe_no = pe->pe_number;
 574         }
 575
 576         /* Clear frozen state for master PE */
 577         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 578         if (rc != OPAL_SUCCESS) {
 579                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 580                         __func__, rc, opt, phb->hose->global_number, pe_no);
 581                 return -EIO;
 582         }
 583
 584         if (!(pe->flags & PNV_IODA_PE_MASTER))
 585                 return 0;
 586
 587         /* Clear frozen state for slave PEs */
 588         list_for_each_entry(slave, &pe->slaves, list) {
 589                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 590                                              slave->pe_number,
 591                                              opt);
 592                 if (rc != OPAL_SUCCESS) {
 593                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 594                                 __func__, rc, opt, phb->hose->global_number,
 595                                 slave->pe_number);
 596                         return -EIO;
 597                 }
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 604 {
 605         struct pnv_ioda_pe *slave, *pe;
 606         u8 fstate = 0, state;
 607         __be16 pcierr = 0;
 608         s64 rc;
 609
 610         /* Sanity check on PE number */
 611         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 612                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 613
 614         /*
 615          * Fetch the master PE and the PE instance might be
 616          * not initialized yet.
 617          */
 618         pe = &phb->ioda.pe_array[pe_no];
 619         if (pe->flags & PNV_IODA_PE_SLAVE) {
 620                 pe = pe->master;
 621                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 622                 pe_no = pe->pe_number;
 623         }
 624
 625         /* Check the master PE */
 626         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 627                                         &state, &pcierr, NULL);
 628         if (rc != OPAL_SUCCESS) {
 629                 pr_warn("%s: Failure %lld getting "
 630                         "PHB#%x-PE#%x state\n",
 631                         __func__, rc,
 632                         phb->hose->global_number, pe_no);
 633                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 634         }
 635
 636         /* Check the slave PE */
 637         if (!(pe->flags & PNV_IODA_PE_MASTER))
 638                 return state;
 639
 640         list_for_each_entry(slave, &pe->slaves, list) {
 641                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 642                                                 slave->pe_number,
 643                                                 &fstate,
 644                                                 &pcierr,
 645                                                 NULL);
 646                 if (rc != OPAL_SUCCESS) {
 647                         pr_warn("%s: Failure %lld getting "
 648                                 "PHB#%x-PE#%x state\n",
 649                                 __func__, rc,
 650                                 phb->hose->global_number, slave->pe_number);
 651                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 652                 }
 653
 654                 /*
 655                  * Override the result based on the ascending
 656                  * priority.
 657                  */
 658                 if (fstate > state)
 659                         state = fstate;
 660         }
 661
 662         return state;
 663 }
 664
 665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 666 {
 667         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 668         struct pnv_phb *phb = hose->private_data;
 669         struct pci_dn *pdn = pci_get_pdn(dev);
 670
 671         if (!pdn)
 672                 return NULL;
 673         if (pdn->pe_number == IODA_INVALID_PE)
 674                 return NULL;
 675         return &phb->ioda.pe_array[pdn->pe_number];
 676 }
 677
 678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 679                                   struct pnv_ioda_pe *parent,
 680                                   struct pnv_ioda_pe *child,
 681                                   bool is_add)
 682 {
 683         const char *desc = is_add ? "adding" : "removing";
 684         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 685                               OPAL_REMOVE_PE_FROM_DOMAIN;
 686         struct pnv_ioda_pe *slave;
 687         long rc;
 688
 689         /* Parent PE affects child PE */
 690         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 691                                 child->pe_number, op);
 692         if (rc != OPAL_SUCCESS) {
 693                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 694                         rc, desc);
 695                 return -ENXIO;
 696         }
 697
 698         if (!(child->flags & PNV_IODA_PE_MASTER))
 699                 return 0;
 700
 701         /* Compound case: parent PE affects slave PEs */
 702         list_for_each_entry(slave, &child->slaves, list) {
 703                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 704                                         slave->pe_number, op);
 705                 if (rc != OPAL_SUCCESS) {
 706                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 707                                 rc, desc);
 708                         return -ENXIO;
 709                 }
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 716                               struct pnv_ioda_pe *pe,
 717                               bool is_add)
 718 {
 719         struct pnv_ioda_pe *slave;
 720         struct pci_dev *pdev = NULL;
 721         int ret;
 722
 723         /*
 724          * Clear PE frozen state. If it's master PE, we need
 725          * clear slave PE frozen state as well.
 726          */
 727         if (is_add) {
 728                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 729                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 730                 if (pe->flags & PNV_IODA_PE_MASTER) {
 731                         list_for_each_entry(slave, &pe->slaves, list)
 732                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 733                                                           slave->pe_number,
 734                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 735                 }
 736         }
 737
 738         /*
 739          * Associate PE in PELT. We need add the PE into the
 740          * corresponding PELT-V as well. Otherwise, the error
 741          * originated from the PE might contribute to other
 742          * PEs.
 743          */
 744         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 745         if (ret)
 746                 return ret;
 747
 748         /* For compound PEs, any one affects all of them */
 749         if (pe->flags & PNV_IODA_PE_MASTER) {
 750                 list_for_each_entry(slave, &pe->slaves, list) {
 751                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 752                         if (ret)
 753                                 return ret;
 754                 }
 755         }
 756
 757         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 758                 pdev = pe->pbus->self;
 759         else if (pe->flags & PNV_IODA_PE_DEV)
 760                 pdev = pe->pdev->bus->self;
 761 #ifdef CONFIG_PCI_IOV
 762         else if (pe->flags & PNV_IODA_PE_VF)
 763                 pdev = pe->parent_dev;
 764 #endif /* CONFIG_PCI_IOV */
 765         while (pdev) {
 766                 struct pci_dn *pdn = pci_get_pdn(pdev);
 767                 struct pnv_ioda_pe *parent;
 768
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         parent = &phb->ioda.pe_array[pdn->pe_number];
 771                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 772                         if (ret)
 773                                 return ret;
 774                 }
 775
 776                 pdev = pdev->bus->self;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 783 {
 784         struct pci_dev *parent;
 785         uint8_t bcomp, dcomp, fcomp;
 786         int64_t rc;
 787         long rid_end, rid;
 788
 789         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 790         if (pe->pbus) {
 791                 int count;
 792
 793                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 794                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 795                 parent = pe->pbus->self;
 796                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 797                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 798                 else
 799                         count = 1;
 800
 801                 switch(count) {
 802                 case  1: bcomp = OpalPciBusAll;         break;
 803                 case  2: bcomp = OpalPciBus7Bits;       break;
 804                 case  4: bcomp = OpalPciBus6Bits;       break;
 805                 case  8: bcomp = OpalPciBus5Bits;       break;
 806                 case 16: bcomp = OpalPciBus4Bits;       break;
 807                 case 32: bcomp = OpalPciBus3Bits;       break;
 808                 default:
 809                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 810                                 count);
 811                         /* Do an exact match only */
 812                         bcomp = OpalPciBusAll;
 813                 }
 814                 rid_end = pe->rid + (count << 8);
 815         } else {
 816 #ifdef CONFIG_PCI_IOV
 817                 if (pe->flags & PNV_IODA_PE_VF)
 818                         parent = pe->parent_dev;
 819                 else
 820 #endif
 821                         parent = pe->pdev->bus->self;
 822                 bcomp = OpalPciBusAll;
 823                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 824                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 825                 rid_end = pe->rid + 1;
 826         }
 827
 828         /* Clear the reverse map */
 829         for (rid = pe->rid; rid < rid_end; rid++)
 830                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 831
 832         /* Release from all parents PELT-V */
 833         while (parent) {
 834                 struct pci_dn *pdn = pci_get_pdn(parent);
 835                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 836                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 837                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 838                         /* XXX What to do in case of error ? */
 839                 }
 840                 parent = parent->bus->self;
 841         }
 842
 843         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 844                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 845
 846         /* Disassociate PE in PELT */
 847         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 848                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 849         if (rc)
 850                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 851         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 852                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 853         if (rc)
 854                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 855
 856         pe->pbus = NULL;
 857         pe->pdev = NULL;
 858 #ifdef CONFIG_PCI_IOV
 859         pe->parent_dev = NULL;
 860 #endif
 861
 862         return 0;
 863 }
 864
 865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 866 {
 867         struct pci_dev *parent;
 868         uint8_t bcomp, dcomp, fcomp;
 869         long rc, rid_end, rid;
 870
 871         /* Bus validation ? */
 872         if (pe->pbus) {
 873                 int count;
 874
 875                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 876                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 877                 parent = pe->pbus->self;
 878                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 879                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 880                 else
 881                         count = 1;
 882
 883                 switch(count) {
 884                 case  1: bcomp = OpalPciBusAll;         break;
 885                 case  2: bcomp = OpalPciBus7Bits;       break;
 886                 case  4: bcomp = OpalPciBus6Bits;       break;
 887                 case  8: bcomp = OpalPciBus5Bits;       break;
 888                 case 16: bcomp = OpalPciBus4Bits;       break;
 889                 case 32: bcomp = OpalPciBus3Bits;       break;
 890                 default:
 891                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 892                                 count);
 893                         /* Do an exact match only */
 894                         bcomp = OpalPciBusAll;
 895                 }
 896                 rid_end = pe->rid + (count << 8);
 897         } else {
 898 #ifdef CONFIG_PCI_IOV
 899                 if (pe->flags & PNV_IODA_PE_VF)
 900                         parent = pe->parent_dev;
 901                 else
 902 #endif /* CONFIG_PCI_IOV */
 903                         parent = pe->pdev->bus->self;
 904                 bcomp = OpalPciBusAll;
 905                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 906                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 907                 rid_end = pe->rid + 1;
 908         }
 909
 910         /*
 911          * Associate PE in PELT. We need add the PE into the
 912          * corresponding PELT-V as well. Otherwise, the error
 913          * originated from the PE might contribute to other
 914          * PEs.
 915          */
 916         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 917                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 918         if (rc) {
 919                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 920                 return -ENXIO;
 921         }
 922
 923         /*
 924          * Configure PELTV. NPUs don't have a PELTV table so skip
 925          * configuration on them.
 926          */
 927         if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
 928                 pnv_ioda_set_peltv(phb, pe, true);
 929
 930         /* Setup reverse map */
 931         for (rid = pe->rid; rid < rid_end; rid++)
 932                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 933
 934         /* Setup one MVTs on IODA1 */
 935         if (phb->type != PNV_PHB_IODA1) {
 936                 pe->mve_number = 0;
 937                 goto out;
 938         }
 939
 940         pe->mve_number = pe->pe_number;
 941         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 942         if (rc != OPAL_SUCCESS) {
 943                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 944                        rc, pe->mve_number);
 945                 pe->mve_number = -1;
 946         } else {
 947                 rc = opal_pci_set_mve_enable(phb->opal_id,
 948                                              pe->mve_number, OPAL_ENABLE_MVE);
 949                 if (rc) {
 950                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 951                                rc, pe->mve_number);
 952                         pe->mve_number = -1;
 953                 }
 954         }
 955
 956 out:
 957         return 0;
 958 }
 959
 960 #ifdef CONFIG_PCI_IOV
 961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 962 {
 963         struct pci_dn *pdn = pci_get_pdn(dev);
 964         int i;
 965         struct resource *res, res2;
 966         resource_size_t size;
 967         u16 num_vfs;
 968
 969         if (!dev->is_physfn)
 970                 return -EINVAL;
 971
 972         /*
 973          * "offset" is in VFs.  The M64 windows are sized so that when they
 974          * are segmented, each segment is the same size as the IOV BAR.
 975          * Each segment is in a separate PE, and the high order bits of the
 976          * address are the PE number.  Therefore, each VF's BAR is in a
 977          * separate PE, and changing the IOV BAR start address changes the
 978          * range of PEs the VFs are in.
 979          */
 980         num_vfs = pdn->num_vfs;
 981         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 982                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 983                 if (!res->flags || !res->parent)
 984                         continue;
 985
 986                 /*
 987                  * The actual IOV BAR range is determined by the start address
 988                  * and the actual size for num_vfs VFs BAR.  This check is to
 989                  * make sure that after shifting, the range will not overlap
 990                  * with another device.
 991                  */
 992                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 993                 res2.flags = res->flags;
 994                 res2.start = res->start + (size * offset);
 995                 res2.end = res2.start + (size * num_vfs) - 1;
 996
 997                 if (res2.end > res->end) {
 998                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 999                                 i, &res2, res, num_vfs, offset);
1000                         return -EBUSY;
1001                 }
1002         }
1003
1004         /*
1005          * Since M64 BAR shares segments among all possible 256 PEs,
1006          * we have to shift the beginning of PF IOV BAR to make it start from
1007          * the segment which belongs to the PE number assigned to the first VF.
1008          * This creates a "hole" in the /proc/iomem which could be used for
1009          * allocating other resources so we reserve this area below and
1010          * release when IOV is released.
1011          */
1012         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1013                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1014                 if (!res->flags || !res->parent)
1015                         continue;
1016
1017                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1018                 res2 = *res;
1019                 res->start += size * offset;
1020
1021                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1022                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1023                          num_vfs, offset);
1024
1025                 if (offset < 0) {
1026                         devm_release_resource(&dev->dev, &pdn->holes[i]);
1027                         memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1028                 }
1029
1030                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1031
1032                 if (offset > 0) {
1033                         pdn->holes[i].start = res2.start;
1034                         pdn->holes[i].end = res2.start + size * offset - 1;
1035                         pdn->holes[i].flags = IORESOURCE_BUS;
1036                         pdn->holes[i].name = "pnv_iov_reserved";
1037                         devm_request_resource(&dev->dev, res->parent,
1038                                         &pdn->holes[i]);
1039                 }
1040         }
1041         return 0;
1042 }
1043 #endif /* CONFIG_PCI_IOV */
1044
1045 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1046 {
1047         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1048         struct pnv_phb *phb = hose->private_data;
1049         struct pci_dn *pdn = pci_get_pdn(dev);
1050         struct pnv_ioda_pe *pe;
1051
1052         if (!pdn) {
1053                 pr_err("%s: Device tree node not associated properly\n",
1054                            pci_name(dev));
1055                 return NULL;
1056         }
1057         if (pdn->pe_number != IODA_INVALID_PE)
1058                 return NULL;
1059
1060         pe = pnv_ioda_alloc_pe(phb);
1061         if (!pe) {
1062                 pr_warn("%s: Not enough PE# available, disabling device\n",
1063                         pci_name(dev));
1064                 return NULL;
1065         }
1066
1067         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1068          * pointer in the PE data structure, both should be destroyed at the
1069          * same time. However, this needs to be looked at more closely again
1070          * once we actually start removing things (Hotplug, SR-IOV, ...)
1071          *
1072          * At some point we want to remove the PDN completely anyways
1073          */
1074         pci_dev_get(dev);
1075         pdn->pe_number = pe->pe_number;
1076         pe->flags = PNV_IODA_PE_DEV;
1077         pe->pdev = dev;
1078         pe->pbus = NULL;
1079         pe->mve_number = -1;
1080         pe->rid = dev->bus->number << 8 | pdn->devfn;
1081
1082         pe_info(pe, "Associated device to PE\n");
1083
1084         if (pnv_ioda_configure_pe(phb, pe)) {
1085                 /* XXX What do we do here ? */
1086                 pnv_ioda_free_pe(pe);
1087                 pdn->pe_number = IODA_INVALID_PE;
1088                 pe->pdev = NULL;
1089                 pci_dev_put(dev);
1090                 return NULL;
1091         }
1092
1093         /* Put PE to the list */
1094         list_add_tail(&pe->list, &phb->ioda.pe_list);
1095
1096         return pe;
1097 }
1098
1099 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1100 {
1101         struct pci_dev *dev;
1102
1103         list_for_each_entry(dev, &bus->devices, bus_list) {
1104                 struct pci_dn *pdn = pci_get_pdn(dev);
1105
1106                 if (pdn == NULL) {
1107                         pr_warn("%s: No device node associated with device !\n",
1108                                 pci_name(dev));
1109                         continue;
1110                 }
1111
1112                 /*
1113                  * In partial hotplug case, the PCI device might be still
1114                  * associated with the PE and needn't attach it to the PE
1115                  * again.
1116                  */
1117                 if (pdn->pe_number != IODA_INVALID_PE)
1118                         continue;
1119
1120                 pe->device_count++;
1121                 pdn->pe_number = pe->pe_number;
1122                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1123                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1124         }
1125 }
1126
1127 /*
1128  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1129  * single PCI bus. Another one that contains the primary PCI bus and its
1130  * subordinate PCI devices and buses. The second type of PE is normally
1131  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1132  */
1133 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1134 {
1135         struct pci_controller *hose = pci_bus_to_host(bus);
1136         struct pnv_phb *phb = hose->private_data;
1137         struct pnv_ioda_pe *pe = NULL;
1138         unsigned int pe_num;
1139
1140         /*
1141          * In partial hotplug case, the PE instance might be still alive.
1142          * We should reuse it instead of allocating a new one.
1143          */
1144         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1145         if (pe_num != IODA_INVALID_PE) {
1146                 pe = &phb->ioda.pe_array[pe_num];
1147                 pnv_ioda_setup_same_PE(bus, pe);
1148                 return NULL;
1149         }
1150
1151         /* PE number for root bus should have been reserved */
1152         if (pci_is_root_bus(bus) &&
1153             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1154                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1155
1156         /* Check if PE is determined by M64 */
1157         if (!pe)
1158                 pe = pnv_ioda_pick_m64_pe(bus, all);
1159
1160         /* The PE number isn't pinned by M64 */
1161         if (!pe)
1162                 pe = pnv_ioda_alloc_pe(phb);
1163
1164         if (!pe) {
1165                 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1166                         __func__, pci_domain_nr(bus), bus->number);
1167                 return NULL;
1168         }
1169
1170         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1171         pe->pbus = bus;
1172         pe->pdev = NULL;
1173         pe->mve_number = -1;
1174         pe->rid = bus->busn_res.start << 8;
1175
1176         if (all)
1177                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1178                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1179         else
1180                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1181                         bus->busn_res.start, pe->pe_number);
1182
1183         if (pnv_ioda_configure_pe(phb, pe)) {
1184                 /* XXX What do we do here ? */
1185                 pnv_ioda_free_pe(pe);
1186                 pe->pbus = NULL;
1187                 return NULL;
1188         }
1189
1190         /* Associate it with all child devices */
1191         pnv_ioda_setup_same_PE(bus, pe);
1192
1193         /* Put PE to the list */
1194         list_add_tail(&pe->list, &phb->ioda.pe_list);
1195
1196         return pe;
1197 }
1198
1199 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1200 {
1201         int pe_num, found_pe = false, rc;
1202         long rid;
1203         struct pnv_ioda_pe *pe;
1204         struct pci_dev *gpu_pdev;
1205         struct pci_dn *npu_pdn;
1206         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1207         struct pnv_phb *phb = hose->private_data;
1208
1209         /*
1210          * Due to a hardware errata PE#0 on the NPU is reserved for
1211          * error handling. This means we only have three PEs remaining
1212          * which need to be assigned to four links, implying some
1213          * links must share PEs.
1214          *
1215          * To achieve this we assign PEs such that NPUs linking the
1216          * same GPU get assigned the same PE.
1217          */
1218         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1219         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1220                 pe = &phb->ioda.pe_array[pe_num];
1221                 if (!pe->pdev)
1222                         continue;
1223
1224                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1225                         /*
1226                          * This device has the same peer GPU so should
1227                          * be assigned the same PE as the existing
1228                          * peer NPU.
1229                          */
1230                         dev_info(&npu_pdev->dev,
1231                                 "Associating to existing PE %x\n", pe_num);
1232                         pci_dev_get(npu_pdev);
1233                         npu_pdn = pci_get_pdn(npu_pdev);
1234                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1235                         npu_pdn->pe_number = pe_num;
1236                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1237
1238                         /* Map the PE to this link */
1239                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1240                                         OpalPciBusAll,
1241                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1242                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1243                                         OPAL_MAP_PE);
1244                         WARN_ON(rc != OPAL_SUCCESS);
1245                         found_pe = true;
1246                         break;
1247                 }
1248         }
1249
1250         if (!found_pe)
1251                 /*
1252                  * Could not find an existing PE so allocate a new
1253                  * one.
1254                  */
1255                 return pnv_ioda_setup_dev_PE(npu_pdev);
1256         else
1257                 return pe;
1258 }
1259
1260 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1261 {
1262         struct pci_dev *pdev;
1263
1264         list_for_each_entry(pdev, &bus->devices, bus_list)
1265                 pnv_ioda_setup_npu_PE(pdev);
1266 }
1267
1268 static void pnv_pci_ioda_setup_PEs(void)
1269 {
1270         struct pci_controller *hose;
1271         struct pnv_phb *phb;
1272         struct pci_bus *bus;
1273         struct pci_dev *pdev;
1274         struct pnv_ioda_pe *pe;
1275
1276         list_for_each_entry(hose, &hose_list, list_node) {
1277                 phb = hose->private_data;
1278                 if (phb->type == PNV_PHB_NPU_NVLINK) {
1279                         /* PE#0 is needed for error reporting */
1280                         pnv_ioda_reserve_pe(phb, 0);
1281                         pnv_ioda_setup_npu_PEs(hose->bus);
1282                         if (phb->model == PNV_PHB_MODEL_NPU2)
1283                                 WARN_ON_ONCE(pnv_npu2_init(hose));
1284                 }
1285                 if (phb->type == PNV_PHB_NPU_OCAPI) {
1286                         bus = hose->bus;
1287                         list_for_each_entry(pdev, &bus->devices, bus_list)
1288                                 pnv_ioda_setup_dev_PE(pdev);
1289                 }
1290         }
1291         list_for_each_entry(hose, &hose_list, list_node) {
1292                 phb = hose->private_data;
1293                 if (phb->type != PNV_PHB_IODA2)
1294                         continue;
1295
1296                 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1297                         pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1298         }
1299 }
1300
1301 #ifdef CONFIG_PCI_IOV
1302 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1303 {
1304         struct pci_bus        *bus;
1305         struct pci_controller *hose;
1306         struct pnv_phb        *phb;
1307         struct pci_dn         *pdn;
1308         int                    i, j;
1309         int                    m64_bars;
1310
1311         bus = pdev->bus;
1312         hose = pci_bus_to_host(bus);
1313         phb = hose->private_data;
1314         pdn = pci_get_pdn(pdev);
1315
1316         if (pdn->m64_single_mode)
1317                 m64_bars = num_vfs;
1318         else
1319                 m64_bars = 1;
1320
1321         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1322                 for (j = 0; j < m64_bars; j++) {
1323                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1324                                 continue;
1325                         opal_pci_phb_mmio_enable(phb->opal_id,
1326                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1327                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1328                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1329                 }
1330
1331         kfree(pdn->m64_map);
1332         return 0;
1333 }
1334
1335 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1336 {
1337         struct pci_bus        *bus;
1338         struct pci_controller *hose;
1339         struct pnv_phb        *phb;
1340         struct pci_dn         *pdn;
1341         unsigned int           win;
1342         struct resource       *res;
1343         int                    i, j;
1344         int64_t                rc;
1345         int                    total_vfs;
1346         resource_size_t        size, start;
1347         int                    pe_num;
1348         int                    m64_bars;
1349
1350         bus = pdev->bus;
1351         hose = pci_bus_to_host(bus);
1352         phb = hose->private_data;
1353         pdn = pci_get_pdn(pdev);
1354         total_vfs = pci_sriov_get_totalvfs(pdev);
1355
1356         if (pdn->m64_single_mode)
1357                 m64_bars = num_vfs;
1358         else
1359                 m64_bars = 1;
1360
1361         pdn->m64_map = kmalloc_array(m64_bars,
1362                                      sizeof(*pdn->m64_map),
1363                                      GFP_KERNEL);
1364         if (!pdn->m64_map)
1365                 return -ENOMEM;
1366         /* Initialize the m64_map to IODA_INVALID_M64 */
1367         for (i = 0; i < m64_bars ; i++)
1368                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1369                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1370
1371
1372         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1373                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1374                 if (!res->flags || !res->parent)
1375                         continue;
1376
1377                 for (j = 0; j < m64_bars; j++) {
1378                         do {
1379                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1380                                                 phb->ioda.m64_bar_idx + 1, 0);
1381
1382                                 if (win >= phb->ioda.m64_bar_idx + 1)
1383                                         goto m64_failed;
1384                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1385
1386                         pdn->m64_map[j][i] = win;
1387
1388                         if (pdn->m64_single_mode) {
1389                                 size = pci_iov_resource_size(pdev,
1390                                                         PCI_IOV_RESOURCES + i);
1391                                 start = res->start + size * j;
1392                         } else {
1393                                 size = resource_size(res);
1394                                 start = res->start;
1395                         }
1396
1397                         /* Map the M64 here */
1398                         if (pdn->m64_single_mode) {
1399                                 pe_num = pdn->pe_num_map[j];
1400                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1401                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1402                                                 pdn->m64_map[j][i], 0);
1403                         }
1404
1405                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1406                                                  OPAL_M64_WINDOW_TYPE,
1407                                                  pdn->m64_map[j][i],
1408                                                  start,
1409                                                  0, /* unused */
1410                                                  size);
1411
1412
1413                         if (rc != OPAL_SUCCESS) {
1414                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1415                                         win, rc);
1416                                 goto m64_failed;
1417                         }
1418
1419                         if (pdn->m64_single_mode)
1420                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1421                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1422                         else
1423                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1424                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1425
1426                         if (rc != OPAL_SUCCESS) {
1427                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1428                                         win, rc);
1429                                 goto m64_failed;
1430                         }
1431                 }
1432         }
1433         return 0;
1434
1435 m64_failed:
1436         pnv_pci_vf_release_m64(pdev, num_vfs);
1437         return -EBUSY;
1438 }
1439
1440 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1441                 int num);
1442
1443 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1444 {
1445         struct iommu_table    *tbl;
1446         int64_t               rc;
1447
1448         tbl = pe->table_group.tables[0];
1449         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1450         if (rc)
1451                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1452
1453         pnv_pci_ioda2_set_bypass(pe, false);
1454         if (pe->table_group.group) {
1455                 iommu_group_put(pe->table_group.group);
1456                 BUG_ON(pe->table_group.group);
1457         }
1458         iommu_tce_table_put(tbl);
1459 }
1460
1461 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1462 {
1463         struct pci_bus        *bus;
1464         struct pci_controller *hose;
1465         struct pnv_phb        *phb;
1466         struct pnv_ioda_pe    *pe, *pe_n;
1467         struct pci_dn         *pdn;
1468
1469         bus = pdev->bus;
1470         hose = pci_bus_to_host(bus);
1471         phb = hose->private_data;
1472         pdn = pci_get_pdn(pdev);
1473
1474         if (!pdev->is_physfn)
1475                 return;
1476
1477         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1478                 if (pe->parent_dev != pdev)
1479                         continue;
1480
1481                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1482
1483                 /* Remove from list */
1484                 mutex_lock(&phb->ioda.pe_list_mutex);
1485                 list_del(&pe->list);
1486                 mutex_unlock(&phb->ioda.pe_list_mutex);
1487
1488                 pnv_ioda_deconfigure_pe(phb, pe);
1489
1490                 pnv_ioda_free_pe(pe);
1491         }
1492 }
1493
1494 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1495 {
1496         struct pci_bus        *bus;
1497         struct pci_controller *hose;
1498         struct pnv_phb        *phb;
1499         struct pnv_ioda_pe    *pe;
1500         struct pci_dn         *pdn;
1501         u16                    num_vfs, i;
1502
1503         bus = pdev->bus;
1504         hose = pci_bus_to_host(bus);
1505         phb = hose->private_data;
1506         pdn = pci_get_pdn(pdev);
1507         num_vfs = pdn->num_vfs;
1508
1509         /* Release VF PEs */
1510         pnv_ioda_release_vf_PE(pdev);
1511
1512         if (phb->type == PNV_PHB_IODA2) {
1513                 if (!pdn->m64_single_mode)
1514                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1515
1516                 /* Release M64 windows */
1517                 pnv_pci_vf_release_m64(pdev, num_vfs);
1518
1519                 /* Release PE numbers */
1520                 if (pdn->m64_single_mode) {
1521                         for (i = 0; i < num_vfs; i++) {
1522                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1523                                         continue;
1524
1525                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1526                                 pnv_ioda_free_pe(pe);
1527                         }
1528                 } else
1529                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1530                 /* Releasing pe_num_map */
1531                 kfree(pdn->pe_num_map);
1532         }
1533 }
1534
1535 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1536                                        struct pnv_ioda_pe *pe);
1537 #ifdef CONFIG_IOMMU_API
1538 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1539                 struct iommu_table_group *table_group, struct pci_bus *bus);
1540
1541 #endif
1542 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1543 {
1544         struct pci_bus        *bus;
1545         struct pci_controller *hose;
1546         struct pnv_phb        *phb;
1547         struct pnv_ioda_pe    *pe;
1548         int                    pe_num;
1549         u16                    vf_index;
1550         struct pci_dn         *pdn;
1551
1552         bus = pdev->bus;
1553         hose = pci_bus_to_host(bus);
1554         phb = hose->private_data;
1555         pdn = pci_get_pdn(pdev);
1556
1557         if (!pdev->is_physfn)
1558                 return;
1559
1560         /* Reserve PE for each VF */
1561         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1562                 if (pdn->m64_single_mode)
1563                         pe_num = pdn->pe_num_map[vf_index];
1564                 else
1565                         pe_num = *pdn->pe_num_map + vf_index;
1566
1567                 pe = &phb->ioda.pe_array[pe_num];
1568                 pe->pe_number = pe_num;
1569                 pe->phb = phb;
1570                 pe->flags = PNV_IODA_PE_VF;
1571                 pe->pbus = NULL;
1572                 pe->parent_dev = pdev;
1573                 pe->mve_number = -1;
1574                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1575                            pci_iov_virtfn_devfn(pdev, vf_index);
1576
1577                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1578                         hose->global_number, pdev->bus->number,
1579                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1580                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1581
1582                 if (pnv_ioda_configure_pe(phb, pe)) {
1583                         /* XXX What do we do here ? */
1584                         pnv_ioda_free_pe(pe);
1585                         pe->pdev = NULL;
1586                         continue;
1587                 }
1588
1589                 /* Put PE to the list */
1590                 mutex_lock(&phb->ioda.pe_list_mutex);
1591                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1592                 mutex_unlock(&phb->ioda.pe_list_mutex);
1593
1594                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1595 #ifdef CONFIG_IOMMU_API
1596                 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1597 #endif
1598         }
1599 }
1600
1601 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1602 {
1603         struct pci_bus        *bus;
1604         struct pci_controller *hose;
1605         struct pnv_phb        *phb;
1606         struct pnv_ioda_pe    *pe;
1607         struct pci_dn         *pdn;
1608         int                    ret;
1609         u16                    i;
1610
1611         bus = pdev->bus;
1612         hose = pci_bus_to_host(bus);
1613         phb = hose->private_data;
1614         pdn = pci_get_pdn(pdev);
1615
1616         if (phb->type == PNV_PHB_IODA2) {
1617                 if (!pdn->vfs_expanded) {
1618                         dev_info(&pdev->dev, "don't support this SRIOV device"
1619                                 " with non 64bit-prefetchable IOV BAR\n");
1620                         return -ENOSPC;
1621                 }
1622
1623                 /*
1624                  * When M64 BARs functions in Single PE mode, the number of VFs
1625                  * could be enabled must be less than the number of M64 BARs.
1626                  */
1627                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1628                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1629                         return -EBUSY;
1630                 }
1631
1632                 /* Allocating pe_num_map */
1633                 if (pdn->m64_single_mode)
1634                         pdn->pe_num_map = kmalloc_array(num_vfs,
1635                                                         sizeof(*pdn->pe_num_map),
1636                                                         GFP_KERNEL);
1637                 else
1638                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1639
1640                 if (!pdn->pe_num_map)
1641                         return -ENOMEM;
1642
1643                 if (pdn->m64_single_mode)
1644                         for (i = 0; i < num_vfs; i++)
1645                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1646
1647                 /* Calculate available PE for required VFs */
1648                 if (pdn->m64_single_mode) {
1649                         for (i = 0; i < num_vfs; i++) {
1650                                 pe = pnv_ioda_alloc_pe(phb);
1651                                 if (!pe) {
1652                                         ret = -EBUSY;
1653                                         goto m64_failed;
1654                                 }
1655
1656                                 pdn->pe_num_map[i] = pe->pe_number;
1657                         }
1658                 } else {
1659                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1660                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1661                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1662                                 0, num_vfs, 0);
1663                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1664                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1665                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1666                                 kfree(pdn->pe_num_map);
1667                                 return -EBUSY;
1668                         }
1669                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1670                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1671                 }
1672                 pdn->num_vfs = num_vfs;
1673
1674                 /* Assign M64 window accordingly */
1675                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1676                 if (ret) {
1677                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1678                         goto m64_failed;
1679                 }
1680
1681                 /*
1682                  * When using one M64 BAR to map one IOV BAR, we need to shift
1683                  * the IOV BAR according to the PE# allocated to the VFs.
1684                  * Otherwise, the PE# for the VF will conflict with others.
1685                  */
1686                 if (!pdn->m64_single_mode) {
1687                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1688                         if (ret)
1689                                 goto m64_failed;
1690                 }
1691         }
1692
1693         /* Setup VF PEs */
1694         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1695
1696         return 0;
1697
1698 m64_failed:
1699         if (pdn->m64_single_mode) {
1700                 for (i = 0; i < num_vfs; i++) {
1701                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1702                                 continue;
1703
1704                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1705                         pnv_ioda_free_pe(pe);
1706                 }
1707         } else
1708                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1709
1710         /* Releasing pe_num_map */
1711         kfree(pdn->pe_num_map);
1712
1713         return ret;
1714 }
1715
1716 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1717 {
1718         pnv_pci_sriov_disable(pdev);
1719
1720         /* Release PCI data */
1721         remove_dev_pci_data(pdev);
1722         return 0;
1723 }
1724
1725 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1726 {
1727         /* Allocate PCI data */
1728         add_dev_pci_data(pdev);
1729
1730         return pnv_pci_sriov_enable(pdev, num_vfs);
1731 }
1732 #endif /* CONFIG_PCI_IOV */
1733
1734 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1735 {
1736         struct pci_dn *pdn = pci_get_pdn(pdev);
1737         struct pnv_ioda_pe *pe;
1738
1739         /*
1740          * The function can be called while the PE#
1741          * hasn't been assigned. Do nothing for the
1742          * case.
1743          */
1744         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1745                 return;
1746
1747         pe = &phb->ioda.pe_array[pdn->pe_number];
1748         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1749         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1750         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1751         /*
1752          * Note: iommu_add_device() will fail here as
1753          * for physical PE: the device is already added by now;
1754          * for virtual PE: sysfs entries are not ready yet and
1755          * tce_iommu_bus_notifier will add the device to a group later.
1756          */
1757 }
1758
1759 /*
1760  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1761  *
1762  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1763  * Devices can only access more than that if bit 59 of the PCI address is set
1764  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1765  * Many PCI devices are not capable of addressing that many bits, and as a
1766  * result are limited to the 4GB of virtual memory made available to 32-bit
1767  * devices in TVE#0.
1768  *
1769  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1770  * devices by configuring the virtual memory past the first 4GB inaccessible
1771  * by 64-bit DMAs.  This should only be used by devices that want more than
1772  * 4GB, and only on PEs that have no 32-bit devices.
1773  *
1774  * Currently this will only work on PHB3 (POWER8).
1775  */
1776 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1777 {
1778         u64 window_size, table_size, tce_count, addr;
1779         struct page *table_pages;
1780         u64 tce_order = 28; /* 256MB TCEs */
1781         __be64 *tces;
1782         s64 rc;
1783
1784         /*
1785          * Window size needs to be a power of two, but needs to account for
1786          * shifting memory by the 4GB offset required to skip 32bit space.
1787          */
1788         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1789         tce_count = window_size >> tce_order;
1790         table_size = tce_count << 3;
1791
1792         if (table_size < PAGE_SIZE)
1793                 table_size = PAGE_SIZE;
1794
1795         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1796                                        get_order(table_size));
1797         if (!table_pages)
1798                 goto err;
1799
1800         tces = page_address(table_pages);
1801         if (!tces)
1802                 goto err;
1803
1804         memset(tces, 0, table_size);
1805
1806         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1807                 tces[(addr + (1ULL << 32)) >> tce_order] =
1808                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1809         }
1810
1811         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1812                                         pe->pe_number,
1813                                         /* reconfigure window 0 */
1814                                         (pe->pe_number << 1) + 0,
1815                                         1,
1816                                         __pa(tces),
1817                                         table_size,
1818                                         1 << tce_order);
1819         if (rc == OPAL_SUCCESS) {
1820                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1821                 return 0;
1822         }
1823 err:
1824         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1825         return -EIO;
1826 }
1827
1828 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1829 {
1830         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1831         struct pnv_phb *phb = hose->private_data;
1832         struct pci_dn *pdn = pci_get_pdn(pdev);
1833         struct pnv_ioda_pe *pe;
1834         uint64_t top;
1835         bool bypass = false;
1836         s64 rc;
1837
1838         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1839                 return -ENODEV;
1840
1841         pe = &phb->ioda.pe_array[pdn->pe_number];
1842         if (pe->tce_bypass_enabled) {
1843                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1844                 bypass = (dma_mask >= top);
1845         }
1846
1847         if (bypass) {
1848                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1849                 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1850         } else {
1851                 /*
1852                  * If the device can't set the TCE bypass bit but still wants
1853                  * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1854                  * bypass the 32-bit region and be usable for 64-bit DMAs.
1855                  * The device needs to be able to address all of this space.
1856                  */
1857                 if (dma_mask >> 32 &&
1858                     dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1859                     /* pe->pdev should be set if it's a single device, pe->pbus if not */
1860                     (pe->device_count == 1 || !pe->pbus) &&
1861                     phb->model == PNV_PHB_MODEL_PHB3) {
1862                         /* Configure the bypass mode */
1863                         rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1864                         if (rc)
1865                                 return rc;
1866                         /* 4GB offset bypasses 32-bit space */
1867                         set_dma_offset(&pdev->dev, (1ULL << 32));
1868                         set_dma_ops(&pdev->dev, &dma_nommu_ops);
1869                 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1870                         /*
1871                          * Fail the request if a DMA mask between 32 and 64 bits
1872                          * was requested but couldn't be fulfilled. Ideally we
1873                          * would do this for 64-bits but historically we have
1874                          * always fallen back to 32-bits.
1875                          */
1876                         return -ENOMEM;
1877                 } else {
1878                         dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1879                         set_dma_ops(&pdev->dev, &dma_iommu_ops);
1880                 }
1881         }
1882         *pdev->dev.dma_mask = dma_mask;
1883
1884         /* Update peer npu devices */
1885         pnv_npu_try_dma_set_bypass(pdev, bypass);
1886
1887         return 0;
1888 }
1889
1890 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1891 {
1892         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1893         struct pnv_phb *phb = hose->private_data;
1894         struct pci_dn *pdn = pci_get_pdn(pdev);
1895         struct pnv_ioda_pe *pe;
1896         u64 end, mask;
1897
1898         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1899                 return 0;
1900
1901         pe = &phb->ioda.pe_array[pdn->pe_number];
1902         if (!pe->tce_bypass_enabled)
1903                 return __dma_get_required_mask(&pdev->dev);
1904
1905
1906         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1907         mask = 1ULL << (fls64(end) - 1);
1908         mask += mask - 1;
1909
1910         return mask;
1911 }
1912
1913 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1914 {
1915         struct pci_dev *dev;
1916
1917         list_for_each_entry(dev, &bus->devices, bus_list) {
1918                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1919                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1920
1921                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1922                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1923         }
1924 }
1925
1926 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1927                                                      bool real_mode)
1928 {
1929         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1930                 (phb->regs + 0x210);
1931 }
1932
1933 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1934                 unsigned long index, unsigned long npages, bool rm)
1935 {
1936         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1937                         &tbl->it_group_list, struct iommu_table_group_link,
1938                         next);
1939         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1940                         struct pnv_ioda_pe, table_group);
1941         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1942         unsigned long start, end, inc;
1943
1944         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1945         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1946                         npages - 1);
1947
1948         /* p7ioc-style invalidation, 2 TCEs per write */
1949         start |= (1ull << 63);
1950         end |= (1ull << 63);
1951         inc = 16;
1952         end |= inc - 1; /* round up end to be different than start */
1953
1954         mb(); /* Ensure above stores are visible */
1955         while (start <= end) {
1956                 if (rm)
1957                         __raw_rm_writeq_be(start, invalidate);
1958                 else
1959                         __raw_writeq_be(start, invalidate);
1960
1961                 start += inc;
1962         }
1963
1964         /*
1965          * The iommu layer will do another mb() for us on build()
1966          * and we don't care on free()
1967          */
1968 }
1969
1970 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1971                 long npages, unsigned long uaddr,
1972                 enum dma_data_direction direction,
1973                 unsigned long attrs)
1974 {
1975         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1976                         attrs);
1977
1978         if (!ret)
1979                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1980
1981         return ret;
1982 }
1983
1984 #ifdef CONFIG_IOMMU_API
1985 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1986                 unsigned long *hpa, enum dma_data_direction *direction)
1987 {
1988         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
1989
1990         if (!ret)
1991                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1992
1993         return ret;
1994 }
1995
1996 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1997                 unsigned long *hpa, enum dma_data_direction *direction)
1998 {
1999         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2000
2001         if (!ret)
2002                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2003
2004         return ret;
2005 }
2006 #endif
2007
2008 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2009                 long npages)
2010 {
2011         pnv_tce_free(tbl, index, npages);
2012
2013         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2014 }
2015
2016 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2017         .set = pnv_ioda1_tce_build,
2018 #ifdef CONFIG_IOMMU_API
2019         .exchange = pnv_ioda1_tce_xchg,
2020         .exchange_rm = pnv_ioda1_tce_xchg_rm,
2021         .useraddrptr = pnv_tce_useraddrptr,
2022 #endif
2023         .clear = pnv_ioda1_tce_free,
2024         .get = pnv_tce_get,
2025 };
2026
2027 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
2028 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
2029 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
2030
2031 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2032 {
2033         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2034         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2035
2036         mb(); /* Ensure previous TCE table stores are visible */
2037         if (rm)
2038                 __raw_rm_writeq_be(val, invalidate);
2039         else
2040                 __raw_writeq_be(val, invalidate);
2041 }
2042
2043 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2044 {
2045         /* 01xb - invalidate TCEs that match the specified PE# */
2046         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2047         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2048
2049         mb(); /* Ensure above stores are visible */
2050         __raw_writeq_be(val, invalidate);
2051 }
2052
2053 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2054                                         unsigned shift, unsigned long index,
2055                                         unsigned long npages)
2056 {
2057         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2058         unsigned long start, end, inc;
2059
2060         /* We'll invalidate DMA address in PE scope */
2061         start = PHB3_TCE_KILL_INVAL_ONE;
2062         start |= (pe->pe_number & 0xFF);
2063         end = start;
2064
2065         /* Figure out the start, end and step */
2066         start |= (index << shift);
2067         end |= ((index + npages - 1) << shift);
2068         inc = (0x1ull << shift);
2069         mb();
2070
2071         while (start <= end) {
2072                 if (rm)
2073                         __raw_rm_writeq_be(start, invalidate);
2074                 else
2075                         __raw_writeq_be(start, invalidate);
2076                 start += inc;
2077         }
2078 }
2079
2080 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2081 {
2082         struct pnv_phb *phb = pe->phb;
2083
2084         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2085                 pnv_pci_phb3_tce_invalidate_pe(pe);
2086         else
2087                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2088                                   pe->pe_number, 0, 0, 0);
2089 }
2090
2091 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2092                 unsigned long index, unsigned long npages, bool rm)
2093 {
2094         struct iommu_table_group_link *tgl;
2095
2096         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2097                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2098                                 struct pnv_ioda_pe, table_group);
2099                 struct pnv_phb *phb = pe->phb;
2100                 unsigned int shift = tbl->it_page_shift;
2101
2102                 /*
2103                  * NVLink1 can use the TCE kill register directly as
2104                  * it's the same as PHB3. NVLink2 is different and
2105                  * should go via the OPAL call.
2106                  */
2107                 if (phb->model == PNV_PHB_MODEL_NPU) {
2108                         /*
2109                          * The NVLink hardware does not support TCE kill
2110                          * per TCE entry so we have to invalidate
2111                          * the entire cache for it.
2112                          */
2113                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2114                         continue;
2115                 }
2116                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2117                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2118                                                     index, npages);
2119                 else
2120                         opal_pci_tce_kill(phb->opal_id,
2121                                           OPAL_PCI_TCE_KILL_PAGES,
2122                                           pe->pe_number, 1u << shift,
2123                                           index << shift, npages);
2124         }
2125 }
2126
2127 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2128 {
2129         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2130                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2131         else
2132                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2133 }
2134
2135 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2136                 long npages, unsigned long uaddr,
2137                 enum dma_data_direction direction,
2138                 unsigned long attrs)
2139 {
2140         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2141                         attrs);
2142
2143         if (!ret)
2144                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2145
2146         return ret;
2147 }
2148
2149 #ifdef CONFIG_IOMMU_API
2150 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2151                 unsigned long *hpa, enum dma_data_direction *direction)
2152 {
2153         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2154
2155         if (!ret)
2156                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2157
2158         return ret;
2159 }
2160
2161 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2162                 unsigned long *hpa, enum dma_data_direction *direction)
2163 {
2164         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2165
2166         if (!ret)
2167                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2168
2169         return ret;
2170 }
2171 #endif
2172
2173 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2174                 long npages)
2175 {
2176         pnv_tce_free(tbl, index, npages);
2177
2178         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2179 }
2180
2181 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2182         .set = pnv_ioda2_tce_build,
2183 #ifdef CONFIG_IOMMU_API
2184         .exchange = pnv_ioda2_tce_xchg,
2185         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2186         .useraddrptr = pnv_tce_useraddrptr,
2187 #endif
2188         .clear = pnv_ioda2_tce_free,
2189         .get = pnv_tce_get,
2190         .free = pnv_pci_ioda2_table_free_pages,
2191 };
2192
2193 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2194 {
2195         unsigned int *weight = (unsigned int *)data;
2196
2197         /* This is quite simplistic. The "base" weight of a device
2198          * is 10. 0 means no DMA is to be accounted for it.
2199          */
2200         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2201                 return 0;
2202
2203         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2204             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2205             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2206                 *weight += 3;
2207         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2208                 *weight += 15;
2209         else
2210                 *weight += 10;
2211
2212         return 0;
2213 }
2214
2215 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2216 {
2217         unsigned int weight = 0;
2218
2219         /* SRIOV VF has same DMA32 weight as its PF */
2220 #ifdef CONFIG_PCI_IOV
2221         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2222                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2223                 return weight;
2224         }
2225 #endif
2226
2227         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2228                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2229         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2230                 struct pci_dev *pdev;
2231
2232                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2233                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2234         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2235                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2236         }
2237
2238         return weight;
2239 }
2240
2241 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2242                                        struct pnv_ioda_pe *pe)
2243 {
2244
2245         struct page *tce_mem = NULL;
2246         struct iommu_table *tbl;
2247         unsigned int weight, total_weight = 0;
2248         unsigned int tce32_segsz, base, segs, avail, i;
2249         int64_t rc;
2250         void *addr;
2251
2252         /* XXX FIXME: Handle 64-bit only DMA devices */
2253         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2254         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2255         weight = pnv_pci_ioda_pe_dma_weight(pe);
2256         if (!weight)
2257                 return;
2258
2259         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2260                      &total_weight);
2261         segs = (weight * phb->ioda.dma32_count) / total_weight;
2262         if (!segs)
2263                 segs = 1;
2264
2265         /*
2266          * Allocate contiguous DMA32 segments. We begin with the expected
2267          * number of segments. With one more attempt, the number of DMA32
2268          * segments to be allocated is decreased by one until one segment
2269          * is allocated successfully.
2270          */
2271         do {
2272                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2273                         for (avail = 0, i = base; i < base + segs; i++) {
2274                                 if (phb->ioda.dma32_segmap[i] ==
2275                                     IODA_INVALID_PE)
2276                                         avail++;
2277                         }
2278
2279                         if (avail == segs)
2280                                 goto found;
2281                 }
2282         } while (--segs);
2283
2284         if (!segs) {
2285                 pe_warn(pe, "No available DMA32 segments\n");
2286                 return;
2287         }
2288
2289 found:
2290         tbl = pnv_pci_table_alloc(phb->hose->node);
2291         if (WARN_ON(!tbl))
2292                 return;
2293
2294         iommu_register_group(&pe->table_group, phb->hose->global_number,
2295                         pe->pe_number);
2296         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2297
2298         /* Grab a 32-bit TCE table */
2299         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2300                 weight, total_weight, base, segs);
2301         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2302                 base * PNV_IODA1_DMA32_SEGSIZE,
2303                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2304
2305         /* XXX Currently, we allocate one big contiguous table for the
2306          * TCEs. We only really need one chunk per 256M of TCE space
2307          * (ie per segment) but that's an optimization for later, it
2308          * requires some added smarts with our get/put_tce implementation
2309          *
2310          * Each TCE page is 4KB in size and each TCE entry occupies 8
2311          * bytes
2312          */
2313         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2314         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2315                                    get_order(tce32_segsz * segs));
2316         if (!tce_mem) {
2317                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2318                 goto fail;
2319         }
2320         addr = page_address(tce_mem);
2321         memset(addr, 0, tce32_segsz * segs);
2322
2323         /* Configure HW */
2324         for (i = 0; i < segs; i++) {
2325                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2326                                               pe->pe_number,
2327                                               base + i, 1,
2328                                               __pa(addr) + tce32_segsz * i,
2329                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2330                 if (rc) {
2331                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2332                                " err %ld\n", rc);
2333                         goto fail;
2334                 }
2335         }
2336
2337         /* Setup DMA32 segment mapping */
2338         for (i = base; i < base + segs; i++)
2339                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2340
2341         /* Setup linux iommu table */
2342         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2343                                   base * PNV_IODA1_DMA32_SEGSIZE,
2344                                   IOMMU_PAGE_SHIFT_4K);
2345
2346         tbl->it_ops = &pnv_ioda1_iommu_ops;
2347         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2348         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2349         iommu_init_table(tbl, phb->hose->node);
2350
2351         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2352                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2353
2354         return;
2355  fail:
2356         /* XXX Failure: Try to fallback to 64-bit only ? */
2357         if (tce_mem)
2358                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2359         if (tbl) {
2360                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2361                 iommu_tce_table_put(tbl);
2362         }
2363 }
2364
2365 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2366                 int num, struct iommu_table *tbl)
2367 {
2368         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2369                         table_group);
2370         struct pnv_phb *phb = pe->phb;
2371         int64_t rc;
2372         const unsigned long size = tbl->it_indirect_levels ?
2373                         tbl->it_level_size : tbl->it_size;
2374         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2375         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2376
2377         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2378                         start_addr, start_addr + win_size - 1,
2379                         IOMMU_PAGE_SIZE(tbl));
2380
2381         /*
2382          * Map TCE table through TVT. The TVE index is the PE number
2383          * shifted by 1 bit for 32-bits DMA space.
2384          */
2385         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2386                         pe->pe_number,
2387                         (pe->pe_number << 1) + num,
2388                         tbl->it_indirect_levels + 1,
2389                         __pa(tbl->it_base),
2390                         size << 3,
2391                         IOMMU_PAGE_SIZE(tbl));
2392         if (rc) {
2393                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2394                 return rc;
2395         }
2396
2397         pnv_pci_link_table_and_group(phb->hose->node, num,
2398                         tbl, &pe->table_group);
2399         pnv_pci_ioda2_tce_invalidate_pe(pe);
2400
2401         return 0;
2402 }
2403
2404 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2405 {
2406         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2407         int64_t rc;
2408
2409         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2410         if (enable) {
2411                 phys_addr_t top = memblock_end_of_DRAM();
2412
2413                 top = roundup_pow_of_two(top);
2414                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2415                                                      pe->pe_number,
2416                                                      window_id,
2417                                                      pe->tce_bypass_base,
2418                                                      top);
2419         } else {
2420                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2421                                                      pe->pe_number,
2422                                                      window_id,
2423                                                      pe->tce_bypass_base,
2424                                                      0);
2425         }
2426         if (rc)
2427                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2428         else
2429                 pe->tce_bypass_enabled = enable;
2430 }
2431
2432 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2433                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2434                 bool alloc_userspace_copy, struct iommu_table **ptbl)
2435 {
2436         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2437                         table_group);
2438         int nid = pe->phb->hose->node;
2439         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2440         long ret;
2441         struct iommu_table *tbl;
2442
2443         tbl = pnv_pci_table_alloc(nid);
2444         if (!tbl)
2445                 return -ENOMEM;
2446
2447         tbl->it_ops = &pnv_ioda2_iommu_ops;
2448
2449         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2450                         bus_offset, page_shift, window_size,
2451                         levels, alloc_userspace_copy, tbl);
2452         if (ret) {
2453                 iommu_tce_table_put(tbl);
2454                 return ret;
2455         }
2456
2457         *ptbl = tbl;
2458
2459         return 0;
2460 }
2461
2462 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2463 {
2464         struct iommu_table *tbl = NULL;
2465         long rc;
2466
2467         /*
2468          * crashkernel= specifies the kdump kernel's maximum memory at
2469          * some offset and there is no guaranteed the result is a power
2470          * of 2, which will cause errors later.
2471          */
2472         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2473
2474         /*
2475          * In memory constrained environments, e.g. kdump kernel, the
2476          * DMA window can be larger than available memory, which will
2477          * cause errors later.
2478          */
2479         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2480
2481         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2482                         IOMMU_PAGE_SHIFT_4K,
2483                         window_size,
2484                         POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2485         if (rc) {
2486                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2487                                 rc);
2488                 return rc;
2489         }
2490
2491         iommu_init_table(tbl, pe->phb->hose->node);
2492
2493         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2494         if (rc) {
2495                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2496                                 rc);
2497                 iommu_tce_table_put(tbl);
2498                 return rc;
2499         }
2500
2501         if (!pnv_iommu_bypass_disabled)
2502                 pnv_pci_ioda2_set_bypass(pe, true);
2503
2504         return 0;
2505 }
2506
2507 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2508 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2509                 int num)
2510 {
2511         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2512                         table_group);
2513         struct pnv_phb *phb = pe->phb;
2514         long ret;
2515
2516         pe_info(pe, "Removing DMA window #%d\n", num);
2517
2518         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2519                         (pe->pe_number << 1) + num,
2520                         0/* levels */, 0/* table address */,
2521                         0/* table size */, 0/* page size */);
2522         if (ret)
2523                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2524         else
2525                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2526
2527         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2528
2529         return ret;
2530 }
2531 #endif
2532
2533 #ifdef CONFIG_IOMMU_API
2534 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2535                 __u64 window_size, __u32 levels)
2536 {
2537         unsigned long bytes = 0;
2538         const unsigned window_shift = ilog2(window_size);
2539         unsigned entries_shift = window_shift - page_shift;
2540         unsigned table_shift = entries_shift + 3;
2541         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2542         unsigned long direct_table_size;
2543
2544         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2545                         !is_power_of_2(window_size))
2546                 return 0;
2547
2548         /* Calculate a direct table size from window_size and levels */
2549         entries_shift = (entries_shift + levels - 1) / levels;
2550         table_shift = entries_shift + 3;
2551         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2552         direct_table_size =  1UL << table_shift;
2553
2554         for ( ; levels; --levels) {
2555                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2556
2557                 tce_table_size /= direct_table_size;
2558                 tce_table_size <<= 3;
2559                 tce_table_size = max_t(unsigned long,
2560                                 tce_table_size, direct_table_size);
2561         }
2562
2563         return bytes + bytes; /* one for HW table, one for userspace copy */
2564 }
2565
2566 static long pnv_pci_ioda2_create_table_userspace(
2567                 struct iommu_table_group *table_group,
2568                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2569                 struct iommu_table **ptbl)
2570 {
2571         return pnv_pci_ioda2_create_table(table_group,
2572                         num, page_shift, window_size, levels, true, ptbl);
2573 }
2574
2575 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2576 {
2577         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2578                                                 table_group);
2579         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2580         struct iommu_table *tbl = pe->table_group.tables[0];
2581
2582         pnv_pci_ioda2_set_bypass(pe, false);
2583         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2584         if (pe->pbus)
2585                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2586         iommu_tce_table_put(tbl);
2587 }
2588
2589 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2590 {
2591         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2592                                                 table_group);
2593
2594         pnv_pci_ioda2_setup_default_config(pe);
2595         if (pe->pbus)
2596                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2597 }
2598
2599 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2600         .get_table_size = pnv_pci_ioda2_get_table_size,
2601         .create_table = pnv_pci_ioda2_create_table_userspace,
2602         .set_window = pnv_pci_ioda2_set_window,
2603         .unset_window = pnv_pci_ioda2_unset_window,
2604         .take_ownership = pnv_ioda2_take_ownership,
2605         .release_ownership = pnv_ioda2_release_ownership,
2606 };
2607
2608 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2609                 struct iommu_table_group *table_group,
2610                 struct pci_bus *bus)
2611 {
2612         struct pci_dev *dev;
2613
2614         list_for_each_entry(dev, &bus->devices, bus_list) {
2615                 iommu_add_device(table_group, &dev->dev);
2616
2617                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2618                         pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2619                                         table_group, dev->subordinate);
2620         }
2621 }
2622
2623 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2624                 struct iommu_table_group *table_group, struct pci_bus *bus)
2625 {
2626
2627         if (pe->flags & PNV_IODA_PE_DEV)
2628                 iommu_add_device(table_group, &pe->pdev->dev);
2629
2630         if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2631                 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2632                                 bus);
2633 }
2634
2635 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2636
2637 static void pnv_pci_ioda_setup_iommu_api(void)
2638 {
2639         struct pci_controller *hose;
2640         struct pnv_phb *phb;
2641         struct pnv_ioda_pe *pe;
2642
2643         /*
2644          * There are 4 types of PEs:
2645          * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2646          *   created from pnv_pci_setup_bridge();
2647          * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2648          *   created from pnv_pci_setup_bridge();
2649          * - PNV_IODA_PE_VF: a SRIOV virtual function,
2650          *   created from pnv_pcibios_sriov_enable();
2651          * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2652          *   created from pnv_pci_ioda_fixup().
2653          *
2654          * Normally a PE is represented by an IOMMU group, however for
2655          * devices with side channels the groups need to be more strict.
2656          */
2657         list_for_each_entry(hose, &hose_list, list_node) {
2658                 phb = hose->private_data;
2659
2660                 if (phb->type == PNV_PHB_NPU_NVLINK)
2661                         continue;
2662
2663                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2664                         struct iommu_table_group *table_group;
2665
2666                         table_group = pnv_try_setup_npu_table_group(pe);
2667                         if (!table_group) {
2668                                 if (!pnv_pci_ioda_pe_dma_weight(pe))
2669                                         continue;
2670
2671                                 table_group = &pe->table_group;
2672                                 iommu_register_group(&pe->table_group,
2673                                                 pe->phb->hose->global_number,
2674                                                 pe->pe_number);
2675                         }
2676                         pnv_ioda_setup_bus_iommu_group(pe, table_group,
2677                                         pe->pbus);
2678                 }
2679         }
2680
2681         /*
2682          * Now we have all PHBs discovered, time to add NPU devices to
2683          * the corresponding IOMMU groups.
2684          */
2685         list_for_each_entry(hose, &hose_list, list_node) {
2686                 unsigned long  pgsizes;
2687
2688                 phb = hose->private_data;
2689
2690                 if (phb->type != PNV_PHB_NPU_NVLINK)
2691                         continue;
2692
2693                 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2694                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2695                         /*
2696                          * IODA2 bridges get this set up from
2697                          * pci_controller_ops::setup_bridge but NPU bridges
2698                          * do not have this hook defined so we do it here.
2699                          */
2700                         pe->table_group.pgsizes = pgsizes;
2701                         pnv_npu_compound_attach(pe);
2702                 }
2703         }
2704 }
2705 #else /* !CONFIG_IOMMU_API */
2706 static void pnv_pci_ioda_setup_iommu_api(void) { };
2707 #endif
2708
2709 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2710 {
2711         struct pci_controller *hose = phb->hose;
2712         struct device_node *dn = hose->dn;
2713         unsigned long mask = 0;
2714         int i, rc, count;
2715         u32 val;
2716
2717         count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2718         if (count <= 0) {
2719                 mask = SZ_4K | SZ_64K;
2720                 /* Add 16M for POWER8 by default */
2721                 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2722                                 !cpu_has_feature(CPU_FTR_ARCH_300))
2723                         mask |= SZ_16M | SZ_256M;
2724                 return mask;
2725         }
2726
2727         for (i = 0; i < count; i++) {
2728                 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2729                                                 i, &val);
2730                 if (rc == 0)
2731                         mask |= 1ULL << val;
2732         }
2733
2734         return mask;
2735 }
2736
2737 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2738                                        struct pnv_ioda_pe *pe)
2739 {
2740         int64_t rc;
2741
2742         if (!pnv_pci_ioda_pe_dma_weight(pe))
2743                 return;
2744
2745         /* TVE #1 is selected by PCI address bit 59 */
2746         pe->tce_bypass_base = 1ull << 59;
2747
2748         /* The PE will reserve all possible 32-bits space */
2749         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2750                 phb->ioda.m32_pci_base);
2751
2752         /* Setup linux iommu table */
2753         pe->table_group.tce32_start = 0;
2754         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2755         pe->table_group.max_dynamic_windows_supported =
2756                         IOMMU_TABLE_GROUP_MAX_TABLES;
2757         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2758         pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2759 #ifdef CONFIG_IOMMU_API
2760         pe->table_group.ops = &pnv_pci_ioda2_ops;
2761 #endif
2762
2763         rc = pnv_pci_ioda2_setup_default_config(pe);
2764         if (rc)
2765                 return;
2766
2767         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2768                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2769 }
2770
2771 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2772 {
2773         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2774                                            ioda.irq_chip);
2775
2776         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2777 }
2778
2779 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2780 {
2781         int64_t rc;
2782         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2783         struct irq_chip *chip = irq_data_get_irq_chip(d);
2784
2785         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2786         WARN_ON_ONCE(rc);
2787
2788         icp_native_eoi(d);
2789 }
2790
2791
2792 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2793 {
2794         struct irq_data *idata;
2795         struct irq_chip *ichip;
2796
2797         /* The MSI EOI OPAL call is only needed on PHB3 */
2798         if (phb->model != PNV_PHB_MODEL_PHB3)
2799                 return;
2800
2801         if (!phb->ioda.irq_chip_init) {
2802                 /*
2803                  * First time we setup an MSI IRQ, we need to setup the
2804                  * corresponding IRQ chip to route correctly.
2805                  */
2806                 idata = irq_get_irq_data(virq);
2807                 ichip = irq_data_get_irq_chip(idata);
2808                 phb->ioda.irq_chip_init = 1;
2809                 phb->ioda.irq_chip = *ichip;
2810                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2811         }
2812         irq_set_chip(virq, &phb->ioda.irq_chip);
2813 }
2814
2815 /*
2816  * Returns true iff chip is something that we could call
2817  * pnv_opal_pci_msi_eoi for.
2818  */
2819 bool is_pnv_opal_msi(struct irq_chip *chip)
2820 {
2821         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2822 }
2823 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2824
2825 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2826                                   unsigned int hwirq, unsigned int virq,
2827                                   unsigned int is_64, struct msi_msg *msg)
2828 {
2829         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2830         unsigned int xive_num = hwirq - phb->msi_base;
2831         __be32 data;
2832         int rc;
2833
2834         /* No PE assigned ? bail out ... no MSI for you ! */
2835         if (pe == NULL)
2836                 return -ENXIO;
2837
2838         /* Check if we have an MVE */
2839         if (pe->mve_number < 0)
2840                 return -ENXIO;
2841
2842         /* Force 32-bit MSI on some broken devices */
2843         if (dev->no_64bit_msi)
2844                 is_64 = 0;
2845
2846         /* Assign XIVE to PE */
2847         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2848         if (rc) {
2849                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2850                         pci_name(dev), rc, xive_num);
2851                 return -EIO;
2852         }
2853
2854         if (is_64) {
2855                 __be64 addr64;
2856
2857                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2858                                      &addr64, &data);
2859                 if (rc) {
2860                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2861                                 pci_name(dev), rc);
2862                         return -EIO;
2863                 }
2864                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2865                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2866         } else {
2867                 __be32 addr32;
2868
2869                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2870                                      &addr32, &data);
2871                 if (rc) {
2872                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2873                                 pci_name(dev), rc);
2874                         return -EIO;
2875                 }
2876                 msg->address_hi = 0;
2877                 msg->address_lo = be32_to_cpu(addr32);
2878         }
2879         msg->data = be32_to_cpu(data);
2880
2881         pnv_set_msi_irq_chip(phb, virq);
2882
2883         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2884                  " address=%x_%08x data=%x PE# %x\n",
2885                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2886                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2887
2888         return 0;
2889 }
2890
2891 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2892 {
2893         unsigned int count;
2894         const __be32 *prop = of_get_property(phb->hose->dn,
2895                                              "ibm,opal-msi-ranges", NULL);
2896         if (!prop) {
2897                 /* BML Fallback */
2898                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2899         }
2900         if (!prop)
2901                 return;
2902
2903         phb->msi_base = be32_to_cpup(prop);
2904         count = be32_to_cpup(prop + 1);
2905         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2906                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2907                        phb->hose->global_number);
2908                 return;
2909         }
2910
2911         phb->msi_setup = pnv_pci_ioda_msi_setup;
2912         phb->msi32_support = 1;
2913         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2914                 count, phb->msi_base);
2915 }
2916
2917 #ifdef CONFIG_PCI_IOV
2918 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2919 {
2920         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2921         struct pnv_phb *phb = hose->private_data;
2922         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2923         struct resource *res;
2924         int i;
2925         resource_size_t size, total_vf_bar_sz;
2926         struct pci_dn *pdn;
2927         int mul, total_vfs;
2928
2929         if (!pdev->is_physfn || pci_dev_is_added(pdev))
2930                 return;
2931
2932         pdn = pci_get_pdn(pdev);
2933         pdn->vfs_expanded = 0;
2934         pdn->m64_single_mode = false;
2935
2936         total_vfs = pci_sriov_get_totalvfs(pdev);
2937         mul = phb->ioda.total_pe_num;
2938         total_vf_bar_sz = 0;
2939
2940         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2941                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2942                 if (!res->flags || res->parent)
2943                         continue;
2944                 if (!pnv_pci_is_m64_flags(res->flags)) {
2945                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2946                                         " non M64 VF BAR%d: %pR. \n",
2947                                  i, res);
2948                         goto truncate_iov;
2949                 }
2950
2951                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2952                                 i + PCI_IOV_RESOURCES);
2953
2954                 /*
2955                  * If bigger than quarter of M64 segment size, just round up
2956                  * power of two.
2957                  *
2958                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2959                  * with other devices, IOV BAR size is expanded to be
2960                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2961                  * segment size , the expanded size would equal to half of the
2962                  * whole M64 space size, which will exhaust the M64 Space and
2963                  * limit the system flexibility.  This is a design decision to
2964                  * set the boundary to quarter of the M64 segment size.
2965                  */
2966                 if (total_vf_bar_sz > gate) {
2967                         mul = roundup_pow_of_two(total_vfs);
2968                         dev_info(&pdev->dev,
2969                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2970                                 total_vf_bar_sz, gate, mul);
2971                         pdn->m64_single_mode = true;
2972                         break;
2973                 }
2974         }
2975
2976         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2977                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2978                 if (!res->flags || res->parent)
2979                         continue;
2980
2981                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2982                 /*
2983                  * On PHB3, the minimum size alignment of M64 BAR in single
2984                  * mode is 32MB.
2985                  */
2986                 if (pdn->m64_single_mode && (size < SZ_32M))
2987                         goto truncate_iov;
2988                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2989                 res->end = res->start + size * mul - 1;
2990                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2991                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2992                          i, res, mul);
2993         }
2994         pdn->vfs_expanded = mul;
2995
2996         return;
2997
2998 truncate_iov:
2999         /* To save MMIO space, IOV BAR is truncated. */
3000         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3001                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3002                 res->flags = 0;
3003                 res->end = res->start - 1;
3004         }
3005 }
3006 #endif /* CONFIG_PCI_IOV */
3007
3008 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3009                                   struct resource *res)
3010 {
3011         struct pnv_phb *phb = pe->phb;
3012         struct pci_bus_region region;
3013         int index;
3014         int64_t rc;
3015
3016         if (!res || !res->flags || res->start > res->end)
3017                 return;
3018
3019         if (res->flags & IORESOURCE_IO) {
3020                 region.start = res->start - phb->ioda.io_pci_base;
3021                 region.end   = res->end - phb->ioda.io_pci_base;
3022                 index = region.start / phb->ioda.io_segsize;
3023
3024                 while (index < phb->ioda.total_pe_num &&
3025                        region.start <= region.end) {
3026                         phb->ioda.io_segmap[index] = pe->pe_number;
3027                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3028                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3029                         if (rc != OPAL_SUCCESS) {
3030                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3031                                        __func__, rc, index, pe->pe_number);
3032                                 break;
3033                         }
3034
3035                         region.start += phb->ioda.io_segsize;
3036                         index++;
3037                 }
3038         } else if ((res->flags & IORESOURCE_MEM) &&
3039                    !pnv_pci_is_m64(phb, res)) {
3040                 region.start = res->start -
3041                                phb->hose->mem_offset[0] -
3042                                phb->ioda.m32_pci_base;
3043                 region.end   = res->end -
3044                                phb->hose->mem_offset[0] -
3045                                phb->ioda.m32_pci_base;
3046                 index = region.start / phb->ioda.m32_segsize;
3047
3048                 while (index < phb->ioda.total_pe_num &&
3049                        region.start <= region.end) {
3050                         phb->ioda.m32_segmap[index] = pe->pe_number;
3051                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3052                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3053                         if (rc != OPAL_SUCCESS) {
3054                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3055                                        __func__, rc, index, pe->pe_number);
3056                                 break;
3057                         }
3058
3059                         region.start += phb->ioda.m32_segsize;
3060                         index++;
3061                 }
3062         }
3063 }
3064
3065 /*
3066  * This function is supposed to be called on basis of PE from top
3067  * to bottom style. So the the I/O or MMIO segment assigned to
3068  * parent PE could be overridden by its child PEs if necessary.
3069  */
3070 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3071 {
3072         struct pci_dev *pdev;
3073         int i;
3074
3075         /*
3076          * NOTE: We only care PCI bus based PE for now. For PCI
3077          * device based PE, for example SRIOV sensitive VF should
3078          * be figured out later.
3079          */
3080         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3081
3082         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3083                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3084                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3085
3086                 /*
3087                  * If the PE contains all subordinate PCI buses, the
3088                  * windows of the child bridges should be mapped to
3089                  * the PE as well.
3090                  */
3091                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3092                         continue;
3093                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3094                         pnv_ioda_setup_pe_res(pe,
3095                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3096         }
3097 }
3098
3099 #ifdef CONFIG_DEBUG_FS
3100 static int pnv_pci_diag_data_set(void *data, u64 val)
3101 {
3102         struct pci_controller *hose;
3103         struct pnv_phb *phb;
3104         s64 ret;
3105
3106         if (val != 1ULL)
3107                 return -EINVAL;
3108
3109         hose = (struct pci_controller *)data;
3110         if (!hose || !hose->private_data)
3111                 return -ENODEV;
3112
3113         phb = hose->private_data;
3114
3115         /* Retrieve the diag data from firmware */
3116         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3117                                           phb->diag_data_size);
3118         if (ret != OPAL_SUCCESS)
3119                 return -EIO;
3120
3121         /* Print the diag data to the kernel log */
3122         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3123         return 0;
3124 }
3125
3126 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3127                         pnv_pci_diag_data_set, "%llu\n");
3128
3129 #endif /* CONFIG_DEBUG_FS */
3130
3131 static void pnv_pci_ioda_create_dbgfs(void)
3132 {
3133 #ifdef CONFIG_DEBUG_FS
3134         struct pci_controller *hose, *tmp;
3135         struct pnv_phb *phb;
3136         char name[16];
3137
3138         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3139                 phb = hose->private_data;
3140
3141                 /* Notify initialization of PHB done */
3142                 phb->initialized = 1;
3143
3144                 sprintf(name, "PCI%04x", hose->global_number);
3145                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3146                 if (!phb->dbgfs) {
3147                         pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3148                                 __func__, hose->global_number);
3149                         continue;
3150                 }
3151
3152                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3153                                     &pnv_pci_diag_data_fops);
3154         }
3155 #endif /* CONFIG_DEBUG_FS */
3156 }
3157
3158 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3159 {
3160         struct pci_dev *dev = bus->self;
3161         struct pci_bus *child;
3162
3163         /* Empty bus ? bail */
3164         if (list_empty(&bus->devices))
3165                 return;
3166
3167         /*
3168          * If there's a bridge associated with that bus enable it. This works
3169          * around races in the generic code if the enabling is done during
3170          * parallel probing. This can be removed once those races have been
3171          * fixed.
3172          */
3173         if (dev) {
3174                 int rc = pci_enable_device(dev);
3175                 if (rc)
3176                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3177                 pci_set_master(dev);
3178         }
3179
3180         /* Perform the same to child busses */
3181         list_for_each_entry(child, &bus->children, node)
3182                 pnv_pci_enable_bridge(child);
3183 }
3184
3185 static void pnv_pci_enable_bridges(void)
3186 {
3187         struct pci_controller *hose;
3188
3189         list_for_each_entry(hose, &hose_list, list_node)
3190                 pnv_pci_enable_bridge(hose->bus);
3191 }
3192
3193 static void pnv_pci_ioda_fixup(void)
3194 {
3195         pnv_pci_ioda_setup_PEs();
3196         pnv_pci_ioda_setup_iommu_api();
3197         pnv_pci_ioda_create_dbgfs();
3198
3199         pnv_pci_enable_bridges();
3200
3201 #ifdef CONFIG_EEH
3202         pnv_eeh_post_init();
3203 #endif
3204 }
3205
3206 /*
3207  * Returns the alignment for I/O or memory windows for P2P
3208  * bridges. That actually depends on how PEs are segmented.
3209  * For now, we return I/O or M32 segment size for PE sensitive
3210  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3211  * 1MiB for memory) will be returned.
3212  *
3213  * The current PCI bus might be put into one PE, which was
3214  * create against the parent PCI bridge. For that case, we
3215  * needn't enlarge the alignment so that we can save some
3216  * resources.
3217  */
3218 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3219                                                 unsigned long type)
3220 {
3221         struct pci_dev *bridge;
3222         struct pci_controller *hose = pci_bus_to_host(bus);
3223         struct pnv_phb *phb = hose->private_data;
3224         int num_pci_bridges = 0;
3225
3226         bridge = bus->self;
3227         while (bridge) {
3228                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3229                         num_pci_bridges++;
3230                         if (num_pci_bridges >= 2)
3231                                 return 1;
3232                 }
3233
3234                 bridge = bridge->bus->self;
3235         }
3236
3237         /*
3238          * We fall back to M32 if M64 isn't supported. We enforce the M64
3239          * alignment for any 64-bit resource, PCIe doesn't care and
3240          * bridges only do 64-bit prefetchable anyway.
3241          */
3242         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3243                 return phb->ioda.m64_segsize;
3244         if (type & IORESOURCE_MEM)
3245                 return phb->ioda.m32_segsize;
3246
3247         return phb->ioda.io_segsize;
3248 }
3249
3250 /*
3251  * We are updating root port or the upstream port of the
3252  * bridge behind the root port with PHB's windows in order
3253  * to accommodate the changes on required resources during
3254  * PCI (slot) hotplug, which is connected to either root
3255  * port or the downstream ports of PCIe switch behind the
3256  * root port.
3257  */
3258 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3259                                            unsigned long type)
3260 {
3261         struct pci_controller *hose = pci_bus_to_host(bus);
3262         struct pnv_phb *phb = hose->private_data;
3263         struct pci_dev *bridge = bus->self;
3264         struct resource *r, *w;
3265         bool msi_region = false;
3266         int i;
3267
3268         /* Check if we need apply fixup to the bridge's windows */
3269         if (!pci_is_root_bus(bridge->bus) &&
3270             !pci_is_root_bus(bridge->bus->self->bus))
3271                 return;
3272
3273         /* Fixup the resources */
3274         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3275                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3276                 if (!r->flags || !r->parent)
3277                         continue;
3278
3279                 w = NULL;
3280                 if (r->flags & type & IORESOURCE_IO)
3281                         w = &hose->io_resource;
3282                 else if (pnv_pci_is_m64(phb, r) &&
3283                          (type & IORESOURCE_PREFETCH) &&
3284                          phb->ioda.m64_segsize)
3285                         w = &hose->mem_resources[1];
3286                 else if (r->flags & type & IORESOURCE_MEM) {
3287                         w = &hose->mem_resources[0];
3288                         msi_region = true;
3289                 }
3290
3291                 r->start = w->start;
3292                 r->end = w->end;
3293
3294                 /* The 64KB 32-bits MSI region shouldn't be included in
3295                  * the 32-bits bridge window. Otherwise, we can see strange
3296                  * issues. One of them is EEH error observed on Garrison.
3297                  *
3298                  * Exclude top 1MB region which is the minimal alignment of
3299                  * 32-bits bridge window.
3300                  */
3301                 if (msi_region) {
3302                         r->end += 0x10000;
3303                         r->end -= 0x100000;
3304                 }
3305         }
3306 }
3307
3308 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3309 {
3310         struct pci_controller *hose = pci_bus_to_host(bus);
3311         struct pnv_phb *phb = hose->private_data;
3312         struct pci_dev *bridge = bus->self;
3313         struct pnv_ioda_pe *pe;
3314         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3315
3316         /* Extend bridge's windows if necessary */
3317         pnv_pci_fixup_bridge_resources(bus, type);
3318
3319         /* The PE for root bus should be realized before any one else */
3320         if (!phb->ioda.root_pe_populated) {
3321                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3322                 if (pe) {
3323                         phb->ioda.root_pe_idx = pe->pe_number;
3324                         phb->ioda.root_pe_populated = true;
3325                 }
3326         }
3327
3328         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3329         if (list_empty(&bus->devices))
3330                 return;
3331
3332         /* Reserve PEs according to used M64 resources */
3333         pnv_ioda_reserve_m64_pe(bus, NULL, all);
3334
3335         /*
3336          * Assign PE. We might run here because of partial hotplug.
3337          * For the case, we just pick up the existing PE and should
3338          * not allocate resources again.
3339          */
3340         pe = pnv_ioda_setup_bus_PE(bus, all);
3341         if (!pe)
3342                 return;
3343
3344         pnv_ioda_setup_pe_seg(pe);
3345         switch (phb->type) {
3346         case PNV_PHB_IODA1:
3347                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3348                 break;
3349         case PNV_PHB_IODA2:
3350                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3351                 break;
3352         default:
3353                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3354                         __func__, phb->hose->global_number, phb->type);
3355         }
3356 }
3357
3358 static resource_size_t pnv_pci_default_alignment(void)
3359 {
3360         return PAGE_SIZE;
3361 }
3362
3363 #ifdef CONFIG_PCI_IOV
3364 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3365                                                       int resno)
3366 {
3367         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3368         struct pnv_phb *phb = hose->private_data;
3369         struct pci_dn *pdn = pci_get_pdn(pdev);
3370         resource_size_t align;
3371
3372         /*
3373          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3374          * SR-IOV. While from hardware perspective, the range mapped by M64
3375          * BAR should be size aligned.
3376          *
3377          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3378          * powernv-specific hardware restriction is gone. But if just use the
3379          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3380          * in one segment of M64 #15, which introduces the PE conflict between
3381          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3382          * m64_segsize.
3383          *
3384          * This function returns the total IOV BAR size if M64 BAR is in
3385          * Shared PE mode or just VF BAR size if not.
3386          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3387          * M64 segment size if IOV BAR size is less.
3388          */
3389         align = pci_iov_resource_size(pdev, resno);
3390         if (!pdn->vfs_expanded)
3391                 return align;
3392         if (pdn->m64_single_mode)
3393                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3394
3395         return pdn->vfs_expanded * align;
3396 }
3397 #endif /* CONFIG_PCI_IOV */
3398
3399 /* Prevent enabling devices for which we couldn't properly
3400  * assign a PE
3401  */
3402 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3403 {
3404         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3405         struct pnv_phb *phb = hose->private_data;
3406         struct pci_dn *pdn;
3407
3408         /* The function is probably called while the PEs have
3409          * not be created yet. For example, resource reassignment
3410          * during PCI probe period. We just skip the check if
3411          * PEs isn't ready.
3412          */
3413         if (!phb->initialized)
3414                 return true;
3415
3416         pdn = pci_get_pdn(dev);
3417         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3418                 return false;
3419
3420         return true;
3421 }
3422
3423 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3424                                        int num)
3425 {
3426         struct pnv_ioda_pe *pe = container_of(table_group,
3427                                               struct pnv_ioda_pe, table_group);
3428         struct pnv_phb *phb = pe->phb;
3429         unsigned int idx;
3430         long rc;
3431
3432         pe_info(pe, "Removing DMA window #%d\n", num);
3433         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3434                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3435                         continue;
3436
3437                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3438                                                 idx, 0, 0ul, 0ul, 0ul);
3439                 if (rc != OPAL_SUCCESS) {
3440                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3441                                 rc, idx);
3442                         return rc;
3443                 }
3444
3445                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3446         }
3447
3448         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3449         return OPAL_SUCCESS;
3450 }
3451
3452 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3453 {
3454         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3455         struct iommu_table *tbl = pe->table_group.tables[0];
3456         int64_t rc;
3457
3458         if (!weight)
3459                 return;
3460
3461         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3462         if (rc != OPAL_SUCCESS)
3463                 return;
3464
3465         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3466         if (pe->table_group.group) {
3467                 iommu_group_put(pe->table_group.group);
3468                 WARN_ON(pe->table_group.group);
3469         }
3470
3471         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3472         iommu_tce_table_put(tbl);
3473 }
3474
3475 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3476 {
3477         struct iommu_table *tbl = pe->table_group.tables[0];
3478         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3479 #ifdef CONFIG_IOMMU_API
3480         int64_t rc;
3481 #endif
3482
3483         if (!weight)
3484                 return;
3485
3486 #ifdef CONFIG_IOMMU_API
3487         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3488         if (rc)
3489                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3490 #endif
3491
3492         pnv_pci_ioda2_set_bypass(pe, false);
3493         if (pe->table_group.group) {
3494                 iommu_group_put(pe->table_group.group);
3495                 WARN_ON(pe->table_group.group);
3496         }
3497
3498         iommu_tce_table_put(tbl);
3499 }
3500
3501 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3502                                  unsigned short win,
3503                                  unsigned int *map)
3504 {
3505         struct pnv_phb *phb = pe->phb;
3506         int idx;
3507         int64_t rc;
3508
3509         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3510                 if (map[idx] != pe->pe_number)
3511                         continue;
3512
3513                 if (win == OPAL_M64_WINDOW_TYPE)
3514                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3515                                         phb->ioda.reserved_pe_idx, win,
3516                                         idx / PNV_IODA1_M64_SEGS,
3517                                         idx % PNV_IODA1_M64_SEGS);
3518                 else
3519                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3520                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3521
3522                 if (rc != OPAL_SUCCESS)
3523                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3524                                 rc, win, idx);
3525
3526                 map[idx] = IODA_INVALID_PE;
3527         }
3528 }
3529
3530 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3531 {
3532         struct pnv_phb *phb = pe->phb;
3533
3534         if (phb->type == PNV_PHB_IODA1) {
3535                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3536                                      phb->ioda.io_segmap);
3537                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3538                                      phb->ioda.m32_segmap);
3539                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3540                                      phb->ioda.m64_segmap);
3541         } else if (phb->type == PNV_PHB_IODA2) {
3542                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3543                                      phb->ioda.m32_segmap);
3544         }
3545 }
3546
3547 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3548 {
3549         struct pnv_phb *phb = pe->phb;
3550         struct pnv_ioda_pe *slave, *tmp;
3551
3552         list_del(&pe->list);
3553         switch (phb->type) {
3554         case PNV_PHB_IODA1:
3555                 pnv_pci_ioda1_release_pe_dma(pe);
3556                 break;
3557         case PNV_PHB_IODA2:
3558                 pnv_pci_ioda2_release_pe_dma(pe);
3559                 break;
3560         default:
3561                 WARN_ON(1);
3562         }
3563
3564         pnv_ioda_release_pe_seg(pe);
3565         pnv_ioda_deconfigure_pe(pe->phb, pe);
3566
3567         /* Release slave PEs in the compound PE */
3568         if (pe->flags & PNV_IODA_PE_MASTER) {
3569                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3570                         list_del(&slave->list);
3571                         pnv_ioda_free_pe(slave);
3572                 }
3573         }
3574
3575         /*
3576          * The PE for root bus can be removed because of hotplug in EEH
3577          * recovery for fenced PHB error. We need to mark the PE dead so
3578          * that it can be populated again in PCI hot add path. The PE
3579          * shouldn't be destroyed as it's the global reserved resource.
3580          */
3581         if (phb->ioda.root_pe_populated &&
3582             phb->ioda.root_pe_idx == pe->pe_number)
3583                 phb->ioda.root_pe_populated = false;
3584         else
3585                 pnv_ioda_free_pe(pe);
3586 }
3587
3588 static void pnv_pci_release_device(struct pci_dev *pdev)
3589 {
3590         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3591         struct pnv_phb *phb = hose->private_data;
3592         struct pci_dn *pdn = pci_get_pdn(pdev);
3593         struct pnv_ioda_pe *pe;
3594
3595         if (pdev->is_virtfn)
3596                 return;
3597
3598         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3599                 return;
3600
3601         /*
3602          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3603          * isn't removed and added afterwards in this scenario. We should
3604          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3605          * device count is decreased on removing devices while failing to
3606          * be increased on adding devices. It leads to unbalanced PE's device
3607          * count and eventually make normal PCI hotplug path broken.
3608          */
3609         pe = &phb->ioda.pe_array[pdn->pe_number];
3610         pdn->pe_number = IODA_INVALID_PE;
3611
3612         WARN_ON(--pe->device_count < 0);
3613         if (pe->device_count == 0)
3614                 pnv_ioda_release_pe(pe);
3615 }
3616
3617 static void pnv_npu_disable_device(struct pci_dev *pdev)
3618 {
3619         struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3620         struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3621
3622         if (eehpe && eeh_ops && eeh_ops->reset)
3623                 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3624 }
3625
3626 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3627 {
3628         struct pnv_phb *phb = hose->private_data;
3629
3630         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3631                        OPAL_ASSERT_RESET);
3632 }
3633
3634 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3635         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3636         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3637         .setup_msi_irqs         = pnv_setup_msi_irqs,
3638         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3639         .enable_device_hook     = pnv_pci_enable_device_hook,
3640         .release_device         = pnv_pci_release_device,
3641         .window_alignment       = pnv_pci_window_alignment,
3642         .setup_bridge           = pnv_pci_setup_bridge,
3643         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3644         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3645         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3646         .shutdown               = pnv_pci_ioda_shutdown,
3647 };
3648
3649 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3650         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3651         .setup_msi_irqs         = pnv_setup_msi_irqs,
3652         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3653         .enable_device_hook     = pnv_pci_enable_device_hook,
3654         .window_alignment       = pnv_pci_window_alignment,
3655         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3656         .shutdown               = pnv_pci_ioda_shutdown,
3657         .disable_device         = pnv_npu_disable_device,
3658 };
3659
3660 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3661         .enable_device_hook     = pnv_pci_enable_device_hook,
3662         .window_alignment       = pnv_pci_window_alignment,
3663         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3664         .shutdown               = pnv_pci_ioda_shutdown,
3665 };
3666
3667 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3668                                          u64 hub_id, int ioda_type)
3669 {
3670         struct pci_controller *hose;
3671         struct pnv_phb *phb;
3672         unsigned long size, m64map_off, m32map_off, pemap_off;
3673         unsigned long iomap_off = 0, dma32map_off = 0;
3674         struct resource r;
3675         const __be64 *prop64;
3676         const __be32 *prop32;
3677         int len;
3678         unsigned int segno;
3679         u64 phb_id;
3680         void *aux;
3681         long rc;
3682
3683         if (!of_device_is_available(np))
3684                 return;
3685
3686         pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3687
3688         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3689         if (!prop64) {
3690                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3691                 return;
3692         }
3693         phb_id = be64_to_cpup(prop64);
3694         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3695
3696         phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3697
3698         /* Allocate PCI controller */
3699         phb->hose = hose = pcibios_alloc_controller(np);
3700         if (!phb->hose) {
3701                 pr_err("  Can't allocate PCI controller for %pOF\n",
3702                        np);
3703                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3704                 return;
3705         }
3706
3707         spin_lock_init(&phb->lock);
3708         prop32 = of_get_property(np, "bus-range", &len);
3709         if (prop32 && len == 8) {
3710                 hose->first_busno = be32_to_cpu(prop32[0]);
3711                 hose->last_busno = be32_to_cpu(prop32[1]);
3712         } else {
3713                 pr_warn("  Broken <bus-range> on %pOF\n", np);
3714                 hose->first_busno = 0;
3715                 hose->last_busno = 0xff;
3716         }
3717         hose->private_data = phb;
3718         phb->hub_id = hub_id;
3719         phb->opal_id = phb_id;
3720         phb->type = ioda_type;
3721         mutex_init(&phb->ioda.pe_alloc_mutex);
3722
3723         /* Detect specific models for error handling */
3724         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3725                 phb->model = PNV_PHB_MODEL_P7IOC;
3726         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3727                 phb->model = PNV_PHB_MODEL_PHB3;
3728         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3729                 phb->model = PNV_PHB_MODEL_NPU;
3730         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3731                 phb->model = PNV_PHB_MODEL_NPU2;
3732         else
3733                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3734
3735         /* Initialize diagnostic data buffer */
3736         prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3737         if (prop32)
3738                 phb->diag_data_size = be32_to_cpup(prop32);
3739         else
3740                 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3741
3742         phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3743
3744         /* Parse 32-bit and IO ranges (if any) */
3745         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3746
3747         /* Get registers */
3748         if (!of_address_to_resource(np, 0, &r)) {
3749                 phb->regs_phys = r.start;
3750                 phb->regs = ioremap(r.start, resource_size(&r));
3751                 if (phb->regs == NULL)
3752                         pr_err("  Failed to map registers !\n");
3753         }
3754
3755         /* Initialize more IODA stuff */
3756         phb->ioda.total_pe_num = 1;
3757         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3758         if (prop32)
3759                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3760         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3761         if (prop32)
3762                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3763
3764         /* Invalidate RID to PE# mapping */
3765         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3766                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3767
3768         /* Parse 64-bit MMIO range */
3769         pnv_ioda_parse_m64_window(phb);
3770
3771         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3772         /* FW Has already off top 64k of M32 space (MSI space) */
3773         phb->ioda.m32_size += 0x10000;
3774
3775         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3776         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3777         phb->ioda.io_size = hose->pci_io_size;
3778         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3779         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3780
3781         /* Calculate how many 32-bit TCE segments we have */
3782         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3783                                 PNV_IODA1_DMA32_SEGSIZE;
3784
3785         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3786         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3787                         sizeof(unsigned long));
3788         m64map_off = size;
3789         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3790         m32map_off = size;
3791         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3792         if (phb->type == PNV_PHB_IODA1) {
3793                 iomap_off = size;
3794                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3795                 dma32map_off = size;
3796                 size += phb->ioda.dma32_count *
3797                         sizeof(phb->ioda.dma32_segmap[0]);
3798         }
3799         pemap_off = size;
3800         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3801         aux = memblock_alloc(size, SMP_CACHE_BYTES);
3802         phb->ioda.pe_alloc = aux;
3803         phb->ioda.m64_segmap = aux + m64map_off;
3804         phb->ioda.m32_segmap = aux + m32map_off;
3805         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3806                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3807                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3808         }
3809         if (phb->type == PNV_PHB_IODA1) {
3810                 phb->ioda.io_segmap = aux + iomap_off;
3811                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3812                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3813
3814                 phb->ioda.dma32_segmap = aux + dma32map_off;
3815                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3816                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3817         }
3818         phb->ioda.pe_array = aux + pemap_off;
3819
3820         /*
3821          * Choose PE number for root bus, which shouldn't have
3822          * M64 resources consumed by its child devices. To pick
3823          * the PE number adjacent to the reserved one if possible.
3824          */
3825         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3826         if (phb->ioda.reserved_pe_idx == 0) {
3827                 phb->ioda.root_pe_idx = 1;
3828                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3829         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3830                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3831                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3832         } else {
3833                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3834         }
3835
3836         INIT_LIST_HEAD(&phb->ioda.pe_list);
3837         mutex_init(&phb->ioda.pe_list_mutex);
3838
3839         /* Calculate how many 32-bit TCE segments we have */
3840         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3841                                 PNV_IODA1_DMA32_SEGSIZE;
3842
3843 #if 0 /* We should really do that ... */
3844         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3845                                          window_type,
3846                                          window_num,
3847                                          starting_real_address,
3848                                          starting_pci_address,
3849                                          segment_size);
3850 #endif
3851
3852         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3853                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3854                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3855         if (phb->ioda.m64_size)
3856                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3857                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3858         if (phb->ioda.io_size)
3859                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3860                         phb->ioda.io_size, phb->ioda.io_segsize);
3861
3862
3863         phb->hose->ops = &pnv_pci_ops;
3864         phb->get_pe_state = pnv_ioda_get_pe_state;
3865         phb->freeze_pe = pnv_ioda_freeze_pe;
3866         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3867
3868         /* Setup MSI support */
3869         pnv_pci_init_ioda_msis(phb);
3870
3871         /*
3872          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3873          * to let the PCI core do resource assignment. It's supposed
3874          * that the PCI core will do correct I/O and MMIO alignment
3875          * for the P2P bridge bars so that each PCI bus (excluding
3876          * the child P2P bridges) can form individual PE.
3877          */
3878         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3879
3880         switch (phb->type) {
3881         case PNV_PHB_NPU_NVLINK:
3882                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3883                 break;
3884         case PNV_PHB_NPU_OCAPI:
3885                 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3886                 break;
3887         default:
3888                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3889                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3890         }
3891
3892         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3893
3894 #ifdef CONFIG_PCI_IOV
3895         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3896         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3897         ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3898         ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3899 #endif
3900
3901         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3902
3903         /* Reset IODA tables to a clean state */
3904         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3905         if (rc)
3906                 pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
3907
3908         /*
3909          * If we're running in kdump kernel, the previous kernel never
3910          * shutdown PCI devices correctly. We already got IODA table
3911          * cleaned out. So we have to issue PHB reset to stop all PCI
3912          * transactions from previous kernel. The ppc_pci_reset_phbs
3913          * kernel parameter will force this reset too.
3914          */
3915         if (is_kdump_kernel() || pci_reset_phbs) {
3916                 pr_info("  Issue PHB reset ...\n");
3917                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3918                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3919         }
3920
3921         /* Remove M64 resource if we can't configure it successfully */
3922         if (!phb->init_m64 || phb->init_m64(phb))
3923                 hose->mem_resources[1].flags = 0;
3924 }
3925
3926 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3927 {
3928         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3929 }
3930
3931 void __init pnv_pci_init_npu_phb(struct device_node *np)
3932 {
3933         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3934 }
3935
3936 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3937 {
3938         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3939 }
3940
3941 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3942 {
3943         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3944         struct pnv_phb *phb = hose->private_data;
3945
3946         if (!machine_is(powernv))
3947                 return;
3948
3949         if (phb->type == PNV_PHB_NPU_OCAPI)
3950                 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3951 }
3952 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3953
3954 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3955 {
3956         struct device_node *phbn;
3957         const __be64 *prop64;
3958         u64 hub_id;
3959
3960         pr_info("Probing IODA IO-Hub %pOF\n", np);
3961
3962         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3963         if (!prop64) {
3964                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3965                 return;
3966         }
3967         hub_id = be64_to_cpup(prop64);
3968         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3969
3970         /* Count child PHBs */
3971         for_each_child_of_node(np, phbn) {
3972                 /* Look for IODA1 PHBs */
3973                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3974                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3975         }
3976 }