2 * BPF Jit compiler for s390.
4 * Minimum build requirements:
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
29 int bpf_jit_enable __read_mostly;
32 u32 seen; /* Flags to remember seen eBPF instructions */
33 u32 seen_reg[16]; /* Array to remember which registers are used */
34 u32 *addrs; /* Array with relative instruction addresses */
35 u8 *prg_buf; /* Start of program */
36 int size; /* Size of program and literal pool */
37 int size_prg; /* Size of program */
38 int prg; /* Current position in program */
39 int lit_start; /* Start of literal pool */
40 int lit; /* Current position in literal pool */
41 int base_ip; /* Base address for literal pool */
42 int ret0_ip; /* Address of return 0 */
43 int exit_ip; /* Address of exit */
44 int tail_call_start; /* Tail call start offset */
45 int labels[1]; /* Labels for local jumps */
48 #define BPF_SIZE_MAX 0x7ffff /* Max size for program (20 bit signed displ) */
50 #define SEEN_SKB 1 /* skb access */
51 #define SEEN_MEM 2 /* use mem[] for temporary storage */
52 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
53 #define SEEN_LITERAL 8 /* code uses literals */
54 #define SEEN_FUNC 16 /* calls C functions */
55 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
56 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
61 #define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
62 #define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
63 #define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
64 #define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
65 #define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
66 #define REG_0 REG_W0 /* Register 0 */
67 #define REG_1 REG_W1 /* Register 1 */
68 #define REG_2 BPF_REG_1 /* Register 2 */
69 #define REG_14 BPF_REG_0 /* Register 14 */
72 * Mapping of BPF registers to s390 registers
74 static const int reg2hex[] = {
77 /* Function parameters */
83 /* Call saved registers */
88 /* BPF stack pointer */
90 /* SKB data pointer */
92 /* Work registers for s390x backend */
99 static inline u32 reg(u32 dst_reg, u32 src_reg)
101 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
104 static inline u32 reg_high(u32 reg)
106 return reg2hex[reg] << 4;
109 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
111 u32 r1 = reg2hex[b1];
113 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
114 jit->seen_reg[r1] = 1;
117 #define REG_SET_SEEN(b1) \
119 reg_set_seen(jit, b1); \
122 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
125 * EMIT macros for code generation
131 *(u16 *) (jit->prg_buf + jit->prg) = op; \
135 #define EMIT2(op, b1, b2) \
137 _EMIT2(op | reg(b1, b2)); \
145 *(u32 *) (jit->prg_buf + jit->prg) = op; \
149 #define EMIT4(op, b1, b2) \
151 _EMIT4(op | reg(b1, b2)); \
156 #define EMIT4_RRF(op, b1, b2, b3) \
158 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
164 #define _EMIT4_DISP(op, disp) \
166 unsigned int __disp = (disp) & 0xfff; \
167 _EMIT4(op | __disp); \
170 #define EMIT4_DISP(op, b1, b2, disp) \
172 _EMIT4_DISP(op | reg_high(b1) << 16 | \
173 reg_high(b2) << 8, disp); \
178 #define EMIT4_IMM(op, b1, imm) \
180 unsigned int __imm = (imm) & 0xffff; \
181 _EMIT4(op | reg_high(b1) << 16 | __imm); \
185 #define EMIT4_PCREL(op, pcrel) \
187 long __pcrel = ((pcrel) >> 1) & 0xffff; \
188 _EMIT4(op | __pcrel); \
191 #define _EMIT6(op1, op2) \
193 if (jit->prg_buf) { \
194 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
195 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
200 #define _EMIT6_DISP(op1, op2, disp) \
202 unsigned int __disp = (disp) & 0xfff; \
203 _EMIT6(op1 | __disp, op2); \
206 #define _EMIT6_DISP_LH(op1, op2, disp) \
208 u32 _disp = (u32) disp; \
209 unsigned int __disp_h = _disp & 0xff000; \
210 unsigned int __disp_l = _disp & 0x00fff; \
211 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
214 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
216 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
217 reg_high(b3) << 8, op2, disp); \
223 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
225 int rel = (jit->labels[label] - jit->prg) >> 1; \
226 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
232 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
234 int rel = (jit->labels[label] - jit->prg) >> 1; \
235 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
236 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
238 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
241 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
243 /* Branch instruction needs 6 bytes */ \
244 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
245 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
250 #define _EMIT6_IMM(op, imm) \
252 unsigned int __imm = (imm); \
253 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
256 #define EMIT6_IMM(op, b1, imm) \
258 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
262 #define EMIT_CONST_U32(val) \
265 ret = jit->lit - jit->base_ip; \
266 jit->seen |= SEEN_LITERAL; \
268 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
273 #define EMIT_CONST_U64(val) \
276 ret = jit->lit - jit->base_ip; \
277 jit->seen |= SEEN_LITERAL; \
279 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
284 #define EMIT_ZERO(b1) \
286 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
287 EMIT4(0xb9160000, b1, b1); \
292 * Fill whole space with illegal instructions
294 static void jit_fill_hole(void *area, unsigned int size)
296 memset(area, 0, size);
300 * Save registers from "rs" (register start) to "re" (register end) on stack
302 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
304 u32 off = STK_OFF_R6 + (rs - 6) * 8;
307 /* stg %rs,off(%r15) */
308 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
310 /* stmg %rs,%re,off(%r15) */
311 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
315 * Restore registers from "rs" (register start) to "re" (register end) on stack
317 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
319 u32 off = STK_OFF_R6 + (rs - 6) * 8;
321 if (jit->seen & SEEN_STACK)
325 /* lg %rs,off(%r15) */
326 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
328 /* lmg %rs,%re,off(%r15) */
329 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
333 * Return first seen register (from start)
335 static int get_start(struct bpf_jit *jit, int start)
339 for (i = start; i <= 15; i++) {
340 if (jit->seen_reg[i])
347 * Return last seen register (from start) (gap >= 2)
349 static int get_end(struct bpf_jit *jit, int start)
353 for (i = start; i < 15; i++) {
354 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
357 return jit->seen_reg[15] ? 15 : 14;
361 #define REGS_RESTORE 0
363 * Save and restore clobbered registers (6-15) on stack.
364 * We save/restore registers in chunks with gap >= 2 registers.
366 static void save_restore_regs(struct bpf_jit *jit, int op)
372 rs = get_start(jit, re);
375 re = get_end(jit, rs + 1);
377 save_regs(jit, rs, re);
379 restore_regs(jit, rs, re);
385 * Emit function prologue
387 * Save registers and create stack frame if necessary.
388 * See stack frame layout desription in "bpf_jit.h"!
390 static void bpf_jit_prologue(struct bpf_jit *jit)
392 if (jit->seen & SEEN_TAIL_CALL) {
393 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
394 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
396 /* j tail_call_start: NOP if no tail calls are used */
397 EMIT4_PCREL(0xa7f40000, 6);
400 /* Tail calls have to skip above initialization */
401 jit->tail_call_start = jit->prg;
403 save_restore_regs(jit, REGS_SAVE);
404 /* Setup literal pool */
405 if (jit->seen & SEEN_LITERAL) {
407 EMIT2(0x0d00, REG_L, REG_0);
408 jit->base_ip = jit->prg;
410 /* Setup stack and backchain */
411 if (jit->seen & SEEN_STACK) {
412 if (jit->seen & SEEN_FUNC)
413 /* lgr %w1,%r15 (backchain) */
414 EMIT4(0xb9040000, REG_W1, REG_15);
415 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
416 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
417 /* aghi %r15,-STK_OFF */
418 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
419 if (jit->seen & SEEN_FUNC)
420 /* stg %w1,152(%r15) (backchain) */
421 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
425 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
426 * we store the SKB header length on the stack and the SKB data
427 * pointer in REG_SKB_DATA.
429 if (jit->seen & SEEN_SKB) {
430 /* Header length: llgf %w1,<len>(%b1) */
431 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
432 offsetof(struct sk_buff, len));
433 /* s %w1,<data_len>(%b1) */
434 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
435 offsetof(struct sk_buff, data_len));
436 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
437 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,
439 /* lg %skb_data,data_off(%b1) */
440 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
441 BPF_REG_1, offsetof(struct sk_buff, data));
443 /* BPF compatibility: clear A (%b0) and X (%b7) registers */
444 if (REG_SEEN(BPF_REG_A))
446 EMIT4_IMM(0xa7090000, BPF_REG_A, 0);
447 if (REG_SEEN(BPF_REG_X))
449 EMIT4_IMM(0xa7090000, BPF_REG_X, 0);
455 static void bpf_jit_epilogue(struct bpf_jit *jit)
458 if (jit->seen & SEEN_RET0) {
459 jit->ret0_ip = jit->prg;
461 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
463 jit->exit_ip = jit->prg;
464 /* Load exit code: lgr %r2,%b0 */
465 EMIT4(0xb9040000, REG_2, BPF_REG_0);
466 /* Restore registers */
467 save_restore_regs(jit, REGS_RESTORE);
473 * Compile one eBPF instruction into s390x code
475 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
476 * stack space for the large switch statement.
478 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
480 struct bpf_insn *insn = &fp->insnsi[i];
481 int jmp_off, last, insn_count = 1;
482 unsigned int func_addr, mask;
483 u32 dst_reg = insn->dst_reg;
484 u32 src_reg = insn->src_reg;
485 u32 *addrs = jit->addrs;
489 switch (insn->code) {
493 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
494 /* llgfr %dst,%src */
495 EMIT4(0xb9160000, dst_reg, src_reg);
497 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
499 EMIT4(0xb9040000, dst_reg, src_reg);
501 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
503 EMIT6_IMM(0xc00f0000, dst_reg, imm);
505 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
507 EMIT6_IMM(0xc0010000, dst_reg, imm);
512 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
514 /* 16 byte instruction that uses two 'struct bpf_insn' */
517 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
518 /* lg %dst,<d(imm)>(%l) */
519 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
520 EMIT_CONST_U64(imm64));
527 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
529 EMIT2(0x1a00, dst_reg, src_reg);
532 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
534 EMIT4(0xb9080000, dst_reg, src_reg);
536 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
540 EMIT6_IMM(0xc20b0000, dst_reg, imm);
543 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
547 EMIT6_IMM(0xc2080000, dst_reg, imm);
552 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
554 EMIT2(0x1b00, dst_reg, src_reg);
557 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
559 EMIT4(0xb9090000, dst_reg, src_reg);
561 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
565 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
568 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
572 EMIT6_IMM(0xc2080000, dst_reg, -imm);
577 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
579 EMIT4(0xb2520000, dst_reg, src_reg);
582 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
584 EMIT4(0xb90c0000, dst_reg, src_reg);
586 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
590 EMIT6_IMM(0xc2010000, dst_reg, imm);
593 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
597 EMIT6_IMM(0xc2000000, dst_reg, imm);
602 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
603 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
605 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
607 jit->seen |= SEEN_RET0;
608 /* ltr %src,%src (if src == 0 goto fail) */
609 EMIT2(0x1200, src_reg, src_reg);
611 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
613 EMIT4_IMM(0xa7080000, REG_W0, 0);
615 EMIT2(0x1800, REG_W1, dst_reg);
617 EMIT4(0xb9970000, REG_W0, src_reg);
619 EMIT4(0xb9160000, dst_reg, rc_reg);
622 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
623 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
625 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
627 jit->seen |= SEEN_RET0;
628 /* ltgr %src,%src (if src == 0 goto fail) */
629 EMIT4(0xb9020000, src_reg, src_reg);
631 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
633 EMIT4_IMM(0xa7090000, REG_W0, 0);
635 EMIT4(0xb9040000, REG_W1, dst_reg);
637 EMIT4(0xb9870000, REG_W0, src_reg);
639 EMIT4(0xb9040000, dst_reg, rc_reg);
642 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
643 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
645 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
648 if (BPF_OP(insn->code) == BPF_MOD)
650 EMIT4_IMM(0xa7090000, dst_reg, 0);
654 EMIT4_IMM(0xa7080000, REG_W0, 0);
656 EMIT2(0x1800, REG_W1, dst_reg);
657 /* dl %w0,<d(imm)>(%l) */
658 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
659 EMIT_CONST_U32(imm));
661 EMIT4(0xb9160000, dst_reg, rc_reg);
664 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
665 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
667 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
670 if (BPF_OP(insn->code) == BPF_MOD)
672 EMIT4_IMM(0xa7090000, dst_reg, 0);
676 EMIT4_IMM(0xa7090000, REG_W0, 0);
678 EMIT4(0xb9040000, REG_W1, dst_reg);
679 /* dlg %w0,<d(imm)>(%l) */
680 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
681 EMIT_CONST_U64(imm));
683 EMIT4(0xb9040000, dst_reg, rc_reg);
689 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
691 EMIT2(0x1400, dst_reg, src_reg);
694 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
696 EMIT4(0xb9800000, dst_reg, src_reg);
698 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
700 EMIT6_IMM(0xc00b0000, dst_reg, imm);
703 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
704 /* ng %dst,<d(imm)>(%l) */
705 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
706 EMIT_CONST_U64(imm));
711 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
713 EMIT2(0x1600, dst_reg, src_reg);
716 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
718 EMIT4(0xb9810000, dst_reg, src_reg);
720 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
722 EMIT6_IMM(0xc00d0000, dst_reg, imm);
725 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
726 /* og %dst,<d(imm)>(%l) */
727 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
728 EMIT_CONST_U64(imm));
733 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
735 EMIT2(0x1700, dst_reg, src_reg);
738 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
740 EMIT4(0xb9820000, dst_reg, src_reg);
742 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
746 EMIT6_IMM(0xc0070000, dst_reg, imm);
749 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
750 /* xg %dst,<d(imm)>(%l) */
751 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
752 EMIT_CONST_U64(imm));
757 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
758 /* sll %dst,0(%src) */
759 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
762 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
763 /* sllg %dst,%dst,0(%src) */
764 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
766 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
769 /* sll %dst,imm(%r0) */
770 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
773 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
776 /* sllg %dst,%dst,imm(%r0) */
777 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
782 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
783 /* srl %dst,0(%src) */
784 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
787 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
788 /* srlg %dst,%dst,0(%src) */
789 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
791 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
794 /* srl %dst,imm(%r0) */
795 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
798 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
801 /* srlg %dst,%dst,imm(%r0) */
802 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
807 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
808 /* srag %dst,%dst,0(%src) */
809 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
811 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
814 /* srag %dst,%dst,imm(%r0) */
815 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
820 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
822 EMIT2(0x1300, dst_reg, dst_reg);
825 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
827 EMIT4(0xb9130000, dst_reg, dst_reg);
832 case BPF_ALU | BPF_END | BPF_FROM_BE:
833 /* s390 is big endian, therefore only clear high order bytes */
835 case 16: /* dst = (u16) cpu_to_be16(dst) */
836 /* llghr %dst,%dst */
837 EMIT4(0xb9850000, dst_reg, dst_reg);
839 case 32: /* dst = (u32) cpu_to_be32(dst) */
840 /* llgfr %dst,%dst */
841 EMIT4(0xb9160000, dst_reg, dst_reg);
843 case 64: /* dst = (u64) cpu_to_be64(dst) */
847 case BPF_ALU | BPF_END | BPF_FROM_LE:
849 case 16: /* dst = (u16) cpu_to_le16(dst) */
851 EMIT4(0xb91f0000, dst_reg, dst_reg);
852 /* srl %dst,16(%r0) */
853 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
854 /* llghr %dst,%dst */
855 EMIT4(0xb9850000, dst_reg, dst_reg);
857 case 32: /* dst = (u32) cpu_to_le32(dst) */
859 EMIT4(0xb91f0000, dst_reg, dst_reg);
860 /* llgfr %dst,%dst */
861 EMIT4(0xb9160000, dst_reg, dst_reg);
863 case 64: /* dst = (u64) cpu_to_le64(dst) */
864 /* lrvgr %dst,%dst */
865 EMIT4(0xb90f0000, dst_reg, dst_reg);
872 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
873 /* stcy %src,off(%dst) */
874 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
875 jit->seen |= SEEN_MEM;
877 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
878 /* sthy %src,off(%dst) */
879 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
880 jit->seen |= SEEN_MEM;
882 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
883 /* sty %src,off(%dst) */
884 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
885 jit->seen |= SEEN_MEM;
887 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
888 /* stg %src,off(%dst) */
889 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
890 jit->seen |= SEEN_MEM;
892 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
894 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
895 /* stcy %w0,off(dst) */
896 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
897 jit->seen |= SEEN_MEM;
899 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
901 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
902 /* sthy %w0,off(dst) */
903 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
904 jit->seen |= SEEN_MEM;
906 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
908 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
909 /* sty %w0,off(%dst) */
910 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
911 jit->seen |= SEEN_MEM;
913 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
915 EMIT6_IMM(0xc0010000, REG_W0, imm);
916 /* stg %w0,off(%dst) */
917 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
918 jit->seen |= SEEN_MEM;
921 * BPF_STX XADD (atomic_add)
923 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
924 /* laal %w0,%src,off(%dst) */
925 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
927 jit->seen |= SEEN_MEM;
929 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
930 /* laalg %w0,%src,off(%dst) */
931 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
933 jit->seen |= SEEN_MEM;
938 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
939 /* llgc %dst,0(off,%src) */
940 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
941 jit->seen |= SEEN_MEM;
943 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
944 /* llgh %dst,0(off,%src) */
945 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
946 jit->seen |= SEEN_MEM;
948 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
949 /* llgf %dst,off(%src) */
950 jit->seen |= SEEN_MEM;
951 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
953 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
954 /* lg %dst,0(off,%src) */
955 jit->seen |= SEEN_MEM;
956 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
961 case BPF_JMP | BPF_CALL:
964 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
966 const u64 func = (u64)__bpf_call_base + imm;
968 if (bpf_helper_changes_skb_data((void *)func))
969 /* TODO reload skb->data, hlen */
972 REG_SET_SEEN(BPF_REG_5);
973 jit->seen |= SEEN_FUNC;
974 /* lg %w1,<d(imm)>(%l) */
975 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
976 EMIT_CONST_U64(func));
978 EMIT2(0x0d00, REG_14, REG_W1);
979 /* lgr %b0,%r2: load return value into %b0 */
980 EMIT4(0xb9040000, BPF_REG_0, REG_2);
983 case BPF_JMP | BPF_CALL | BPF_X:
987 * B2: pointer to bpf_array
988 * B3: index in bpf_array
990 jit->seen |= SEEN_TAIL_CALL;
993 * if (index >= array->map.max_entries)
997 /* llgf %w1,map.max_entries(%b2) */
998 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
999 offsetof(struct bpf_array, map.max_entries));
1000 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1001 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
1005 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1009 if (jit->seen & SEEN_STACK)
1010 off = STK_OFF_TCCNT + STK_OFF;
1012 off = STK_OFF_TCCNT;
1014 EMIT4_IMM(0xa7080000, REG_W0, 1);
1015 /* laal %w1,%w0,off(%r15) */
1016 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1017 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1018 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1019 MAX_TAIL_CALL_CNT, 0, 0x2);
1022 * prog = array->prog[index];
1027 /* sllg %r1,%b3,3: %r1 = index * 8 */
1028 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
1029 /* lg %r1,prog(%b2,%r1) */
1030 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1031 REG_1, offsetof(struct bpf_array, prog));
1032 /* clgij %r1,0,0x8,label0 */
1033 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1036 * Restore registers before calling function
1038 save_restore_regs(jit, REGS_RESTORE);
1041 * goto *(prog->bpf_func + tail_call_start);
1044 /* lg %r1,bpf_func(%r1) */
1045 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1046 offsetof(struct bpf_prog, bpf_func));
1047 /* bc 0xf,tail_call_start(%r1) */
1048 _EMIT4(0x47f01000 + jit->tail_call_start);
1050 jit->labels[0] = jit->prg;
1052 case BPF_JMP | BPF_EXIT: /* return b0 */
1053 last = (i == fp->len - 1) ? 1 : 0;
1054 if (last && !(jit->seen & SEEN_RET0))
1057 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1060 * Branch relative (number of skipped instructions) to offset on
1063 * Condition code to mask mapping:
1065 * CC | Description | Mask
1066 * ------------------------------
1067 * 0 | Operands equal | 8
1068 * 1 | First operand low | 4
1069 * 2 | First operand high | 2
1072 * For s390x relative branches: ip = ip + off_bytes
1073 * For BPF relative branches: insn = insn + off_insns + 1
1075 * For example for s390x with offset 0 we jump to the branch
1076 * instruction itself (loop) and for BPF with offset 0 we
1077 * branch to the instruction behind the branch.
1079 case BPF_JMP | BPF_JA: /* if (true) */
1080 mask = 0xf000; /* j */
1082 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1083 mask = 0x2000; /* jh */
1085 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1086 mask = 0xa000; /* jhe */
1088 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1089 mask = 0x2000; /* jh */
1091 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1092 mask = 0xa000; /* jhe */
1094 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1095 mask = 0x7000; /* jne */
1097 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1098 mask = 0x8000; /* je */
1100 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1101 mask = 0x7000; /* jnz */
1102 /* lgfi %w1,imm (load sign extend imm) */
1103 EMIT6_IMM(0xc0010000, REG_W1, imm);
1105 EMIT4(0xb9800000, REG_W1, dst_reg);
1108 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1109 mask = 0x2000; /* jh */
1111 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1112 mask = 0xa000; /* jhe */
1114 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1115 mask = 0x2000; /* jh */
1117 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1118 mask = 0xa000; /* jhe */
1120 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1121 mask = 0x7000; /* jne */
1123 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1124 mask = 0x8000; /* je */
1126 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1127 mask = 0x7000; /* jnz */
1128 /* ngrk %w1,%dst,%src */
1129 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1132 /* lgfi %w1,imm (load sign extend imm) */
1133 EMIT6_IMM(0xc0010000, REG_W1, imm);
1134 /* cgrj %dst,%w1,mask,off */
1135 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1138 /* lgfi %w1,imm (load sign extend imm) */
1139 EMIT6_IMM(0xc0010000, REG_W1, imm);
1140 /* clgrj %dst,%w1,mask,off */
1141 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1144 /* cgrj %dst,%src,mask,off */
1145 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1148 /* clgrj %dst,%src,mask,off */
1149 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1152 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1153 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1154 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1159 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1160 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1161 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1162 func_addr = __pa(sk_load_byte_pos);
1164 func_addr = __pa(sk_load_byte);
1166 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1167 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1168 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1169 func_addr = __pa(sk_load_half_pos);
1171 func_addr = __pa(sk_load_half);
1173 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1174 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1175 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1176 func_addr = __pa(sk_load_word_pos);
1178 func_addr = __pa(sk_load_word);
1181 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1182 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1186 * BPF_REG_6 (R7) : skb pointer
1187 * REG_SKB_DATA (R12): skb data pointer
1190 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1191 * BPF_REG_5 (R6) : return address
1194 * BPF_REG_0 (R14): data read from skb
1196 * Scratch registers (BPF_REG_1-5)
1199 /* Call function: llilf %w1,func_addr */
1200 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1202 /* Offset: lgfi %b2,imm */
1203 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1204 if (BPF_MODE(insn->code) == BPF_IND)
1205 /* agfr %b2,%src (%src is s32 here) */
1206 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1208 /* basr %b5,%w1 (%b5 is call saved) */
1209 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1212 * Note: For fast access we jump directly after the
1213 * jnz instruction from bpf_jit.S
1216 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1218 default: /* too complex, give up */
1219 pr_err("Unknown opcode %02x\n", insn->code);
1226 * Compile eBPF program into s390x code
1228 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1232 jit->lit = jit->lit_start;
1235 bpf_jit_prologue(jit);
1236 for (i = 0; i < fp->len; i += insn_count) {
1237 insn_count = bpf_jit_insn(jit, fp, i);
1240 jit->addrs[i + 1] = jit->prg; /* Next instruction address */
1242 bpf_jit_epilogue(jit);
1244 jit->lit_start = jit->prg;
1245 jit->size = jit->lit;
1246 jit->size_prg = jit->prg;
1251 * Classic BPF function stub. BPF programs will be converted into
1252 * eBPF and then bpf_int_jit_compile() will be called.
1254 void bpf_jit_compile(struct bpf_prog *fp)
1259 * Compile eBPF program "fp"
1261 void bpf_int_jit_compile(struct bpf_prog *fp)
1263 struct bpf_binary_header *header;
1267 if (!bpf_jit_enable)
1269 memset(&jit, 0, sizeof(jit));
1270 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1271 if (jit.addrs == NULL)
1274 * Three initial passes:
1275 * - 1/2: Determine clobbered registers
1276 * - 3: Calculate program size and addrs arrray
1278 for (pass = 1; pass <= 3; pass++) {
1279 if (bpf_jit_prog(&jit, fp))
1283 * Final pass: Allocate and generate program
1285 if (jit.size >= BPF_SIZE_MAX)
1287 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1290 if (bpf_jit_prog(&jit, fp))
1292 if (bpf_jit_enable > 1) {
1293 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1295 print_fn_code(jit.prg_buf, jit.size_prg);
1298 set_memory_ro((unsigned long)header, header->pages);
1299 fp->bpf_func = (void *) jit.prg_buf;
1309 void bpf_jit_free(struct bpf_prog *fp)
1311 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1312 struct bpf_binary_header *header = (void *)addr;
1317 set_memory_rw(addr, header->pages);
1318 bpf_jit_binary_free(header);
1321 bpf_prog_unlock_free(fp);