1 /* SPDX-License-Identifier: GPL-2.0 */
7 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
8 * while in{b,w,l}/out{b,w,l} are for ISA
10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
11 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
14 * automatically, there are also __raw versions, which do not.
16 #include <linux/errno.h>
17 #include <asm/cache.h>
18 #include <asm/addrspace.h>
19 #include <asm/machvec.h>
20 #include <asm/pgtable.h>
21 #include <asm-generic/iomap.h>
24 #define __IO_PREFIX generic
25 #include <asm/io_generic.h>
26 #include <asm/io_trapped.h>
27 #include <asm-generic/pci_iomap.h>
28 #include <mach/mangle-port.h>
30 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
31 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
32 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
33 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
35 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
36 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
37 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
38 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
40 #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
41 #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
42 #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
43 #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
45 #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
46 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
47 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
48 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
50 #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
51 #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
52 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
53 #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
55 #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
56 #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
57 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
58 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
60 #define readsb(p,d,l) __raw_readsb(p,d,l)
61 #define readsw(p,d,l) __raw_readsw(p,d,l)
62 #define readsl(p,d,l) __raw_readsl(p,d,l)
64 #define writesb(p,d,l) __raw_writesb(p,d,l)
65 #define writesw(p,d,l) __raw_writesw(p,d,l)
66 #define writesl(p,d,l) __raw_writesl(p,d,l)
68 #define __BUILD_UNCACHED_IO(bwlq, type) \
69 static inline type read##bwlq##_uncached(unsigned long addr) \
73 ret = __raw_read##bwlq(addr); \
78 static inline void write##bwlq##_uncached(type v, unsigned long addr) \
81 __raw_write##bwlq(v, addr); \
85 __BUILD_UNCACHED_IO(b, u8)
86 __BUILD_UNCACHED_IO(w, u16)
87 __BUILD_UNCACHED_IO(l, u32)
88 __BUILD_UNCACHED_IO(q, u64)
90 #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
93 pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
96 const volatile type *__addr = addr; \
99 __raw_write##bwlq(*__addr, mem); \
104 static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
105 void *addr, unsigned int count) \
107 volatile type *__addr = addr; \
110 *__addr = __raw_read##bwlq(mem); \
115 __BUILD_MEMORY_STRING(__raw_, b, u8)
116 __BUILD_MEMORY_STRING(__raw_, w, u16)
118 #ifdef CONFIG_SUPERH32
119 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
120 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
122 __BUILD_MEMORY_STRING(__raw_, l, u32)
125 __BUILD_MEMORY_STRING(__raw_, q, u64)
127 #ifdef CONFIG_HAS_IOPORT_MAP
130 * Slowdown I/O port space accesses for antique hardware.
132 #undef CONF_SLOWDOWN_IO
135 * On SuperH I/O ports are memory mapped, so we access them using normal
136 * load/store instructions. sh_io_port_base is the virtual address to
137 * which all ports are being mapped.
139 extern unsigned long sh_io_port_base;
141 static inline void __set_io_port_base(unsigned long pbase)
143 *(unsigned long *)&sh_io_port_base = pbase;
147 #ifdef CONFIG_GENERIC_IOMAP
148 #define __ioport_map ioport_map
150 extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
153 #ifdef CONF_SLOWDOWN_IO
154 #define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
159 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
161 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
163 volatile type *__addr; \
165 __addr = __ioport_map(port, sizeof(type)); \
170 static inline type pfx##in##bwlq##p(unsigned long port) \
172 volatile type *__addr; \
175 __addr = __ioport_map(port, sizeof(type)); \
182 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
183 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
184 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
186 #define BUILDIO_IOPORT(bwlq, type) \
187 __BUILD_IOPORT_PFX(, bwlq, type)
189 BUILDIO_IOPORT(b, u8)
190 BUILDIO_IOPORT(w, u16)
191 BUILDIO_IOPORT(l, u32)
192 BUILDIO_IOPORT(q, u64)
194 #define __BUILD_IOPORT_STRING(bwlq, type) \
196 static inline void outs##bwlq(unsigned long port, const void *addr, \
197 unsigned int count) \
199 const volatile type *__addr = addr; \
202 out##bwlq(*__addr, port); \
207 static inline void ins##bwlq(unsigned long port, void *addr, \
208 unsigned int count) \
210 volatile type *__addr = addr; \
213 *__addr = in##bwlq(port); \
218 __BUILD_IOPORT_STRING(b, u8)
219 __BUILD_IOPORT_STRING(w, u16)
220 __BUILD_IOPORT_STRING(l, u32)
221 __BUILD_IOPORT_STRING(q, u64)
223 #else /* !CONFIG_HAS_IOPORT_MAP */
225 #include <asm/io_noioport.h>
230 #define IO_SPACE_LIMIT 0xffffffff
232 /* synco on SH-4A, otherwise a nop */
233 #define mmiowb() wmb()
235 /* We really want to try and get these to memcpy etc */
236 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
237 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
238 void memset_io(volatile void __iomem *, int, unsigned long);
240 /* Quad-word real-mode I/O, don't ask.. */
241 unsigned long long peek_real_address_q(unsigned long long addr);
242 unsigned long long poke_real_address_q(unsigned long long addr,
243 unsigned long long val);
245 #if !defined(CONFIG_MMU)
246 #define virt_to_phys(address) ((unsigned long)(address))
247 #define phys_to_virt(address) ((void *)(address))
249 #define virt_to_phys(address) (__pa(address))
250 #define phys_to_virt(address) (__va(address))
254 * On 32-bit SH, we traditionally have the whole physical address space
255 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
256 * not need to do anything but place the address in the proper segment.
257 * This is true for P1 and P2 addresses, as well as some P3 ones.
258 * However, most of the P3 addresses and newer cores using extended
259 * addressing need to map through page tables, so the ioremap()
260 * implementation becomes a bit more complicated.
262 * See arch/sh/mm/ioremap.c for additional notes on this.
264 * We cheat a bit and always return uncachable areas until we've fixed
265 * the drivers to handle caching properly.
267 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
268 * doesn't exist, so everything must go through page tables.
271 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
272 pgprot_t prot, void *caller);
273 void __iounmap(void __iomem *addr);
275 static inline void __iomem *
276 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
278 return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
281 static inline void __iomem *
282 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
285 phys_addr_t last_addr = offset + size - 1;
288 * For P1 and P2 space this is trivial, as everything is already
289 * mapped. Uncached access for P1 addresses are done through P2.
290 * In the P3 case or for addresses outside of the 29-bit space,
291 * mapping must be done by the PMB or by using page tables.
293 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
294 u64 flags = pgprot_val(prot);
297 * Anything using the legacy PTEA space attributes needs
298 * to be kicked down to page table mappings.
300 if (unlikely(flags & _PAGE_PCC_MASK))
302 if (unlikely(flags & _PAGE_CACHABLE))
303 return (void __iomem *)P1SEGADDR(offset);
305 return (void __iomem *)P2SEGADDR(offset);
308 /* P4 above the store queues are always mapped. */
309 if (unlikely(offset >= P3_ADDR_MAX))
310 return (void __iomem *)P4SEGADDR(offset);
316 static inline void __iomem *
317 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
321 ret = __ioremap_trapped(offset, size);
325 ret = __ioremap_29bit(offset, size, prot);
329 return __ioremap(offset, size, prot);
332 #define __ioremap(offset, size, prot) ((void __iomem *)(offset))
333 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
334 #define __iounmap(addr) do { } while (0)
335 #endif /* CONFIG_MMU */
337 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
339 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
342 static inline void __iomem *
343 ioremap_cache(phys_addr_t offset, unsigned long size)
345 return __ioremap_mode(offset, size, PAGE_KERNEL);
347 #define ioremap_cache ioremap_cache
349 #ifdef CONFIG_HAVE_IOREMAP_PROT
350 static inline void __iomem *
351 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
353 return __ioremap_mode(offset, size, __pgprot(flags));
357 #ifdef CONFIG_IOREMAP_FIXED
358 extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
359 extern int iounmap_fixed(void __iomem *);
360 extern void ioremap_fixed_init(void);
362 static inline void __iomem *
363 ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
369 static inline void ioremap_fixed_init(void) { }
370 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
373 #define ioremap_nocache ioremap
374 #define ioremap_uc ioremap
375 #define iounmap __iounmap
378 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
381 #define xlate_dev_mem_ptr(p) __va(p)
384 * Convert a virtual cached pointer to an uncached pointer
386 #define xlate_dev_kmem_ptr(p) p
388 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
389 int valid_phys_addr_range(phys_addr_t addr, size_t size);
390 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
392 #endif /* __KERNEL__ */
394 #endif /* __ASM_SH_IO_H */