1 #ifndef __SPARC64_MMU_CONTEXT_H
2 #define __SPARC64_MMU_CONTEXT_H
4 /* Derived heavily from Linus's Alpha/AXP ASN code... */
8 #include <linux/spinlock.h>
9 #include <linux/mm_types.h>
11 #include <asm/spitfire.h>
12 #include <asm-generic/mm_hooks.h>
14 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
18 extern spinlock_t ctx_alloc_lock;
19 extern unsigned long tlb_context_cache;
20 extern unsigned long mmu_context_bmap[];
22 DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
23 void get_new_mmu_context(struct mm_struct *mm);
24 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
25 void destroy_context(struct mm_struct *mm);
27 void __tsb_context_switch(unsigned long pgd_pa,
28 struct tsb_config *tsb_base,
29 struct tsb_config *tsb_huge,
30 unsigned long tsb_descr_pa,
31 unsigned long secondary_ctx);
33 static inline void tsb_context_switch_ctx(struct mm_struct *mm,
36 __tsb_context_switch(__pa(mm->pgd),
37 &mm->context.tsb_block[MM_TSB_BASE],
38 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
39 (mm->context.tsb_block[MM_TSB_HUGE].tsb ?
40 &mm->context.tsb_block[MM_TSB_HUGE] :
45 , __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
49 #define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
51 void tsb_grow(struct mm_struct *mm,
52 unsigned long tsb_index,
53 unsigned long mm_rss);
55 void smp_tsb_sync(struct mm_struct *mm);
57 #define smp_tsb_sync(__mm) do { } while (0)
60 /* Set MMU context in the actual hardware. */
61 #define load_secondary_context(__mm) \
62 __asm__ __volatile__( \
63 "\n661: stxa %0, [%1] %2\n" \
64 " .section .sun4v_1insn_patch, \"ax\"\n" \
66 " stxa %0, [%1] %3\n" \
70 : "r" (CTX_HWBITS((__mm)->context)), \
71 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
73 void __flush_tlb_mm(unsigned long, unsigned long);
75 /* Switch the current MM context. */
76 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
78 unsigned long ctx_valid, flags;
79 int cpu = smp_processor_id();
81 per_cpu(per_cpu_secondary_mm, cpu) = mm;
82 if (unlikely(mm == &init_mm))
85 spin_lock_irqsave(&mm->context.lock, flags);
86 ctx_valid = CTX_VALID(mm->context);
88 get_new_mmu_context(mm);
90 /* We have to be extremely careful here or else we will miss
91 * a TSB grow if we switch back and forth between a kernel
92 * thread and an address space which has it's TSB size increased
93 * on another processor.
95 * It is possible to play some games in order to optimize the
96 * switch, but the safest thing to do is to unconditionally
97 * perform the secondary context load and the TSB context switch.
99 * For reference the bad case is, for address space "A":
102 * run address space A
103 * set cpu0's bits in cpu_vm_mask
104 * switch to kernel thread, borrow
105 * address space A via entry_lazy_tlb
106 * run address space A
107 * set cpu1's bit in cpu_vm_mask
108 * flush_tlb_pending()
109 * reset cpu_vm_mask to just cpu1
111 * run address space A
112 * context was valid, so skip
115 * At that point cpu0 continues to use a stale TSB, the one from
116 * before the TSB grow performed on cpu1. cpu1 did not cross-call
117 * cpu0 to update it's TSB because at that point the cpu_vm_mask
118 * only had cpu1 set in it.
120 tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
122 /* Any time a processor runs a context on an address space
123 * for the first time, we must flush that context out of the
126 if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
127 cpumask_set_cpu(cpu, mm_cpumask(mm));
128 __flush_tlb_mm(CTX_HWBITS(mm->context),
131 spin_unlock_irqrestore(&mm->context.lock, flags);
134 #define deactivate_mm(tsk,mm) do { } while (0)
135 #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
136 #endif /* !(__ASSEMBLY__) */
138 #endif /* !(__SPARC64_MMU_CONTEXT_H) */