1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/mm/init.c
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/memblock.h>
29 #include <linux/mmzone.h>
30 #include <linux/gfp.h>
34 #include <asm/pgalloc.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/iommu.h>
39 #include <linux/uaccess.h>
40 #include <asm/mmu_context.h>
41 #include <asm/tlbflush.h>
43 #include <asm/starfire.h>
45 #include <asm/spitfire.h>
46 #include <asm/sections.h>
48 #include <asm/hypervisor.h>
50 #include <asm/mdesc.h>
51 #include <asm/cpudata.h>
52 #include <asm/setup.h>
57 unsigned long kern_linear_pte_xor[4] __read_mostly;
58 static unsigned long page_cache4v_flag;
60 /* A bitmap, two bits for every 256MB of physical memory. These two
61 * bits determine what page size we use for kernel linear
62 * translations. They form an index into kern_linear_pte_xor[]. The
63 * value in the indexed slot is XOR'd with the TLB miss virtual
64 * address to form the resulting TTE. The mapping is:
71 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
72 * support 2GB pages, and hopefully future cpus will support the 16GB
73 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
74 * if these larger page sizes are not supported by the cpu.
76 * It would be nice to determine this from the machine description
77 * 'cpu' properties, but we need to have this table setup before the
78 * MDESC is initialized.
81 #ifndef CONFIG_DEBUG_PAGEALLOC
82 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
83 * Space is allocated for this right after the trap table in
84 * arch/sparc64/kernel/head.S
86 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
88 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
90 static unsigned long cpu_pgsz_mask;
92 #define MAX_BANKS 1024
94 static struct linux_prom64_registers pavail[MAX_BANKS];
95 static int pavail_ents;
97 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
99 static int cmp_p64(const void *a, const void *b)
101 const struct linux_prom64_registers *x = a, *y = b;
103 if (x->phys_addr > y->phys_addr)
105 if (x->phys_addr < y->phys_addr)
110 static void __init read_obp_memory(const char *property,
111 struct linux_prom64_registers *regs,
114 phandle node = prom_finddevice("/memory");
115 int prop_size = prom_getproplen(node, property);
118 ents = prop_size / sizeof(struct linux_prom64_registers);
119 if (ents > MAX_BANKS) {
120 prom_printf("The machine has more %s property entries than "
121 "this kernel can support (%d).\n",
122 property, MAX_BANKS);
126 ret = prom_getproperty(node, property, (char *) regs, prop_size);
128 prom_printf("Couldn't get %s property from /memory.\n",
133 /* Sanitize what we got from the firmware, by page aligning
136 for (i = 0; i < ents; i++) {
137 unsigned long base, size;
139 base = regs[i].phys_addr;
140 size = regs[i].reg_size;
143 if (base & ~PAGE_MASK) {
144 unsigned long new_base = PAGE_ALIGN(base);
146 size -= new_base - base;
147 if ((long) size < 0L)
152 /* If it is empty, simply get rid of it.
153 * This simplifies the logic of the other
154 * functions that process these arrays.
156 memmove(®s[i], ®s[i + 1],
157 (ents - i - 1) * sizeof(regs[0]));
162 regs[i].phys_addr = base;
163 regs[i].reg_size = size;
168 sort(regs, ents, sizeof(struct linux_prom64_registers),
172 /* Kernel physical address base and size in bytes. */
173 unsigned long kern_base __read_mostly;
174 unsigned long kern_size __read_mostly;
176 /* Initial ramdisk setup */
177 extern unsigned long sparc_ramdisk_image64;
178 extern unsigned int sparc_ramdisk_image;
179 extern unsigned int sparc_ramdisk_size;
181 struct page *mem_map_zero __read_mostly;
182 EXPORT_SYMBOL(mem_map_zero);
184 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
186 unsigned long sparc64_kern_pri_context __read_mostly;
187 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
188 unsigned long sparc64_kern_sec_context __read_mostly;
190 int num_kernel_image_mappings;
192 #ifdef CONFIG_DEBUG_DCFLUSH
193 atomic_t dcpage_flushes = ATOMIC_INIT(0);
195 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
199 inline void flush_dcache_page_impl(struct page *page)
201 BUG_ON(tlb_type == hypervisor);
202 #ifdef CONFIG_DEBUG_DCFLUSH
203 atomic_inc(&dcpage_flushes);
206 #ifdef DCACHE_ALIASING_POSSIBLE
207 __flush_dcache_page(page_address(page),
208 ((tlb_type == spitfire) &&
209 page_mapping(page) != NULL));
211 if (page_mapping(page) != NULL &&
212 tlb_type == spitfire)
213 __flush_icache_page(__pa(page_address(page)));
217 #define PG_dcache_dirty PG_arch_1
218 #define PG_dcache_cpu_shift 32UL
219 #define PG_dcache_cpu_mask \
220 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
222 #define dcache_dirty_cpu(page) \
223 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
225 static inline void set_dcache_dirty(struct page *page, int this_cpu)
227 unsigned long mask = this_cpu;
228 unsigned long non_cpu_bits;
230 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
231 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
233 __asm__ __volatile__("1:\n\t"
235 "and %%g7, %1, %%g1\n\t"
236 "or %%g1, %0, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
239 "bne,pn %%xcc, 1b\n\t"
242 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
246 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
248 unsigned long mask = (1UL << PG_dcache_dirty);
250 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
253 "srlx %%g7, %4, %%g1\n\t"
254 "and %%g1, %3, %%g1\n\t"
256 "bne,pn %%icc, 2f\n\t"
257 " andn %%g7, %1, %%g1\n\t"
258 "casx [%2], %%g7, %%g1\n\t"
260 "bne,pn %%xcc, 1b\n\t"
264 : "r" (cpu), "r" (mask), "r" (&page->flags),
265 "i" (PG_dcache_cpu_mask),
266 "i" (PG_dcache_cpu_shift)
270 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
272 unsigned long tsb_addr = (unsigned long) ent;
274 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
275 tsb_addr = __pa(tsb_addr);
277 __tsb_insert(tsb_addr, tag, pte);
280 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
282 static void flush_dcache(unsigned long pfn)
286 page = pfn_to_page(pfn);
288 unsigned long pg_flags;
290 pg_flags = page->flags;
291 if (pg_flags & (1UL << PG_dcache_dirty)) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
294 int this_cpu = get_cpu();
296 /* This is just to optimize away some function calls
300 flush_dcache_page_impl(page);
302 smp_flush_dcache_page_impl(page, cpu);
304 clear_dcache_dirty_cpu(page, cpu);
311 /* mm->context.lock must be held */
312 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
313 unsigned long tsb_hash_shift, unsigned long address,
316 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
322 tsb += ((address >> tsb_hash_shift) &
323 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
324 tag = (address >> 22UL);
325 tsb_insert(tsb, tag, tte);
328 #ifdef CONFIG_HUGETLB_PAGE
329 static void __init add_huge_page_size(unsigned long size)
333 if (size_to_hstate(size))
336 order = ilog2(size) - PAGE_SHIFT;
337 hugetlb_add_hstate(order);
340 static int __init hugetlbpage_init(void)
342 add_huge_page_size(1UL << HPAGE_64K_SHIFT);
343 add_huge_page_size(1UL << HPAGE_SHIFT);
344 add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
345 add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
350 arch_initcall(hugetlbpage_init);
352 static void __init pud_huge_patch(void)
354 struct pud_huge_patch_entry *p;
357 p = &__pud_huge_patch;
359 *(unsigned int *)addr = p->insn;
361 __asm__ __volatile__("flush %0" : : "r" (addr));
364 static int __init setup_hugepagesz(char *string)
366 unsigned long long hugepage_size;
367 unsigned int hugepage_shift;
368 unsigned short hv_pgsz_idx;
369 unsigned int hv_pgsz_mask;
372 hugepage_size = memparse(string, &string);
373 hugepage_shift = ilog2(hugepage_size);
375 switch (hugepage_shift) {
376 case HPAGE_16GB_SHIFT:
377 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
378 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
381 case HPAGE_2GB_SHIFT:
382 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
383 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
385 case HPAGE_256MB_SHIFT:
386 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
387 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
390 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
391 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
393 case HPAGE_64K_SHIFT:
394 hv_pgsz_mask = HV_PGSZ_MASK_64K;
395 hv_pgsz_idx = HV_PGSZ_IDX_64K;
401 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
403 pr_err("hugepagesz=%llu not supported by MMU.\n",
408 add_huge_page_size(hugepage_size);
414 __setup("hugepagesz=", setup_hugepagesz);
415 #endif /* CONFIG_HUGETLB_PAGE */
417 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
419 struct mm_struct *mm;
424 if (tlb_type != hypervisor) {
425 unsigned long pfn = pte_pfn(pte);
433 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
434 if (!pte_accessible(mm, pte))
437 spin_lock_irqsave(&mm->context.lock, flags);
440 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
441 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
442 unsigned long hugepage_size = PAGE_SIZE;
444 if (is_vm_hugetlb_page(vma))
445 hugepage_size = huge_page_size(hstate_vma(vma));
447 if (hugepage_size >= PUD_SIZE) {
448 unsigned long mask = 0x1ffc00000UL;
450 /* Transfer bits [32:22] from address to resolve
453 pte_val(pte) &= ~mask;
454 pte_val(pte) |= (address & mask);
455 } else if (hugepage_size >= PMD_SIZE) {
456 /* We are fabricating 8MB pages using 4MB
459 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
462 if (hugepage_size >= PMD_SIZE) {
463 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
464 REAL_HPAGE_SHIFT, address, pte_val(pte));
470 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
471 address, pte_val(pte));
473 spin_unlock_irqrestore(&mm->context.lock, flags);
476 void flush_dcache_page(struct page *page)
478 struct address_space *mapping;
481 if (tlb_type == hypervisor)
484 /* Do not bother with the expensive D-cache flush if it
485 * is merely the zero page. The 'bigcore' testcase in GDB
486 * causes this case to run millions of times.
488 if (page == ZERO_PAGE(0))
491 this_cpu = get_cpu();
493 mapping = page_mapping(page);
494 if (mapping && !mapping_mapped(mapping)) {
495 int dirty = test_bit(PG_dcache_dirty, &page->flags);
497 int dirty_cpu = dcache_dirty_cpu(page);
499 if (dirty_cpu == this_cpu)
501 smp_flush_dcache_page_impl(page, dirty_cpu);
503 set_dcache_dirty(page, this_cpu);
505 /* We could delay the flush for the !page_mapping
506 * case too. But that case is for exec env/arg
507 * pages and those are %99 certainly going to get
508 * faulted into the tlb (and thus flushed) anyways.
510 flush_dcache_page_impl(page);
516 EXPORT_SYMBOL(flush_dcache_page);
518 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
520 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
521 if (tlb_type == spitfire) {
524 /* This code only runs on Spitfire cpus so this is
525 * why we can assume _PAGE_PADDR_4U.
527 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
528 unsigned long paddr, mask = _PAGE_PADDR_4U;
530 if (kaddr >= PAGE_OFFSET)
531 paddr = kaddr & mask;
533 pgd_t *pgdp = pgd_offset_k(kaddr);
534 pud_t *pudp = pud_offset(pgdp, kaddr);
535 pmd_t *pmdp = pmd_offset(pudp, kaddr);
536 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
538 paddr = pte_val(*ptep) & mask;
540 __flush_icache_page(paddr);
544 EXPORT_SYMBOL(flush_icache_range);
546 void mmu_info(struct seq_file *m)
548 static const char *pgsz_strings[] = {
549 "8K", "64K", "512K", "4MB", "32MB",
550 "256MB", "2GB", "16GB",
554 if (tlb_type == cheetah)
555 seq_printf(m, "MMU Type\t: Cheetah\n");
556 else if (tlb_type == cheetah_plus)
557 seq_printf(m, "MMU Type\t: Cheetah+\n");
558 else if (tlb_type == spitfire)
559 seq_printf(m, "MMU Type\t: Spitfire\n");
560 else if (tlb_type == hypervisor)
561 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
563 seq_printf(m, "MMU Type\t: ???\n");
565 seq_printf(m, "MMU PGSZs\t: ");
567 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
568 if (cpu_pgsz_mask & (1UL << i)) {
569 seq_printf(m, "%s%s",
570 printed ? "," : "", pgsz_strings[i]);
576 #ifdef CONFIG_DEBUG_DCFLUSH
577 seq_printf(m, "DCPageFlushes\t: %d\n",
578 atomic_read(&dcpage_flushes));
580 seq_printf(m, "DCPageFlushesXC\t: %d\n",
581 atomic_read(&dcpage_flushes_xcall));
582 #endif /* CONFIG_SMP */
583 #endif /* CONFIG_DEBUG_DCFLUSH */
586 struct linux_prom_translation prom_trans[512] __read_mostly;
587 unsigned int prom_trans_ents __read_mostly;
589 unsigned long kern_locked_tte_data;
591 /* The obp translations are saved based on 8k pagesize, since obp can
592 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
593 * HI_OBP_ADDRESS range are handled in ktlb.S.
595 static inline int in_obp_range(unsigned long vaddr)
597 return (vaddr >= LOW_OBP_ADDRESS &&
598 vaddr < HI_OBP_ADDRESS);
601 static int cmp_ptrans(const void *a, const void *b)
603 const struct linux_prom_translation *x = a, *y = b;
605 if (x->virt > y->virt)
607 if (x->virt < y->virt)
612 /* Read OBP translations property into 'prom_trans[]'. */
613 static void __init read_obp_translations(void)
615 int n, node, ents, first, last, i;
617 node = prom_finddevice("/virtual-memory");
618 n = prom_getproplen(node, "translations");
619 if (unlikely(n == 0 || n == -1)) {
620 prom_printf("prom_mappings: Couldn't get size.\n");
623 if (unlikely(n > sizeof(prom_trans))) {
624 prom_printf("prom_mappings: Size %d is too big.\n", n);
628 if ((n = prom_getproperty(node, "translations",
629 (char *)&prom_trans[0],
630 sizeof(prom_trans))) == -1) {
631 prom_printf("prom_mappings: Couldn't get property.\n");
635 n = n / sizeof(struct linux_prom_translation);
639 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
642 /* Now kick out all the non-OBP entries. */
643 for (i = 0; i < ents; i++) {
644 if (in_obp_range(prom_trans[i].virt))
648 for (; i < ents; i++) {
649 if (!in_obp_range(prom_trans[i].virt))
654 for (i = 0; i < (last - first); i++) {
655 struct linux_prom_translation *src = &prom_trans[i + first];
656 struct linux_prom_translation *dest = &prom_trans[i];
660 for (; i < ents; i++) {
661 struct linux_prom_translation *dest = &prom_trans[i];
662 dest->virt = dest->size = dest->data = 0x0UL;
665 prom_trans_ents = last - first;
667 if (tlb_type == spitfire) {
668 /* Clear diag TTE bits. */
669 for (i = 0; i < prom_trans_ents; i++)
670 prom_trans[i].data &= ~0x0003fe0000000000UL;
673 /* Force execute bit on. */
674 for (i = 0; i < prom_trans_ents; i++)
675 prom_trans[i].data |= (tlb_type == hypervisor ?
676 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
679 static void __init hypervisor_tlb_lock(unsigned long vaddr,
683 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
686 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
687 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
692 static unsigned long kern_large_tte(unsigned long paddr);
694 static void __init remap_kernel(void)
696 unsigned long phys_page, tte_vaddr, tte_data;
697 int i, tlb_ent = sparc64_highest_locked_tlbent();
699 tte_vaddr = (unsigned long) KERNBASE;
700 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
701 tte_data = kern_large_tte(phys_page);
703 kern_locked_tte_data = tte_data;
705 /* Now lock us into the TLBs via Hypervisor or OBP. */
706 if (tlb_type == hypervisor) {
707 for (i = 0; i < num_kernel_image_mappings; i++) {
708 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
709 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
710 tte_vaddr += 0x400000;
711 tte_data += 0x400000;
714 for (i = 0; i < num_kernel_image_mappings; i++) {
715 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
716 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
717 tte_vaddr += 0x400000;
718 tte_data += 0x400000;
720 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
722 if (tlb_type == cheetah_plus) {
723 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
724 CTX_CHEETAH_PLUS_NUC);
725 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
726 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
731 static void __init inherit_prom_mappings(void)
733 /* Now fixup OBP's idea about where we really are mapped. */
734 printk("Remapping the kernel... ");
739 void prom_world(int enter)
744 __asm__ __volatile__("flushw");
747 void __flush_dcache_range(unsigned long start, unsigned long end)
751 if (tlb_type == spitfire) {
754 for (va = start; va < end; va += 32) {
755 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
759 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
762 for (va = start; va < end; va += 32)
763 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
767 "i" (ASI_DCACHE_INVALIDATE));
770 EXPORT_SYMBOL(__flush_dcache_range);
772 /* get_new_mmu_context() uses "cache + 1". */
773 DEFINE_SPINLOCK(ctx_alloc_lock);
774 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
775 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
776 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
777 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
778 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
780 static void mmu_context_wrap(void)
782 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
783 unsigned long new_ver, new_ctx, old_ctx;
784 struct mm_struct *mm;
787 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
789 /* Reserve kernel context */
790 set_bit(0, mmu_context_bmap);
792 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
793 if (unlikely(new_ver == 0))
794 new_ver = CTX_FIRST_VERSION;
795 tlb_context_cache = new_ver;
798 * Make sure that any new mm that are added into per_cpu_secondary_mm,
799 * are going to go through get_new_mmu_context() path.
804 * Updated versions to current on those CPUs that had valid secondary
807 for_each_online_cpu(cpu) {
809 * If a new mm is stored after we took this mm from the array,
810 * it will go into get_new_mmu_context() path, because we
811 * already bumped the version in tlb_context_cache.
813 mm = per_cpu(per_cpu_secondary_mm, cpu);
815 if (unlikely(!mm || mm == &init_mm))
818 old_ctx = mm->context.sparc64_ctx_val;
819 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
820 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
821 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
822 mm->context.sparc64_ctx_val = new_ctx;
827 /* Caller does TLB context flushing on local CPU if necessary.
828 * The caller also ensures that CTX_VALID(mm->context) is false.
830 * We must be careful about boundary cases so that we never
831 * let the user have CTX 0 (nucleus) or we ever use a CTX
832 * version of zero (and thus NO_CONTEXT would not be caught
833 * by version mis-match tests in mmu_context.h).
835 * Always invoked with interrupts disabled.
837 void get_new_mmu_context(struct mm_struct *mm)
839 unsigned long ctx, new_ctx;
840 unsigned long orig_pgsz_bits;
842 spin_lock(&ctx_alloc_lock);
844 /* wrap might have happened, test again if our context became valid */
845 if (unlikely(CTX_VALID(mm->context)))
847 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
848 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
849 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
850 if (new_ctx >= (1 << CTX_NR_BITS)) {
851 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
852 if (new_ctx >= ctx) {
857 if (mm->context.sparc64_ctx_val)
858 cpumask_clear(mm_cpumask(mm));
859 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
860 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
861 tlb_context_cache = new_ctx;
862 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
864 spin_unlock(&ctx_alloc_lock);
867 static int numa_enabled = 1;
868 static int numa_debug;
870 static int __init early_numa(char *p)
875 if (strstr(p, "off"))
878 if (strstr(p, "debug"))
883 early_param("numa", early_numa);
885 #define numadbg(f, a...) \
886 do { if (numa_debug) \
887 printk(KERN_INFO f, ## a); \
890 static void __init find_ramdisk(unsigned long phys_base)
892 #ifdef CONFIG_BLK_DEV_INITRD
893 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
894 unsigned long ramdisk_image;
896 /* Older versions of the bootloader only supported a
897 * 32-bit physical address for the ramdisk image
898 * location, stored at sparc_ramdisk_image. Newer
899 * SILO versions set sparc_ramdisk_image to zero and
900 * provide a full 64-bit physical address at
901 * sparc_ramdisk_image64.
903 ramdisk_image = sparc_ramdisk_image;
905 ramdisk_image = sparc_ramdisk_image64;
907 /* Another bootloader quirk. The bootloader normalizes
908 * the physical address to KERNBASE, so we have to
909 * factor that back out and add in the lowest valid
910 * physical page address to get the true physical address.
912 ramdisk_image -= KERNBASE;
913 ramdisk_image += phys_base;
915 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
916 ramdisk_image, sparc_ramdisk_size);
918 initrd_start = ramdisk_image;
919 initrd_end = ramdisk_image + sparc_ramdisk_size;
921 memblock_reserve(initrd_start, sparc_ramdisk_size);
923 initrd_start += PAGE_OFFSET;
924 initrd_end += PAGE_OFFSET;
929 struct node_mem_mask {
933 static struct node_mem_mask node_masks[MAX_NUMNODES];
934 static int num_node_masks;
936 #ifdef CONFIG_NEED_MULTIPLE_NODES
938 struct mdesc_mlgroup {
945 static struct mdesc_mlgroup *mlgroups;
946 static int num_mlgroups;
948 int numa_cpu_lookup_table[NR_CPUS];
949 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
951 struct mdesc_mblock {
954 u64 offset; /* RA-to-PA */
956 static struct mdesc_mblock *mblocks;
957 static int num_mblocks;
959 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
961 struct mdesc_mblock *m = NULL;
964 for (i = 0; i < num_mblocks; i++) {
967 if (addr >= m->base &&
968 addr < (m->base + m->size)) {
976 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
978 int prev_nid, new_nid;
981 for ( ; start < end; start += PAGE_SIZE) {
982 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
983 struct node_mem_mask *p = &node_masks[new_nid];
985 if ((start & p->mask) == p->match) {
992 if (new_nid == num_node_masks) {
994 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
999 if (prev_nid != new_nid)
1004 return start > end ? end : start;
1007 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
1009 u64 ret_end, pa_start, m_mask, m_match, m_end;
1010 struct mdesc_mblock *mblock;
1013 if (tlb_type != hypervisor)
1014 return memblock_nid_range_sun4u(start, end, nid);
1016 mblock = addr_to_mblock(start);
1018 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1026 pa_start = start + mblock->offset;
1030 for (_nid = 0; _nid < num_node_masks; _nid++) {
1031 struct node_mem_mask *const m = &node_masks[_nid];
1033 if ((pa_start & m->mask) == m->match) {
1040 if (num_node_masks == _nid) {
1041 /* We could not find NUMA group, so default to 0, but lets
1042 * search for latency group, so we could calculate the correct
1043 * end address that we return
1047 for (i = 0; i < num_mlgroups; i++) {
1048 struct mdesc_mlgroup *const m = &mlgroups[i];
1050 if ((pa_start & m->mask) == m->match) {
1057 if (i == num_mlgroups) {
1058 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1067 * Each latency group has match and mask, and each memory block has an
1068 * offset. An address belongs to a latency group if its address matches
1069 * the following formula: ((addr + offset) & mask) == match
1070 * It is, however, slow to check every single page if it matches a
1071 * particular latency group. As optimization we calculate end value by
1072 * using bit arithmetics.
1074 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1075 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1076 ret_end = m_end > end ? end : m_end;
1084 /* This must be invoked after performing all of the necessary
1085 * memblock_set_node() calls for 'nid'. We need to be able to get
1086 * correct data from get_pfn_range_for_nid().
1088 static void __init allocate_node_data(int nid)
1090 struct pglist_data *p;
1091 unsigned long start_pfn, end_pfn;
1092 #ifdef CONFIG_NEED_MULTIPLE_NODES
1093 unsigned long paddr;
1095 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
1097 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1100 NODE_DATA(nid) = __va(paddr);
1101 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
1103 NODE_DATA(nid)->node_id = nid;
1108 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1109 p->node_start_pfn = start_pfn;
1110 p->node_spanned_pages = end_pfn - start_pfn;
1113 static void init_node_masks_nonnuma(void)
1115 #ifdef CONFIG_NEED_MULTIPLE_NODES
1119 numadbg("Initializing tables for non-numa.\n");
1121 node_masks[0].mask = 0;
1122 node_masks[0].match = 0;
1125 #ifdef CONFIG_NEED_MULTIPLE_NODES
1126 for (i = 0; i < NR_CPUS; i++)
1127 numa_cpu_lookup_table[i] = 0;
1129 cpumask_setall(&numa_cpumask_lookup_table[0]);
1133 #ifdef CONFIG_NEED_MULTIPLE_NODES
1134 struct pglist_data *node_data[MAX_NUMNODES];
1136 EXPORT_SYMBOL(numa_cpu_lookup_table);
1137 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1138 EXPORT_SYMBOL(node_data);
1140 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1145 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1146 u64 target = mdesc_arc_target(md, arc);
1149 val = mdesc_get_property(md, target,
1150 "cfg-handle", NULL);
1151 if (val && *val == cfg_handle)
1157 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1160 u64 arc, candidate, best_latency = ~(u64)0;
1162 candidate = MDESC_NODE_NULL;
1163 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1164 u64 target = mdesc_arc_target(md, arc);
1165 const char *name = mdesc_node_name(md, target);
1168 if (strcmp(name, "pio-latency-group"))
1171 val = mdesc_get_property(md, target, "latency", NULL);
1175 if (*val < best_latency) {
1177 best_latency = *val;
1181 if (candidate == MDESC_NODE_NULL)
1184 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1187 int of_node_to_nid(struct device_node *dp)
1189 const struct linux_prom64_registers *regs;
1190 struct mdesc_handle *md;
1195 /* This is the right thing to do on currently supported
1196 * SUN4U NUMA platforms as well, as the PCI controller does
1197 * not sit behind any particular memory controller.
1202 regs = of_get_property(dp, "reg", NULL);
1206 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1212 mdesc_for_each_node_by_name(md, grp, "group") {
1213 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1225 static void __init add_node_ranges(void)
1227 struct memblock_region *reg;
1228 unsigned long prev_max;
1231 prev_max = memblock.memory.max;
1233 for_each_memblock(memory, reg) {
1234 unsigned long size = reg->size;
1235 unsigned long start, end;
1239 while (start < end) {
1240 unsigned long this_end;
1243 this_end = memblock_nid_range(start, end, &nid);
1245 numadbg("Setting memblock NUMA node nid[%d] "
1246 "start[%lx] end[%lx]\n",
1247 nid, start, this_end);
1249 memblock_set_node(start, this_end - start,
1250 &memblock.memory, nid);
1251 if (memblock.memory.max != prev_max)
1252 goto memblock_resized;
1258 static int __init grab_mlgroups(struct mdesc_handle *md)
1260 unsigned long paddr;
1264 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1269 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1274 mlgroups = __va(paddr);
1275 num_mlgroups = count;
1278 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1279 struct mdesc_mlgroup *m = &mlgroups[count++];
1284 val = mdesc_get_property(md, node, "latency", NULL);
1286 val = mdesc_get_property(md, node, "address-match", NULL);
1288 val = mdesc_get_property(md, node, "address-mask", NULL);
1291 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1292 "match[%llx] mask[%llx]\n",
1293 count - 1, m->node, m->latency, m->match, m->mask);
1299 static int __init grab_mblocks(struct mdesc_handle *md)
1301 unsigned long paddr;
1305 mdesc_for_each_node_by_name(md, node, "mblock")
1310 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1315 mblocks = __va(paddr);
1316 num_mblocks = count;
1319 mdesc_for_each_node_by_name(md, node, "mblock") {
1320 struct mdesc_mblock *m = &mblocks[count++];
1323 val = mdesc_get_property(md, node, "base", NULL);
1325 val = mdesc_get_property(md, node, "size", NULL);
1327 val = mdesc_get_property(md, node,
1328 "address-congruence-offset", NULL);
1330 /* The address-congruence-offset property is optional.
1331 * Explicity zero it be identifty this.
1338 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1339 count - 1, m->base, m->size, m->offset);
1345 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1346 u64 grp, cpumask_t *mask)
1350 cpumask_clear(mask);
1352 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1353 u64 target = mdesc_arc_target(md, arc);
1354 const char *name = mdesc_node_name(md, target);
1357 if (strcmp(name, "cpu"))
1359 id = mdesc_get_property(md, target, "id", NULL);
1360 if (*id < nr_cpu_ids)
1361 cpumask_set_cpu(*id, mask);
1365 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1369 for (i = 0; i < num_mlgroups; i++) {
1370 struct mdesc_mlgroup *m = &mlgroups[i];
1371 if (m->node == node)
1377 int __node_distance(int from, int to)
1379 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1380 pr_warn("Returning default NUMA distance value for %d->%d\n",
1382 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1384 return numa_latency[from][to];
1387 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1391 for (i = 0; i < MAX_NUMNODES; i++) {
1392 struct node_mem_mask *n = &node_masks[i];
1394 if ((grp->mask == n->mask) && (grp->match == n->match))
1400 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1405 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1407 u64 target = mdesc_arc_target(md, arc);
1408 struct mdesc_mlgroup *m = find_mlgroup(target);
1412 tnode = find_best_numa_node_for_mlgroup(m);
1413 if (tnode == MAX_NUMNODES)
1415 numa_latency[index][tnode] = m->latency;
1419 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1422 struct mdesc_mlgroup *candidate = NULL;
1423 u64 arc, best_latency = ~(u64)0;
1424 struct node_mem_mask *n;
1426 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1427 u64 target = mdesc_arc_target(md, arc);
1428 struct mdesc_mlgroup *m = find_mlgroup(target);
1431 if (m->latency < best_latency) {
1433 best_latency = m->latency;
1439 if (num_node_masks != index) {
1440 printk(KERN_ERR "Inconsistent NUMA state, "
1441 "index[%d] != num_node_masks[%d]\n",
1442 index, num_node_masks);
1446 n = &node_masks[num_node_masks++];
1448 n->mask = candidate->mask;
1449 n->match = candidate->match;
1451 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1452 index, n->mask, n->match, candidate->latency);
1457 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1463 numa_parse_mdesc_group_cpus(md, grp, &mask);
1465 for_each_cpu(cpu, &mask)
1466 numa_cpu_lookup_table[cpu] = index;
1467 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1470 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1471 for_each_cpu(cpu, &mask)
1476 return numa_attach_mlgroup(md, grp, index);
1479 static int __init numa_parse_mdesc(void)
1481 struct mdesc_handle *md = mdesc_grab();
1482 int i, j, err, count;
1485 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1486 if (node == MDESC_NODE_NULL) {
1491 err = grab_mblocks(md);
1495 err = grab_mlgroups(md);
1500 mdesc_for_each_node_by_name(md, node, "group") {
1501 err = numa_parse_mdesc_group(md, node, count);
1508 mdesc_for_each_node_by_name(md, node, "group") {
1509 find_numa_latencies_for_group(md, node, count);
1513 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1514 for (i = 0; i < MAX_NUMNODES; i++) {
1515 u64 self_latency = numa_latency[i][i];
1517 for (j = 0; j < MAX_NUMNODES; j++) {
1518 numa_latency[i][j] =
1519 (numa_latency[i][j] * LOCAL_DISTANCE) /
1526 for (i = 0; i < num_node_masks; i++) {
1527 allocate_node_data(i);
1537 static int __init numa_parse_jbus(void)
1539 unsigned long cpu, index;
1541 /* NUMA node id is encoded in bits 36 and higher, and there is
1542 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1545 for_each_present_cpu(cpu) {
1546 numa_cpu_lookup_table[cpu] = index;
1547 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1548 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1549 node_masks[index].match = cpu << 36UL;
1553 num_node_masks = index;
1557 for (index = 0; index < num_node_masks; index++) {
1558 allocate_node_data(index);
1559 node_set_online(index);
1565 static int __init numa_parse_sun4u(void)
1567 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1570 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1571 if ((ver >> 32UL) == __JALAPENO_ID ||
1572 (ver >> 32UL) == __SERRANO_ID)
1573 return numa_parse_jbus();
1578 static int __init bootmem_init_numa(void)
1583 numadbg("bootmem_init_numa()\n");
1585 /* Some sane defaults for numa latency values */
1586 for (i = 0; i < MAX_NUMNODES; i++) {
1587 for (j = 0; j < MAX_NUMNODES; j++)
1588 numa_latency[i][j] = (i == j) ?
1589 LOCAL_DISTANCE : REMOTE_DISTANCE;
1593 if (tlb_type == hypervisor)
1594 err = numa_parse_mdesc();
1596 err = numa_parse_sun4u();
1603 static int bootmem_init_numa(void)
1610 static void __init bootmem_init_nonnuma(void)
1612 unsigned long top_of_ram = memblock_end_of_DRAM();
1613 unsigned long total_ram = memblock_phys_mem_size();
1615 numadbg("bootmem_init_nonnuma()\n");
1617 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1618 top_of_ram, total_ram);
1619 printk(KERN_INFO "Memory hole size: %ldMB\n",
1620 (top_of_ram - total_ram) >> 20);
1622 init_node_masks_nonnuma();
1623 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1624 allocate_node_data(0);
1628 static unsigned long __init bootmem_init(unsigned long phys_base)
1630 unsigned long end_pfn;
1632 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1633 max_pfn = max_low_pfn = end_pfn;
1634 min_low_pfn = (phys_base >> PAGE_SHIFT);
1636 if (bootmem_init_numa() < 0)
1637 bootmem_init_nonnuma();
1639 /* Dump memblock with node info. */
1640 memblock_dump_all();
1642 /* XXX cpu notifier XXX */
1644 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1650 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1651 static int pall_ents __initdata;
1653 static unsigned long max_phys_bits = 40;
1655 bool kern_addr_valid(unsigned long addr)
1662 if ((long)addr < 0L) {
1663 unsigned long pa = __pa(addr);
1665 if ((pa >> max_phys_bits) != 0UL)
1668 return pfn_valid(pa >> PAGE_SHIFT);
1671 if (addr >= (unsigned long) KERNBASE &&
1672 addr < (unsigned long)&_end)
1675 pgd = pgd_offset_k(addr);
1679 pud = pud_offset(pgd, addr);
1683 if (pud_large(*pud))
1684 return pfn_valid(pud_pfn(*pud));
1686 pmd = pmd_offset(pud, addr);
1690 if (pmd_large(*pmd))
1691 return pfn_valid(pmd_pfn(*pmd));
1693 pte = pte_offset_kernel(pmd, addr);
1697 return pfn_valid(pte_pfn(*pte));
1699 EXPORT_SYMBOL(kern_addr_valid);
1701 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1705 const unsigned long mask16gb = (1UL << 34) - 1UL;
1706 u64 pte_val = vstart;
1708 /* Each PUD is 8GB */
1709 if ((vstart & mask16gb) ||
1710 (vend - vstart <= mask16gb)) {
1711 pte_val ^= kern_linear_pte_xor[2];
1712 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1714 return vstart + PUD_SIZE;
1717 pte_val ^= kern_linear_pte_xor[3];
1718 pte_val |= _PAGE_PUD_HUGE;
1720 vend = vstart + mask16gb + 1UL;
1721 while (vstart < vend) {
1722 pud_val(*pud) = pte_val;
1724 pte_val += PUD_SIZE;
1731 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1734 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1740 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1744 const unsigned long mask256mb = (1UL << 28) - 1UL;
1745 const unsigned long mask2gb = (1UL << 31) - 1UL;
1746 u64 pte_val = vstart;
1748 /* Each PMD is 8MB */
1749 if ((vstart & mask256mb) ||
1750 (vend - vstart <= mask256mb)) {
1751 pte_val ^= kern_linear_pte_xor[0];
1752 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1754 return vstart + PMD_SIZE;
1757 if ((vstart & mask2gb) ||
1758 (vend - vstart <= mask2gb)) {
1759 pte_val ^= kern_linear_pte_xor[1];
1760 pte_val |= _PAGE_PMD_HUGE;
1761 vend = vstart + mask256mb + 1UL;
1763 pte_val ^= kern_linear_pte_xor[2];
1764 pte_val |= _PAGE_PMD_HUGE;
1765 vend = vstart + mask2gb + 1UL;
1768 while (vstart < vend) {
1769 pmd_val(*pmd) = pte_val;
1771 pte_val += PMD_SIZE;
1779 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1782 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1788 static unsigned long __ref kernel_map_range(unsigned long pstart,
1789 unsigned long pend, pgprot_t prot,
1792 unsigned long vstart = PAGE_OFFSET + pstart;
1793 unsigned long vend = PAGE_OFFSET + pend;
1794 unsigned long alloc_bytes = 0UL;
1796 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1797 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1802 while (vstart < vend) {
1803 unsigned long this_end, paddr = __pa(vstart);
1804 pgd_t *pgd = pgd_offset_k(vstart);
1809 if (pgd_none(*pgd)) {
1812 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1813 alloc_bytes += PAGE_SIZE;
1814 pgd_populate(&init_mm, pgd, new);
1816 pud = pud_offset(pgd, vstart);
1817 if (pud_none(*pud)) {
1820 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1821 vstart = kernel_map_hugepud(vstart, vend, pud);
1824 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1825 alloc_bytes += PAGE_SIZE;
1826 pud_populate(&init_mm, pud, new);
1829 pmd = pmd_offset(pud, vstart);
1830 if (pmd_none(*pmd)) {
1833 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1834 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1837 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1838 alloc_bytes += PAGE_SIZE;
1839 pmd_populate_kernel(&init_mm, pmd, new);
1842 pte = pte_offset_kernel(pmd, vstart);
1843 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1844 if (this_end > vend)
1847 while (vstart < this_end) {
1848 pte_val(*pte) = (paddr | pgprot_val(prot));
1850 vstart += PAGE_SIZE;
1859 static void __init flush_all_kernel_tsbs(void)
1863 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1864 struct tsb *ent = &swapper_tsb[i];
1866 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1868 #ifndef CONFIG_DEBUG_PAGEALLOC
1869 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1870 struct tsb *ent = &swapper_4m_tsb[i];
1872 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1877 extern unsigned int kvmap_linear_patch[1];
1879 static void __init kernel_physical_mapping_init(void)
1881 unsigned long i, mem_alloced = 0UL;
1882 bool use_huge = true;
1884 #ifdef CONFIG_DEBUG_PAGEALLOC
1887 for (i = 0; i < pall_ents; i++) {
1888 unsigned long phys_start, phys_end;
1890 phys_start = pall[i].phys_addr;
1891 phys_end = phys_start + pall[i].reg_size;
1893 mem_alloced += kernel_map_range(phys_start, phys_end,
1894 PAGE_KERNEL, use_huge);
1897 printk("Allocated %ld bytes for kernel page tables.\n",
1900 kvmap_linear_patch[0] = 0x01000000; /* nop */
1901 flushi(&kvmap_linear_patch[0]);
1903 flush_all_kernel_tsbs();
1908 #ifdef CONFIG_DEBUG_PAGEALLOC
1909 void __kernel_map_pages(struct page *page, int numpages, int enable)
1911 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1912 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1914 kernel_map_range(phys_start, phys_end,
1915 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1917 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1918 PAGE_OFFSET + phys_end);
1920 /* we should perform an IPI and flush all tlbs,
1921 * but that can deadlock->flush only current cpu.
1923 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1924 PAGE_OFFSET + phys_end);
1928 unsigned long __init find_ecache_flush_span(unsigned long size)
1932 for (i = 0; i < pavail_ents; i++) {
1933 if (pavail[i].reg_size >= size)
1934 return pavail[i].phys_addr;
1940 unsigned long PAGE_OFFSET;
1941 EXPORT_SYMBOL(PAGE_OFFSET);
1943 unsigned long VMALLOC_END = 0x0000010000000000UL;
1944 EXPORT_SYMBOL(VMALLOC_END);
1946 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1947 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1949 static void __init setup_page_offset(void)
1951 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1952 /* Cheetah/Panther support a full 64-bit virtual
1953 * address, so we can use all that our page tables
1956 sparc64_va_hole_top = 0xfff0000000000000UL;
1957 sparc64_va_hole_bottom = 0x0010000000000000UL;
1960 } else if (tlb_type == hypervisor) {
1961 switch (sun4v_chip_type) {
1962 case SUN4V_CHIP_NIAGARA1:
1963 case SUN4V_CHIP_NIAGARA2:
1964 /* T1 and T2 support 48-bit virtual addresses. */
1965 sparc64_va_hole_top = 0xffff800000000000UL;
1966 sparc64_va_hole_bottom = 0x0000800000000000UL;
1970 case SUN4V_CHIP_NIAGARA3:
1971 /* T3 supports 48-bit virtual addresses. */
1972 sparc64_va_hole_top = 0xffff800000000000UL;
1973 sparc64_va_hole_bottom = 0x0000800000000000UL;
1977 case SUN4V_CHIP_NIAGARA4:
1978 case SUN4V_CHIP_NIAGARA5:
1979 case SUN4V_CHIP_SPARC64X:
1980 case SUN4V_CHIP_SPARC_M6:
1981 /* T4 and later support 52-bit virtual addresses. */
1982 sparc64_va_hole_top = 0xfff8000000000000UL;
1983 sparc64_va_hole_bottom = 0x0008000000000000UL;
1986 case SUN4V_CHIP_SPARC_M7:
1987 case SUN4V_CHIP_SPARC_SN:
1988 /* M7 and later support 52-bit virtual addresses. */
1989 sparc64_va_hole_top = 0xfff8000000000000UL;
1990 sparc64_va_hole_bottom = 0x0008000000000000UL;
1993 case SUN4V_CHIP_SPARC_M8:
1995 /* M8 and later support 54-bit virtual addresses.
1996 * However, restricting M8 and above VA bits to 53
1997 * as 4-level page table cannot support more than
2000 sparc64_va_hole_top = 0xfff0000000000000UL;
2001 sparc64_va_hole_bottom = 0x0010000000000000UL;
2007 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2008 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2013 PAGE_OFFSET = sparc64_va_hole_top;
2014 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2015 (sparc64_va_hole_bottom >> 2));
2017 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2018 PAGE_OFFSET, max_phys_bits);
2019 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2020 VMALLOC_START, VMALLOC_END);
2021 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2022 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2025 static void __init tsb_phys_patch(void)
2027 struct tsb_ldquad_phys_patch_entry *pquad;
2028 struct tsb_phys_patch_entry *p;
2030 pquad = &__tsb_ldquad_phys_patch;
2031 while (pquad < &__tsb_ldquad_phys_patch_end) {
2032 unsigned long addr = pquad->addr;
2034 if (tlb_type == hypervisor)
2035 *(unsigned int *) addr = pquad->sun4v_insn;
2037 *(unsigned int *) addr = pquad->sun4u_insn;
2039 __asm__ __volatile__("flush %0"
2046 p = &__tsb_phys_patch;
2047 while (p < &__tsb_phys_patch_end) {
2048 unsigned long addr = p->addr;
2050 *(unsigned int *) addr = p->insn;
2052 __asm__ __volatile__("flush %0"
2060 /* Don't mark as init, we give this to the Hypervisor. */
2061 #ifndef CONFIG_DEBUG_PAGEALLOC
2062 #define NUM_KTSB_DESCR 2
2064 #define NUM_KTSB_DESCR 1
2066 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2068 /* The swapper TSBs are loaded with a base sequence of:
2070 * sethi %uhi(SYMBOL), REG1
2071 * sethi %hi(SYMBOL), REG2
2072 * or REG1, %ulo(SYMBOL), REG1
2073 * or REG2, %lo(SYMBOL), REG2
2074 * sllx REG1, 32, REG1
2075 * or REG1, REG2, REG1
2077 * When we use physical addressing for the TSB accesses, we patch the
2078 * first four instructions in the above sequence.
2081 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2083 unsigned long high_bits, low_bits;
2085 high_bits = (pa >> 32) & 0xffffffff;
2086 low_bits = (pa >> 0) & 0xffffffff;
2088 while (start < end) {
2089 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2091 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2092 __asm__ __volatile__("flush %0" : : "r" (ia));
2094 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2095 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2097 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2098 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2100 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2101 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2107 static void ktsb_phys_patch(void)
2109 extern unsigned int __swapper_tsb_phys_patch;
2110 extern unsigned int __swapper_tsb_phys_patch_end;
2111 unsigned long ktsb_pa;
2113 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2114 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2115 &__swapper_tsb_phys_patch_end, ktsb_pa);
2116 #ifndef CONFIG_DEBUG_PAGEALLOC
2118 extern unsigned int __swapper_4m_tsb_phys_patch;
2119 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2120 ktsb_pa = (kern_base +
2121 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2122 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2123 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2128 static void __init sun4v_ktsb_init(void)
2130 unsigned long ktsb_pa;
2132 /* First KTSB for PAGE_SIZE mappings. */
2133 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2135 switch (PAGE_SIZE) {
2138 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2139 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2143 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2144 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2148 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2149 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2152 case 4 * 1024 * 1024:
2153 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2154 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2158 ktsb_descr[0].assoc = 1;
2159 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2160 ktsb_descr[0].ctx_idx = 0;
2161 ktsb_descr[0].tsb_base = ktsb_pa;
2162 ktsb_descr[0].resv = 0;
2164 #ifndef CONFIG_DEBUG_PAGEALLOC
2165 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2166 ktsb_pa = (kern_base +
2167 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2169 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2170 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2171 HV_PGSZ_MASK_256MB |
2173 HV_PGSZ_MASK_16GB) &
2175 ktsb_descr[1].assoc = 1;
2176 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2177 ktsb_descr[1].ctx_idx = 0;
2178 ktsb_descr[1].tsb_base = ktsb_pa;
2179 ktsb_descr[1].resv = 0;
2183 void sun4v_ktsb_register(void)
2185 unsigned long pa, ret;
2187 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2189 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2191 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2192 "errors with %lx\n", pa, ret);
2197 static void __init sun4u_linear_pte_xor_finalize(void)
2199 #ifndef CONFIG_DEBUG_PAGEALLOC
2200 /* This is where we would add Panther support for
2201 * 32MB and 256MB pages.
2206 static void __init sun4v_linear_pte_xor_finalize(void)
2208 unsigned long pagecv_flag;
2210 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2211 * enables MCD error. Do not set bit 9 on M7 processor.
2213 switch (sun4v_chip_type) {
2214 case SUN4V_CHIP_SPARC_M7:
2215 case SUN4V_CHIP_SPARC_M8:
2216 case SUN4V_CHIP_SPARC_SN:
2220 pagecv_flag = _PAGE_CV_4V;
2223 #ifndef CONFIG_DEBUG_PAGEALLOC
2224 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2225 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2227 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2228 _PAGE_P_4V | _PAGE_W_4V);
2230 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2233 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2234 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2236 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2237 _PAGE_P_4V | _PAGE_W_4V);
2239 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2242 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2243 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2245 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2246 _PAGE_P_4V | _PAGE_W_4V);
2248 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2253 /* paging_init() sets up the page tables */
2255 static unsigned long last_valid_pfn;
2257 static void sun4u_pgprot_init(void);
2258 static void sun4v_pgprot_init(void);
2260 static phys_addr_t __init available_memory(void)
2262 phys_addr_t available = 0ULL;
2263 phys_addr_t pa_start, pa_end;
2266 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2268 available = available + (pa_end - pa_start);
2273 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2274 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2275 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2276 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2277 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2278 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2280 /* We need to exclude reserved regions. This exclusion will include
2281 * vmlinux and initrd. To be more precise the initrd size could be used to
2282 * compute a new lower limit because it is freed later during initialization.
2284 static void __init reduce_memory(phys_addr_t limit_ram)
2286 phys_addr_t avail_ram = available_memory();
2287 phys_addr_t pa_start, pa_end;
2290 if (limit_ram >= avail_ram)
2293 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2295 phys_addr_t region_size = pa_end - pa_start;
2296 phys_addr_t clip_start = pa_start;
2298 avail_ram = avail_ram - region_size;
2299 /* Are we consuming too much? */
2300 if (avail_ram < limit_ram) {
2301 phys_addr_t give_back = limit_ram - avail_ram;
2303 region_size = region_size - give_back;
2304 clip_start = clip_start + give_back;
2307 memblock_remove(clip_start, region_size);
2309 if (avail_ram <= limit_ram)
2315 void __init paging_init(void)
2317 unsigned long end_pfn, shift, phys_base;
2318 unsigned long real_end, i;
2320 setup_page_offset();
2322 /* These build time checkes make sure that the dcache_dirty_cpu()
2323 * page->flags usage will work.
2325 * When a page gets marked as dcache-dirty, we store the
2326 * cpu number starting at bit 32 in the page->flags. Also,
2327 * functions like clear_dcache_dirty_cpu use the cpu mask
2328 * in 13-bit signed-immediate instruction fields.
2332 * Page flags must not reach into upper 32 bits that are used
2333 * for the cpu number
2335 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2338 * The bit fields placed in the high range must not reach below
2339 * the 32 bit boundary. Otherwise we cannot place the cpu field
2340 * at the 32 bit boundary.
2342 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2343 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2345 BUILD_BUG_ON(NR_CPUS > 4096);
2347 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2348 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2350 /* Invalidate both kernel TSBs. */
2351 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2352 #ifndef CONFIG_DEBUG_PAGEALLOC
2353 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2356 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2357 * bit on M7 processor. This is a conflicting usage of the same
2358 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2359 * Detection error on all pages and this will lead to problems
2360 * later. Kernel does not run with MCD enabled and hence rest
2361 * of the required steps to fully configure memory corruption
2362 * detection are not taken. We need to ensure TTE.mcde is not
2363 * set on M7 processor. Compute the value of cacheability
2364 * flag for use later taking this into consideration.
2366 switch (sun4v_chip_type) {
2367 case SUN4V_CHIP_SPARC_M7:
2368 case SUN4V_CHIP_SPARC_M8:
2369 case SUN4V_CHIP_SPARC_SN:
2370 page_cache4v_flag = _PAGE_CP_4V;
2373 page_cache4v_flag = _PAGE_CACHE_4V;
2377 if (tlb_type == hypervisor)
2378 sun4v_pgprot_init();
2380 sun4u_pgprot_init();
2382 if (tlb_type == cheetah_plus ||
2383 tlb_type == hypervisor) {
2388 if (tlb_type == hypervisor)
2389 sun4v_patch_tlb_handlers();
2391 /* Find available physical memory...
2393 * Read it twice in order to work around a bug in openfirmware.
2394 * The call to grab this table itself can cause openfirmware to
2395 * allocate memory, which in turn can take away some space from
2396 * the list of available memory. Reading it twice makes sure
2397 * we really do get the final value.
2399 read_obp_translations();
2400 read_obp_memory("reg", &pall[0], &pall_ents);
2401 read_obp_memory("available", &pavail[0], &pavail_ents);
2402 read_obp_memory("available", &pavail[0], &pavail_ents);
2404 phys_base = 0xffffffffffffffffUL;
2405 for (i = 0; i < pavail_ents; i++) {
2406 phys_base = min(phys_base, pavail[i].phys_addr);
2407 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2410 memblock_reserve(kern_base, kern_size);
2412 find_ramdisk(phys_base);
2414 if (cmdline_memory_size)
2415 reduce_memory(cmdline_memory_size);
2417 memblock_allow_resize();
2418 memblock_dump_all();
2420 set_bit(0, mmu_context_bmap);
2422 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2424 real_end = (unsigned long)_end;
2425 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2426 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2427 num_kernel_image_mappings);
2429 /* Set kernel pgd to upper alias so physical page computations
2432 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2434 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2436 inherit_prom_mappings();
2438 /* Ok, we can use our TLB miss and window trap handlers safely. */
2443 prom_build_devicetree();
2444 of_populate_present_mask();
2446 of_fill_in_cpu_data();
2449 if (tlb_type == hypervisor) {
2451 mdesc_populate_present_mask(cpu_all_mask);
2453 mdesc_fill_in_cpu_data(cpu_all_mask);
2455 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2457 sun4v_linear_pte_xor_finalize();
2460 sun4v_ktsb_register();
2462 unsigned long impl, ver;
2464 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2465 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2467 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2468 impl = ((ver >> 32) & 0xffff);
2469 if (impl == PANTHER_IMPL)
2470 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2471 HV_PGSZ_MASK_256MB);
2473 sun4u_linear_pte_xor_finalize();
2476 /* Flush the TLBs and the 4M TSB so that the updated linear
2477 * pte XOR settings are realized for all mappings.
2480 #ifndef CONFIG_DEBUG_PAGEALLOC
2481 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2485 /* Setup bootmem... */
2486 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2488 kernel_physical_mapping_init();
2491 unsigned long max_zone_pfns[MAX_NR_ZONES];
2493 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2495 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2497 free_area_init_nodes(max_zone_pfns);
2500 printk("Booting Linux...\n");
2503 int page_in_phys_avail(unsigned long paddr)
2509 for (i = 0; i < pavail_ents; i++) {
2510 unsigned long start, end;
2512 start = pavail[i].phys_addr;
2513 end = start + pavail[i].reg_size;
2515 if (paddr >= start && paddr < end)
2518 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2520 #ifdef CONFIG_BLK_DEV_INITRD
2521 if (paddr >= __pa(initrd_start) &&
2522 paddr < __pa(PAGE_ALIGN(initrd_end)))
2529 static void __init register_page_bootmem_info(void)
2531 #ifdef CONFIG_NEED_MULTIPLE_NODES
2534 for_each_online_node(i)
2535 if (NODE_DATA(i)->node_spanned_pages)
2536 register_page_bootmem_info_node(NODE_DATA(i));
2539 void __init mem_init(void)
2541 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2546 * Must be done after boot memory is put on freelist, because here we
2547 * might set fields in deferred struct pages that have not yet been
2548 * initialized, and free_all_bootmem() initializes all the reserved
2549 * deferred pages for us.
2551 register_page_bootmem_info();
2554 * Set up the zero page, mark it reserved, so that page count
2555 * is not manipulated when freeing the page from user ptes.
2557 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2558 if (mem_map_zero == NULL) {
2559 prom_printf("paging_init: Cannot alloc zero page.\n");
2562 mark_page_reserved(mem_map_zero);
2564 mem_init_print_info(NULL);
2566 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2567 cheetah_ecache_flush_init();
2570 void free_initmem(void)
2572 unsigned long addr, initend;
2575 /* If the physical memory maps were trimmed by kernel command
2576 * line options, don't even try freeing this initmem stuff up.
2577 * The kernel image could have been in the trimmed out region
2578 * and if so the freeing below will free invalid page structs.
2580 if (cmdline_memory_size)
2584 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2586 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2587 initend = (unsigned long)(__init_end) & PAGE_MASK;
2588 for (; addr < initend; addr += PAGE_SIZE) {
2592 ((unsigned long) __va(kern_base)) -
2593 ((unsigned long) KERNBASE));
2594 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2597 free_reserved_page(virt_to_page(page));
2601 #ifdef CONFIG_BLK_DEV_INITRD
2602 void free_initrd_mem(unsigned long start, unsigned long end)
2604 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2609 pgprot_t PAGE_KERNEL __read_mostly;
2610 EXPORT_SYMBOL(PAGE_KERNEL);
2612 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2613 pgprot_t PAGE_COPY __read_mostly;
2615 pgprot_t PAGE_SHARED __read_mostly;
2616 EXPORT_SYMBOL(PAGE_SHARED);
2618 unsigned long pg_iobits __read_mostly;
2620 unsigned long _PAGE_IE __read_mostly;
2621 EXPORT_SYMBOL(_PAGE_IE);
2623 unsigned long _PAGE_E __read_mostly;
2624 EXPORT_SYMBOL(_PAGE_E);
2626 unsigned long _PAGE_CACHE __read_mostly;
2627 EXPORT_SYMBOL(_PAGE_CACHE);
2629 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2630 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2633 unsigned long pte_base;
2635 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2636 _PAGE_CP_4U | _PAGE_CV_4U |
2637 _PAGE_P_4U | _PAGE_W_4U);
2638 if (tlb_type == hypervisor)
2639 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2640 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2642 pte_base |= _PAGE_PMD_HUGE;
2644 vstart = vstart & PMD_MASK;
2645 vend = ALIGN(vend, PMD_SIZE);
2646 for (; vstart < vend; vstart += PMD_SIZE) {
2647 pgd_t *pgd = pgd_offset_k(vstart);
2652 if (pgd_none(*pgd)) {
2653 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2657 pgd_populate(&init_mm, pgd, new);
2660 pud = pud_offset(pgd, vstart);
2661 if (pud_none(*pud)) {
2662 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2666 pud_populate(&init_mm, pud, new);
2669 pmd = pmd_offset(pud, vstart);
2671 pte = pmd_val(*pmd);
2672 if (!(pte & _PAGE_VALID)) {
2673 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2678 pmd_val(*pmd) = pte_base | __pa(block);
2685 void vmemmap_free(unsigned long start, unsigned long end)
2688 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2690 static void prot_init_common(unsigned long page_none,
2691 unsigned long page_shared,
2692 unsigned long page_copy,
2693 unsigned long page_readonly,
2694 unsigned long page_exec_bit)
2696 PAGE_COPY = __pgprot(page_copy);
2697 PAGE_SHARED = __pgprot(page_shared);
2699 protection_map[0x0] = __pgprot(page_none);
2700 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2701 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2702 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2703 protection_map[0x4] = __pgprot(page_readonly);
2704 protection_map[0x5] = __pgprot(page_readonly);
2705 protection_map[0x6] = __pgprot(page_copy);
2706 protection_map[0x7] = __pgprot(page_copy);
2707 protection_map[0x8] = __pgprot(page_none);
2708 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2709 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2710 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2711 protection_map[0xc] = __pgprot(page_readonly);
2712 protection_map[0xd] = __pgprot(page_readonly);
2713 protection_map[0xe] = __pgprot(page_shared);
2714 protection_map[0xf] = __pgprot(page_shared);
2717 static void __init sun4u_pgprot_init(void)
2719 unsigned long page_none, page_shared, page_copy, page_readonly;
2720 unsigned long page_exec_bit;
2723 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2724 _PAGE_CACHE_4U | _PAGE_P_4U |
2725 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2727 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2728 _PAGE_CACHE_4U | _PAGE_P_4U |
2729 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2730 _PAGE_EXEC_4U | _PAGE_L_4U);
2732 _PAGE_IE = _PAGE_IE_4U;
2733 _PAGE_E = _PAGE_E_4U;
2734 _PAGE_CACHE = _PAGE_CACHE_4U;
2736 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2737 __ACCESS_BITS_4U | _PAGE_E_4U);
2739 #ifdef CONFIG_DEBUG_PAGEALLOC
2740 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2742 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2745 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2746 _PAGE_P_4U | _PAGE_W_4U);
2748 for (i = 1; i < 4; i++)
2749 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2751 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2752 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2753 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2756 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2757 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2758 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2759 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2760 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2761 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2762 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2764 page_exec_bit = _PAGE_EXEC_4U;
2766 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2770 static void __init sun4v_pgprot_init(void)
2772 unsigned long page_none, page_shared, page_copy, page_readonly;
2773 unsigned long page_exec_bit;
2776 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2777 page_cache4v_flag | _PAGE_P_4V |
2778 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2780 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2782 _PAGE_IE = _PAGE_IE_4V;
2783 _PAGE_E = _PAGE_E_4V;
2784 _PAGE_CACHE = page_cache4v_flag;
2786 #ifdef CONFIG_DEBUG_PAGEALLOC
2787 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2789 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2792 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2795 for (i = 1; i < 4; i++)
2796 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2798 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2799 __ACCESS_BITS_4V | _PAGE_E_4V);
2801 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2802 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2803 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2804 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2806 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2807 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2808 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2809 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2810 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2811 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2812 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2814 page_exec_bit = _PAGE_EXEC_4V;
2816 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2820 unsigned long pte_sz_bits(unsigned long sz)
2822 if (tlb_type == hypervisor) {
2826 return _PAGE_SZ8K_4V;
2828 return _PAGE_SZ64K_4V;
2830 return _PAGE_SZ512K_4V;
2831 case 4 * 1024 * 1024:
2832 return _PAGE_SZ4MB_4V;
2838 return _PAGE_SZ8K_4U;
2840 return _PAGE_SZ64K_4U;
2842 return _PAGE_SZ512K_4U;
2843 case 4 * 1024 * 1024:
2844 return _PAGE_SZ4MB_4U;
2849 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2853 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2854 pte_val(pte) |= (((unsigned long)space) << 32);
2855 pte_val(pte) |= pte_sz_bits(page_size);
2860 static unsigned long kern_large_tte(unsigned long paddr)
2864 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2865 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2866 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2867 if (tlb_type == hypervisor)
2868 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2869 page_cache4v_flag | _PAGE_P_4V |
2870 _PAGE_EXEC_4V | _PAGE_W_4V);
2875 /* If not locked, zap it. */
2876 void __flush_tlb_all(void)
2878 unsigned long pstate;
2881 __asm__ __volatile__("flushw\n\t"
2882 "rdpr %%pstate, %0\n\t"
2883 "wrpr %0, %1, %%pstate"
2886 if (tlb_type == hypervisor) {
2887 sun4v_mmu_demap_all();
2888 } else if (tlb_type == spitfire) {
2889 for (i = 0; i < 64; i++) {
2890 /* Spitfire Errata #32 workaround */
2891 /* NOTE: Always runs on spitfire, so no
2892 * cheetah+ page size encodings.
2894 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2898 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2900 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2901 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2904 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2905 spitfire_put_dtlb_data(i, 0x0UL);
2908 /* Spitfire Errata #32 workaround */
2909 /* NOTE: Always runs on spitfire, so no
2910 * cheetah+ page size encodings.
2912 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2916 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2918 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2919 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2922 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2923 spitfire_put_itlb_data(i, 0x0UL);
2926 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2927 cheetah_flush_dtlb_all();
2928 cheetah_flush_itlb_all();
2930 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2934 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2935 unsigned long address)
2937 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2941 pte = (pte_t *) page_address(page);
2946 pgtable_t pte_alloc_one(struct mm_struct *mm,
2947 unsigned long address)
2949 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2952 if (!pgtable_page_ctor(page)) {
2953 free_hot_cold_page(page, 0);
2956 return (pte_t *) page_address(page);
2959 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2961 free_page((unsigned long)pte);
2964 static void __pte_free(pgtable_t pte)
2966 struct page *page = virt_to_page(pte);
2968 pgtable_page_dtor(page);
2972 void pte_free(struct mm_struct *mm, pgtable_t pte)
2977 void pgtable_free(void *table, bool is_page)
2982 kmem_cache_free(pgtable_cache, table);
2985 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2986 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2989 unsigned long pte, flags;
2990 struct mm_struct *mm;
2993 if (!pmd_large(entry) || !pmd_young(entry))
2996 pte = pmd_val(entry);
2998 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2999 if (!(pte & _PAGE_VALID))
3002 /* We are fabricating 8MB pages using 4MB real hw pages. */
3003 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
3007 spin_lock_irqsave(&mm->context.lock, flags);
3009 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
3010 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
3013 spin_unlock_irqrestore(&mm->context.lock, flags);
3015 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3017 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
3018 static void context_reload(void *__data)
3020 struct mm_struct *mm = __data;
3022 if (mm == current->mm)
3023 load_secondary_context(mm);
3026 void hugetlb_setup(struct pt_regs *regs)
3028 struct mm_struct *mm = current->mm;
3029 struct tsb_config *tp;
3031 if (faulthandler_disabled() || !mm) {
3032 const struct exception_table_entry *entry;
3034 entry = search_exception_tables(regs->tpc);
3036 regs->tpc = entry->fixup;
3037 regs->tnpc = regs->tpc + 4;
3040 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3041 die_if_kernel("HugeTSB in atomic", regs);
3044 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3045 if (likely(tp->tsb == NULL))
3046 tsb_grow(mm, MM_TSB_HUGE, 0);
3048 tsb_context_switch(mm);
3051 /* On UltraSPARC-III+ and later, configure the second half of
3052 * the Data-TLB for huge pages.
3054 if (tlb_type == cheetah_plus) {
3055 bool need_context_reload = false;
3058 spin_lock_irq(&ctx_alloc_lock);
3059 ctx = mm->context.sparc64_ctx_val;
3060 ctx &= ~CTX_PGSZ_MASK;
3061 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3062 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3064 if (ctx != mm->context.sparc64_ctx_val) {
3065 /* When changing the page size fields, we
3066 * must perform a context flush so that no
3067 * stale entries match. This flush must
3068 * occur with the original context register
3071 do_flush_tlb_mm(mm);
3073 /* Reload the context register of all processors
3074 * also executing in this address space.
3076 mm->context.sparc64_ctx_val = ctx;
3077 need_context_reload = true;
3079 spin_unlock_irq(&ctx_alloc_lock);
3081 if (need_context_reload)
3082 on_each_cpu(context_reload, mm, 0);
3087 static struct resource code_resource = {
3088 .name = "Kernel code",
3089 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3092 static struct resource data_resource = {
3093 .name = "Kernel data",
3094 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3097 static struct resource bss_resource = {
3098 .name = "Kernel bss",
3099 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3102 static inline resource_size_t compute_kern_paddr(void *addr)
3104 return (resource_size_t) (addr - KERNBASE + kern_base);
3107 static void __init kernel_lds_init(void)
3109 code_resource.start = compute_kern_paddr(_text);
3110 code_resource.end = compute_kern_paddr(_etext - 1);
3111 data_resource.start = compute_kern_paddr(_etext);
3112 data_resource.end = compute_kern_paddr(_edata - 1);
3113 bss_resource.start = compute_kern_paddr(__bss_start);
3114 bss_resource.end = compute_kern_paddr(_end - 1);
3117 static int __init report_memory(void)
3120 struct resource *res;
3124 for (i = 0; i < pavail_ents; i++) {
3125 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3128 pr_warn("Failed to allocate source.\n");
3132 res->name = "System RAM";
3133 res->start = pavail[i].phys_addr;
3134 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3135 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3137 if (insert_resource(&iomem_resource, res) < 0) {
3138 pr_warn("Resource insertion failed.\n");
3142 insert_resource(res, &code_resource);
3143 insert_resource(res, &data_resource);
3144 insert_resource(res, &bss_resource);
3149 arch_initcall(report_memory);
3152 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3154 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3157 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3159 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3160 if (start < LOW_OBP_ADDRESS) {
3161 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3162 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3164 if (end > HI_OBP_ADDRESS) {
3165 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3166 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3169 flush_tsb_kernel_range(start, end);
3170 do_flush_tlb_kernel_range(start, end);