1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/unicore32/kernel/irq.c
5 * Code specific to PKUnity SoC and UniCore ISA
7 * Copyright (C) 2001-2010 GUAN Xue-tao
9 #include <linux/kernel_stat.h>
10 #include <linux/module.h>
11 #include <linux/signal.h>
12 #include <linux/ioport.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/random.h>
16 #include <linux/smp.h>
17 #include <linux/init.h>
18 #include <linux/seq_file.h>
19 #include <linux/errno.h>
20 #include <linux/list.h>
21 #include <linux/kallsyms.h>
22 #include <linux/proc_fs.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/gpio.h>
26 #include <mach/hardware.h>
31 * PKUnity GPIO edge detection for IRQs:
32 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
33 * Use this instead of directly setting GRER/GFER.
35 static int GPIO_IRQ_rising_edge;
36 static int GPIO_IRQ_falling_edge;
37 static int GPIO_IRQ_mask = 0;
39 #define GPIO_MASK(irq) (1 << (irq - IRQ_GPIO0))
41 static int puv3_gpio_type(struct irq_data *d, unsigned int type)
45 if (d->irq < IRQ_GPIOHIGH)
48 mask = GPIO_MASK(d->irq);
50 if (type == IRQ_TYPE_PROBE) {
51 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
53 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
56 if (type & IRQ_TYPE_EDGE_RISING)
57 GPIO_IRQ_rising_edge |= mask;
59 GPIO_IRQ_rising_edge &= ~mask;
60 if (type & IRQ_TYPE_EDGE_FALLING)
61 GPIO_IRQ_falling_edge |= mask;
63 GPIO_IRQ_falling_edge &= ~mask;
65 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
66 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
72 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 7.
74 static void puv3_low_gpio_ack(struct irq_data *d)
76 writel((1 << d->irq), GPIO_GEDR);
79 static void puv3_low_gpio_mask(struct irq_data *d)
81 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
84 static void puv3_low_gpio_unmask(struct irq_data *d)
86 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
89 static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on)
92 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER);
94 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER);
98 static struct irq_chip puv3_low_gpio_chip = {
100 .irq_ack = puv3_low_gpio_ack,
101 .irq_mask = puv3_low_gpio_mask,
102 .irq_unmask = puv3_low_gpio_unmask,
103 .irq_set_type = puv3_gpio_type,
104 .irq_set_wake = puv3_low_gpio_wake,
108 * IRQ8 (GPIO0 through 27) handler. We enter here with the
109 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
110 * and call the handler.
112 static void puv3_gpio_handler(struct irq_desc *desc)
114 unsigned int mask, irq;
116 mask = readl(GPIO_GEDR);
119 * clear down all currently active IRQ sources.
120 * We will be processing them all.
122 writel(mask, GPIO_GEDR);
127 generic_handle_irq(irq);
131 mask = readl(GPIO_GEDR);
136 * GPIO0-27 edge IRQs need to be handled specially.
137 * In addition, the IRQs are all collected up into one bit in the
138 * interrupt controller registers.
140 static void puv3_high_gpio_ack(struct irq_data *d)
142 unsigned int mask = GPIO_MASK(d->irq);
144 writel(mask, GPIO_GEDR);
147 static void puv3_high_gpio_mask(struct irq_data *d)
149 unsigned int mask = GPIO_MASK(d->irq);
151 GPIO_IRQ_mask &= ~mask;
153 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
154 writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
157 static void puv3_high_gpio_unmask(struct irq_data *d)
159 unsigned int mask = GPIO_MASK(d->irq);
161 GPIO_IRQ_mask |= mask;
163 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
164 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
167 static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on)
170 writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER);
172 writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER);
176 static struct irq_chip puv3_high_gpio_chip = {
178 .irq_ack = puv3_high_gpio_ack,
179 .irq_mask = puv3_high_gpio_mask,
180 .irq_unmask = puv3_high_gpio_unmask,
181 .irq_set_type = puv3_gpio_type,
182 .irq_set_wake = puv3_high_gpio_wake,
186 * We don't need to ACK IRQs on the PKUnity unless they're GPIOs
187 * this is for internal IRQs i.e. from 8 to 31.
189 static void puv3_mask_irq(struct irq_data *d)
191 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
194 static void puv3_unmask_irq(struct irq_data *d)
196 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
200 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
202 static int puv3_set_wake(struct irq_data *d, unsigned int on)
204 if (d->irq == IRQ_RTCAlarm) {
206 writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER);
208 writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER);
214 static struct irq_chip puv3_normal_chip = {
215 .name = "PKUnity-v3",
216 .irq_ack = puv3_mask_irq,
217 .irq_mask = puv3_mask_irq,
218 .irq_unmask = puv3_unmask_irq,
219 .irq_set_wake = puv3_set_wake,
222 static struct resource irq_resource = {
224 .start = io_v2p(PKUNITY_INTC_BASE),
225 .end = io_v2p(PKUNITY_INTC_BASE) + 0xFFFFF,
228 static struct puv3_irq_state {
235 static int puv3_irq_suspend(void)
237 struct puv3_irq_state *st = &puv3_irq_state;
240 st->icmr = readl(INTC_ICMR);
241 st->iclr = readl(INTC_ICLR);
242 st->iccr = readl(INTC_ICCR);
245 * Disable all GPIO-based interrupts.
247 writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR);
250 * Set the appropriate edges for wakeup.
252 writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER);
253 writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER);
256 * Clear any pending GPIO interrupts.
258 writel(readl(GPIO_GEDR), GPIO_GEDR);
263 static void puv3_irq_resume(void)
265 struct puv3_irq_state *st = &puv3_irq_state;
268 writel(st->iccr, INTC_ICCR);
269 writel(st->iclr, INTC_ICLR);
271 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
272 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
274 writel(st->icmr, INTC_ICMR);
278 static struct syscore_ops puv3_irq_syscore_ops = {
279 .suspend = puv3_irq_suspend,
280 .resume = puv3_irq_resume,
283 static int __init puv3_irq_init_syscore(void)
285 register_syscore_ops(&puv3_irq_syscore_ops);
289 device_initcall(puv3_irq_init_syscore);
291 void __init init_IRQ(void)
295 request_resource(&iomem_resource, &irq_resource);
297 /* disable all IRQs */
298 writel(0, INTC_ICMR);
300 /* all IRQs are IRQ, not REAL */
301 writel(0, INTC_ICLR);
303 /* clear all GPIO edge detects */
304 writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
305 writel(0, GPIO_GFER);
306 writel(0, GPIO_GRER);
307 writel(0x0FFFFFFF, GPIO_GEDR);
309 writel(1, INTC_ICCR);
311 for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
312 irq_set_chip(irq, &puv3_low_gpio_chip);
313 irq_set_handler(irq, handle_edge_irq);
314 irq_modify_status(irq,
315 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
319 for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
320 irq_set_chip(irq, &puv3_normal_chip);
321 irq_set_handler(irq, handle_level_irq);
322 irq_modify_status(irq,
323 IRQ_NOREQUEST | IRQ_NOAUTOEN,
327 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
328 irq_set_chip(irq, &puv3_high_gpio_chip);
329 irq_set_handler(irq, handle_edge_irq);
330 irq_modify_status(irq,
331 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
336 * Install handler for GPIO 0-27 edge detect interrupts
338 irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
339 irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
341 #ifdef CONFIG_PUV3_GPIO
347 * do_IRQ handles all hardware IRQ's. Decoded IRQs should not
348 * come via this function. Instead, they should provide their
351 asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
353 struct pt_regs *old_regs = set_irq_regs(regs);
358 * Some hardware gives randomly wrong interrupts. Rather
359 * than crashing, do something sensible.
361 if (unlikely(irq >= nr_irqs)) {
362 if (printk_ratelimit())
363 printk(KERN_WARNING "Bad IRQ%u\n", irq);
366 generic_handle_irq(irq);
370 set_irq_regs(old_regs);