1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1991,1992 Linus Torvalds
5 * entry_32.S contains the system-call and low-level fault and trap handling routines.
7 * Stack layout while running C code:
8 * ptrace needs to have all registers on the stack.
9 * If the order here is changed, it needs to be
10 * updated in fork.c:copy_process(), signal.c:do_signal(),
11 * ptrace.c and ptrace.h
23 * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS
32 #include <linux/linkage.h>
33 #include <linux/err.h>
34 #include <asm/thread_info.h>
35 #include <asm/irqflags.h>
36 #include <asm/errno.h>
37 #include <asm/segment.h>
39 #include <asm/percpu.h>
40 #include <asm/processor-flags.h>
41 #include <asm/irq_vectors.h>
42 #include <asm/cpufeatures.h>
43 #include <asm/alternative-asm.h>
46 #include <asm/frame.h>
47 #include <asm/nospec-branch.h>
51 .section .entry.text, "ax"
54 * We use macros for low-level operations which need to be overridden
55 * for paravirtualization. The following will never clobber any registers:
56 * INTERRUPT_RETURN (aka. "iret")
57 * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax")
58 * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit").
60 * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must
61 * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY).
62 * Allowing a register to be clobbered can shrink the paravirt replacement
63 * enough to patch inline, increasing performance.
67 # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF
69 # define preempt_stop(clobbers)
70 # define resume_kernel restore_all_kernel
73 .macro TRACE_IRQS_IRET
74 #ifdef CONFIG_TRACE_IRQFLAGS
75 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off?
82 #define PTI_SWITCH_MASK (1 << PAGE_SHIFT)
85 * User gs save/restore
87 * %gs is used for userland TLS and kernel only uses it for stack
88 * canary which is required to be at %gs:20 by gcc. Read the comment
89 * at the top of stackprotector.h for more info.
91 * Local labels 98 and 99 are used.
93 #ifdef CONFIG_X86_32_LAZY_GS
95 /* unfortunately push/pop can't be no-op */
100 addl $(4 + \pop), %esp
105 /* all the rest are no-op */
112 .macro REG_TO_PTGS reg
114 .macro SET_KERNEL_GS reg
117 #else /* CONFIG_X86_32_LAZY_GS */
130 .pushsection .fixup, "ax"
134 _ASM_EXTABLE(98b, 99b)
138 98: mov PT_GS(%esp), %gs
141 .pushsection .fixup, "ax"
142 99: movl $0, PT_GS(%esp)
145 _ASM_EXTABLE(98b, 99b)
151 .macro REG_TO_PTGS reg
152 movl \reg, PT_GS(%esp)
154 .macro SET_KERNEL_GS reg
155 movl $(__KERNEL_STACK_CANARY), \reg
159 #endif /* CONFIG_X86_32_LAZY_GS */
161 /* Unconditionally switch to user cr3 */
162 .macro SWITCH_TO_USER_CR3 scratch_reg:req
163 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
165 movl %cr3, \scratch_reg
166 orl $PTI_SWITCH_MASK, \scratch_reg
167 movl \scratch_reg, %cr3
171 .macro BUG_IF_WRONG_CR3 no_user_check=0
172 #ifdef CONFIG_DEBUG_ENTRY
173 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
174 .if \no_user_check == 0
175 /* coming from usermode? */
176 testl $SEGMENT_RPL_MASK, PT_CS(%esp)
181 testl $PTI_SWITCH_MASK, %eax
183 /* From userspace with kernel cr3 - BUG */
190 * Switch to kernel cr3 if not already loaded and return current cr3 in
193 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
194 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
195 movl %cr3, \scratch_reg
196 /* Test if we are already on kernel CR3 */
197 testl $PTI_SWITCH_MASK, \scratch_reg
199 andl $(~PTI_SWITCH_MASK), \scratch_reg
200 movl \scratch_reg, %cr3
201 /* Return original CR3 in \scratch_reg */
202 orl $PTI_SWITCH_MASK, \scratch_reg
206 .macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0
219 movl $(__USER_DS), %edx
222 movl $(__KERNEL_PERCPU), %edx
226 /* Switch to kernel stack if necessary */
227 .if \switch_stacks > 0
228 SWITCH_TO_KERNEL_STACK
233 .macro SAVE_ALL_NMI cr3_reg:req
239 * Now switch the CR3 when PTI is enabled.
241 * We can enter with either user or kernel cr3, the code will
242 * store the old cr3 in \cr3_reg and switches to the kernel cr3
245 SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg
251 * This is a sneaky trick to help the unwinder find pt_regs on the stack. The
252 * frame pointer is replaced with an encoded pointer to pt_regs. The encoding
253 * is just clearing the MSB, which makes it an invalid stack address and is also
254 * a signal to the unwinder that it's a pt_regs pointer in disguise.
256 * NOTE: This macro must be used *after* SAVE_ALL because it corrupts the
259 .macro ENCODE_FRAME_POINTER
260 #ifdef CONFIG_FRAME_POINTER
262 andl $0x7fffffff, %ebp
266 .macro RESTORE_INT_REGS
276 .macro RESTORE_REGS pop=0
282 .pushsection .fixup, "ax"
296 .macro RESTORE_ALL_NMI cr3_reg:req pop=0
298 * Now switch the CR3 when PTI is enabled.
300 * We enter with kernel cr3 and switch the cr3 to the value
301 * stored on \cr3_reg, which is either a user or a kernel cr3.
303 ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI
305 testl $PTI_SWITCH_MASK, \cr3_reg
308 /* User cr3 in \cr3_reg - write it to hardware cr3 */
315 RESTORE_REGS pop=\pop
318 .macro CHECK_AND_APPLY_ESPFIX
319 #ifdef CONFIG_X86_ESPFIX32
320 #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8)
322 ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
324 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
326 * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
327 * are returning to the kernel.
328 * See comments in process.c:copy_thread() for details.
330 movb PT_OLDSS(%esp), %ah
331 movb PT_CS(%esp), %al
332 andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
333 cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
334 jne .Lend_\@ # returning to user-space with LDT SS
337 * Setup and switch to ESPFIX stack
339 * We're returning to userspace with a 16 bit stack. The CPU will not
340 * restore the high word of ESP for us on executing iret... This is an
341 * "official" bug of all the x86-compatible CPUs, which we can work
342 * around to make dosemu and wine happy. We do this by preloading the
343 * high word of ESP with the high word of the userspace ESP while
344 * compensating for the offset by changing to the ESPFIX segment with
345 * a base address that matches for the difference.
347 mov %esp, %edx /* load kernel esp */
348 mov PT_OLDESP(%esp), %eax /* load userspace esp */
349 mov %dx, %ax /* eax: new kernel esp */
350 sub %eax, %edx /* offset (low word is 0) */
352 mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
353 mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
355 pushl %eax /* new kernel esp */
357 * Disable interrupts, but do not irqtrace this section: we
358 * will soon execute iret and the tracer was already set to
359 * the irqstate after the IRET:
361 DISABLE_INTERRUPTS(CLBR_ANY)
362 lss (%esp), %esp /* switch to espfix segment */
364 #endif /* CONFIG_X86_ESPFIX32 */
368 * Called with pt_regs fully populated and kernel segments loaded,
369 * so we can access PER_CPU and use the integer registers.
371 * We need to be very careful here with the %esp switch, because an NMI
372 * can happen everywhere. If the NMI handler finds itself on the
373 * entry-stack, it will overwrite the task-stack and everything we
374 * copied there. So allocate the stack-frame on the task-stack and
375 * switch to it before we do any copying.
378 #define CS_FROM_ENTRY_STACK (1 << 31)
379 #define CS_FROM_USER_CR3 (1 << 30)
381 .macro SWITCH_TO_KERNEL_STACK
383 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
387 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
390 * %eax now contains the entry cr3 and we carry it forward in
391 * that register for the time this macro runs
395 * The high bits of the CS dword (__csh) are used for
396 * CS_FROM_ENTRY_STACK and CS_FROM_USER_CR3. Clear them in case
397 * hardware didn't do this for us.
399 andl $(0x0000ffff), PT_CS(%esp)
401 /* Are we on the entry stack? Bail out if not! */
402 movl PER_CPU_VAR(cpu_entry_area), %ecx
403 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
404 subl %esp, %ecx /* ecx = (end of entry_stack) - esp */
405 cmpl $SIZEOF_entry_stack, %ecx
408 /* Load stack pointer into %esi and %edi */
412 /* Move %edi to the top of the entry stack */
413 andl $(MASK_entry_stack), %edi
414 addl $(SIZEOF_entry_stack), %edi
416 /* Load top of task-stack into %edi */
417 movl TSS_entry2task_stack(%edi), %edi
419 /* Special case - entry from kernel mode via entry stack */
421 movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS
422 movb PT_CS(%esp), %cl
423 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx
425 movl PT_CS(%esp), %ecx
426 andl $SEGMENT_RPL_MASK, %ecx
429 jb .Lentry_from_kernel_\@
432 movl $PTREGS_SIZE, %ecx
435 testl $X86_EFLAGS_VM, PT_EFLAGS(%esi)
439 * Stack-frame contains 4 additional segment registers when
440 * coming from VM86 mode
447 /* Allocate frame on task-stack */
450 /* Switch to task-stack */
454 * We are now on the task-stack and can safely copy over the
463 .Lentry_from_kernel_\@:
466 * This handles the case when we enter the kernel from
467 * kernel-mode and %esp points to the entry-stack. When this
468 * happens we need to switch to the task-stack to run C code,
469 * but switch back to the entry-stack again when we approach
470 * iret and return to the interrupted code-path. This usually
471 * happens when we hit an exception while restoring user-space
472 * segment registers on the way back to user-space or when the
473 * sysenter handler runs with eflags.tf set.
475 * When we switch to the task-stack here, we can't trust the
476 * contents of the entry-stack anymore, as the exception handler
477 * might be scheduled out or moved to another CPU. Therefore we
478 * copy the complete entry-stack to the task-stack and set a
479 * marker in the iret-frame (bit 31 of the CS dword) to detect
480 * what we've done on the iret path.
482 * On the iret path we copy everything back and switch to the
483 * entry-stack, so that the interrupted kernel code-path
484 * continues on the same stack it was interrupted with.
486 * Be aware that an NMI can happen anytime in this code.
488 * %esi: Entry-Stack pointer (same as %esp)
489 * %edi: Top of the task stack
490 * %eax: CR3 on kernel entry
493 /* Calculate number of bytes on the entry stack in %ecx */
496 /* %ecx to the top of entry-stack */
497 andl $(MASK_entry_stack), %ecx
498 addl $(SIZEOF_entry_stack), %ecx
500 /* Number of bytes on the entry stack to %ecx */
503 /* Mark stackframe as coming from entry stack */
504 orl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
507 * Test the cr3 used to enter the kernel and add a marker
508 * so that we can switch back to it before iret.
510 testl $PTI_SWITCH_MASK, %eax
512 orl $CS_FROM_USER_CR3, PT_CS(%esp)
515 * %esi and %edi are unchanged, %ecx contains the number of
516 * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate
517 * the stack-frame on task-stack and copy everything over
519 jmp .Lcopy_pt_regs_\@
525 * Switch back from the kernel stack to the entry stack.
527 * The %esp register must point to pt_regs on the task stack. It will
528 * first calculate the size of the stack-frame to copy, depending on
529 * whether we return to VM86 mode or not. With that it uses 'rep movsl'
530 * to copy the contents of the stack over to the entry stack.
532 * We must be very careful here, as we can't trust the contents of the
533 * task-stack once we switched to the entry-stack. When an NMI happens
534 * while on the entry-stack, the NMI handler will switch back to the top
535 * of the task stack, overwriting our stack-frame we are about to copy.
536 * Therefore we switch the stack only after everything is copied over.
538 .macro SWITCH_TO_ENTRY_STACK
540 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
543 movl $PTREGS_SIZE, %ecx
546 testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp)
549 /* Additional 4 registers to copy when returning to VM86 mode */
555 /* Initialize source and destination for movsl */
556 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
560 /* Save future stack pointer in %ebx */
563 /* Copy over the stack-frame */
569 * Switch to entry-stack - needs to happen after everything is
570 * copied because the NMI handler will overwrite the task-stack
571 * when on entry-stack
579 * This macro handles the case when we return to kernel-mode on the iret
580 * path and have to switch back to the entry stack and/or user-cr3
582 * See the comments below the .Lentry_from_kernel_\@ label in the
583 * SWITCH_TO_KERNEL_STACK macro for more details.
585 .macro PARANOID_EXIT_TO_KERNEL_MODE
588 * Test if we entered the kernel with the entry-stack. Most
589 * likely we did not, because this code only runs on the
590 * return-to-kernel path.
592 testl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
595 /* Unlikely slow-path */
597 /* Clear marker from stack-frame */
598 andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp)
600 /* Copy the remaining task-stack contents to entry-stack */
602 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
604 /* Bytes on the task-stack to ecx */
605 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx
608 /* Allocate stack-frame on entry-stack */
612 * Save future stack-pointer, we must not switch until the
613 * copy is done, otherwise the NMI handler could destroy the
614 * contents of the task-stack we are about to copy.
623 /* Safe to switch to entry-stack now */
627 * We came from entry-stack and need to check if we also need to
628 * switch back to user cr3.
630 testl $CS_FROM_USER_CR3, PT_CS(%esp)
633 /* Clear marker from stack-frame */
634 andl $(~CS_FROM_USER_CR3), PT_CS(%esp)
636 SWITCH_TO_USER_CR3 scratch_reg=%eax
644 ENTRY(__switch_to_asm)
646 * Save callee-saved registers
647 * This must match the order in struct inactive_task_frame
655 movl %esp, TASK_threadsp(%eax)
656 movl TASK_threadsp(%edx), %esp
658 #ifdef CONFIG_STACKPROTECTOR
659 movl TASK_stack_canary(%edx), %ebx
660 movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
663 #ifdef CONFIG_RETPOLINE
665 * When switching from a shallower to a deeper call stack
666 * the RSB may either underflow or use entries populated
667 * with userspace addresses. On CPUs where those concerns
668 * exist, overwrite the RSB with entries which capture
669 * speculative execution to prevent attack.
671 FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
674 /* restore callee-saved registers */
684 * The unwinder expects the last frame on the stack to always be at the same
685 * offset from the end of the page, which allows it to validate the stack.
686 * Calling schedule_tail() directly would break that convention because its an
687 * asmlinkage function so its argument has to be pushed on the stack. This
688 * wrapper creates a proper "end of stack" frame header before the call.
690 ENTRY(schedule_tail_wrapper)
699 ENDPROC(schedule_tail_wrapper)
701 * A newly forked process directly context switches into this address.
703 * eax: prev task we switched from
704 * ebx: kernel thread func (NULL for user thread)
705 * edi: kernel thread arg
708 call schedule_tail_wrapper
711 jnz 1f /* kernel threads are uncommon */
714 /* When we fork, we trace the syscall return in the child, too. */
716 call syscall_return_slowpath
724 * A kernel thread is allowed to return here after successfully
725 * calling do_execve(). Exit to userspace to complete the execve()
728 movl $0, PT_EAX(%esp)
733 * Return to user mode is not as complex as all this looks,
734 * but we want the default path for a system call return to
735 * go as quickly as possible which is why some of this is
736 * less clear than it otherwise should be.
739 # userspace resumption stub bypassing syscall exit tracing
742 preempt_stop(CLBR_ANY)
745 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
746 movb PT_CS(%esp), %al
747 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
750 * We can be coming here from child spawned by kernel_thread().
752 movl PT_CS(%esp), %eax
753 andl $SEGMENT_RPL_MASK, %eax
756 jb resume_kernel # not returning to v8086 or userspace
758 ENTRY(resume_userspace)
759 DISABLE_INTERRUPTS(CLBR_ANY)
762 call prepare_exit_to_usermode
764 END(ret_from_exception)
766 #ifdef CONFIG_PREEMPT
768 DISABLE_INTERRUPTS(CLBR_ANY)
770 cmpl $0, PER_CPU_VAR(__preempt_count)
771 jnz restore_all_kernel
772 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ?
773 jz restore_all_kernel
774 call preempt_schedule_irq
779 GLOBAL(__begin_SYSENTER_singlestep_region)
781 * All code from here through __end_SYSENTER_singlestep_region is subject
782 * to being single-stepped if a user program sets TF and executes SYSENTER.
783 * There is absolutely nothing that we can do to prevent this from happening
784 * (thanks Intel!). To keep our handling of this situation as simple as
785 * possible, we handle TF just like AC and NT, except that our #DB handler
786 * will ignore all of the single-step traps generated in this range.
791 * Xen doesn't set %esp to be precisely what the normal SYSENTER
792 * entry point expects, so fix it up before using the normal path.
794 ENTRY(xen_sysenter_target)
795 addl $5*4, %esp /* remove xen-provided frame */
796 jmp .Lsysenter_past_esp
800 * 32-bit SYSENTER entry.
802 * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
803 * if X86_FEATURE_SEP is available. This is the preferred system call
804 * entry on 32-bit systems.
806 * The SYSENTER instruction, in principle, should *only* occur in the
807 * vDSO. In practice, a small number of Android devices were shipped
808 * with a copy of Bionic that inlined a SYSENTER instruction. This
809 * never happened in any of Google's Bionic versions -- it only happened
810 * in a narrow range of Intel-provided versions.
812 * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs.
813 * IF and VM in RFLAGS are cleared (IOW: interrupts are off).
814 * SYSENTER does not save anything on the stack,
815 * and does not save old EIP (!!!), ESP, or EFLAGS.
817 * To avoid losing track of EFLAGS.VM (and thus potentially corrupting
818 * user and/or vm86 state), we explicitly disable the SYSENTER
819 * instruction in vm86 mode by reprogramming the MSRs.
822 * eax system call number
831 ENTRY(entry_SYSENTER_32)
833 * On entry-stack with all userspace-regs live - save and
834 * restore eflags and %eax to use it as scratch-reg for the cr3
839 BUG_IF_WRONG_CR3 no_user_check=1
840 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
844 /* Stack empty again, switch to task stack */
845 movl TSS_entry2task_stack(%esp), %esp
848 pushl $__USER_DS /* pt_regs->ss */
849 pushl %ebp /* pt_regs->sp (stashed in bp) */
850 pushfl /* pt_regs->flags (except IF = 0) */
851 orl $X86_EFLAGS_IF, (%esp) /* Fix IF */
852 pushl $__USER_CS /* pt_regs->cs */
853 pushl $0 /* pt_regs->ip = 0 (placeholder) */
854 pushl %eax /* pt_regs->orig_ax */
855 SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */
858 * SYSENTER doesn't filter flags, so we need to clear NT, AC
859 * and TF ourselves. To save a few cycles, we can check whether
860 * either was set instead of doing an unconditional popfq.
861 * This needs to happen before enabling interrupts so that
862 * we don't get preempted with NT set.
864 * If TF is set, we will single-step all the way to here -- do_debug
865 * will ignore all the traps. (Yes, this is slow, but so is
866 * single-stepping in general. This allows us to avoid having
867 * a more complicated code to handle the case where a user program
868 * forces us to single-step through the SYSENTER entry code.)
870 * NB.: .Lsysenter_fix_flags is a label with the code under it moved
871 * out-of-line as an optimization: NT is unlikely to be set in the
872 * majority of the cases and instead of polluting the I$ unnecessarily,
873 * we're keeping that code behind a branch which will predict as
874 * not-taken and therefore its instructions won't be fetched.
876 testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp)
877 jnz .Lsysenter_fix_flags
878 .Lsysenter_flags_fixed:
881 * User mode is traced as though IRQs are on, and SYSENTER
887 call do_fast_syscall_32
888 /* XEN PV guests always use IRET path */
889 ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
890 "jmp .Lsyscall_32_done", X86_FEATURE_XENPV
894 /* Opportunistic SYSEXIT */
895 TRACE_IRQS_ON /* User mode traces as IRQs on. */
898 * Setup entry stack - we keep the pointer in %eax and do the
899 * switch after almost all user-state is restored.
902 /* Load entry stack pointer and allocate frame for eflags/eax */
903 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax
906 /* Copy eflags and eax to entry stack */
907 movl PT_EFLAGS(%esp), %edi
908 movl PT_EAX(%esp), %esi
912 /* Restore user registers and segments */
913 movl PT_EIP(%esp), %edx /* pt_regs->ip */
914 movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */
915 1: mov PT_FS(%esp), %fs
918 popl %ebx /* pt_regs->bx */
919 addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */
920 popl %esi /* pt_regs->si */
921 popl %edi /* pt_regs->di */
922 popl %ebp /* pt_regs->bp */
924 /* Switch to entry stack */
927 /* Now ready to switch the cr3 */
928 SWITCH_TO_USER_CR3 scratch_reg=%eax
931 * Restore all flags except IF. (We restore IF separately because
932 * STI gives a one-instruction window in which we won't be interrupted,
933 * whereas POPF does not.)
935 btrl $X86_EFLAGS_IF_BIT, (%esp)
936 BUG_IF_WRONG_CR3 no_user_check=1
941 * Return back to the vDSO, which will pop ecx and edx.
942 * Don't bother with DS and ES (they already contain __USER_DS).
947 .pushsection .fixup, "ax"
948 2: movl $0, PT_FS(%esp)
954 .Lsysenter_fix_flags:
955 pushl $X86_EFLAGS_FIXED
957 jmp .Lsysenter_flags_fixed
958 GLOBAL(__end_SYSENTER_singlestep_region)
959 ENDPROC(entry_SYSENTER_32)
962 * 32-bit legacy system call entry.
964 * 32-bit x86 Linux system calls traditionally used the INT $0x80
965 * instruction. INT $0x80 lands here.
967 * This entry point can be used by any 32-bit perform system calls.
968 * Instances of INT $0x80 can be found inline in various programs and
969 * libraries. It is also used by the vDSO's __kernel_vsyscall
970 * fallback for hardware that doesn't support a faster entry method.
971 * Restarted 32-bit system calls also fall back to INT $0x80
972 * regardless of what instruction was originally used to do the system
973 * call. (64-bit programs can use INT $0x80 as well, but they can
974 * only run on 64-bit kernels and therefore land in
975 * entry_INT80_compat.)
977 * This is considered a slow path. It is not used by most libc
978 * implementations on modern hardware except during process startup.
981 * eax system call number
989 ENTRY(entry_INT80_32)
991 pushl %eax /* pt_regs->orig_ax */
993 SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */
996 * User mode is traced as though IRQs are on, and the interrupt gate
1002 call do_int80_syscall_32
1009 SWITCH_TO_ENTRY_STACK
1010 .Lrestore_all_notrace:
1011 CHECK_AND_APPLY_ESPFIX
1013 /* Switch back to user CR3 */
1014 SWITCH_TO_USER_CR3 scratch_reg=%eax
1018 /* Restore user state */
1019 RESTORE_REGS pop=4 # skip orig_eax/error_code
1022 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
1023 * when returning from IPI handler and when returning from
1024 * scheduler to user-space.
1030 PARANOID_EXIT_TO_KERNEL_MODE
1035 .section .fixup, "ax"
1037 pushl $0 # no error code
1038 pushl $do_iret_error
1040 #ifdef CONFIG_DEBUG_ENTRY
1042 * The stack-frame here is the one that iret faulted on, so its a
1043 * return-to-user frame. We are on kernel-cr3 because we come here from
1044 * the fixup code. This confuses the CR3 checker, so switch to user-cr3
1045 * as the checker expects it.
1048 SWITCH_TO_USER_CR3 scratch_reg=%eax
1052 jmp common_exception
1054 _ASM_EXTABLE(.Lirq_return, iret_exc)
1055 ENDPROC(entry_INT80_32)
1057 .macro FIXUP_ESPFIX_STACK
1059 * Switch back for ESPFIX stack to the normal zerobased stack
1061 * We can't call C functions using the ESPFIX stack. This code reads
1062 * the high word of the segment base from the GDT and swiches to the
1063 * normal stack and adjusts ESP with the matching offset.
1065 #ifdef CONFIG_X86_ESPFIX32
1066 /* fixup the stack */
1067 mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */
1068 mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */
1070 addl %esp, %eax /* the adjusted stack pointer */
1073 lss (%esp), %esp /* switch to the normal stack segment */
1076 .macro UNWIND_ESPFIX_STACK
1077 #ifdef CONFIG_X86_ESPFIX32
1079 /* see if on espfix stack */
1080 cmpw $__ESPFIX_SS, %ax
1082 movl $__KERNEL_DS, %eax
1085 /* switch to normal stack */
1092 * Build the entry stubs with some assembler magic.
1093 * We pack 1 stub into every 8-byte block.
1096 ENTRY(irq_entries_start)
1097 vector=FIRST_EXTERNAL_VECTOR
1098 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
1099 pushl $(~vector+0x80) /* Note: always in signed byte range */
1101 jmp common_interrupt
1104 END(irq_entries_start)
1107 * the CPU automatically disables interrupts when executing an IRQ vector,
1108 * so IRQ-flags tracing has to follow that:
1110 .p2align CONFIG_X86_L1_CACHE_SHIFT
1113 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
1115 SAVE_ALL switch_stacks=1
1116 ENCODE_FRAME_POINTER
1121 ENDPROC(common_interrupt)
1123 #define BUILD_INTERRUPT3(name, nr, fn) \
1127 SAVE_ALL switch_stacks=1; \
1128 ENCODE_FRAME_POINTER; \
1132 jmp ret_from_intr; \
1135 #define BUILD_INTERRUPT(name, nr) \
1136 BUILD_INTERRUPT3(name, nr, smp_##name); \
1138 /* The include is where all of the SMP etc. interrupts come from */
1139 #include <asm/entry_arch.h>
1141 ENTRY(coprocessor_error)
1144 pushl $do_coprocessor_error
1145 jmp common_exception
1146 END(coprocessor_error)
1148 ENTRY(simd_coprocessor_error)
1151 #ifdef CONFIG_X86_INVD_BUG
1152 /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */
1153 ALTERNATIVE "pushl $do_general_protection", \
1154 "pushl $do_simd_coprocessor_error", \
1157 pushl $do_simd_coprocessor_error
1159 jmp common_exception
1160 END(simd_coprocessor_error)
1162 ENTRY(device_not_available)
1164 pushl $-1 # mark this as an int
1165 pushl $do_device_not_available
1166 jmp common_exception
1167 END(device_not_available)
1169 #ifdef CONFIG_PARAVIRT
1172 _ASM_EXTABLE(native_iret, iret_exc)
1180 jmp common_exception
1187 jmp common_exception
1193 pushl $do_invalid_op
1194 jmp common_exception
1197 ENTRY(coprocessor_segment_overrun)
1200 pushl $do_coprocessor_segment_overrun
1201 jmp common_exception
1202 END(coprocessor_segment_overrun)
1206 pushl $do_invalid_TSS
1207 jmp common_exception
1210 ENTRY(segment_not_present)
1212 pushl $do_segment_not_present
1213 jmp common_exception
1214 END(segment_not_present)
1216 ENTRY(stack_segment)
1218 pushl $do_stack_segment
1219 jmp common_exception
1222 ENTRY(alignment_check)
1224 pushl $do_alignment_check
1225 jmp common_exception
1226 END(alignment_check)
1230 pushl $0 # no error code
1231 pushl $do_divide_error
1232 jmp common_exception
1235 #ifdef CONFIG_X86_MCE
1236 ENTRY(machine_check)
1239 pushl machine_check_vector
1240 jmp common_exception
1244 ENTRY(spurious_interrupt_bug)
1247 pushl $do_spurious_interrupt_bug
1248 jmp common_exception
1249 END(spurious_interrupt_bug)
1251 #ifdef CONFIG_XEN_PV
1252 ENTRY(xen_hypervisor_callback)
1253 pushl $-1 /* orig_ax = -1 => not a system call */
1255 ENCODE_FRAME_POINTER
1259 * Check to see if we got the event in the critical
1260 * region in xen_iret_direct, after we've reenabled
1261 * events and checked for pending events. This simulates
1262 * iret instruction's behaviour where it delivers a
1263 * pending interrupt when enabling interrupts:
1265 movl PT_EIP(%esp), %eax
1266 cmpl $xen_iret_start_crit, %eax
1268 cmpl $xen_iret_end_crit, %eax
1271 jmp xen_iret_crit_fixup
1273 ENTRY(xen_do_upcall)
1275 call xen_evtchn_do_upcall
1276 #ifndef CONFIG_PREEMPT
1277 call xen_maybe_preempt_hcall
1280 ENDPROC(xen_hypervisor_callback)
1283 * Hypervisor uses this for application faults while it executes.
1284 * We get here for two reasons:
1285 * 1. Fault while reloading DS, ES, FS or GS
1286 * 2. Fault while executing IRET
1287 * Category 1 we fix up by reattempting the load, and zeroing the segment
1288 * register if the load fails.
1289 * Category 2 we fix up by jumping to do_iret_error. We cannot use the
1290 * normal Linux return path in this case because if we use the IRET hypercall
1291 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1292 * We distinguish between categories by maintaining a status value in EAX.
1294 ENTRY(xen_failsafe_callback)
1299 3: mov 12(%esp), %fs
1300 4: mov 16(%esp), %gs
1301 /* EAX == 0 => Category 1 (Bad segment)
1302 EAX != 0 => Category 2 (Bad IRET) */
1308 5: pushl $-1 /* orig_ax = -1 => not a system call */
1310 ENCODE_FRAME_POINTER
1311 jmp ret_from_exception
1313 .section .fixup, "ax"
1327 _ASM_EXTABLE(1b, 6b)
1328 _ASM_EXTABLE(2b, 7b)
1329 _ASM_EXTABLE(3b, 8b)
1330 _ASM_EXTABLE(4b, 9b)
1331 ENDPROC(xen_failsafe_callback)
1332 #endif /* CONFIG_XEN_PV */
1334 #ifdef CONFIG_XEN_PVHVM
1335 BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1336 xen_evtchn_do_upcall)
1340 #if IS_ENABLED(CONFIG_HYPERV)
1342 BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1343 hyperv_vector_handler)
1345 BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR,
1346 hyperv_reenlightenment_intr)
1348 BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR,
1349 hv_stimer0_vector_handler)
1351 #endif /* CONFIG_HYPERV */
1355 pushl $do_page_fault
1357 jmp common_exception
1361 /* the function address is in %gs's slot on the stack */
1366 movl $(__USER_DS), %eax
1369 movl $(__KERNEL_PERCPU), %eax
1377 SWITCH_TO_KERNEL_STACK
1378 ENCODE_FRAME_POINTER
1382 movl PT_GS(%esp), %edi # get the function address
1383 movl PT_ORIG_EAX(%esp), %edx # get the error code
1384 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1388 movl %esp, %eax # pt_regs pointer
1390 jmp ret_from_exception
1391 END(common_exception)
1395 * Entry from sysenter is now handled in common_exception
1398 pushl $-1 # mark this as an int
1400 jmp common_exception
1404 * NMI is doubly nasty. It can happen on the first instruction of
1405 * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning
1406 * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32
1407 * switched stacks. We handle both conditions by simply checking whether we
1408 * interrupted kernel code running on the SYSENTER stack.
1413 #ifdef CONFIG_X86_ESPFIX32
1416 cmpw $__ESPFIX_SS, %ax
1418 je .Lnmi_espfix_stack
1421 pushl %eax # pt_regs->orig_ax
1422 SAVE_ALL_NMI cr3_reg=%edi
1423 ENCODE_FRAME_POINTER
1424 xorl %edx, %edx # zero error code
1425 movl %esp, %eax # pt_regs pointer
1427 /* Are we currently on the SYSENTER stack? */
1428 movl PER_CPU_VAR(cpu_entry_area), %ecx
1429 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
1430 subl %eax, %ecx /* ecx = (end of entry_stack) - esp */
1431 cmpl $SIZEOF_entry_stack, %ecx
1432 jb .Lnmi_from_sysenter_stack
1434 /* Not on SYSENTER stack. */
1438 .Lnmi_from_sysenter_stack:
1440 * We're on the SYSENTER stack. Switch off. No one (not even debug)
1441 * is using the thread stack right now, so it's safe for us to use it.
1444 movl PER_CPU_VAR(cpu_current_top_of_stack), %esp
1449 CHECK_AND_APPLY_ESPFIX
1450 RESTORE_ALL_NMI cr3_reg=%edi pop=4
1453 #ifdef CONFIG_X86_ESPFIX32
1456 * create the pointer to lss back
1461 /* copy the iret frame of 12 bytes */
1466 SAVE_ALL_NMI cr3_reg=%edi
1467 ENCODE_FRAME_POINTER
1468 FIXUP_ESPFIX_STACK # %eax == %esp
1469 xorl %edx, %edx # zero error code
1471 RESTORE_ALL_NMI cr3_reg=%edi
1472 lss 12+4(%esp), %esp # back to espfix stack
1479 pushl $-1 # mark this as an int
1481 SAVE_ALL switch_stacks=1
1482 ENCODE_FRAME_POINTER
1484 xorl %edx, %edx # zero error code
1485 movl %esp, %eax # pt_regs pointer
1487 jmp ret_from_exception
1490 ENTRY(general_protection)
1491 pushl $do_general_protection
1492 jmp common_exception
1493 END(general_protection)
1495 #ifdef CONFIG_KVM_GUEST
1496 ENTRY(async_page_fault)
1498 pushl $do_async_page_fault
1499 jmp common_exception
1500 END(async_page_fault)
1503 ENTRY(rewind_stack_do_exit)
1504 /* Prevent any naive code from trying to unwind to our caller. */
1507 movl PER_CPU_VAR(cpu_current_top_of_stack), %esi
1508 leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp
1512 END(rewind_stack_do_exit)