1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.txt
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, \flags /* interrupts off? */
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
85 call debug_stack_reset
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
91 call debug_stack_reset
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 bt $9, EFLAGS(%rsp) /* interrupts off? */
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
126 * Registers on entry:
127 * rax system call number
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
138 * Only called from user space.
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
145 .pushsection .entry_trampoline, "ax"
148 * The code in here gets remapped into cpu_entry_area's trampoline. This means
149 * that the assembler and linker have the wrong idea as to where this code
150 * lives (and, in fact, it's mapped more than once, so it's not even at a
151 * fixed address). So we can't reference any symbols outside the entry
152 * trampoline and expect it to work.
154 * Instead, we carefully abuse %rip-relative addressing.
155 * _entry_trampoline(%rip) refers to the start of the remapped) entry
156 * trampoline. We can thus find cpu_entry_area with this macro:
159 #define CPU_ENTRY_AREA \
160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
162 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
163 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
166 ENTRY(entry_SYSCALL_64_trampoline)
170 /* Stash the user RSP. */
171 movq %rsp, RSP_SCRATCH
173 /* Note: using %rsp as a scratch reg. */
174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
176 /* Load the top of the task stack into RSP */
177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
179 /* Start building the simulated IRET frame. */
180 pushq $__USER_DS /* pt_regs->ss */
181 pushq RSP_SCRATCH /* pt_regs->sp */
182 pushq %r11 /* pt_regs->flags */
183 pushq $__USER_CS /* pt_regs->cs */
184 pushq %rcx /* pt_regs->ip */
187 * x86 lacks a near absolute jump, and we can't jump to the real
188 * entry text with a relative jump. We could push the target
189 * address and then use retq, but this destroys the pipeline on
190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
191 * spill RDI and restore it in a second-stage trampoline.
194 movq $entry_SYSCALL_64_stage2, %rdi
196 END(entry_SYSCALL_64_trampoline)
200 ENTRY(entry_SYSCALL_64_stage2)
203 jmp entry_SYSCALL_64_after_hwframe
204 END(entry_SYSCALL_64_stage2)
206 ENTRY(entry_SYSCALL_64)
209 * Interrupts are off on entry.
210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
211 * it is too small to ever cause noticeable irq latency.
216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
217 * is not required to switch CR3.
219 movq %rsp, PER_CPU_VAR(rsp_scratch)
220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
222 /* Construct struct pt_regs on stack */
223 pushq $__USER_DS /* pt_regs->ss */
224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
225 pushq %r11 /* pt_regs->flags */
226 pushq $__USER_CS /* pt_regs->cs */
227 pushq %rcx /* pt_regs->ip */
228 GLOBAL(entry_SYSCALL_64_after_hwframe)
229 pushq %rax /* pt_regs->orig_ax */
231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
237 call do_syscall_64 /* returns with IRQs disabled */
239 TRACE_IRQS_IRETQ /* we're about to change IF */
242 * Try to use SYSRET instead of IRET if we're returning to
243 * a completely clean 64-bit userspace context. If we're not,
244 * go to the slow exit path.
249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
250 jne swapgs_restore_regs_and_return_to_usermode
253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
254 * in kernel space. This essentially lets the user take over
255 * the kernel, since userspace controls RSP.
257 * If width of "canonical tail" ever becomes variable, this will need
258 * to be updated to remain correct on both old and new CPUs.
260 * Change top bits to match most significant bit (47th or 56th bit
261 * depending on paging mode) in the address.
263 #ifdef CONFIG_X86_5LEVEL
264 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
265 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
267 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
268 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
271 /* If this changed %rcx, it was not canonical */
273 jne swapgs_restore_regs_and_return_to_usermode
275 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
276 jne swapgs_restore_regs_and_return_to_usermode
279 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
280 jne swapgs_restore_regs_and_return_to_usermode
283 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
284 * restore RF properly. If the slowpath sets it for whatever reason, we
285 * need to restore it correctly.
287 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
288 * trap from userspace immediately after SYSRET. This would cause an
289 * infinite loop whenever #DB happens with register state that satisfies
290 * the opportunistic SYSRET conditions. For example, single-stepping
293 * movq $stuck_here, %rcx
298 * would never get past 'stuck_here'.
300 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
301 jnz swapgs_restore_regs_and_return_to_usermode
303 /* nothing to check for RSP */
305 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
306 jne swapgs_restore_regs_and_return_to_usermode
309 * We win! This label is here just for ease of understanding
310 * perf profiles. Nothing jumps here.
312 syscall_return_via_sysret:
313 /* rcx and r11 are already restored (see code above) */
315 POP_REGS pop_rdi=0 skip_r11rcx=1
318 * Now all regs are restored except RSP and RDI.
319 * Save old stack pointer and switch to trampoline stack.
322 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
324 pushq RSP-RDI(%rdi) /* RSP */
325 pushq (%rdi) /* RDI */
328 * We are on the trampoline stack. All regs except RDI are live.
329 * We can do future final exit work right here.
331 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
336 END(entry_SYSCALL_64)
342 ENTRY(__switch_to_asm)
345 * Save callee-saved registers
346 * This must match the order in inactive_task_frame
356 movq %rsp, TASK_threadsp(%rdi)
357 movq TASK_threadsp(%rsi), %rsp
359 #ifdef CONFIG_CC_STACKPROTECTOR
360 movq TASK_stack_canary(%rsi), %rbx
361 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
364 #ifdef CONFIG_RETPOLINE
366 * When switching from a shallower to a deeper call stack
367 * the RSB may either underflow or use entries populated
368 * with userspace addresses. On CPUs where those concerns
369 * exist, overwrite the RSB with entries which capture
370 * speculative execution to prevent attack.
372 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
375 /* restore callee-saved registers */
387 * A newly forked process directly context switches into this address.
389 * rax: prev task we switched from
390 * rbx: kernel thread func (NULL for user thread)
391 * r12: kernel thread arg
396 call schedule_tail /* rdi: 'prev' task parameter */
398 testq %rbx, %rbx /* from kernel_thread? */
399 jnz 1f /* kernel threads are uncommon */
404 call syscall_return_slowpath /* returns with IRQs disabled */
405 TRACE_IRQS_ON /* user mode is traced as IRQS on */
406 jmp swapgs_restore_regs_and_return_to_usermode
413 * A kernel thread is allowed to return here after successfully
414 * calling do_execve(). Exit to userspace to complete the execve()
422 * Build the entry stubs with some assembler magic.
423 * We pack 1 stub into every 8-byte block.
426 ENTRY(irq_entries_start)
427 vector=FIRST_EXTERNAL_VECTOR
428 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
429 UNWIND_HINT_IRET_REGS
430 pushq $(~vector+0x80) /* Note: always in signed byte range */
435 END(irq_entries_start)
437 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
438 #ifdef CONFIG_DEBUG_ENTRY
441 testl $X86_EFLAGS_IF, %eax
450 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
451 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
452 * Requires kernel GSBASE.
454 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
456 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
457 DEBUG_ENTRY_ASSERT_IRQS_OFF
461 * If save_ret is set, the original stack contains one additional
462 * entry -- the return address. Therefore, move the address one
463 * entry below %rsp to \old_rsp.
465 leaq 8(%rsp), \old_rsp
471 UNWIND_HINT_REGS base=\old_rsp
474 incl PER_CPU_VAR(irq_count)
475 jnz .Lirq_stack_push_old_rsp_\@
478 * Right now, if we just incremented irq_count to zero, we've
479 * claimed the IRQ stack but we haven't switched to it yet.
481 * If anything is added that can interrupt us here without using IST,
482 * it must be *extremely* careful to limit its stack usage. This
483 * could include kprobes and a hypothetical future IST-less #DB
486 * The OOPS unwinder relies on the word at the top of the IRQ
487 * stack linking back to the previous RSP for the entire time we're
488 * on the IRQ stack. For this to work reliably, we need to write
489 * it before we actually move ourselves to the IRQ stack.
492 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
493 movq PER_CPU_VAR(irq_stack_ptr), %rsp
495 #ifdef CONFIG_DEBUG_ENTRY
497 * If the first movq above becomes wrong due to IRQ stack layout
498 * changes, the only way we'll notice is if we try to unwind right
499 * here. Assert that we set up the stack right to catch this type
502 cmpq -8(%rsp), \old_rsp
503 je .Lirq_stack_okay\@
508 .Lirq_stack_push_old_rsp_\@:
512 UNWIND_HINT_REGS indirect=1
517 * Push the return address to the stack. This return address can
518 * be found at the "real" original RSP, which was offset by 8 at
519 * the beginning of this macro.
526 * Undoes ENTER_IRQ_STACK.
528 .macro LEAVE_IRQ_STACK regs=1
529 DEBUG_ENTRY_ASSERT_IRQS_OFF
530 /* We need to be off the IRQ stack before decrementing irq_count. */
538 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
539 * the irq stack but we're not on it.
542 decl PER_CPU_VAR(irq_count)
546 * Interrupt entry helper function.
548 * Entry runs with interrupts off. Stack layout at entry:
549 * +----------------------------------------------------+
555 * +----------------------------------------------------+
556 * | regs->orig_ax = ~(interrupt number) |
557 * +----------------------------------------------------+
559 * +----------------------------------------------------+
561 ENTRY(interrupt_entry)
566 testb $3, CS-ORIG_RAX+8(%rsp)
571 * Switch to the thread stack. The IRET frame and orig_ax are
572 * on the stack, as well as the return address. RDI..R12 are
573 * not (yet) on the stack and space has not (yet) been
574 * allocated for them.
578 /* Need to switch before accessing the thread stack. */
579 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
581 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
584 * We have RDI, return address, and orig_ax on the stack on
585 * top of the IRET frame. That means offset=24
587 UNWIND_HINT_IRET_REGS base=%rdi offset=24
589 pushq 7*8(%rdi) /* regs->ss */
590 pushq 6*8(%rdi) /* regs->rsp */
591 pushq 5*8(%rdi) /* regs->eflags */
592 pushq 4*8(%rdi) /* regs->cs */
593 pushq 3*8(%rdi) /* regs->ip */
594 pushq 2*8(%rdi) /* regs->orig_ax */
595 pushq 8(%rdi) /* return address */
601 PUSH_AND_CLEAR_REGS save_ret=1
602 ENCODE_FRAME_POINTER 8
608 * IRQ from user mode.
610 * We need to tell lockdep that IRQs are off. We can't do this until
611 * we fix gsbase, and we should do it before enter_from_user_mode
612 * (which can take locks). Since TRACE_IRQS_OFF is idempotent,
613 * the simplest way to handle it is to just call it twice if
614 * we enter from user mode. There's no reason to optimize this since
615 * TRACE_IRQS_OFF is a no-op if lockdep is off.
619 CALL_enter_from_user_mode
622 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
623 /* We entered an interrupt context - irqs are off: */
630 /* Interrupt entry/exit. */
633 * The interrupt stubs push (~vector+0x80) onto the stack and
634 * then jump to common_interrupt.
636 .p2align CONFIG_X86_L1_CACHE_SHIFT
638 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
640 UNWIND_HINT_REGS indirect=1
641 call do_IRQ /* rdi points to pt_regs */
642 /* 0(%rsp): old RSP */
644 DISABLE_INTERRUPTS(CLBR_ANY)
652 /* Interrupt came from user space */
655 call prepare_exit_to_usermode
658 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
659 #ifdef CONFIG_DEBUG_ENTRY
660 /* Assert that pt_regs indicates user mode. */
669 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
670 * Save old stack pointer and switch to trampoline stack.
673 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
675 /* Copy the IRET frame to the trampoline stack. */
676 pushq 6*8(%rdi) /* SS */
677 pushq 5*8(%rdi) /* RSP */
678 pushq 4*8(%rdi) /* EFLAGS */
679 pushq 3*8(%rdi) /* CS */
680 pushq 2*8(%rdi) /* RIP */
682 /* Push user RDI on the trampoline stack. */
686 * We are on the trampoline stack. All regs except RDI are live.
687 * We can do future final exit work right here.
690 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
698 /* Returning to kernel space */
700 #ifdef CONFIG_PREEMPT
701 /* Interrupts are off */
702 /* Check if we need preemption */
703 bt $9, EFLAGS(%rsp) /* were interrupts off? */
705 0: cmpl $0, PER_CPU_VAR(__preempt_count)
707 call preempt_schedule_irq
712 * The iretq could re-enable interrupts:
716 GLOBAL(restore_regs_and_return_to_kernel)
717 #ifdef CONFIG_DEBUG_ENTRY
718 /* Assert that pt_regs indicates kernel mode. */
725 addq $8, %rsp /* skip regs->orig_ax */
727 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
728 * when returning from IPI handler.
733 UNWIND_HINT_IRET_REGS
735 * Are we returning to a stack segment from the LDT? Note: in
736 * 64-bit mode SS:RSP on the exception stack is always valid.
738 #ifdef CONFIG_X86_ESPFIX64
739 testb $4, (SS-RIP)(%rsp)
740 jnz native_irq_return_ldt
743 .global native_irq_return_iret
744 native_irq_return_iret:
746 * This may fault. Non-paranoid faults on return to userspace are
747 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
748 * Double-faults due to espfix64 are handled in do_double_fault.
749 * Other faults here are fatal.
753 #ifdef CONFIG_X86_ESPFIX64
754 native_irq_return_ldt:
756 * We are running with user GSBASE. All GPRs contain their user
757 * values. We have a percpu ESPFIX stack that is eight slots
758 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
759 * of the ESPFIX stack.
761 * We clobber RAX and RDI in this code. We stash RDI on the
762 * normal stack and RAX on the ESPFIX stack.
764 * The ESPFIX stack layout we set up looks like this:
766 * --- top of ESPFIX stack ---
771 * RIP <-- RSP points here when we're done
772 * RAX <-- espfix_waddr points here
773 * --- bottom of ESPFIX stack ---
776 pushq %rdi /* Stash user RDI */
777 SWAPGS /* to kernel GS */
778 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
780 movq PER_CPU_VAR(espfix_waddr), %rdi
781 movq %rax, (0*8)(%rdi) /* user RAX */
782 movq (1*8)(%rsp), %rax /* user RIP */
783 movq %rax, (1*8)(%rdi)
784 movq (2*8)(%rsp), %rax /* user CS */
785 movq %rax, (2*8)(%rdi)
786 movq (3*8)(%rsp), %rax /* user RFLAGS */
787 movq %rax, (3*8)(%rdi)
788 movq (5*8)(%rsp), %rax /* user SS */
789 movq %rax, (5*8)(%rdi)
790 movq (4*8)(%rsp), %rax /* user RSP */
791 movq %rax, (4*8)(%rdi)
792 /* Now RAX == RSP. */
794 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
797 * espfix_stack[31:16] == 0. The page tables are set up such that
798 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
799 * espfix_waddr for any X. That is, there are 65536 RO aliases of
800 * the same page. Set up RSP so that RSP[31:16] contains the
801 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
802 * still points to an RO alias of the ESPFIX stack.
804 orq PER_CPU_VAR(espfix_stack), %rax
806 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
807 SWAPGS /* to user GS */
808 popq %rdi /* Restore user RDI */
811 UNWIND_HINT_IRET_REGS offset=8
814 * At this point, we cannot write to the stack any more, but we can
817 popq %rax /* Restore user RAX */
820 * RSP now points to an ordinary IRET frame, except that the page
821 * is read-only and RSP[31:16] are preloaded with the userspace
822 * values. We can now IRET back to userspace.
824 jmp native_irq_return_iret
826 END(common_interrupt)
831 .macro apicinterrupt3 num sym do_sym
833 UNWIND_HINT_IRET_REGS
837 UNWIND_HINT_REGS indirect=1
838 call \do_sym /* rdi points to pt_regs */
843 /* Make sure APIC interrupt handlers end up in the irqentry section: */
844 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
845 #define POP_SECTION_IRQENTRY .popsection
847 .macro apicinterrupt num sym do_sym
848 PUSH_SECTION_IRQENTRY
849 apicinterrupt3 \num \sym \do_sym
854 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
855 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
859 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
862 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
863 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
865 #ifdef CONFIG_HAVE_KVM
866 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
867 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
868 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
871 #ifdef CONFIG_X86_MCE_THRESHOLD
872 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
875 #ifdef CONFIG_X86_MCE_AMD
876 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
879 #ifdef CONFIG_X86_THERMAL_VECTOR
880 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
884 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
885 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
886 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
889 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
890 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
892 #ifdef CONFIG_IRQ_WORK
893 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
897 * Exception entry points.
899 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
901 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
903 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
906 .if \shift_ist != -1 && \paranoid == 0
907 .error "using shift_ist requires paranoid=1"
912 .if \has_error_code == 0
913 pushq $-1 /* ORIG_RAX: no syscall to restart */
917 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
918 jnz .Lfrom_usermode_switch_stack_\@
927 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
931 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
937 movq %rsp, %rdi /* pt_regs pointer */
940 movq ORIG_RAX(%rsp), %rsi /* get error code */
941 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
943 xorl %esi, %esi /* no error code */
947 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
953 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
956 /* these procedures expect "no swapgs" flag in ebx */
965 * Entry from userspace. Switch stacks and treat it
966 * as a normal entry. This means that paranoid handlers
967 * run in real process context if user_mode(regs).
969 .Lfrom_usermode_switch_stack_\@:
972 movq %rsp, %rdi /* pt_regs pointer */
975 movq ORIG_RAX(%rsp), %rsi /* get error code */
976 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
978 xorl %esi, %esi /* no error code */
983 jmp error_exit /* %ebx: no swapgs flag */
988 idtentry divide_error do_divide_error has_error_code=0
989 idtentry overflow do_overflow has_error_code=0
990 idtentry bounds do_bounds has_error_code=0
991 idtentry invalid_op do_invalid_op has_error_code=0
992 idtentry device_not_available do_device_not_available has_error_code=0
993 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
994 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
995 idtentry invalid_TSS do_invalid_TSS has_error_code=1
996 idtentry segment_not_present do_segment_not_present has_error_code=1
997 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
998 idtentry coprocessor_error do_coprocessor_error has_error_code=0
999 idtentry alignment_check do_alignment_check has_error_code=1
1000 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1004 * Reload gs selector with exception handling
1007 ENTRY(native_load_gs_index)
1010 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1015 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1017 TRACE_IRQS_FLAGS (%rsp)
1021 ENDPROC(native_load_gs_index)
1022 EXPORT_SYMBOL(native_load_gs_index)
1024 _ASM_EXTABLE(.Lgs_change, bad_gs)
1025 .section .fixup, "ax"
1026 /* running with kernelgs */
1028 SWAPGS /* switch back to user gs */
1030 /* This can't be a string because the preprocessor needs to see it. */
1031 movl $__USER_DS, %eax
1034 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1040 /* Call softirq on interrupt stack. Interrupts are off. */
1041 ENTRY(do_softirq_own_stack)
1044 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1046 LEAVE_IRQ_STACK regs=0
1049 ENDPROC(do_softirq_own_stack)
1052 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1055 * A note on the "critical region" in our callback handler.
1056 * We want to avoid stacking callback handlers due to events occurring
1057 * during handling of the last event. To do this, we keep events disabled
1058 * until we've done all processing. HOWEVER, we must enable events before
1059 * popping the stack frame (can't be done atomically) and so it would still
1060 * be possible to get enough handler activations to overflow the stack.
1061 * Although unlikely, bugs of that kind are hard to track down, so we'd
1062 * like to avoid the possibility.
1063 * So, on entry to the handler we detect whether we interrupted an
1064 * existing activation in its critical region -- if so, we pop the current
1065 * activation and restart the handler using the previous one.
1067 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1070 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1071 * see the correct pointer to the pt_regs
1074 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1077 ENTER_IRQ_STACK old_rsp=%r10
1078 call xen_evtchn_do_upcall
1081 #ifndef CONFIG_PREEMPT
1082 call xen_maybe_preempt_hcall
1085 END(xen_do_hypervisor_callback)
1088 * Hypervisor uses this for application faults while it executes.
1089 * We get here for two reasons:
1090 * 1. Fault while reloading DS, ES, FS or GS
1091 * 2. Fault while executing IRET
1092 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1093 * registers that could be reloaded and zeroed the others.
1094 * Category 2 we fix up by killing the current process. We cannot use the
1095 * normal Linux return path in this case because if we use the IRET hypercall
1096 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1097 * We distinguish between categories by comparing each saved segment register
1098 * with its current contents: any discrepancy means we in category 1.
1100 ENTRY(xen_failsafe_callback)
1103 cmpw %cx, 0x10(%rsp)
1106 cmpw %cx, 0x18(%rsp)
1109 cmpw %cx, 0x20(%rsp)
1112 cmpw %cx, 0x28(%rsp)
1114 /* All segments match their saved values => Category 2 (Bad IRET). */
1119 UNWIND_HINT_IRET_REGS offset=8
1120 jmp general_protection
1121 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1125 UNWIND_HINT_IRET_REGS
1126 pushq $-1 /* orig_ax = -1 => not a system call */
1128 ENCODE_FRAME_POINTER
1130 END(xen_failsafe_callback)
1132 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1133 xen_hvm_callback_vector xen_evtchn_do_upcall
1135 #endif /* CONFIG_XEN */
1137 #if IS_ENABLED(CONFIG_HYPERV)
1138 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1139 hyperv_callback_vector hyperv_vector_handler
1141 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
1142 hyperv_reenlightenment_vector hyperv_reenlightenment_intr
1143 #endif /* CONFIG_HYPERV */
1145 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1146 idtentry int3 do_int3 has_error_code=0
1147 idtentry stack_segment do_stack_segment has_error_code=1
1150 idtentry xennmi do_nmi has_error_code=0
1151 idtentry xendebug do_debug has_error_code=0
1152 idtentry xenint3 do_int3 has_error_code=0
1155 idtentry general_protection do_general_protection has_error_code=1
1156 idtentry page_fault do_page_fault has_error_code=1
1158 #ifdef CONFIG_KVM_GUEST
1159 idtentry async_page_fault do_async_page_fault has_error_code=1
1162 #ifdef CONFIG_X86_MCE
1163 idtentry machine_check do_mce has_error_code=0 paranoid=1
1167 * Save all registers in pt_regs, and switch gs if needed.
1168 * Use slow, but surefire "are we in kernel?" check.
1169 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1171 ENTRY(paranoid_entry)
1174 PUSH_AND_CLEAR_REGS save_ret=1
1175 ENCODE_FRAME_POINTER 8
1177 movl $MSR_GS_BASE, %ecx
1180 js 1f /* negative -> in kernel */
1185 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1191 * "Paranoid" exit path from exception stack. This is invoked
1192 * only on return from non-NMI IST interrupts that came
1193 * from kernel space.
1195 * We may be returning to very strange contexts (e.g. very early
1196 * in syscall entry), so checking for preemption here would
1197 * be complicated. Fortunately, we there's no good reason
1198 * to try to handle preemption here.
1200 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1202 ENTRY(paranoid_exit)
1204 DISABLE_INTERRUPTS(CLBR_ANY)
1205 TRACE_IRQS_OFF_DEBUG
1206 testl %ebx, %ebx /* swapgs needed? */
1207 jnz .Lparanoid_exit_no_swapgs
1209 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1211 jmp .Lparanoid_exit_restore
1212 .Lparanoid_exit_no_swapgs:
1213 TRACE_IRQS_IRETQ_DEBUG
1214 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1215 .Lparanoid_exit_restore:
1216 jmp restore_regs_and_return_to_kernel
1220 * Save all registers in pt_regs, and switch GS if needed.
1221 * Return: EBX=0: came from user mode; EBX=1: otherwise
1226 PUSH_AND_CLEAR_REGS save_ret=1
1227 ENCODE_FRAME_POINTER 8
1228 testb $3, CS+8(%rsp)
1229 jz .Lerror_kernelspace
1232 * We entered from user mode or we're pretending to have entered
1233 * from user mode due to an IRET fault.
1236 /* We have user CR3. Change to kernel CR3. */
1237 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1239 .Lerror_entry_from_usermode_after_swapgs:
1240 /* Put us onto the real thread stack. */
1241 popq %r12 /* save return addr in %12 */
1242 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1244 movq %rax, %rsp /* switch stack */
1245 ENCODE_FRAME_POINTER
1249 * We need to tell lockdep that IRQs are off. We can't do this until
1250 * we fix gsbase, and we should do it before enter_from_user_mode
1251 * (which can take locks).
1254 CALL_enter_from_user_mode
1262 * There are two places in the kernel that can potentially fault with
1263 * usergs. Handle them here. B stepping K8s sometimes report a
1264 * truncated RIP for IRET exceptions returning to compat mode. Check
1265 * for these here too.
1267 .Lerror_kernelspace:
1269 leaq native_irq_return_iret(%rip), %rcx
1270 cmpq %rcx, RIP+8(%rsp)
1272 movl %ecx, %eax /* zero extend */
1273 cmpq %rax, RIP+8(%rsp)
1275 cmpq $.Lgs_change, RIP+8(%rsp)
1276 jne .Lerror_entry_done
1279 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1280 * gsbase and proceed. We'll fix up the exception and land in
1281 * .Lgs_change's error handler with kernel gsbase.
1284 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1285 jmp .Lerror_entry_done
1288 /* Fix truncated RIP */
1289 movq %rcx, RIP+8(%rsp)
1294 * We came from an IRET to user mode, so we have user
1295 * gsbase and CR3. Switch to kernel gsbase and CR3:
1298 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1301 * Pretend that the exception came from user mode: set up pt_regs
1302 * as if we faulted immediately after IRET and clear EBX so that
1303 * error_exit knows that we will be returning to user mode.
1309 jmp .Lerror_entry_from_usermode_after_swapgs
1314 * On entry, EBX is a "return to kernel mode" flag:
1315 * 1: already in kernel mode, don't need SWAPGS
1316 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
1320 DISABLE_INTERRUPTS(CLBR_ANY)
1328 * Runs on exception stack. Xen PV does not go through this path at all,
1329 * so we can use real assembly here.
1332 * %r14: Used to save/restore the CR3 of the interrupted context
1333 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1336 UNWIND_HINT_IRET_REGS
1339 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1340 * the iretq it performs will take us out of NMI context.
1341 * This means that we can have nested NMIs where the next
1342 * NMI is using the top of the stack of the previous NMI. We
1343 * can't let it execute because the nested NMI will corrupt the
1344 * stack of the previous NMI. NMI handlers are not re-entrant
1347 * To handle this case we do the following:
1348 * Check the a special location on the stack that contains
1349 * a variable that is set when NMIs are executing.
1350 * The interrupted task's stack is also checked to see if it
1352 * If the variable is not set and the stack is not the NMI
1354 * o Set the special variable on the stack
1355 * o Copy the interrupt frame into an "outermost" location on the
1357 * o Copy the interrupt frame into an "iret" location on the stack
1358 * o Continue processing the NMI
1359 * If the variable is set or the previous stack is the NMI stack:
1360 * o Modify the "iret" location to jump to the repeat_nmi
1361 * o return back to the first NMI
1363 * Now on exit of the first NMI, we first clear the stack variable
1364 * The NMI stack will tell any nested NMIs at that point that it is
1365 * nested. Then we pop the stack normally with iret, and if there was
1366 * a nested NMI that updated the copy interrupt stack frame, a
1367 * jump will be made to the repeat_nmi code that will handle the second
1370 * However, espfix prevents us from directly returning to userspace
1371 * with a single IRET instruction. Similarly, IRET to user mode
1372 * can fault. We therefore handle NMIs from user space like
1373 * other IST entries.
1378 /* Use %rdx as our temp variable throughout */
1381 testb $3, CS-RIP+8(%rsp)
1382 jz .Lnmi_from_kernel
1385 * NMI from user mode. We need to run on the thread stack, but we
1386 * can't go through the normal entry paths: NMIs are masked, and
1387 * we don't want to enable interrupts, because then we'll end
1388 * up in an awkward situation in which IRQs are on but NMIs
1391 * We also must not push anything to the stack before switching
1392 * stacks lest we corrupt the "NMI executing" variable.
1397 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1399 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1400 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1401 pushq 5*8(%rdx) /* pt_regs->ss */
1402 pushq 4*8(%rdx) /* pt_regs->rsp */
1403 pushq 3*8(%rdx) /* pt_regs->flags */
1404 pushq 2*8(%rdx) /* pt_regs->cs */
1405 pushq 1*8(%rdx) /* pt_regs->rip */
1406 UNWIND_HINT_IRET_REGS
1407 pushq $-1 /* pt_regs->orig_ax */
1408 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1409 ENCODE_FRAME_POINTER
1412 * At this point we no longer need to worry about stack damage
1413 * due to nesting -- we're on the normal thread stack and we're
1414 * done with the NMI stack.
1422 * Return back to user mode. We must *not* do the normal exit
1423 * work, because we don't want to enable interrupts.
1425 jmp swapgs_restore_regs_and_return_to_usermode
1429 * Here's what our stack frame will look like:
1430 * +---------------------------------------------------------+
1432 * | original Return RSP |
1433 * | original RFLAGS |
1436 * +---------------------------------------------------------+
1437 * | temp storage for rdx |
1438 * +---------------------------------------------------------+
1439 * | "NMI executing" variable |
1440 * +---------------------------------------------------------+
1441 * | iret SS } Copied from "outermost" frame |
1442 * | iret Return RSP } on each loop iteration; overwritten |
1443 * | iret RFLAGS } by a nested NMI to force another |
1444 * | iret CS } iteration if needed. |
1446 * +---------------------------------------------------------+
1447 * | outermost SS } initialized in first_nmi; |
1448 * | outermost Return RSP } will not be changed before |
1449 * | outermost RFLAGS } NMI processing is done. |
1450 * | outermost CS } Copied to "iret" frame on each |
1451 * | outermost RIP } iteration. |
1452 * +---------------------------------------------------------+
1454 * +---------------------------------------------------------+
1456 * The "original" frame is used by hardware. Before re-enabling
1457 * NMIs, we need to be done with it, and we need to leave enough
1458 * space for the asm code here.
1460 * We return by executing IRET while RSP points to the "iret" frame.
1461 * That will either return for real or it will loop back into NMI
1464 * The "outermost" frame is copied to the "iret" frame on each
1465 * iteration of the loop, so each iteration starts with the "iret"
1466 * frame pointing to the final return target.
1470 * Determine whether we're a nested NMI.
1472 * If we interrupted kernel code between repeat_nmi and
1473 * end_repeat_nmi, then we are a nested NMI. We must not
1474 * modify the "iret" frame because it's being written by
1475 * the outer NMI. That's okay; the outer NMI handler is
1476 * about to about to call do_nmi anyway, so we can just
1477 * resume the outer NMI.
1480 movq $repeat_nmi, %rdx
1483 movq $end_repeat_nmi, %rdx
1489 * Now check "NMI executing". If it's set, then we're nested.
1490 * This will not detect if we interrupted an outer NMI just
1497 * Now test if the previous stack was an NMI stack. This covers
1498 * the case where we interrupt an outer NMI after it clears
1499 * "NMI executing" but before IRET. We need to be careful, though:
1500 * there is one case in which RSP could point to the NMI stack
1501 * despite there being no NMI active: naughty userspace controls
1502 * RSP at the very beginning of the SYSCALL targets. We can
1503 * pull a fast one on naughty userspace, though: we program
1504 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1505 * if it controls the kernel's RSP. We set DF before we clear
1509 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1510 cmpq %rdx, 4*8(%rsp)
1511 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1514 subq $EXCEPTION_STKSZ, %rdx
1515 cmpq %rdx, 4*8(%rsp)
1516 /* If it is below the NMI stack, it is a normal NMI */
1519 /* Ah, it is within the NMI stack. */
1521 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1522 jz first_nmi /* RSP was user controlled. */
1524 /* This is a nested NMI. */
1528 * Modify the "iret" frame to point to repeat_nmi, forcing another
1529 * iteration of NMI handling.
1532 leaq -10*8(%rsp), %rdx
1539 /* Put stack back */
1545 /* We are returning to kernel mode, so this cannot result in a fault. */
1552 /* Make room for "NMI executing". */
1555 /* Leave room for the "iret" frame */
1558 /* Copy the "original" frame to the "outermost" frame */
1562 UNWIND_HINT_IRET_REGS
1564 /* Everything up to here is safe from nested NMIs */
1566 #ifdef CONFIG_DEBUG_ENTRY
1568 * For ease of testing, unmask NMIs right away. Disabled by
1569 * default because IRET is very expensive.
1572 pushq %rsp /* RSP (minus 8 because of the previous push) */
1573 addq $8, (%rsp) /* Fix up RSP */
1575 pushq $__KERNEL_CS /* CS */
1577 iretq /* continues at repeat_nmi below */
1578 UNWIND_HINT_IRET_REGS
1584 * If there was a nested NMI, the first NMI's iret will return
1585 * here. But NMIs are still enabled and we can take another
1586 * nested NMI. The nested NMI checks the interrupted RIP to see
1587 * if it is between repeat_nmi and end_repeat_nmi, and if so
1588 * it will just return, as we are about to repeat an NMI anyway.
1589 * This makes it safe to copy to the stack frame that a nested
1592 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1593 * we're repeating an NMI, gsbase has the same value that it had on
1594 * the first iteration. paranoid_entry will load the kernel
1595 * gsbase if needed before we call do_nmi. "NMI executing"
1598 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1601 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1602 * here must not modify the "iret" frame while we're writing to
1603 * it or it will end up containing garbage.
1613 * Everything below this point can be preempted by a nested NMI.
1614 * If this happens, then the inner NMI will change the "iret"
1615 * frame to point back to repeat_nmi.
1617 pushq $-1 /* ORIG_RAX: no syscall to restart */
1620 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1621 * as we should not be calling schedule in NMI context.
1622 * Even with normal interrupts enabled. An NMI should not be
1623 * setting NEED_RESCHED or anything that normal interrupts and
1624 * exceptions might do.
1629 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1634 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1636 testl %ebx, %ebx /* swapgs needed? */
1644 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1645 * at the "iret" frame.
1650 * Clear "NMI executing". Set DF first so that we can easily
1651 * distinguish the remaining code between here and IRET from
1652 * the SYSCALL entry and exit paths.
1654 * We arguably should just inspect RIP instead, but I (Andy) wrote
1655 * this code when I had the misapprehension that Xen PV supported
1656 * NMIs, and Xen PV would break that approach.
1659 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1662 * iretq reads the "iret" frame and exits the NMI stack in a
1663 * single instruction. We are returning to kernel mode, so this
1664 * cannot result in a fault. Similarly, we don't need to worry
1665 * about espfix64 on the way back to kernel mode.
1670 ENTRY(ignore_sysret)
1676 ENTRY(rewind_stack_do_exit)
1678 /* Prevent any naive code from trying to unwind to our caller. */
1681 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1682 leaq -PTREGS_SIZE(%rax), %rsp
1683 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE
1686 END(rewind_stack_do_exit)