1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "../perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
18 * pebs_record_32 for p4 and core not supported
20 struct pebs_record_32 {
28 union intel_x86_pebs_dse {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
54 /* Version for Sandy Bridge and later */
55 static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
74 /* Patch up minor differences in the bits */
75 void __init intel_pmu_pebs_data_source_nhm(void)
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
82 static u64 precise_store_data(u64 status)
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
91 * 1 = stored missed 2nd level TLB
93 * so it either hit the walker or the OS
94 * otherwise hit 2nd level TLB
102 * bit 0: hit L1 data cache
103 * if not set, then all we know is that
112 * bit 5: Locked prefix
115 val |= P(LOCK, LOCKED);
120 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
122 union perf_mem_data_src dse;
124 dse.val = PERF_MEM_NA;
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
132 * L1 info only valid for following events:
134 * MEM_UOPS_RETIRED.STLB_MISS_STORES
135 * MEM_UOPS_RETIRED.LOCK_STORES
136 * MEM_UOPS_RETIRED.SPLIT_STORES
137 * MEM_UOPS_RETIRED.ALL_STORES
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
148 static u64 load_latency_data(u64 status)
150 union intel_x86_pebs_dse dse;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
158 * use the mapping table for bit 0-3
160 val = pebs_data_source[dse.ld_dse];
163 * Nehalem models do not support TLB, Lock infos
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
172 * 0 = did not miss 2nd level TLB
173 * 1 = missed 2nd level TLB
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
181 * bit 5: locked prefix
184 val |= P(LOCK, LOCKED);
189 struct pebs_record_core {
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
197 struct pebs_record_nhm {
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
207 * Same as pebs_record_nhm, with two additional fields.
209 struct pebs_record_hsw {
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
219 union hsw_tsx_tuning {
221 u32 cycles_last_block : 32,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
236 /* Same as HSW, plus TSC */
238 struct pebs_record_skl {
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
249 void init_debug_store_on_cpu(int cpu)
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
261 void fini_debug_store_on_cpu(int cpu)
263 if (!per_cpu(cpu_hw_events, cpu).ds)
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
269 static DEFINE_PER_CPU(void *, insn_buffer);
271 static int alloc_pebs_buffer(int cpu)
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
276 void *buffer, *ibuffer;
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
286 * HSW+ already provides us the eventing ip; no need to allocate this
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
295 per_cpu(insn_buffer, cpu) = ibuffer;
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
308 static void release_pebs_buffer(int cpu)
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
312 if (!ds || !x86_pmu.pebs)
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
322 static int alloc_bts_buffer(int cpu)
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
351 static void release_bts_buffer(int cpu)
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
355 if (!ds || !x86_pmu.bts)
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
362 static int alloc_ds_buffer(int cpu)
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
371 per_cpu(cpu_hw_events, cpu).ds = ds;
376 static void release_ds_buffer(int cpu)
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
387 void release_ds_buffers(void)
391 if (!x86_pmu.bts && !x86_pmu.pebs)
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
406 void reserve_ds_buffers(void)
408 int bts_err = 0, pebs_err = 0;
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
414 if (!x86_pmu.bts && !x86_pmu.pebs)
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
431 if (!bts_err && alloc_bts_buffer(cpu))
434 if (!pebs_err && alloc_pebs_buffer(cpu))
437 if (bts_err && pebs_err)
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
472 struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
475 void intel_pmu_enable_bts(u64 config)
477 unsigned long debugctlmsr;
479 debugctlmsr = get_debugctlmsr();
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
492 update_debugctlmsr(debugctlmsr);
495 void intel_pmu_disable_bts(void)
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
503 debugctlmsr = get_debugctlmsr();
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
509 update_debugctlmsr(debugctlmsr);
512 int intel_pmu_drain_bts_buffer(void)
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
532 if (!x86_pmu.bts_active)
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
541 memset(®s, 0, sizeof(regs));
543 ds->bts_index = ds->bts_buffer_base;
545 perf_sample_data_init(&data, 0, event->hw.last_period);
548 * BTS leaks kernel addresses in branches across the cpl boundary,
549 * such as traps or system calls, so unless the user is asking for
550 * kernel tracing (and right now it's not possible), we'd need to
551 * filter them out. But first we need to count how many of those we
552 * have in the current batch. This is an extra O(n) pass, however,
553 * it's much faster than the other one especially considering that
554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
555 * alloc_bts_buffer()).
557 for (at = base; at < top; at++) {
559 * Note that right now *this* BTS code only works if
560 * attr::exclude_kernel is set, but let's keep this extra
561 * check here in case that changes.
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
569 * Prepare a generic sample, i.e. fill in the invariant fields.
570 * We will overwrite the from and to address before we output
574 perf_prepare_sample(&header, &data, event, ®s);
576 if (perf_output_begin(&handle, event, header.size *
577 (top - base - skip)))
580 for (at = base; at < top; at++) {
581 /* Filter out any records that contain kernel addresses. */
582 if (event->attr.exclude_kernel &&
583 (kernel_ip(at->from) || kernel_ip(at->to)))
589 perf_output_sample(&handle, &header, &data, event);
592 perf_output_end(&handle);
594 /* There's new data available. */
595 event->hw.interrupts++;
596 event->pending_kill = POLL_IN;
602 static inline void intel_pmu_drain_pebs_buffer(void)
606 x86_pmu.drain_pebs(®s);
609 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
612 intel_pmu_drain_pebs_buffer();
618 struct event_constraint intel_core2_pebs_event_constraints[] = {
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
620 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
621 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
622 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
623 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
624 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
629 struct event_constraint intel_atom_pebs_event_constraints[] = {
630 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
631 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
632 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
633 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
634 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
635 /* Allow all events as PEBS with no flags */
636 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
640 struct event_constraint intel_slm_pebs_event_constraints[] = {
641 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
642 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
643 /* Allow all events as PEBS with no flags */
644 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
648 struct event_constraint intel_glm_pebs_event_constraints[] = {
649 /* Allow all events as PEBS with no flags */
650 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
654 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
655 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
656 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
657 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
658 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
659 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
660 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
661 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
662 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
663 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
664 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
665 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
666 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
667 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
671 struct event_constraint intel_westmere_pebs_event_constraints[] = {
672 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
673 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
674 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
675 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
676 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
677 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
678 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
679 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
680 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
681 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
683 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
684 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
688 struct event_constraint intel_snb_pebs_event_constraints[] = {
689 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
690 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
691 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
692 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
693 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
694 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
695 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
696 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
697 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
698 /* Allow all events as PEBS with no flags */
699 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
703 struct event_constraint intel_ivb_pebs_event_constraints[] = {
704 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
705 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
706 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
707 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
708 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
709 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
710 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
711 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
712 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
713 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
714 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
715 /* Allow all events as PEBS with no flags */
716 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
720 struct event_constraint intel_hsw_pebs_event_constraints[] = {
721 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
722 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
723 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
724 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
725 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
726 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
727 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
728 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
729 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
730 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
731 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
732 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
733 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
734 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
735 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
736 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
737 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
738 /* Allow all events as PEBS with no flags */
739 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
743 struct event_constraint intel_bdw_pebs_event_constraints[] = {
744 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
745 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
746 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
747 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
748 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
749 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
750 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
751 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
752 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
753 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
754 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
755 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
756 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
757 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
758 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
759 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
760 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
761 /* Allow all events as PEBS with no flags */
762 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
767 struct event_constraint intel_skl_pebs_event_constraints[] = {
768 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
769 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
770 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
771 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
772 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
773 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
774 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
775 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
776 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
777 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
778 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
779 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
780 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
781 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
782 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
783 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
784 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
785 /* Allow all events as PEBS with no flags */
786 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
790 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
792 struct event_constraint *c;
794 if (!event->attr.precise_ip)
797 if (x86_pmu.pebs_constraints) {
798 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
799 if ((event->hw.config & c->cmask) == c->code) {
800 event->hw.flags |= c->flags;
806 return &emptyconstraint;
810 * We need the sched_task callback even for per-cpu events when we use
811 * the large interrupt threshold, such that we can provide PID and TID
814 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
816 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
819 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
821 struct debug_store *ds = cpuc->ds;
824 if (cpuc->n_pebs == cpuc->n_large_pebs) {
825 threshold = ds->pebs_absolute_maximum -
826 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
828 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
831 ds->pebs_interrupt_threshold = threshold;
835 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
838 * Make sure we get updated with the first PEBS
839 * event. It will trigger also during removal, but
840 * that does not hurt:
842 bool update = cpuc->n_pebs == 1;
844 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
846 perf_sched_cb_inc(pmu);
848 perf_sched_cb_dec(pmu);
854 pebs_update_threshold(cpuc);
857 void intel_pmu_pebs_add(struct perf_event *event)
859 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
860 struct hw_perf_event *hwc = &event->hw;
861 bool needed_cb = pebs_needs_sched_cb(cpuc);
864 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
865 cpuc->n_large_pebs++;
867 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
870 void intel_pmu_pebs_enable(struct perf_event *event)
872 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
873 struct hw_perf_event *hwc = &event->hw;
874 struct debug_store *ds = cpuc->ds;
876 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
878 cpuc->pebs_enabled |= 1ULL << hwc->idx;
880 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
881 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
882 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
883 cpuc->pebs_enabled |= 1ULL << 63;
886 * Use auto-reload if possible to save a MSR write in the PMI.
887 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
889 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
890 ds->pebs_event_reset[hwc->idx] =
891 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
895 void intel_pmu_pebs_del(struct perf_event *event)
897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
898 struct hw_perf_event *hwc = &event->hw;
899 bool needed_cb = pebs_needs_sched_cb(cpuc);
902 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
903 cpuc->n_large_pebs--;
905 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
908 void intel_pmu_pebs_disable(struct perf_event *event)
910 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
911 struct hw_perf_event *hwc = &event->hw;
913 if (cpuc->n_pebs == cpuc->n_large_pebs)
914 intel_pmu_drain_pebs_buffer();
916 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
918 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
919 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
920 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
921 cpuc->pebs_enabled &= ~(1ULL << 63);
924 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
926 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
929 void intel_pmu_pebs_enable_all(void)
931 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
933 if (cpuc->pebs_enabled)
934 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
937 void intel_pmu_pebs_disable_all(void)
939 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
941 if (cpuc->pebs_enabled)
942 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
945 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
947 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
948 unsigned long from = cpuc->lbr_entries[0].from;
949 unsigned long old_to, to = cpuc->lbr_entries[0].to;
950 unsigned long ip = regs->ip;
956 * We don't need to fixup if the PEBS assist is fault like
958 if (!x86_pmu.intel_cap.pebs_trap)
962 * No LBR entry, no basic block, no rewinding
964 if (!cpuc->lbr_stack.nr || !from || !to)
968 * Basic blocks should never cross user/kernel boundaries
970 if (kernel_ip(ip) != kernel_ip(to))
974 * unsigned math, either ip is before the start (impossible) or
975 * the basic block is larger than 1 page (sanity)
977 if ((ip - to) > PEBS_FIXUP_SIZE)
981 * We sampled a branch insn, rewind using the LBR stack
984 set_linear_ip(regs, from);
989 if (!kernel_ip(ip)) {
991 u8 *buf = this_cpu_read(insn_buffer);
993 /* 'size' must fit our buffer, see above */
994 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1008 #ifdef CONFIG_X86_64
1009 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1011 insn_init(&insn, kaddr, size, is_64bit);
1012 insn_get_length(&insn);
1014 * Make sure there was not a problem decoding the
1015 * instruction and getting the length. This is
1016 * doubly important because we have an infinite
1017 * loop if insn.length=0.
1023 kaddr += insn.length;
1024 size -= insn.length;
1028 set_linear_ip(regs, old_to);
1033 * Even though we decoded the basic block, the instruction stream
1034 * never matched the given IP, either the TO or the IP got corrupted.
1039 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1041 if (pebs->tsx_tuning) {
1042 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
1043 return tsx.cycles_last_block;
1048 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1050 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1052 /* For RTM XABORTs also log the abort code from AX */
1053 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1054 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1058 static void setup_pebs_sample_data(struct perf_event *event,
1059 struct pt_regs *iregs, void *__pebs,
1060 struct perf_sample_data *data,
1061 struct pt_regs *regs)
1063 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1064 (PERF_X86_EVENT_PEBS_ST_HSW | \
1065 PERF_X86_EVENT_PEBS_LD_HSW | \
1066 PERF_X86_EVENT_PEBS_NA_HSW)
1068 * We cast to the biggest pebs_record but are careful not to
1069 * unconditionally access the 'extra' entries.
1071 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1072 struct pebs_record_skl *pebs = __pebs;
1075 int fl = event->hw.flags;
1080 sample_type = event->attr.sample_type;
1081 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1083 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1084 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1086 perf_sample_data_init(data, 0, event->hw.last_period);
1088 data->period = event->hw.last_period;
1091 * Use latency for weight (only avail with PEBS-LL)
1093 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1094 data->weight = pebs->lat;
1097 * data.data_src encodes the data source
1100 u64 val = PERF_MEM_NA;
1102 val = load_latency_data(pebs->dse);
1103 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1104 val = precise_datala_hsw(event, pebs->dse);
1106 val = precise_store_data(pebs->dse);
1107 data->data_src.val = val;
1111 * We use the interrupt regs as a base because the PEBS record does not
1112 * contain a full regs set, specifically it seems to lack segment
1113 * descriptors, which get used by things like user_mode().
1115 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1117 * We must however always use BP,SP from iregs for the unwinder to stay
1118 * sane; the record BP,SP can point into thin air when the record is
1119 * from a previous PMI context or an (I)RET happend between the record
1123 regs->flags = pebs->flags;
1124 set_linear_ip(regs, pebs->ip);
1126 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1127 regs->ax = pebs->ax;
1128 regs->bx = pebs->bx;
1129 regs->cx = pebs->cx;
1130 regs->dx = pebs->dx;
1131 regs->si = pebs->si;
1132 regs->di = pebs->di;
1135 * Per the above; only set BP,SP if we don't need callchains.
1137 * XXX: does this make sense?
1139 if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) {
1140 regs->bp = pebs->bp;
1141 regs->sp = pebs->sp;
1145 * Preserve PERF_EFLAGS_VM from set_linear_ip().
1147 regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
1148 #ifndef CONFIG_X86_32
1149 regs->r8 = pebs->r8;
1150 regs->r9 = pebs->r9;
1151 regs->r10 = pebs->r10;
1152 regs->r11 = pebs->r11;
1153 regs->r12 = pebs->r12;
1154 regs->r13 = pebs->r13;
1155 regs->r14 = pebs->r14;
1156 regs->r15 = pebs->r15;
1160 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1161 regs->ip = pebs->real_ip;
1162 regs->flags |= PERF_EFLAGS_EXACT;
1163 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1164 regs->flags |= PERF_EFLAGS_EXACT;
1166 regs->flags &= ~PERF_EFLAGS_EXACT;
1168 if ((sample_type & PERF_SAMPLE_ADDR) &&
1169 x86_pmu.intel_cap.pebs_format >= 1)
1170 data->addr = pebs->dla;
1172 if (x86_pmu.intel_cap.pebs_format >= 2) {
1173 /* Only set the TSX weight when no memory weight. */
1174 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1175 data->weight = intel_hsw_weight(pebs);
1177 if (sample_type & PERF_SAMPLE_TRANSACTION)
1178 data->txn = intel_hsw_transaction(pebs);
1182 * v3 supplies an accurate time stamp, so we use that
1183 * for the time stamp.
1185 * We can only do this for the default trace clock.
1187 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1188 event->attr.use_clockid == 0)
1189 data->time = native_sched_clock_from_tsc(pebs->tsc);
1191 if (has_branch_stack(event))
1192 data->br_stack = &cpuc->lbr_stack;
1195 static inline void *
1196 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1198 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1203 * fmt0 does not have a status bitfield (does not use
1204 * perf_record_nhm format)
1206 if (x86_pmu.intel_cap.pebs_format < 1)
1212 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1213 struct pebs_record_nhm *p = at;
1215 if (test_bit(bit, (unsigned long *)&p->status)) {
1216 /* PEBS v3 has accurate status bits */
1217 if (x86_pmu.intel_cap.pebs_format >= 3)
1220 if (p->status == (1 << bit))
1223 /* clear non-PEBS bit and re-check */
1224 pebs_status = p->status & cpuc->pebs_enabled;
1225 pebs_status &= PEBS_COUNTER_MASK;
1226 if (pebs_status == (1 << bit))
1233 static void __intel_pmu_pebs_event(struct perf_event *event,
1234 struct pt_regs *iregs,
1235 void *base, void *top,
1238 struct perf_sample_data data;
1239 struct pt_regs regs;
1240 void *at = get_next_pebs_record_by_bit(base, top, bit);
1242 if (!intel_pmu_save_and_restart(event) &&
1243 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1247 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1248 perf_event_output(event, &data, ®s);
1249 at += x86_pmu.pebs_record_size;
1250 at = get_next_pebs_record_by_bit(at, top, bit);
1254 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1257 * All but the last records are processed.
1258 * The last one is left to be able to call the overflow handler.
1260 if (perf_event_overflow(event, &data, ®s)) {
1261 x86_pmu_stop(event, 0);
1267 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1270 struct debug_store *ds = cpuc->ds;
1271 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1272 struct pebs_record_core *at, *top;
1275 if (!x86_pmu.pebs_active)
1278 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1279 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1282 * Whatever else happens, drain the thing
1284 ds->pebs_index = ds->pebs_buffer_base;
1286 if (!test_bit(0, cpuc->active_mask))
1289 WARN_ON_ONCE(!event);
1291 if (!event->attr.precise_ip)
1298 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1301 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1303 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1304 struct debug_store *ds = cpuc->ds;
1305 struct perf_event *event;
1306 void *base, *at, *top;
1307 short counts[MAX_PEBS_EVENTS] = {};
1308 short error[MAX_PEBS_EVENTS] = {};
1311 if (!x86_pmu.pebs_active)
1314 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1315 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1317 ds->pebs_index = ds->pebs_buffer_base;
1319 if (unlikely(base >= top))
1322 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1323 struct pebs_record_nhm *p = at;
1326 pebs_status = p->status & cpuc->pebs_enabled;
1327 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1329 /* PEBS v3 has more accurate status bits */
1330 if (x86_pmu.intel_cap.pebs_format >= 3) {
1331 for_each_set_bit(bit, (unsigned long *)&pebs_status,
1332 x86_pmu.max_pebs_events)
1339 * On some CPUs the PEBS status can be zero when PEBS is
1340 * racing with clearing of GLOBAL_STATUS.
1342 * Normally we would drop that record, but in the
1343 * case when there is only a single active PEBS event
1344 * we can assume it's for that event.
1346 if (!pebs_status && cpuc->pebs_enabled &&
1347 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1348 pebs_status = cpuc->pebs_enabled;
1350 bit = find_first_bit((unsigned long *)&pebs_status,
1351 x86_pmu.max_pebs_events);
1352 if (bit >= x86_pmu.max_pebs_events)
1356 * The PEBS hardware does not deal well with the situation
1357 * when events happen near to each other and multiple bits
1358 * are set. But it should happen rarely.
1360 * If these events include one PEBS and multiple non-PEBS
1361 * events, it doesn't impact PEBS record. The record will
1362 * be handled normally. (slow path)
1364 * If these events include two or more PEBS events, the
1365 * records for the events can be collapsed into a single
1366 * one, and it's not possible to reconstruct all events
1367 * that caused the PEBS record. It's called collision.
1368 * If collision happened, the record will be dropped.
1370 if (p->status != (1ULL << bit)) {
1371 for_each_set_bit(i, (unsigned long *)&pebs_status,
1372 x86_pmu.max_pebs_events)
1380 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1381 if ((counts[bit] == 0) && (error[bit] == 0))
1384 event = cpuc->events[bit];
1385 if (WARN_ON_ONCE(!event))
1388 if (WARN_ON_ONCE(!event->attr.precise_ip))
1391 /* log dropped samples number */
1393 perf_log_lost_samples(event, error[bit]);
1395 if (perf_event_account_interrupt(event))
1396 x86_pmu_stop(event, 0);
1400 __intel_pmu_pebs_event(event, iregs, base,
1401 top, bit, counts[bit]);
1407 * BTS, PEBS probe and setup
1410 void __init intel_ds_init(void)
1413 * No support for 32bit formats
1415 if (!boot_cpu_has(X86_FEATURE_DTES64))
1418 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1419 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1420 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1422 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1423 int format = x86_pmu.intel_cap.pebs_format;
1427 pr_cont("PEBS fmt0%c, ", pebs_type);
1428 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1430 * Using >PAGE_SIZE buffers makes the WRMSR to
1431 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1432 * mysteriously hang on Core2.
1434 * As a workaround, we don't do this.
1436 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1437 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1441 pr_cont("PEBS fmt1%c, ", pebs_type);
1442 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1443 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1447 pr_cont("PEBS fmt2%c, ", pebs_type);
1448 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1449 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1453 pr_cont("PEBS fmt3%c, ", pebs_type);
1454 x86_pmu.pebs_record_size =
1455 sizeof(struct pebs_record_skl);
1456 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1457 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1461 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1467 void perf_restore_debug_store(void)
1469 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1471 if (!x86_pmu.bts && !x86_pmu.pebs)
1474 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);