arch/x86/hyperv/hv_apic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Hyper-V specific APIC code.
   5  *
   6  * Copyright (C) 2018, Microsoft, Inc.
   7  *
   8  * Author : K. Y. Srinivasan <kys@microsoft.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  17  * NON INFRINGEMENT.  See the GNU General Public License for more
  18  * details.
  19  *
  20  */
  21
  22 #include <linux/types.h>
  23 #include <linux/version.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/mm.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/hyperv.h>
  28 #include <linux/slab.h>
  29 #include <linux/cpuhotplug.h>
  30 #include <asm/hypervisor.h>
  31 #include <asm/mshyperv.h>
  32 #include <asm/apic.h>
  33
  34 static struct apic orig_apic;
  35
  36 static u64 hv_apic_icr_read(void)
  37 {
  38         u64 reg_val;
  39
  40         rdmsrl(HV_X64_MSR_ICR, reg_val);
  41         return reg_val;
  42 }
  43
  44 static void hv_apic_icr_write(u32 low, u32 id)
  45 {
  46         u64 reg_val;
  47
  48         reg_val = SET_APIC_DEST_FIELD(id);
  49         reg_val = reg_val << 32;
  50         reg_val |= low;
  51
  52         wrmsrl(HV_X64_MSR_ICR, reg_val);
  53 }
  54
  55 static u32 hv_apic_read(u32 reg)
  56 {
  57         u32 reg_val, hi;
  58
  59         switch (reg) {
  60         case APIC_EOI:
  61                 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
  62                 return reg_val;
  63         case APIC_TASKPRI:
  64                 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
  65                 return reg_val;
  66
  67         default:
  68                 return native_apic_mem_read(reg);
  69         }
  70 }
  71
  72 static void hv_apic_write(u32 reg, u32 val)
  73 {
  74         switch (reg) {
  75         case APIC_EOI:
  76                 wrmsr(HV_X64_MSR_EOI, val, 0);
  77                 break;
  78         case APIC_TASKPRI:
  79                 wrmsr(HV_X64_MSR_TPR, val, 0);
  80                 break;
  81         default:
  82                 native_apic_mem_write(reg, val);
  83         }
  84 }
  85
  86 static void hv_apic_eoi_write(u32 reg, u32 val)
  87 {
  88         wrmsr(HV_X64_MSR_EOI, val, 0);
  89 }
  90
  91 /*
  92  * IPI implementation on Hyper-V.
  93  */
  94 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
  95 {
  96         struct ipi_arg_ex **arg;
  97         struct ipi_arg_ex *ipi_arg;
  98         unsigned long flags;
  99         int nr_bank = 0;
 100         int ret = 1;
 101
 102         local_irq_save(flags);
 103         arg = (struct ipi_arg_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
 104
 105         ipi_arg = *arg;
 106         if (unlikely(!ipi_arg))
 107                 goto ipi_mask_ex_done;
 108
 109         ipi_arg->vector = vector;
 110         ipi_arg->reserved = 0;
 111         ipi_arg->vp_set.valid_bank_mask = 0;
 112
 113         if (!cpumask_equal(mask, cpu_present_mask)) {
 114                 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
 115                 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
 116         }
 117         if (!nr_bank)
 118                 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
 119
 120         ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
 121                               ipi_arg, NULL);
 122
 123 ipi_mask_ex_done:
 124         local_irq_restore(flags);
 125         return ((ret == 0) ? true : false);
 126 }
 127
 128 static bool __send_ipi_mask(const struct cpumask *mask, int vector)
 129 {
 130         int cur_cpu, vcpu;
 131         struct ipi_arg_non_ex **arg;
 132         struct ipi_arg_non_ex *ipi_arg;
 133         int ret = 1;
 134         unsigned long flags;
 135
 136         if (cpumask_empty(mask))
 137                 return true;
 138
 139         if (!hv_hypercall_pg)
 140                 return false;
 141
 142         if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
 143                 return false;
 144
 145         if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
 146                 return __send_ipi_mask_ex(mask, vector);
 147
 148         local_irq_save(flags);
 149         arg = (struct ipi_arg_non_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
 150
 151         ipi_arg = *arg;
 152         if (unlikely(!ipi_arg))
 153                 goto ipi_mask_done;
 154
 155         ipi_arg->vector = vector;
 156         ipi_arg->reserved = 0;
 157         ipi_arg->cpu_mask = 0;
 158
 159         for_each_cpu(cur_cpu, mask) {
 160                 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
 161                 /*
 162                  * This particular version of the IPI hypercall can
 163                  * only target upto 64 CPUs.
 164                  */
 165                 if (vcpu >= 64)
 166                         goto ipi_mask_done;
 167
 168                 __set_bit(vcpu, (unsigned long *)&ipi_arg->cpu_mask);
 169         }
 170
 171         ret = hv_do_hypercall(HVCALL_SEND_IPI, ipi_arg, NULL);
 172
 173 ipi_mask_done:
 174         local_irq_restore(flags);
 175         return ((ret == 0) ? true : false);
 176 }
 177
 178 static bool __send_ipi_one(int cpu, int vector)
 179 {
 180         struct cpumask mask = CPU_MASK_NONE;
 181
 182         cpumask_set_cpu(cpu, &mask);
 183         return __send_ipi_mask(&mask, vector);
 184 }
 185
 186 static void hv_send_ipi(int cpu, int vector)
 187 {
 188         if (!__send_ipi_one(cpu, vector))
 189                 orig_apic.send_IPI(cpu, vector);
 190 }
 191
 192 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
 193 {
 194         if (!__send_ipi_mask(mask, vector))
 195                 orig_apic.send_IPI_mask(mask, vector);
 196 }
 197
 198 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
 199 {
 200         unsigned int this_cpu = smp_processor_id();
 201         struct cpumask new_mask;
 202         const struct cpumask *local_mask;
 203
 204         cpumask_copy(&new_mask, mask);
 205         cpumask_clear_cpu(this_cpu, &new_mask);
 206         local_mask = &new_mask;
 207         if (!__send_ipi_mask(local_mask, vector))
 208                 orig_apic.send_IPI_mask_allbutself(mask, vector);
 209 }
 210
 211 static void hv_send_ipi_allbutself(int vector)
 212 {
 213         hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
 214 }
 215
 216 static void hv_send_ipi_all(int vector)
 217 {
 218         if (!__send_ipi_mask(cpu_online_mask, vector))
 219                 orig_apic.send_IPI_all(vector);
 220 }
 221
 222 static void hv_send_ipi_self(int vector)
 223 {
 224         if (!__send_ipi_one(smp_processor_id(), vector))
 225                 orig_apic.send_IPI_self(vector);
 226 }
 227
 228 void __init hv_apic_init(void)
 229 {
 230         if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
 231                 if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
 232                         pr_info("Hyper-V: Using ext hypercalls for IPI\n");
 233                 else
 234                         pr_info("Hyper-V: Using IPI hypercalls\n");
 235                 /*
 236                  * Set the IPI entry points.
 237                  */
 238                 orig_apic = *apic;
 239
 240                 apic->send_IPI = hv_send_ipi;
 241                 apic->send_IPI_mask = hv_send_ipi_mask;
 242                 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
 243                 apic->send_IPI_allbutself = hv_send_ipi_allbutself;
 244                 apic->send_IPI_all = hv_send_ipi_all;
 245                 apic->send_IPI_self = hv_send_ipi_self;
 246         }
 247
 248         if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
 249                 pr_info("Hyper-V: Using MSR based APIC access\n");
 250                 apic_set_eoi_write(hv_apic_eoi_write);
 251                 apic->read      = hv_apic_read;
 252                 apic->write     = hv_apic_write;
 253                 apic->icr_write = hv_apic_icr_write;
 254                 apic->icr_read  = hv_apic_icr_read;
 255         }
 256 }