arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14
  15 /*
  16  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  17  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  18  */
  19 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  20 #define HYPERV_CPUID_INTERFACE                  0x40000001
  21 #define HYPERV_CPUID_VERSION                    0x40000002
  22 #define HYPERV_CPUID_FEATURES                   0x40000003
  23 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  24 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  25 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  26
  27 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  28 #define HYPERV_CPUID_MIN                        0x40000005
  29 #define HYPERV_CPUID_MAX                        0x4000ffff
  30
  31 /*
  32  * Feature identification. EAX indicates which features are available
  33  * to the partition based upon the current partition privileges.
  34  * These are HYPERV_CPUID_FEATURES.EAX bits.
  35  */
  36
  37 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  38 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         BIT(0)
  39 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  40 #define HV_MSR_TIME_REF_COUNT_AVAILABLE         BIT(1)
  41 /*
  42  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  43  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  44  */
  45 #define HV_X64_MSR_SYNIC_AVAILABLE              BIT(2)
  46 /*
  47  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  48  * HV_X64_MSR_STIMER3_COUNT) available
  49  */
  50 #define HV_MSR_SYNTIMER_AVAILABLE               BIT(3)
  51 /*
  52  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  53  * are available
  54  */
  55 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        BIT(4)
  56 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  57 #define HV_X64_MSR_HYPERCALL_AVAILABLE          BIT(5)
  58 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  59 #define HV_X64_MSR_VP_INDEX_AVAILABLE           BIT(6)
  60 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  61 #define HV_X64_MSR_RESET_AVAILABLE              BIT(7)
  62 /*
  63  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  64  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  65  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  66  */
  67 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         BIT(8)
  68 /* Partition reference TSC MSR is available */
  69 #define HV_MSR_REFERENCE_TSC_AVAILABLE          BIT(9)
  70 /* Partition Guest IDLE MSR is available */
  71 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE         BIT(10)
  72 /*
  73  * There is a single feature flag that signifies if the partition has access
  74  * to MSRs with local APIC and TSC frequencies.
  75  */
  76 #define HV_X64_ACCESS_FREQUENCY_MSRS            BIT(11)
  77 /* AccessReenlightenmentControls privilege */
  78 #define HV_X64_ACCESS_REENLIGHTENMENT           BIT(13)
  79
  80 /*
  81  * Feature identification: indicates which flags were specified at partition
  82  * creation. The format is the same as the partition creation flag structure
  83  * defined in section Partition Creation Flags.
  84  * These are HYPERV_CPUID_FEATURES.EBX bits.
  85  */
  86 #define HV_X64_CREATE_PARTITIONS                BIT(0)
  87 #define HV_X64_ACCESS_PARTITION_ID              BIT(1)
  88 #define HV_X64_ACCESS_MEMORY_POOL               BIT(2)
  89 #define HV_X64_ADJUST_MESSAGE_BUFFERS           BIT(3)
  90 #define HV_X64_POST_MESSAGES                    BIT(4)
  91 #define HV_X64_SIGNAL_EVENTS                    BIT(5)
  92 #define HV_X64_CREATE_PORT                      BIT(6)
  93 #define HV_X64_CONNECT_PORT                     BIT(7)
  94 #define HV_X64_ACCESS_STATS                     BIT(8)
  95 #define HV_X64_DEBUGGING                        BIT(11)
  96 #define HV_X64_CPU_POWER_MANAGEMENT             BIT(12)
  97
  98 /*
  99  * Feature identification. EDX indicates which miscellaneous features
 100  * are available to the partition.
 101  * These are HYPERV_CPUID_FEATURES.EDX bits.
 102  */
 103 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
 104 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
 105 /* Guest debugging support is available */
 106 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
 107 /* Performance Monitor support is available*/
 108 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
 109 /* Support for physical CPU dynamic partitioning events is available*/
 110 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
 111 /*
 112  * Support for passing hypercall input parameter block via XMM
 113  * registers is available
 114  */
 115 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           BIT(4)
 116 /* Support for a virtual guest idle state is available */
 117 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
 118 /* Frequency MSRs available */
 119 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
 120 /* Crash MSR available */
 121 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
 122 /* stimer Direct Mode is available */
 123 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
 124
 125 /*
 126  * Implementation recommendations. Indicates which behaviors the hypervisor
 127  * recommends the OS implement for optimal performance.
 128  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
 129  */
 130 /*
 131  * Recommend using hypercall for address space switches rather
 132  * than MOV to CR3 instruction
 133  */
 134 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
 135 /* Recommend using hypercall for local TLB flushes rather
 136  * than INVLPG or MOV to CR3 instructions */
 137 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
 138 /*
 139  * Recommend using hypercall for remote TLB flushes rather
 140  * than inter-processor interrupts
 141  */
 142 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
 143 /*
 144  * Recommend using MSRs for accessing APIC registers
 145  * EOI, ICR and TPR rather than their memory-mapped counterparts
 146  */
 147 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
 148 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 149 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
 150 /*
 151  * Recommend using relaxed timing for this partition. If used,
 152  * the VM should disable any watchdog timeouts that rely on the
 153  * timely delivery of external interrupts
 154  */
 155 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 156
 157 /*
 158  * Recommend not using Auto End-Of-Interrupt feature
 159  */
 160 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 161
 162 /*
 163  * Recommend using cluster IPI hypercalls.
 164  */
 165 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 166
 167 /* Recommend using the newer ExProcessorMasks interface */
 168 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 169
 170 /* Recommend using enlightened VMCS */
 171 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 172
 173 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 174 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 175 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 176
 177 /* Hyper-V specific model specific registers (MSRs) */
 178
 179 /* MSR used to identify the guest OS. */
 180 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 181
 182 /* MSR used to setup pages used to communicate with the hypervisor. */
 183 #define HV_X64_MSR_HYPERCALL                    0x40000001
 184
 185 /* MSR used to provide vcpu index */
 186 #define HV_X64_MSR_VP_INDEX                     0x40000002
 187
 188 /* MSR used to reset the guest OS. */
 189 #define HV_X64_MSR_RESET                        0x40000003
 190
 191 /* MSR used to provide vcpu runtime in 100ns units */
 192 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 193
 194 /* MSR used to read the per-partition time reference counter */
 195 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 196
 197 /* A partition's reference time stamp counter (TSC) page */
 198 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
 199
 200 /* MSR used to retrieve the TSC frequency */
 201 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 202
 203 /* MSR used to retrieve the local APIC timer frequency */
 204 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 205
 206 /* Define the virtual APIC registers */
 207 #define HV_X64_MSR_EOI                          0x40000070
 208 #define HV_X64_MSR_ICR                          0x40000071
 209 #define HV_X64_MSR_TPR                          0x40000072
 210 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 211
 212 /* Define synthetic interrupt controller model specific registers. */
 213 #define HV_X64_MSR_SCONTROL                     0x40000080
 214 #define HV_X64_MSR_SVERSION                     0x40000081
 215 #define HV_X64_MSR_SIEFP                        0x40000082
 216 #define HV_X64_MSR_SIMP                         0x40000083
 217 #define HV_X64_MSR_EOM                          0x40000084
 218 #define HV_X64_MSR_SINT0                        0x40000090
 219 #define HV_X64_MSR_SINT1                        0x40000091
 220 #define HV_X64_MSR_SINT2                        0x40000092
 221 #define HV_X64_MSR_SINT3                        0x40000093
 222 #define HV_X64_MSR_SINT4                        0x40000094
 223 #define HV_X64_MSR_SINT5                        0x40000095
 224 #define HV_X64_MSR_SINT6                        0x40000096
 225 #define HV_X64_MSR_SINT7                        0x40000097
 226 #define HV_X64_MSR_SINT8                        0x40000098
 227 #define HV_X64_MSR_SINT9                        0x40000099
 228 #define HV_X64_MSR_SINT10                       0x4000009A
 229 #define HV_X64_MSR_SINT11                       0x4000009B
 230 #define HV_X64_MSR_SINT12                       0x4000009C
 231 #define HV_X64_MSR_SINT13                       0x4000009D
 232 #define HV_X64_MSR_SINT14                       0x4000009E
 233 #define HV_X64_MSR_SINT15                       0x4000009F
 234
 235 /*
 236  * Synthetic Timer MSRs. Four timers per vcpu.
 237  */
 238 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 239 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 240 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 241 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 242 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 243 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 244 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 245 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 246
 247 /* Hyper-V guest idle MSR */
 248 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 249
 250 /* Hyper-V guest crash notification MSR's */
 251 #define HV_X64_MSR_CRASH_P0                     0x40000100
 252 #define HV_X64_MSR_CRASH_P1                     0x40000101
 253 #define HV_X64_MSR_CRASH_P2                     0x40000102
 254 #define HV_X64_MSR_CRASH_P3                     0x40000103
 255 #define HV_X64_MSR_CRASH_P4                     0x40000104
 256 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 257
 258 /* TSC emulation after migration */
 259 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 260 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 261 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 262
 263 /*
 264  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 265  */
 266 union hv_x64_msr_hypercall_contents {
 267         u64 as_uint64;
 268         struct {
 269                 u64 enable:1;
 270                 u64 reserved:11;
 271                 u64 guest_physical_address:52;
 272         } __packed;
 273 };
 274
 275 /*
 276  * TSC page layout.
 277  */
 278 struct ms_hyperv_tsc_page {
 279         volatile u32 tsc_sequence;
 280         u32 reserved1;
 281         volatile u64 tsc_scale;
 282         volatile s64 tsc_offset;
 283         u64 reserved2[509];
 284 }  __packed;
 285
 286 /*
 287  * The guest OS needs to register the guest ID with the hypervisor.
 288  * The guest ID is a 64 bit entity and the structure of this ID is
 289  * specified in the Hyper-V specification:
 290  *
 291  * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx
 292  *
 293  * While the current guideline does not specify how Linux guest ID(s)
 294  * need to be generated, our plan is to publish the guidelines for
 295  * Linux and other guest operating systems that currently are hosted
 296  * on Hyper-V. The implementation here conforms to this yet
 297  * unpublished guidelines.
 298  *
 299  *
 300  * Bit(s)
 301  * 63 - Indicates if the OS is Open Source or not; 1 is Open Source
 302  * 62:56 - Os Type; Linux is 0x100
 303  * 55:48 - Distro specific identification
 304  * 47:16 - Linux kernel version number
 305  * 15:0  - Distro specific identification
 306  *
 307  *
 308  */
 309
 310 #define HV_LINUX_VENDOR_ID              0x8100
 311
 312 struct hv_reenlightenment_control {
 313         __u64 vector:8;
 314         __u64 reserved1:8;
 315         __u64 enabled:1;
 316         __u64 reserved2:15;
 317         __u64 target_vp:32;
 318 }  __packed;
 319
 320 struct hv_tsc_emulation_control {
 321         __u64 enabled:1;
 322         __u64 reserved:63;
 323 } __packed;
 324
 325 struct hv_tsc_emulation_status {
 326         __u64 inprogress:1;
 327         __u64 reserved:63;
 328 } __packed;
 329
 330 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 331 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 332 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 333                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 334
 335 /*
 336  * Crash notification (HV_X64_MSR_CRASH_CTL) flags.
 337  */
 338 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG           BIT_ULL(62)
 339 #define HV_CRASH_CTL_CRASH_NOTIFY               BIT_ULL(63)
 340 #define HV_X64_MSR_CRASH_PARAMS         \
 341                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 342
 343 #define HV_IPI_LOW_VECTOR       0x10
 344 #define HV_IPI_HIGH_VECTOR      0xff
 345
 346 /* Declare the various hypercall operations. */
 347 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 348 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 349 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 350 #define HVCALL_SEND_IPI                         0x000b
 351 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 352 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 353 #define HVCALL_SEND_IPI_EX                      0x0015
 354 #define HVCALL_POST_MESSAGE                     0x005c
 355 #define HVCALL_SIGNAL_EVENT                     0x005d
 356 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
 357 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
 358
 359 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 360 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 361 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 362                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 363
 364 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 365 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 366
 367 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 368 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 369
 370 #define HV_PROCESSOR_POWER_STATE_C0             0
 371 #define HV_PROCESSOR_POWER_STATE_C1             1
 372 #define HV_PROCESSOR_POWER_STATE_C2             2
 373 #define HV_PROCESSOR_POWER_STATE_C3             3
 374
 375 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 376 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 377 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 378 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 379
 380 enum HV_GENERIC_SET_FORMAT {
 381         HV_GENERIC_SET_SPARSE_4K,
 382         HV_GENERIC_SET_ALL,
 383 };
 384
 385 #define HV_HYPERCALL_RESULT_MASK        GENMASK_ULL(15, 0)
 386 #define HV_HYPERCALL_FAST_BIT           BIT(16)
 387 #define HV_HYPERCALL_VARHEAD_OFFSET     17
 388 #define HV_HYPERCALL_REP_COMP_OFFSET    32
 389 #define HV_HYPERCALL_REP_COMP_MASK      GENMASK_ULL(43, 32)
 390 #define HV_HYPERCALL_REP_START_OFFSET   48
 391 #define HV_HYPERCALL_REP_START_MASK     GENMASK_ULL(59, 48)
 392
 393 /* hypercall status code */
 394 #define HV_STATUS_SUCCESS                       0
 395 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 396 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 397 #define HV_STATUS_INVALID_ALIGNMENT             4
 398 #define HV_STATUS_INVALID_PARAMETER             5
 399 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 400 #define HV_STATUS_INVALID_PORT_ID               17
 401 #define HV_STATUS_INVALID_CONNECTION_ID         18
 402 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 403
 404 typedef struct _HV_REFERENCE_TSC_PAGE {
 405         __u32 tsc_sequence;
 406         __u32 res1;
 407         __u64 tsc_scale;
 408         __s64 tsc_offset;
 409 }  __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 410
 411 /* Define the number of synthetic interrupt sources. */
 412 #define HV_SYNIC_SINT_COUNT             (16)
 413 /* Define the expected SynIC version. */
 414 #define HV_SYNIC_VERSION_1              (0x1)
 415 /* Valid SynIC vectors are 16-255. */
 416 #define HV_SYNIC_FIRST_VALID_VECTOR     (16)
 417
 418 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 419 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 420 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 421 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 422 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 423 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 424
 425 #define HV_SYNIC_STIMER_COUNT           (4)
 426
 427 /* Define synthetic interrupt controller message constants. */
 428 #define HV_MESSAGE_SIZE                 (256)
 429 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 430 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 431
 432 /* Define hypervisor message types. */
 433 enum hv_message_type {
 434         HVMSG_NONE                      = 0x00000000,
 435
 436         /* Memory access messages. */
 437         HVMSG_UNMAPPED_GPA              = 0x80000000,
 438         HVMSG_GPA_INTERCEPT             = 0x80000001,
 439
 440         /* Timer notification messages. */
 441         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 442
 443         /* Error messages. */
 444         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 445         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 446         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 447
 448         /* Trace buffer complete messages. */
 449         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 450
 451         /* Platform-specific processor intercept messages. */
 452         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 453         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 454         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 455         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 456         HVMSG_X64_APIC_EOI                      = 0x80010004,
 457         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 458 };
 459
 460 /* Define synthetic interrupt controller message flags. */
 461 union hv_message_flags {
 462         __u8 asu8;
 463         struct {
 464                 __u8 msg_pending:1;
 465                 __u8 reserved:7;
 466         } __packed;
 467 };
 468
 469 /* Define port identifier type. */
 470 union hv_port_id {
 471         __u32 asu32;
 472         struct {
 473                 __u32 id:24;
 474                 __u32 reserved:8;
 475         } __packed u;
 476 };
 477
 478 /* Define synthetic interrupt controller message header. */
 479 struct hv_message_header {
 480         __u32 message_type;
 481         __u8 payload_size;
 482         union hv_message_flags message_flags;
 483         __u8 reserved[2];
 484         union {
 485                 __u64 sender;
 486                 union hv_port_id port;
 487         };
 488 } __packed;
 489
 490 /* Define synthetic interrupt controller message format. */
 491 struct hv_message {
 492         struct hv_message_header header;
 493         union {
 494                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 495         } u;
 496 } __packed;
 497
 498 /* Define the synthetic interrupt message page layout. */
 499 struct hv_message_page {
 500         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 501 } __packed;
 502
 503 /* Define timer message payload structure. */
 504 struct hv_timer_message_payload {
 505         __u32 timer_index;
 506         __u32 reserved;
 507         __u64 expiration_time;  /* When the timer expired */
 508         __u64 delivery_time;    /* When the message was delivered */
 509 } __packed;
 510
 511 /* Define virtual processor assist page structure. */
 512 struct hv_vp_assist_page {
 513         __u32 apic_assist;
 514         __u32 reserved;
 515         __u64 vtl_control[2];
 516         __u64 nested_enlightenments_control[2];
 517         __u32 enlighten_vmentry;
 518         __u32 padding;
 519         __u64 current_nested_vmcs;
 520 } __packed;
 521
 522 struct hv_enlightened_vmcs {
 523         u32 revision_id;
 524         u32 abort;
 525
 526         u16 host_es_selector;
 527         u16 host_cs_selector;
 528         u16 host_ss_selector;
 529         u16 host_ds_selector;
 530         u16 host_fs_selector;
 531         u16 host_gs_selector;
 532         u16 host_tr_selector;
 533
 534         u16 padding16_1;
 535
 536         u64 host_ia32_pat;
 537         u64 host_ia32_efer;
 538
 539         u64 host_cr0;
 540         u64 host_cr3;
 541         u64 host_cr4;
 542
 543         u64 host_ia32_sysenter_esp;
 544         u64 host_ia32_sysenter_eip;
 545         u64 host_rip;
 546         u32 host_ia32_sysenter_cs;
 547
 548         u32 pin_based_vm_exec_control;
 549         u32 vm_exit_controls;
 550         u32 secondary_vm_exec_control;
 551
 552         u64 io_bitmap_a;
 553         u64 io_bitmap_b;
 554         u64 msr_bitmap;
 555
 556         u16 guest_es_selector;
 557         u16 guest_cs_selector;
 558         u16 guest_ss_selector;
 559         u16 guest_ds_selector;
 560         u16 guest_fs_selector;
 561         u16 guest_gs_selector;
 562         u16 guest_ldtr_selector;
 563         u16 guest_tr_selector;
 564
 565         u32 guest_es_limit;
 566         u32 guest_cs_limit;
 567         u32 guest_ss_limit;
 568         u32 guest_ds_limit;
 569         u32 guest_fs_limit;
 570         u32 guest_gs_limit;
 571         u32 guest_ldtr_limit;
 572         u32 guest_tr_limit;
 573         u32 guest_gdtr_limit;
 574         u32 guest_idtr_limit;
 575
 576         u32 guest_es_ar_bytes;
 577         u32 guest_cs_ar_bytes;
 578         u32 guest_ss_ar_bytes;
 579         u32 guest_ds_ar_bytes;
 580         u32 guest_fs_ar_bytes;
 581         u32 guest_gs_ar_bytes;
 582         u32 guest_ldtr_ar_bytes;
 583         u32 guest_tr_ar_bytes;
 584
 585         u64 guest_es_base;
 586         u64 guest_cs_base;
 587         u64 guest_ss_base;
 588         u64 guest_ds_base;
 589         u64 guest_fs_base;
 590         u64 guest_gs_base;
 591         u64 guest_ldtr_base;
 592         u64 guest_tr_base;
 593         u64 guest_gdtr_base;
 594         u64 guest_idtr_base;
 595
 596         u64 padding64_1[3];
 597
 598         u64 vm_exit_msr_store_addr;
 599         u64 vm_exit_msr_load_addr;
 600         u64 vm_entry_msr_load_addr;
 601
 602         u64 cr3_target_value0;
 603         u64 cr3_target_value1;
 604         u64 cr3_target_value2;
 605         u64 cr3_target_value3;
 606
 607         u32 page_fault_error_code_mask;
 608         u32 page_fault_error_code_match;
 609
 610         u32 cr3_target_count;
 611         u32 vm_exit_msr_store_count;
 612         u32 vm_exit_msr_load_count;
 613         u32 vm_entry_msr_load_count;
 614
 615         u64 tsc_offset;
 616         u64 virtual_apic_page_addr;
 617         u64 vmcs_link_pointer;
 618
 619         u64 guest_ia32_debugctl;
 620         u64 guest_ia32_pat;
 621         u64 guest_ia32_efer;
 622
 623         u64 guest_pdptr0;
 624         u64 guest_pdptr1;
 625         u64 guest_pdptr2;
 626         u64 guest_pdptr3;
 627
 628         u64 guest_pending_dbg_exceptions;
 629         u64 guest_sysenter_esp;
 630         u64 guest_sysenter_eip;
 631
 632         u32 guest_activity_state;
 633         u32 guest_sysenter_cs;
 634
 635         u64 cr0_guest_host_mask;
 636         u64 cr4_guest_host_mask;
 637         u64 cr0_read_shadow;
 638         u64 cr4_read_shadow;
 639         u64 guest_cr0;
 640         u64 guest_cr3;
 641         u64 guest_cr4;
 642         u64 guest_dr7;
 643
 644         u64 host_fs_base;
 645         u64 host_gs_base;
 646         u64 host_tr_base;
 647         u64 host_gdtr_base;
 648         u64 host_idtr_base;
 649         u64 host_rsp;
 650
 651         u64 ept_pointer;
 652
 653         u16 virtual_processor_id;
 654         u16 padding16_2[3];
 655
 656         u64 padding64_2[5];
 657         u64 guest_physical_address;
 658
 659         u32 vm_instruction_error;
 660         u32 vm_exit_reason;
 661         u32 vm_exit_intr_info;
 662         u32 vm_exit_intr_error_code;
 663         u32 idt_vectoring_info_field;
 664         u32 idt_vectoring_error_code;
 665         u32 vm_exit_instruction_len;
 666         u32 vmx_instruction_info;
 667
 668         u64 exit_qualification;
 669         u64 exit_io_instruction_ecx;
 670         u64 exit_io_instruction_esi;
 671         u64 exit_io_instruction_edi;
 672         u64 exit_io_instruction_eip;
 673
 674         u64 guest_linear_address;
 675         u64 guest_rsp;
 676         u64 guest_rflags;
 677
 678         u32 guest_interruptibility_info;
 679         u32 cpu_based_vm_exec_control;
 680         u32 exception_bitmap;
 681         u32 vm_entry_controls;
 682         u32 vm_entry_intr_info_field;
 683         u32 vm_entry_exception_error_code;
 684         u32 vm_entry_instruction_len;
 685         u32 tpr_threshold;
 686
 687         u64 guest_rip;
 688
 689         u32 hv_clean_fields;
 690         u32 hv_padding_32;
 691         u32 hv_synthetic_controls;
 692         struct {
 693                 u32 nested_flush_hypercall:1;
 694                 u32 msr_bitmap:1;
 695                 u32 reserved:30;
 696         }  __packed hv_enlightenments_control;
 697         u32 hv_vp_id;
 698
 699         u64 hv_vm_id;
 700         u64 partition_assist_page;
 701         u64 padding64_4[4];
 702         u64 guest_bndcfgs;
 703         u64 padding64_5[7];
 704         u64 xss_exit_bitmap;
 705         u64 padding64_6[7];
 706 } __packed;
 707
 708 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 709 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 710 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 711 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 712 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 713 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 714 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 715 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 716 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 717 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 718 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 719 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 720 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 721 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 722 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 723 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 724 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 725
 726 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 727
 728 /* Define synthetic interrupt controller flag constants. */
 729 #define HV_EVENT_FLAGS_COUNT            (256 * 8)
 730 #define HV_EVENT_FLAGS_LONG_COUNT       (256 / sizeof(unsigned long))
 731
 732 /*
 733  * Synthetic timer configuration.
 734  */
 735 union hv_stimer_config {
 736         u64 as_uint64;
 737         struct {
 738                 u64 enable:1;
 739                 u64 periodic:1;
 740                 u64 lazy:1;
 741                 u64 auto_enable:1;
 742                 u64 apic_vector:8;
 743                 u64 direct_mode:1;
 744                 u64 reserved_z0:3;
 745                 u64 sintx:4;
 746                 u64 reserved_z1:44;
 747         } __packed;
 748 };
 749
 750
 751 /* Define the synthetic interrupt controller event flags format. */
 752 union hv_synic_event_flags {
 753         unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT];
 754 };
 755
 756 /* Define SynIC control register. */
 757 union hv_synic_scontrol {
 758         u64 as_uint64;
 759         struct {
 760                 u64 enable:1;
 761                 u64 reserved:63;
 762         } __packed;
 763 };
 764
 765 /* Define synthetic interrupt source. */
 766 union hv_synic_sint {
 767         u64 as_uint64;
 768         struct {
 769                 u64 vector:8;
 770                 u64 reserved1:8;
 771                 u64 masked:1;
 772                 u64 auto_eoi:1;
 773                 u64 reserved2:46;
 774         } __packed;
 775 };
 776
 777 /* Define the format of the SIMP register */
 778 union hv_synic_simp {
 779         u64 as_uint64;
 780         struct {
 781                 u64 simp_enabled:1;
 782                 u64 preserved:11;
 783                 u64 base_simp_gpa:52;
 784         } __packed;
 785 };
 786
 787 /* Define the format of the SIEFP register */
 788 union hv_synic_siefp {
 789         u64 as_uint64;
 790         struct {
 791                 u64 siefp_enabled:1;
 792                 u64 preserved:11;
 793                 u64 base_siefp_gpa:52;
 794         } __packed;
 795 };
 796
 797 struct hv_vpset {
 798         u64 format;
 799         u64 valid_bank_mask;
 800         u64 bank_contents[];
 801 } __packed;
 802
 803 /* HvCallSendSyntheticClusterIpi hypercall */
 804 struct hv_send_ipi {
 805         u32 vector;
 806         u32 reserved;
 807         u64 cpu_mask;
 808 } __packed;
 809
 810 /* HvCallSendSyntheticClusterIpiEx hypercall */
 811 struct hv_send_ipi_ex {
 812         u32 vector;
 813         u32 reserved;
 814         struct hv_vpset vp_set;
 815 } __packed;
 816
 817 /* HvFlushGuestPhysicalAddressSpace hypercalls */
 818 struct hv_guest_mapping_flush {
 819         u64 address_space;
 820         u64 flags;
 821 } __packed;
 822
 823 /*
 824  *  HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
 825  *  by the bitwidth of "additional_pages" in union hv_gpa_page_range.
 826  */
 827 #define HV_MAX_FLUSH_PAGES (2048)
 828
 829 /* HvFlushGuestPhysicalAddressList hypercall */
 830 union hv_gpa_page_range {
 831         u64 address_space;
 832         struct {
 833                 u64 additional_pages:11;
 834                 u64 largepage:1;
 835                 u64 basepfn:52;
 836         } page;
 837 };
 838
 839 /*
 840  * All input flush parameters should be in single page. The max flush
 841  * count is equal with how many entries of union hv_gpa_page_range can
 842  * be populated into the input parameter page.
 843  */
 844 #define HV_MAX_FLUSH_REP_COUNT ((PAGE_SIZE - 2 * sizeof(u64)) / \
 845                                 sizeof(union hv_gpa_page_range))
 846
 847 struct hv_guest_mapping_flush_list {
 848         u64 address_space;
 849         u64 flags;
 850         union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
 851 };
 852
 853 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */
 854 struct hv_tlb_flush {
 855         u64 address_space;
 856         u64 flags;
 857         u64 processor_mask;
 858         u64 gva_list[];
 859 } __packed;
 860
 861 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
 862 struct hv_tlb_flush_ex {
 863         u64 address_space;
 864         u64 flags;
 865         struct hv_vpset hv_vp_set;
 866         u64 gva_list[];
 867 } __packed;
 868
 869 #endif