arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24
  25 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  26 #define HYPERV_CPUID_MIN                        0x40000005
  27 #define HYPERV_CPUID_MAX                        0x4000ffff
  28
  29 /*
  30  * Feature identification. EAX indicates which features are available
  31  * to the partition based upon the current partition privileges.
  32  */
  33
  34 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  35 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
  36 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  37 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
  38 /* Partition reference TSC MSR is available */
  39 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)
  40
  41 /* A partition's reference time stamp counter (TSC) page */
  42 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
  43
  44 /*
  45  * There is a single feature flag that signifies if the partition has access
  46  * to MSRs with local APIC and TSC frequencies.
  47  */
  48 #define HV_X64_ACCESS_FREQUENCY_MSRS            (1 << 11)
  49
  50 /* AccessReenlightenmentControls privilege */
  51 #define HV_X64_ACCESS_REENLIGHTENMENT           BIT(13)
  52
  53 /*
  54  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  55  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  56  */
  57 #define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
  58 /*
  59  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  60  * HV_X64_MSR_STIMER3_COUNT) available
  61  */
  62 #define HV_X64_MSR_SYNTIMER_AVAILABLE           (1 << 3)
  63 /*
  64  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  65  * are available
  66  */
  67 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
  68 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  69 #define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
  70 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  71 #define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
  72 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  73 #define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
  74  /*
  75   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  76   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  77   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  78   */
  79 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
  80
  81 /* Frequency MSRs available */
  82 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE     (1 << 8)
  83
  84 /* Crash MSR available */
  85 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
  86
  87 /*
  88  * Feature identification: EBX indicates which flags were specified at
  89  * partition creation. The format is the same as the partition creation
  90  * flag structure defined in section Partition Creation Flags.
  91  */
  92 #define HV_X64_CREATE_PARTITIONS                (1 << 0)
  93 #define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
  94 #define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
  95 #define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
  96 #define HV_X64_POST_MESSAGES                    (1 << 4)
  97 #define HV_X64_SIGNAL_EVENTS                    (1 << 5)
  98 #define HV_X64_CREATE_PORT                      (1 << 6)
  99 #define HV_X64_CONNECT_PORT                     (1 << 7)
 100 #define HV_X64_ACCESS_STATS                     (1 << 8)
 101 #define HV_X64_DEBUGGING                        (1 << 11)
 102 #define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
 103 #define HV_X64_CONFIGURE_PROFILER               (1 << 13)
 104
 105 /*
 106  * Feature identification. EDX indicates which miscellaneous features
 107  * are available to the partition.
 108  */
 109 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
 110 #define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
 111 /* Guest debugging support is available */
 112 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
 113 /* Performance Monitor support is available*/
 114 #define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
 115 /* Support for physical CPU dynamic partitioning events is available*/
 116 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
 117 /*
 118  * Support for passing hypercall input parameter block via XMM
 119  * registers is available
 120  */
 121 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
 122 /* Support for a virtual guest idle state is available */
 123 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
 124 /* Guest crash data handler available */
 125 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE                (1 << 10)
 126
 127 /*
 128  * Implementation recommendations. Indicates which behaviors the hypervisor
 129  * recommends the OS implement for optimal performance.
 130  */
 131  /*
 132   * Recommend using hypercall for address space switches rather
 133   * than MOV to CR3 instruction
 134   */
 135 #define HV_X64_AS_SWITCH_RECOMMENDED            (1 << 0)
 136 /* Recommend using hypercall for local TLB flushes rather
 137  * than INVLPG or MOV to CR3 instructions */
 138 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
 139 /*
 140  * Recommend using hypercall for remote TLB flushes rather
 141  * than inter-processor interrupts
 142  */
 143 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
 144 /*
 145  * Recommend using MSRs for accessing APIC registers
 146  * EOI, ICR and TPR rather than their memory-mapped counterparts
 147  */
 148 #define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
 149 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 150 #define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
 151 /*
 152  * Recommend using relaxed timing for this partition. If used,
 153  * the VM should disable any watchdog timeouts that rely on the
 154  * timely delivery of external interrupts
 155  */
 156 #define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
 157
 158 /*
 159  * Virtual APIC support
 160  */
 161 #define HV_X64_DEPRECATING_AEOI_RECOMMENDED     (1 << 9)
 162
 163 /* Recommend using the newer ExProcessorMasks interface */
 164 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED   (1 << 11)
 165
 166 /*
 167  * Crash notification flag.
 168  */
 169 #define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
 170
 171 /* MSR used to identify the guest OS. */
 172 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 173
 174 /* MSR used to setup pages used to communicate with the hypervisor. */
 175 #define HV_X64_MSR_HYPERCALL                    0x40000001
 176
 177 /* MSR used to provide vcpu index */
 178 #define HV_X64_MSR_VP_INDEX                     0x40000002
 179
 180 /* MSR used to reset the guest OS. */
 181 #define HV_X64_MSR_RESET                        0x40000003
 182
 183 /* MSR used to provide vcpu runtime in 100ns units */
 184 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 185
 186 /* MSR used to read the per-partition time reference counter */
 187 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 188
 189 /* MSR used to retrieve the TSC frequency */
 190 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 191
 192 /* MSR used to retrieve the local APIC timer frequency */
 193 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 194
 195 /* Define the virtual APIC registers */
 196 #define HV_X64_MSR_EOI                          0x40000070
 197 #define HV_X64_MSR_ICR                          0x40000071
 198 #define HV_X64_MSR_TPR                          0x40000072
 199 #define HV_X64_MSR_APIC_ASSIST_PAGE             0x40000073
 200
 201 /* Define synthetic interrupt controller model specific registers. */
 202 #define HV_X64_MSR_SCONTROL                     0x40000080
 203 #define HV_X64_MSR_SVERSION                     0x40000081
 204 #define HV_X64_MSR_SIEFP                        0x40000082
 205 #define HV_X64_MSR_SIMP                         0x40000083
 206 #define HV_X64_MSR_EOM                          0x40000084
 207 #define HV_X64_MSR_SINT0                        0x40000090
 208 #define HV_X64_MSR_SINT1                        0x40000091
 209 #define HV_X64_MSR_SINT2                        0x40000092
 210 #define HV_X64_MSR_SINT3                        0x40000093
 211 #define HV_X64_MSR_SINT4                        0x40000094
 212 #define HV_X64_MSR_SINT5                        0x40000095
 213 #define HV_X64_MSR_SINT6                        0x40000096
 214 #define HV_X64_MSR_SINT7                        0x40000097
 215 #define HV_X64_MSR_SINT8                        0x40000098
 216 #define HV_X64_MSR_SINT9                        0x40000099
 217 #define HV_X64_MSR_SINT10                       0x4000009A
 218 #define HV_X64_MSR_SINT11                       0x4000009B
 219 #define HV_X64_MSR_SINT12                       0x4000009C
 220 #define HV_X64_MSR_SINT13                       0x4000009D
 221 #define HV_X64_MSR_SINT14                       0x4000009E
 222 #define HV_X64_MSR_SINT15                       0x4000009F
 223
 224 /*
 225  * Synthetic Timer MSRs. Four timers per vcpu.
 226  */
 227 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 228 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 229 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 230 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 231 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 232 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 233 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 234 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 235
 236 /* Hyper-V guest crash notification MSR's */
 237 #define HV_X64_MSR_CRASH_P0                     0x40000100
 238 #define HV_X64_MSR_CRASH_P1                     0x40000101
 239 #define HV_X64_MSR_CRASH_P2                     0x40000102
 240 #define HV_X64_MSR_CRASH_P3                     0x40000103
 241 #define HV_X64_MSR_CRASH_P4                     0x40000104
 242 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 243 #define HV_X64_MSR_CRASH_CTL_NOTIFY             (1ULL << 63)
 244 #define HV_X64_MSR_CRASH_PARAMS         \
 245                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 246
 247 /* TSC emulation after migration */
 248 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 249
 250 struct hv_reenlightenment_control {
 251         __u64 vector:8;
 252         __u64 reserved1:8;
 253         __u64 enabled:1;
 254         __u64 reserved2:15;
 255         __u64 target_vp:32;
 256 };
 257
 258 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 259 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 260
 261 struct hv_tsc_emulation_control {
 262         __u64 enabled:1;
 263         __u64 reserved:63;
 264 };
 265
 266 struct hv_tsc_emulation_status {
 267         __u64 inprogress:1;
 268         __u64 reserved:63;
 269 };
 270
 271 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 272 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 273 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 274                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 275
 276 /* Declare the various hypercall operations. */
 277 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 278 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 279 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 280 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 281 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 282 #define HVCALL_POST_MESSAGE                     0x005c
 283 #define HVCALL_SIGNAL_EVENT                     0x005d
 284
 285 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE              0x00000001
 286 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT       12
 287 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
 288                 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 289
 290 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 291 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 292
 293 #define HV_PROCESSOR_POWER_STATE_C0             0
 294 #define HV_PROCESSOR_POWER_STATE_C1             1
 295 #define HV_PROCESSOR_POWER_STATE_C2             2
 296 #define HV_PROCESSOR_POWER_STATE_C3             3
 297
 298 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 299 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 300 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 301 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 302
 303 enum HV_GENERIC_SET_FORMAT {
 304         HV_GENERIC_SET_SPARCE_4K,
 305         HV_GENERIC_SET_ALL,
 306 };
 307
 308 /* hypercall status code */
 309 #define HV_STATUS_SUCCESS                       0
 310 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 311 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 312 #define HV_STATUS_INVALID_ALIGNMENT             4
 313 #define HV_STATUS_INVALID_PARAMETER             5
 314 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 315 #define HV_STATUS_INVALID_PORT_ID               17
 316 #define HV_STATUS_INVALID_CONNECTION_ID         18
 317 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 318
 319 typedef struct _HV_REFERENCE_TSC_PAGE {
 320         __u32 tsc_sequence;
 321         __u32 res1;
 322         __u64 tsc_scale;
 323         __s64 tsc_offset;
 324 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 325
 326 /* Define the number of synthetic interrupt sources. */
 327 #define HV_SYNIC_SINT_COUNT             (16)
 328 /* Define the expected SynIC version. */
 329 #define HV_SYNIC_VERSION_1              (0x1)
 330 /* Valid SynIC vectors are 16-255. */
 331 #define HV_SYNIC_FIRST_VALID_VECTOR     (16)
 332
 333 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 334 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 335 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 336 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 337 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 338 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 339
 340 #define HV_SYNIC_STIMER_COUNT           (4)
 341
 342 /* Define synthetic interrupt controller message constants. */
 343 #define HV_MESSAGE_SIZE                 (256)
 344 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 345 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 346
 347 /* Define hypervisor message types. */
 348 enum hv_message_type {
 349         HVMSG_NONE                      = 0x00000000,
 350
 351         /* Memory access messages. */
 352         HVMSG_UNMAPPED_GPA              = 0x80000000,
 353         HVMSG_GPA_INTERCEPT             = 0x80000001,
 354
 355         /* Timer notification messages. */
 356         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 357
 358         /* Error messages. */
 359         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 360         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 361         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 362
 363         /* Trace buffer complete messages. */
 364         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 365
 366         /* Platform-specific processor intercept messages. */
 367         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 368         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 369         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 370         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 371         HVMSG_X64_APIC_EOI                      = 0x80010004,
 372         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 373 };
 374
 375 /* Define synthetic interrupt controller message flags. */
 376 union hv_message_flags {
 377         __u8 asu8;
 378         struct {
 379                 __u8 msg_pending:1;
 380                 __u8 reserved:7;
 381         };
 382 };
 383
 384 /* Define port identifier type. */
 385 union hv_port_id {
 386         __u32 asu32;
 387         struct {
 388                 __u32 id:24;
 389                 __u32 reserved:8;
 390         } u;
 391 };
 392
 393 /* Define synthetic interrupt controller message header. */
 394 struct hv_message_header {
 395         __u32 message_type;
 396         __u8 payload_size;
 397         union hv_message_flags message_flags;
 398         __u8 reserved[2];
 399         union {
 400                 __u64 sender;
 401                 union hv_port_id port;
 402         };
 403 };
 404
 405 /* Define synthetic interrupt controller message format. */
 406 struct hv_message {
 407         struct hv_message_header header;
 408         union {
 409                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 410         } u;
 411 };
 412
 413 /* Define the synthetic interrupt message page layout. */
 414 struct hv_message_page {
 415         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 416 };
 417
 418 /* Define timer message payload structure. */
 419 struct hv_timer_message_payload {
 420         __u32 timer_index;
 421         __u32 reserved;
 422         __u64 expiration_time;  /* When the timer expired */
 423         __u64 delivery_time;    /* When the message was delivered */
 424 };
 425
 426 #define HV_STIMER_ENABLE                (1ULL << 0)
 427 #define HV_STIMER_PERIODIC              (1ULL << 1)
 428 #define HV_STIMER_LAZY                  (1ULL << 2)
 429 #define HV_STIMER_AUTOENABLE            (1ULL << 3)
 430 #define HV_STIMER_SINT(config)          (__u8)(((config) >> 16) & 0x0F)
 431
 432 #endif