1 #ifndef _ASM_X86_PARAVIRT_H
2 #define _ASM_X86_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
7 #include <asm/pgtable_types.h>
10 #include <asm/paravirt_types.h>
13 #include <linux/bug.h>
14 #include <linux/types.h>
15 #include <linux/cpumask.h>
16 #include <asm/frame.h>
18 static inline void load_sp0(struct tss_struct *tss,
19 struct thread_struct *thread)
21 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
24 /* The paravirtualized CPUID instruction. */
25 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
26 unsigned int *ecx, unsigned int *edx)
28 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
32 * These special macros can be used to get or set a debugging register
34 static inline unsigned long paravirt_get_debugreg(int reg)
36 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
38 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
39 static inline void set_debugreg(unsigned long val, int reg)
41 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
44 static inline void clts(void)
46 PVOP_VCALL0(pv_cpu_ops.clts);
49 static inline unsigned long read_cr0(void)
51 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
54 static inline void write_cr0(unsigned long x)
56 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
59 static inline unsigned long read_cr2(void)
61 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
64 static inline void write_cr2(unsigned long x)
66 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
69 static inline unsigned long read_cr3(void)
71 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
74 static inline void write_cr3(unsigned long x)
76 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
79 static inline unsigned long __read_cr4(void)
81 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
84 static inline void __write_cr4(unsigned long x)
86 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
90 static inline unsigned long read_cr8(void)
92 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
95 static inline void write_cr8(unsigned long x)
97 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
101 static inline void arch_safe_halt(void)
103 PVOP_VCALL0(pv_irq_ops.safe_halt);
106 static inline void halt(void)
108 PVOP_VCALL0(pv_irq_ops.halt);
111 static inline void wbinvd(void)
113 PVOP_VCALL0(pv_cpu_ops.wbinvd);
116 #define get_kernel_rpl() (pv_info.kernel_rpl)
118 static inline u64 paravirt_read_msr(unsigned msr)
120 return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr);
123 static inline void paravirt_write_msr(unsigned msr,
124 unsigned low, unsigned high)
126 return PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high);
129 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
131 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err);
134 static inline int paravirt_write_msr_safe(unsigned msr,
135 unsigned low, unsigned high)
137 return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high);
140 #define rdmsr(msr, val1, val2) \
142 u64 _l = paravirt_read_msr(msr); \
147 #define wrmsr(msr, val1, val2) \
149 paravirt_write_msr(msr, val1, val2); \
152 #define rdmsrl(msr, val) \
154 val = paravirt_read_msr(msr); \
157 static inline void wrmsrl(unsigned msr, u64 val)
159 wrmsr(msr, (u32)val, (u32)(val>>32));
162 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
164 /* rdmsr with exception handling */
165 #define rdmsr_safe(msr, a, b) \
168 u64 _l = paravirt_read_msr_safe(msr, &_err); \
174 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
178 *p = paravirt_read_msr_safe(msr, &err);
182 static inline unsigned long long paravirt_sched_clock(void)
184 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
188 extern struct static_key paravirt_steal_enabled;
189 extern struct static_key paravirt_steal_rq_enabled;
191 static inline u64 paravirt_steal_clock(int cpu)
193 return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu);
196 static inline unsigned long long paravirt_read_pmc(int counter)
198 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
201 #define rdpmc(counter, low, high) \
203 u64 _l = paravirt_read_pmc(counter); \
208 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
210 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
212 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
215 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
217 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
220 static inline void load_TR_desc(void)
222 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
224 static inline void load_gdt(const struct desc_ptr *dtr)
226 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
228 static inline void load_idt(const struct desc_ptr *dtr)
230 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
232 static inline void set_ldt(const void *addr, unsigned entries)
234 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
236 static inline void store_idt(struct desc_ptr *dtr)
238 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
240 static inline unsigned long paravirt_store_tr(void)
242 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
244 #define store_tr(tr) ((tr) = paravirt_store_tr())
245 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
247 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
251 static inline void load_gs_index(unsigned int gs)
253 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
257 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
260 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
263 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
264 void *desc, int type)
266 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
269 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
271 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
273 static inline void set_iopl_mask(unsigned mask)
275 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
278 /* The paravirtualized I/O functions */
279 static inline void slow_down_io(void)
281 pv_cpu_ops.io_delay();
282 #ifdef REALLY_SLOW_IO
283 pv_cpu_ops.io_delay();
284 pv_cpu_ops.io_delay();
285 pv_cpu_ops.io_delay();
289 static inline void paravirt_activate_mm(struct mm_struct *prev,
290 struct mm_struct *next)
292 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
295 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
296 struct mm_struct *mm)
298 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
301 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
303 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
306 static inline void __flush_tlb(void)
308 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
310 static inline void __flush_tlb_global(void)
312 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
314 static inline void __flush_tlb_single(unsigned long addr)
316 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
319 static inline void flush_tlb_others(const struct cpumask *cpumask,
320 struct mm_struct *mm,
324 PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end);
327 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
329 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
332 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
334 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
337 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
339 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
341 static inline void paravirt_release_pte(unsigned long pfn)
343 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
346 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
348 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
351 static inline void paravirt_release_pmd(unsigned long pfn)
353 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
356 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
358 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
360 static inline void paravirt_release_pud(unsigned long pfn)
362 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
365 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
368 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
371 static inline pte_t __pte(pteval_t val)
375 if (sizeof(pteval_t) > sizeof(long))
376 ret = PVOP_CALLEE2(pteval_t,
378 val, (u64)val >> 32);
380 ret = PVOP_CALLEE1(pteval_t,
384 return (pte_t) { .pte = ret };
387 static inline pteval_t pte_val(pte_t pte)
391 if (sizeof(pteval_t) > sizeof(long))
392 ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val,
393 pte.pte, (u64)pte.pte >> 32);
395 ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val,
401 static inline pgd_t __pgd(pgdval_t val)
405 if (sizeof(pgdval_t) > sizeof(long))
406 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd,
407 val, (u64)val >> 32);
409 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd,
412 return (pgd_t) { ret };
415 static inline pgdval_t pgd_val(pgd_t pgd)
419 if (sizeof(pgdval_t) > sizeof(long))
420 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val,
421 pgd.pgd, (u64)pgd.pgd >> 32);
423 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val,
429 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
430 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
435 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
438 return (pte_t) { .pte = ret };
441 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
442 pte_t *ptep, pte_t pte)
444 if (sizeof(pteval_t) > sizeof(long))
446 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
448 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
449 mm, addr, ptep, pte.pte);
452 static inline void set_pte(pte_t *ptep, pte_t pte)
454 if (sizeof(pteval_t) > sizeof(long))
455 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
456 pte.pte, (u64)pte.pte >> 32);
458 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
462 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
463 pte_t *ptep, pte_t pte)
465 if (sizeof(pteval_t) > sizeof(long))
467 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
469 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
472 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
473 pmd_t *pmdp, pmd_t pmd)
475 if (sizeof(pmdval_t) > sizeof(long))
477 pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd);
479 PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp,
480 native_pmd_val(pmd));
483 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
485 pmdval_t val = native_pmd_val(pmd);
487 if (sizeof(pmdval_t) > sizeof(long))
488 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
490 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
493 #if CONFIG_PGTABLE_LEVELS >= 3
494 static inline pmd_t __pmd(pmdval_t val)
498 if (sizeof(pmdval_t) > sizeof(long))
499 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd,
500 val, (u64)val >> 32);
502 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd,
505 return (pmd_t) { ret };
508 static inline pmdval_t pmd_val(pmd_t pmd)
512 if (sizeof(pmdval_t) > sizeof(long))
513 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val,
514 pmd.pmd, (u64)pmd.pmd >> 32);
516 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val,
522 static inline void set_pud(pud_t *pudp, pud_t pud)
524 pudval_t val = native_pud_val(pud);
526 if (sizeof(pudval_t) > sizeof(long))
527 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
528 val, (u64)val >> 32);
530 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
533 #if CONFIG_PGTABLE_LEVELS == 4
534 static inline pud_t __pud(pudval_t val)
538 if (sizeof(pudval_t) > sizeof(long))
539 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud,
540 val, (u64)val >> 32);
542 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud,
545 return (pud_t) { ret };
548 static inline pudval_t pud_val(pud_t pud)
552 if (sizeof(pudval_t) > sizeof(long))
553 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val,
554 pud.pud, (u64)pud.pud >> 32);
556 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val,
562 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
564 pgdval_t val = native_pgd_val(pgd);
566 if (sizeof(pgdval_t) > sizeof(long))
567 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
568 val, (u64)val >> 32);
570 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
574 static inline void pgd_clear(pgd_t *pgdp)
576 set_pgd(pgdp, __pgd(0));
579 static inline void pud_clear(pud_t *pudp)
581 set_pud(pudp, __pud(0));
584 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
586 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
588 #ifdef CONFIG_X86_PAE
589 /* Special-case pte-setting operations for PAE, which can't update a
590 64-bit pte atomically */
591 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
593 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
594 pte.pte, pte.pte >> 32);
597 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
600 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
603 static inline void pmd_clear(pmd_t *pmdp)
605 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
607 #else /* !CONFIG_X86_PAE */
608 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
613 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
616 set_pte_at(mm, addr, ptep, __pte(0));
619 static inline void pmd_clear(pmd_t *pmdp)
621 set_pmd(pmdp, __pmd(0));
623 #endif /* CONFIG_X86_PAE */
625 #define __HAVE_ARCH_START_CONTEXT_SWITCH
626 static inline void arch_start_context_switch(struct task_struct *prev)
628 PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev);
631 static inline void arch_end_context_switch(struct task_struct *next)
633 PVOP_VCALL1(pv_cpu_ops.end_context_switch, next);
636 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
637 static inline void arch_enter_lazy_mmu_mode(void)
639 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
642 static inline void arch_leave_lazy_mmu_mode(void)
644 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
647 static inline void arch_flush_lazy_mmu_mode(void)
649 PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush);
652 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
653 phys_addr_t phys, pgprot_t flags)
655 pv_mmu_ops.set_fixmap(idx, phys, flags);
658 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
660 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
663 PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val);
666 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
668 PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock);
671 static __always_inline void pv_wait(u8 *ptr, u8 val)
673 PVOP_VCALL2(pv_lock_ops.wait, ptr, val);
676 static __always_inline void pv_kick(int cpu)
678 PVOP_VCALL1(pv_lock_ops.kick, cpu);
681 #endif /* SMP && PARAVIRT_SPINLOCKS */
684 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
685 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
687 /* save and restore all caller-save registers, except return value */
688 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
689 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
691 #define PV_FLAGS_ARG "0"
692 #define PV_EXTRA_CLOBBERS
693 #define PV_VEXTRA_CLOBBERS
695 /* save and restore all caller-save registers, except return value */
696 #define PV_SAVE_ALL_CALLER_REGS \
705 #define PV_RESTORE_ALL_CALLER_REGS \
715 /* We save some registers, but all of them, that's too much. We clobber all
716 * caller saved registers but the argument parameter */
717 #define PV_SAVE_REGS "pushq %%rdi;"
718 #define PV_RESTORE_REGS "popq %%rdi;"
719 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
720 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
721 #define PV_FLAGS_ARG "D"
725 * Generate a thunk around a function which saves all caller-save
726 * registers except for the return value. This allows C functions to
727 * be called from assembler code where fewer than normal registers are
728 * available. It may also help code generation around calls from C
729 * code if the common case doesn't use many registers.
731 * When a callee is wrapped in a thunk, the caller can assume that all
732 * arg regs and all scratch registers are preserved across the
733 * call. The return value in rax/eax will not be saved, even for void
736 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
737 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
738 extern typeof(func) __raw_callee_save_##func; \
740 asm(".pushsection .text;" \
741 ".globl " PV_THUNK_NAME(func) ";" \
742 ".type " PV_THUNK_NAME(func) ", @function;" \
743 PV_THUNK_NAME(func) ":" \
745 PV_SAVE_ALL_CALLER_REGS \
747 PV_RESTORE_ALL_CALLER_REGS \
752 /* Get a reference to a callee-save function */
753 #define PV_CALLEE_SAVE(func) \
754 ((struct paravirt_callee_save) { __raw_callee_save_##func })
756 /* Promise that "func" already uses the right calling convention */
757 #define __PV_IS_CALLEE_SAVE(func) \
758 ((struct paravirt_callee_save) { func })
760 static inline notrace unsigned long arch_local_save_flags(void)
762 return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
765 static inline notrace void arch_local_irq_restore(unsigned long f)
767 PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
770 static inline notrace void arch_local_irq_disable(void)
772 PVOP_VCALLEE0(pv_irq_ops.irq_disable);
775 static inline notrace void arch_local_irq_enable(void)
777 PVOP_VCALLEE0(pv_irq_ops.irq_enable);
780 static inline notrace unsigned long arch_local_irq_save(void)
784 f = arch_local_save_flags();
785 arch_local_irq_disable();
790 /* Make sure as little as possible of this mess escapes. */
805 extern void default_banner(void);
807 #else /* __ASSEMBLY__ */
809 #define _PVSITE(ptype, clobbers, ops, word, algn) \
813 .pushsection .parainstructions,"a"; \
822 #define COND_PUSH(set, mask, reg) \
823 .if ((~(set)) & mask); push %reg; .endif
824 #define COND_POP(set, mask, reg) \
825 .if ((~(set)) & mask); pop %reg; .endif
829 #define PV_SAVE_REGS(set) \
830 COND_PUSH(set, CLBR_RAX, rax); \
831 COND_PUSH(set, CLBR_RCX, rcx); \
832 COND_PUSH(set, CLBR_RDX, rdx); \
833 COND_PUSH(set, CLBR_RSI, rsi); \
834 COND_PUSH(set, CLBR_RDI, rdi); \
835 COND_PUSH(set, CLBR_R8, r8); \
836 COND_PUSH(set, CLBR_R9, r9); \
837 COND_PUSH(set, CLBR_R10, r10); \
838 COND_PUSH(set, CLBR_R11, r11)
839 #define PV_RESTORE_REGS(set) \
840 COND_POP(set, CLBR_R11, r11); \
841 COND_POP(set, CLBR_R10, r10); \
842 COND_POP(set, CLBR_R9, r9); \
843 COND_POP(set, CLBR_R8, r8); \
844 COND_POP(set, CLBR_RDI, rdi); \
845 COND_POP(set, CLBR_RSI, rsi); \
846 COND_POP(set, CLBR_RDX, rdx); \
847 COND_POP(set, CLBR_RCX, rcx); \
848 COND_POP(set, CLBR_RAX, rax)
850 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
851 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
852 #define PARA_INDIRECT(addr) *addr(%rip)
854 #define PV_SAVE_REGS(set) \
855 COND_PUSH(set, CLBR_EAX, eax); \
856 COND_PUSH(set, CLBR_EDI, edi); \
857 COND_PUSH(set, CLBR_ECX, ecx); \
858 COND_PUSH(set, CLBR_EDX, edx)
859 #define PV_RESTORE_REGS(set) \
860 COND_POP(set, CLBR_EDX, edx); \
861 COND_POP(set, CLBR_ECX, ecx); \
862 COND_POP(set, CLBR_EDI, edi); \
863 COND_POP(set, CLBR_EAX, eax)
865 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
866 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
867 #define PARA_INDIRECT(addr) *%cs:addr
870 #define INTERRUPT_RETURN \
871 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
872 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
874 #define DISABLE_INTERRUPTS(clobbers) \
875 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
876 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
877 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
878 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
880 #define ENABLE_INTERRUPTS(clobbers) \
881 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
882 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
883 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
884 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
887 #define GET_CR0_INTO_EAX \
888 push %ecx; push %edx; \
889 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
891 #else /* !CONFIG_X86_32 */
894 * If swapgs is used while the userspace stack is still current,
895 * there's no way to call a pvop. The PV replacement *must* be
896 * inlined, or the swapgs instruction must be trapped and emulated.
898 #define SWAPGS_UNSAFE_STACK \
899 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
903 * Note: swapgs is very special, and in practise is either going to be
904 * implemented with a single "swapgs" instruction or something very
905 * special. Either way, we don't need to save any registers for
909 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
910 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \
913 #define GET_CR2_INTO_RAX \
914 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2)
916 #define PARAVIRT_ADJUST_EXCEPTION_FRAME \
917 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
919 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
921 #define USERGS_SYSRET64 \
922 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
924 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
925 #endif /* CONFIG_X86_32 */
927 #endif /* __ASSEMBLY__ */
928 #else /* CONFIG_PARAVIRT */
929 # define default_banner x86_init_noop
931 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
932 struct mm_struct *mm)
936 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
939 #endif /* __ASSEMBLY__ */
940 #endif /* !CONFIG_PARAVIRT */
941 #endif /* _ASM_X86_PARAVIRT_H */