1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
25 #include <asm/unwind_hints.h>
27 #include <linux/personality.h>
28 #include <linux/cache.h>
29 #include <linux/threads.h>
30 #include <linux/math64.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
33 #include <linux/mem_encrypt.h>
36 * We handle most unaligned accesses in hardware. On the other hand
37 * unaligned DMA can be quite expensive on some Nehalem processors.
39 * Based on this we disable the IP header alignment in network drivers.
41 #define NET_IP_ALIGN 0
45 * Default implementation of macro that returns current
46 * instruction pointer ("program counter").
48 static inline void *current_text_addr(void)
52 asm volatile("mov $1f, %0; 1:":"=r" (pc));
58 * These alignment constraints are for performance in the vSMP case,
59 * but in the task_struct case we must also meet hardware imposed
60 * alignment requirements of the FPU state:
62 #ifdef CONFIG_X86_VSMP
63 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
64 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
66 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
67 # define ARCH_MIN_MMSTRUCT_ALIGN 0
75 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
76 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
77 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
78 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
79 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
80 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
81 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
84 * CPU type and hardware bug flags. Kept separately for each CPU.
85 * Members of this structure are referenced in head_32.S, so think twice
86 * before touching them. [mj]
90 __u8 x86; /* CPU family */
91 __u8 x86_vendor; /* CPU vendor */
95 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
100 /* CPUID returned core id bits: */
101 __u8 x86_coreid_bits;
103 /* Max extended CPUID function supported: */
104 __u32 extended_cpuid_level;
105 /* Maximum supported CPUID level, -1=no CPUID: */
107 __u32 x86_capability[NCAPINTS + NBUGINTS];
108 char x86_vendor_id[16];
109 char x86_model_id[64];
110 /* in KB - valid for CPUS which support this call: */
112 int x86_cache_alignment; /* In bytes */
113 /* Cache QoS architectural values: */
114 int x86_cache_max_rmid; /* max index */
115 int x86_cache_occ_scale; /* scale to bytes */
117 unsigned long loops_per_jiffy;
118 /* cpuid returned max cores value: */
122 u16 x86_clflush_size;
123 /* number of cores as seen by the OS: */
125 /* Physical processor id: */
127 /* Logical processor id: */
131 /* Index into per_cpu list: */
134 } __randomize_layout;
137 u32 eax, ebx, ecx, edx;
140 enum cpuid_regs_idx {
147 #define X86_VENDOR_INTEL 0
148 #define X86_VENDOR_CYRIX 1
149 #define X86_VENDOR_AMD 2
150 #define X86_VENDOR_UMC 3
151 #define X86_VENDOR_CENTAUR 5
152 #define X86_VENDOR_TRANSMETA 7
153 #define X86_VENDOR_NSC 8
154 #define X86_VENDOR_NUM 9
156 #define X86_VENDOR_UNKNOWN 0xff
159 * capabilities of CPUs
161 extern struct cpuinfo_x86 boot_cpu_data;
162 extern struct cpuinfo_x86 new_cpu_data;
164 extern struct tss_struct doublefault_tss;
165 extern __u32 cpu_caps_cleared[NCAPINTS];
166 extern __u32 cpu_caps_set[NCAPINTS];
169 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
170 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
172 #define cpu_info boot_cpu_data
173 #define cpu_data(cpu) boot_cpu_data
176 extern const struct seq_operations cpuinfo_op;
178 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
180 extern void cpu_detect(struct cpuinfo_x86 *c);
182 extern void early_cpu_init(void);
183 extern void identify_boot_cpu(void);
184 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
185 extern void print_cpu_info(struct cpuinfo_x86 *);
186 void print_cpu_msr(struct cpuinfo_x86 *);
187 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
188 extern u32 get_scattered_cpuid_leaf(unsigned int level,
189 unsigned int sub_leaf,
190 enum cpuid_regs_idx reg);
191 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
192 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
194 extern void detect_extended_topology(struct cpuinfo_x86 *c);
195 extern void detect_ht(struct cpuinfo_x86 *c);
198 extern int have_cpuid_p(void);
200 static inline int have_cpuid_p(void)
205 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
206 unsigned int *ecx, unsigned int *edx)
208 /* ecx is often an input as well as an output. */
214 : "0" (*eax), "2" (*ecx)
218 #define native_cpuid_reg(reg) \
219 static inline unsigned int native_cpuid_##reg(unsigned int op) \
221 unsigned int eax = op, ebx, ecx = 0, edx; \
223 native_cpuid(&eax, &ebx, &ecx, &edx); \
229 * Native CPUID functions returning a single datum.
231 native_cpuid_reg(eax)
232 native_cpuid_reg(ebx)
233 native_cpuid_reg(ecx)
234 native_cpuid_reg(edx)
237 * Friendlier CR3 helpers.
239 static inline unsigned long read_cr3_pa(void)
241 return __read_cr3() & CR3_ADDR_MASK;
244 static inline unsigned long native_read_cr3_pa(void)
246 return __native_read_cr3() & CR3_ADDR_MASK;
249 static inline void load_cr3(pgd_t *pgdir)
251 write_cr3(__sme_pa(pgdir));
255 /* This is the TSS defined by the hardware. */
257 unsigned short back_link, __blh;
259 unsigned short ss0, __ss0h;
263 * We don't use ring 1, so ss1 is a convenient scratch space in
264 * the same cacheline as sp0. We use ss1 to cache the value in
265 * MSR_IA32_SYSENTER_CS. When we context switch
266 * MSR_IA32_SYSENTER_CS, we first check if the new value being
267 * written matches ss1, and, if it's not, then we wrmsr the new
268 * value and update ss1.
270 * The only reason we context switch MSR_IA32_SYSENTER_CS is
271 * that we set it to zero in vm86 tasks to avoid corrupting the
272 * stack if we were to go through the sysenter path from vm86
275 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
277 unsigned short __ss1h;
279 unsigned short ss2, __ss2h;
291 unsigned short es, __esh;
292 unsigned short cs, __csh;
293 unsigned short ss, __ssh;
294 unsigned short ds, __dsh;
295 unsigned short fs, __fsh;
296 unsigned short gs, __gsh;
297 unsigned short ldt, __ldth;
298 unsigned short trace;
299 unsigned short io_bitmap_base;
301 } __attribute__((packed));
315 } __attribute__((packed));
321 #define IO_BITMAP_BITS 65536
322 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
323 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
324 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
325 #define INVALID_IO_BITMAP_OFFSET 0x8000
329 * The hardware state:
331 struct x86_hw_tss x86_tss;
334 * The extra 1 is there because the CPU will access an
335 * additional byte beyond the end of the IO permission
336 * bitmap. The extra byte must be all 1 bits, and must
337 * be within the limit.
339 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
343 * Space for the temporary SYSENTER stack.
345 unsigned long SYSENTER_stack_canary;
346 unsigned long SYSENTER_stack[64];
349 } ____cacheline_aligned;
351 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
354 * sizeof(unsigned long) coming from an extra "long" at the end
357 * -1? seg base+limit should be pointing to the address of the
360 #define __KERNEL_TSS_LIMIT \
361 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
364 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
368 * Save the original ist values for checking stack pointers during debugging
371 unsigned long ist[7];
375 DECLARE_PER_CPU(struct orig_ist, orig_ist);
377 union irq_stack_union {
378 char irq_stack[IRQ_STACK_SIZE];
380 * GCC hardcodes the stack canary as %gs:40. Since the
381 * irq_stack is the object at %gs:0, we reserve the bottom
382 * 48 bytes of the irq stack for the canary.
386 unsigned long stack_canary;
390 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
391 DECLARE_INIT_PER_CPU(irq_stack_union);
393 DECLARE_PER_CPU(char *, irq_stack_ptr);
394 DECLARE_PER_CPU(unsigned int, irq_count);
395 extern asmlinkage void ignore_sysret(void);
397 #ifdef CONFIG_CC_STACKPROTECTOR
399 * Make sure stack canary segment base is cached-aligned:
400 * "For Intel Atom processors, avoid non zero segment base address
401 * that is not aligned to cache line boundary at all cost."
402 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
404 struct stack_canary {
405 char __pad[20]; /* canary at %gs:20 */
406 unsigned long canary;
408 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
411 * per-CPU IRQ handling stacks
414 u32 stack[THREAD_SIZE/sizeof(u32)];
415 } __aligned(THREAD_SIZE);
417 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
418 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
421 extern unsigned int fpu_kernel_xstate_size;
422 extern unsigned int fpu_user_xstate_size;
430 struct thread_struct {
431 /* Cached TLS descriptors: */
432 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
436 unsigned long sysenter_cs;
440 unsigned short fsindex;
441 unsigned short gsindex;
444 u32 status; /* thread synchronous flags */
447 unsigned long fsbase;
448 unsigned long gsbase;
451 * XXX: this could presumably be unsigned short. Alternatively,
452 * 32-bit kernels could be taught to use fsindex instead.
458 /* Save middle states of ptrace breakpoints */
459 struct perf_event *ptrace_bps[HBP_NUM];
460 /* Debug status used for traps, single steps, etc... */
461 unsigned long debugreg6;
462 /* Keep track of the exact dr7 value set by the user */
463 unsigned long ptrace_dr7;
466 unsigned long trap_nr;
467 unsigned long error_code;
469 /* Virtual 86 mode info */
472 /* IO permissions: */
473 unsigned long *io_bitmap_ptr;
475 /* Max allowed port in the bitmap, in bytes: */
476 unsigned io_bitmap_max;
478 mm_segment_t addr_limit;
480 unsigned int sig_on_uaccess_err:1;
481 unsigned int uaccess_err:1; /* uaccess failed */
483 /* Floating point and extended processor state */
486 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
492 * Thread-synchronous status.
494 * This is different from the flags in that nobody else
495 * ever touches our thread-synchronous status, so we don't
496 * have to worry about atomic accesses.
498 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
501 * Set IOPL bits in EFLAGS from given mask
503 static inline void native_set_iopl_mask(unsigned mask)
508 asm volatile ("pushfl;"
515 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
520 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
522 tss->x86_tss.sp0 = thread->sp0;
524 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
525 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
526 tss->x86_tss.ss1 = thread->sysenter_cs;
527 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
532 static inline void native_swapgs(void)
535 asm volatile("swapgs" ::: "memory");
539 static inline unsigned long current_top_of_stack(void)
542 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
544 /* sp0 on x86_32 is special in and around vm86 mode. */
545 return this_cpu_read_stable(cpu_current_top_of_stack);
549 #ifdef CONFIG_PARAVIRT
550 #include <asm/paravirt.h>
552 #define __cpuid native_cpuid
554 static inline void load_sp0(struct tss_struct *tss,
555 struct thread_struct *thread)
557 native_load_sp0(tss, thread);
560 #define set_iopl_mask native_set_iopl_mask
561 #endif /* CONFIG_PARAVIRT */
563 /* Free all resources held by a thread. */
564 extern void release_thread(struct task_struct *);
566 unsigned long get_wchan(struct task_struct *p);
569 * Generic CPUID function
570 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
571 * resulting in stale register contents being returned.
573 static inline void cpuid(unsigned int op,
574 unsigned int *eax, unsigned int *ebx,
575 unsigned int *ecx, unsigned int *edx)
579 __cpuid(eax, ebx, ecx, edx);
582 /* Some CPUID calls want 'count' to be placed in ecx */
583 static inline void cpuid_count(unsigned int op, int count,
584 unsigned int *eax, unsigned int *ebx,
585 unsigned int *ecx, unsigned int *edx)
589 __cpuid(eax, ebx, ecx, edx);
593 * CPUID functions returning a single datum
595 static inline unsigned int cpuid_eax(unsigned int op)
597 unsigned int eax, ebx, ecx, edx;
599 cpuid(op, &eax, &ebx, &ecx, &edx);
604 static inline unsigned int cpuid_ebx(unsigned int op)
606 unsigned int eax, ebx, ecx, edx;
608 cpuid(op, &eax, &ebx, &ecx, &edx);
613 static inline unsigned int cpuid_ecx(unsigned int op)
615 unsigned int eax, ebx, ecx, edx;
617 cpuid(op, &eax, &ebx, &ecx, &edx);
622 static inline unsigned int cpuid_edx(unsigned int op)
624 unsigned int eax, ebx, ecx, edx;
626 cpuid(op, &eax, &ebx, &ecx, &edx);
631 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
632 static __always_inline void rep_nop(void)
634 asm volatile("rep; nop" ::: "memory");
637 static __always_inline void cpu_relax(void)
643 * This function forces the icache and prefetched instruction stream to
644 * catch up with reality in two very specific cases:
646 * a) Text was modified using one virtual address and is about to be executed
647 * from the same physical page at a different virtual address.
649 * b) Text was modified on a different CPU, may subsequently be
650 * executed on this CPU, and you want to make sure the new version
651 * gets executed. This generally means you're calling this in a IPI.
653 * If you're calling this for a different reason, you're probably doing
656 static inline void sync_core(void)
659 * There are quite a few ways to do this. IRET-to-self is nice
660 * because it works on every CPU, at any CPL (so it's compatible
661 * with paravirtualization), and it never exits to a hypervisor.
662 * The only down sides are that it's a bit slow (it seems to be
663 * a bit more than 2x slower than the fastest options) and that
664 * it unmasks NMIs. The "push %cs" is needed because, in
665 * paravirtual environments, __KERNEL_CS may not be a valid CS
666 * value when we do IRET directly.
668 * In case NMI unmasking or performance ever becomes a problem,
669 * the next best option appears to be MOV-to-CR2 and an
670 * unconditional jump. That sequence also works on all CPUs,
671 * but it will fault at CPL3 (i.e. Xen PV).
673 * CPUID is the conventional way, but it's nasty: it doesn't
674 * exist on some 486-like CPUs, and it usually exits to a
677 * Like all of Linux's memory ordering operations, this is a
678 * compiler barrier as well.
687 : ASM_CALL_CONSTRAINT : : "memory");
696 "addq $8, (%%rsp)\n\t"
704 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
708 extern void select_idle_routine(const struct cpuinfo_x86 *c);
709 extern void amd_e400_c1e_apic_setup(void);
711 extern unsigned long boot_option_idle_override;
713 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
716 extern void enable_sep_cpu(void);
717 extern int sysenter_setup(void);
719 extern void early_trap_init(void);
720 void early_trap_pf_init(void);
722 /* Defined in head.S */
723 extern struct desc_ptr early_gdt_descr;
725 extern void cpu_set_gdt(int);
726 extern void switch_to_new_gdt(int);
727 extern void load_direct_gdt(int);
728 extern void load_fixmap_gdt(int);
729 extern void load_percpu_segment(int);
730 extern void cpu_init(void);
732 static inline unsigned long get_debugctlmsr(void)
734 unsigned long debugctlmsr = 0;
736 #ifndef CONFIG_X86_DEBUGCTLMSR
737 if (boot_cpu_data.x86 < 6)
740 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
745 static inline void update_debugctlmsr(unsigned long debugctlmsr)
747 #ifndef CONFIG_X86_DEBUGCTLMSR
748 if (boot_cpu_data.x86 < 6)
751 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
754 extern void set_task_blockstep(struct task_struct *task, bool on);
756 /* Boot loader type from the setup header: */
757 extern int bootloader_type;
758 extern int bootloader_version;
760 extern char ignore_fpu_irq;
762 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
763 #define ARCH_HAS_PREFETCHW
764 #define ARCH_HAS_SPINLOCK_PREFETCH
767 # define BASE_PREFETCH ""
768 # define ARCH_HAS_PREFETCH
770 # define BASE_PREFETCH "prefetcht0 %P1"
774 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
776 * It's not worth to care about 3dnow prefetches for the K6
777 * because they are microcoded there and very slow.
779 static inline void prefetch(const void *x)
781 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
783 "m" (*(const char *)x));
787 * 3dnow prefetch to get an exclusive cache line.
788 * Useful for spinlocks to avoid one state transition in the
789 * cache coherency protocol:
791 static inline void prefetchw(const void *x)
793 alternative_input(BASE_PREFETCH, "prefetchw %P1",
794 X86_FEATURE_3DNOWPREFETCH,
795 "m" (*(const char *)x));
798 static inline void spin_lock_prefetch(const void *x)
803 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
804 TOP_OF_KERNEL_STACK_PADDING)
808 * User space process size: 3GB (default).
810 #define IA32_PAGE_OFFSET PAGE_OFFSET
811 #define TASK_SIZE PAGE_OFFSET
812 #define TASK_SIZE_LOW TASK_SIZE
813 #define TASK_SIZE_MAX TASK_SIZE
814 #define DEFAULT_MAP_WINDOW TASK_SIZE
815 #define STACK_TOP TASK_SIZE
816 #define STACK_TOP_MAX STACK_TOP
818 #define INIT_THREAD { \
819 .sp0 = TOP_OF_INIT_STACK, \
820 .sysenter_cs = __KERNEL_CS, \
821 .io_bitmap_ptr = NULL, \
822 .addr_limit = KERNEL_DS, \
826 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
827 * This is necessary to guarantee that the entire "struct pt_regs"
828 * is accessible even if the CPU haven't stored the SS/ESP registers
829 * on the stack (interrupt gate does not save these registers
830 * when switching to the same priv ring).
831 * Therefore beware: accessing the ss/esp fields of the
832 * "struct pt_regs" is possible, but they may contain the
833 * completely wrong values.
835 #define task_pt_regs(task) \
837 unsigned long __ptr = (unsigned long)task_stack_page(task); \
838 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
839 ((struct pt_regs *)__ptr) - 1; \
842 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
846 * User space process size. 47bits minus one guard page. The guard
847 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
848 * the highest possible canonical userspace address, then that
849 * syscall will enter the kernel with a non-canonical return
850 * address, and SYSRET will explode dangerously. We avoid this
851 * particular problem by preventing anything from being mapped
852 * at the maximum canonical address.
854 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
856 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
858 /* This decides where the kernel will search for a free chunk of vm
859 * space during mmap's.
861 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
862 0xc0000000 : 0xFFFFe000)
864 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
865 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
866 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
867 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
868 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
869 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
871 #define STACK_TOP TASK_SIZE_LOW
872 #define STACK_TOP_MAX TASK_SIZE_MAX
874 #define INIT_THREAD { \
875 .sp0 = TOP_OF_INIT_STACK, \
876 .addr_limit = KERNEL_DS, \
879 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
880 extern unsigned long KSTK_ESP(struct task_struct *task);
882 #endif /* CONFIG_X86_64 */
884 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
885 unsigned long new_sp);
888 * This decides where the kernel will search for a free chunk of vm
889 * space during mmap's.
891 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
892 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
894 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
896 /* Get/set a process' ability to use the timestamp counter instruction */
897 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
898 #define SET_TSC_CTL(val) set_tsc_mode((val))
900 extern int get_tsc_mode(unsigned long adr);
901 extern int set_tsc_mode(unsigned int val);
903 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
905 /* Register/unregister a process' MPX related resource */
906 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
907 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
909 #ifdef CONFIG_X86_INTEL_MPX
910 extern int mpx_enable_management(void);
911 extern int mpx_disable_management(void);
913 static inline int mpx_enable_management(void)
917 static inline int mpx_disable_management(void)
921 #endif /* CONFIG_X86_INTEL_MPX */
923 #ifdef CONFIG_CPU_SUP_AMD
924 extern u16 amd_get_nb_id(int cpu);
925 extern u32 amd_get_nodes_per_socket(void);
927 static inline u16 amd_get_nb_id(int cpu) { return 0; }
928 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
931 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
933 uint32_t base, eax, signature[3];
935 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
936 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
938 if (!memcmp(sig, signature, 12) &&
939 (leaves == 0 || ((eax - base) >= leaves)))
946 extern unsigned long arch_align_stack(unsigned long sp);
947 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
949 void default_idle(void);
951 bool xen_set_default_idle(void);
953 #define xen_set_default_idle 0
956 void stop_this_cpu(void *dummy);
957 void df_debug(struct pt_regs *regs, long error_code);
958 #endif /* _ASM_X86_PROCESSOR_H */