1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
13 static inline void __invpcid(unsigned long pcid, unsigned long addr,
16 struct { u64 d[2]; } desc = { { pcid, addr } };
19 * The memory clobber is because the whole point is to invalidate
20 * stale TLB entries and, especially if we're flushing global
21 * mappings, we don't want the compiler to reorder any subsequent
22 * memory accesses before the TLB flush.
24 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
25 * invpcid (%rcx), %rax in long mode.
27 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
28 : : "m" (desc), "a" (type), "c" (&desc) : "memory");
31 #define INVPCID_TYPE_INDIV_ADDR 0
32 #define INVPCID_TYPE_SINGLE_CTXT 1
33 #define INVPCID_TYPE_ALL_INCL_GLOBAL 2
34 #define INVPCID_TYPE_ALL_NON_GLOBAL 3
36 /* Flush all mappings for a given pcid and addr, not including globals. */
37 static inline void invpcid_flush_one(unsigned long pcid,
40 __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
43 /* Flush all mappings for a given PCID, not including globals. */
44 static inline void invpcid_flush_single_context(unsigned long pcid)
46 __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
49 /* Flush all mappings, including globals, for all PCIDs. */
50 static inline void invpcid_flush_all(void)
52 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
55 /* Flush all mappings for all PCIDs except globals. */
56 static inline void invpcid_flush_all_nonglobals(void)
58 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
61 static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
64 * Bump the generation count. This also serves as a full barrier
65 * that synchronizes with switch_mm(): callers are required to order
66 * their read of mm_cpumask after their writes to the paging
69 return atomic64_inc_return(&mm->context.tlb_gen);
73 * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.
74 * This serves two purposes. It prevents a nasty situation in which
75 * PCID-unaware code saves CR3, loads some other value (with PCID == 0),
76 * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved
77 * ASID was nonzero. It also means that any bugs involving loading a
78 * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically.
81 static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
83 if (static_cpu_has(X86_FEATURE_PCID)) {
84 VM_WARN_ON_ONCE(asid > 4094);
85 return __sme_pa(pgd) | (asid + 1);
87 VM_WARN_ON_ONCE(asid != 0);
92 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
94 VM_WARN_ON_ONCE(asid > 4094);
95 return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
98 #ifdef CONFIG_PARAVIRT
99 #include <asm/paravirt.h>
101 #define __flush_tlb() __native_flush_tlb()
102 #define __flush_tlb_global() __native_flush_tlb_global()
103 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
106 static inline bool tlb_defer_switch_to_init_mm(void)
109 * If we have PCID, then switching to init_mm is reasonably
110 * fast. If we don't have PCID, then switching to init_mm is
111 * quite slow, so we try to defer it in the hopes that we can
112 * avoid it entirely. The latter approach runs the risk of
113 * receiving otherwise unnecessary IPIs.
115 * This choice is just a heuristic. The tlb code can handle this
116 * function returning true or false regardless of whether we have
119 return !static_cpu_has(X86_FEATURE_PCID);
123 * 6 because 6 should be plenty and struct tlb_state will fit in
126 #define TLB_NR_DYN_ASIDS 6
135 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
136 * are on. This means that it may not match current->active_mm,
137 * which will contain the previous user mm when we're in lazy TLB
138 * mode even if we've already switched back to swapper_pg_dir.
140 struct mm_struct *loaded_mm;
145 * We can be in one of several states:
147 * - Actively using an mm. Our CPU's bit will be set in
148 * mm_cpumask(loaded_mm) and is_lazy == false;
150 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
151 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
153 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
154 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
155 * We're heuristically guessing that the CR3 load we
156 * skipped more than makes up for the overhead added by
162 * Access to this CR4 shadow and to H/W CR4 is protected by
163 * disabling interrupts when modifying either one.
168 * This is a list of all contexts that might exist in the TLB.
169 * There is one per ASID that we use, and the ASID (what the
170 * CPU calls PCID) is the index into ctxts.
172 * For each context, ctx_id indicates which mm the TLB's user
173 * entries came from. As an invariant, the TLB will never
174 * contain entries that are out-of-date as when that mm reached
175 * the tlb_gen in the list.
177 * To be clear, this means that it's legal for the TLB code to
178 * flush the TLB without updating tlb_gen. This can happen
179 * (for now, at least) due to paravirt remote flushes.
181 * NB: context 0 is a bit special, since it's also used by
182 * various bits of init code. This is fine -- code that
183 * isn't aware of PCID will end up harmlessly flushing
186 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
188 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
190 /* Initialize cr4 shadow for this CPU. */
191 static inline void cr4_init_shadow(void)
193 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
196 /* Set in this cpu's CR4. */
197 static inline void cr4_set_bits(unsigned long mask)
201 cr4 = this_cpu_read(cpu_tlbstate.cr4);
202 if ((cr4 | mask) != cr4) {
204 this_cpu_write(cpu_tlbstate.cr4, cr4);
209 /* Clear in this cpu's CR4. */
210 static inline void cr4_clear_bits(unsigned long mask)
214 cr4 = this_cpu_read(cpu_tlbstate.cr4);
215 if ((cr4 & ~mask) != cr4) {
217 this_cpu_write(cpu_tlbstate.cr4, cr4);
222 static inline void cr4_toggle_bits(unsigned long mask)
226 cr4 = this_cpu_read(cpu_tlbstate.cr4);
228 this_cpu_write(cpu_tlbstate.cr4, cr4);
232 /* Read the CR4 shadow. */
233 static inline unsigned long cr4_read_shadow(void)
235 return this_cpu_read(cpu_tlbstate.cr4);
239 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
240 * enable and PPro Global page enable), so that any CPU's that boot
241 * up after us can get the correct flags. This should only be used
242 * during boot on the boot cpu.
244 extern unsigned long mmu_cr4_features;
245 extern u32 *trampoline_cr4_features;
247 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
249 mmu_cr4_features |= mask;
250 if (trampoline_cr4_features)
251 *trampoline_cr4_features = mmu_cr4_features;
255 extern void initialize_tlbstate_and_flush(void);
258 * flush the entire current user mapping
260 static inline void __native_flush_tlb(void)
263 * If current->mm == NULL then we borrow a mm which may change during a
264 * task switch and therefore we must not be preempted while we write CR3
268 native_write_cr3(__native_read_cr3());
275 static inline void __native_flush_tlb_global(void)
277 unsigned long cr4, flags;
279 if (static_cpu_has(X86_FEATURE_INVPCID)) {
281 * Using INVPCID is considerably faster than a pair of writes
282 * to CR4 sandwiched inside an IRQ flag save/restore.
289 * Read-modify-write to CR4 - protect it from preemption and
290 * from interrupts. (Use the raw variant because this code can
291 * be called from deep inside debugging code.)
293 raw_local_irq_save(flags);
295 cr4 = this_cpu_read(cpu_tlbstate.cr4);
297 native_write_cr4(cr4 ^ X86_CR4_PGE);
298 /* write old PGE again and flush TLBs */
299 native_write_cr4(cr4);
301 raw_local_irq_restore(flags);
305 * flush one page in the user mapping
307 static inline void __native_flush_tlb_single(unsigned long addr)
309 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
315 static inline void __flush_tlb_all(void)
317 if (boot_cpu_has(X86_FEATURE_PGE)) {
318 __flush_tlb_global();
321 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
327 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
328 * we'd end up flushing kernel translations for the current ASID but
329 * we might fail to flush kernel translations for other cached ASIDs.
331 * To avoid this issue, we force PCID off if PGE is off.
336 * flush one page in the kernel mapping
338 static inline void __flush_tlb_one(unsigned long addr)
340 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
341 __flush_tlb_single(addr);
344 #define TLB_FLUSH_ALL -1UL
349 * - flush_tlb_all() flushes all processes TLBs
350 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
351 * - flush_tlb_page(vma, vmaddr) flushes one page
352 * - flush_tlb_range(vma, start, end) flushes a range of pages
353 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
354 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
356 * ..but the i386 has somewhat limited tlb flushing capabilities,
357 * and page-granular flushes are available only on i486 and up.
359 struct flush_tlb_info {
361 * We support several kinds of flushes.
363 * - Fully flush a single mm. .mm will be set, .end will be
364 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
365 * which the IPI sender is trying to catch us up.
367 * - Partially flush a single mm. .mm will be set, .start and
368 * .end will indicate the range, and .new_tlb_gen will be set
369 * such that the changes between generation .new_tlb_gen-1 and
370 * .new_tlb_gen are entirely contained in the indicated range.
372 * - Fully flush all mms whose tlb_gens have been updated. .mm
373 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
376 struct mm_struct *mm;
382 #define local_flush_tlb() __flush_tlb()
384 #define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
386 #define flush_tlb_range(vma, start, end) \
387 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
389 extern void flush_tlb_all(void);
390 extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
391 unsigned long end, unsigned long vmflag);
392 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
394 static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
396 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
399 void native_flush_tlb_others(const struct cpumask *cpumask,
400 const struct flush_tlb_info *info);
402 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
403 struct mm_struct *mm)
406 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
409 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
411 #ifndef CONFIG_PARAVIRT
412 #define flush_tlb_others(mask, info) \
413 native_flush_tlb_others(mask, info)
416 #endif /* _ASM_X86_TLBFLUSH_H */