2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
58 unsigned int num_processors;
60 unsigned disabled_cpus;
62 /* Processor that is doing the boot up */
63 unsigned int boot_cpu_physical_apicid = -1U;
64 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
66 u8 boot_cpu_apic_version;
69 * The highest APIC ID seen during enumeration.
71 static unsigned int max_physical_apicid;
74 * Bitmask of physically existing CPUs:
76 physid_mask_t phys_cpu_present_map;
79 * Processor to be disabled specified by kernel parameter
80 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
81 * avoid undefined behaviour caused by sending INIT from AP to BSP.
83 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
86 * This variable controls which CPUs receive external NMIs. By default,
87 * external NMIs are delivered only to the BSP.
89 static int apic_extnmi = APIC_EXTNMI_BSP;
92 * Map cpu index to physical APIC ID
94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
97 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
104 * On x86_32, the mapping between cpu and logical apicid may vary
105 * depending on apic in use. The following early percpu variable is
106 * used for the mapping. This is where the behaviors of x86_64 and 32
107 * actually diverge. Let's keep it ugly for now.
109 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
111 /* Local APIC was disabled by the BIOS and enabled by the kernel */
112 static int enabled_via_apicbase;
115 * Handle interrupt mode configuration register (IMCR).
116 * This register controls whether the interrupt signals
117 * that reach the BSP come from the master PIC or from the
118 * local APIC. Before entering Symmetric I/O Mode, either
119 * the BIOS or the operating system must switch out of
120 * PIC Mode by changing the IMCR.
122 static inline void imcr_pic_to_apic(void)
124 /* select IMCR register */
126 /* NMI and 8259 INTR go through APIC */
130 static inline void imcr_apic_to_pic(void)
132 /* select IMCR register */
134 /* NMI and 8259 INTR go directly to BSP */
140 * Knob to control our willingness to enable the local APIC.
144 static int force_enable_local_apic __initdata;
147 * APIC command line parameters
149 static int __init parse_lapic(char *arg)
151 if (IS_ENABLED(CONFIG_X86_32) && !arg)
152 force_enable_local_apic = 1;
153 else if (arg && !strncmp(arg, "notscdeadline", 13))
154 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
157 early_param("lapic", parse_lapic);
160 static int apic_calibrate_pmtmr __initdata;
161 static __init int setup_apicpmtimer(char *s)
163 apic_calibrate_pmtmr = 1;
167 __setup("apicpmtimer", setup_apicpmtimer);
170 unsigned long mp_lapic_addr;
172 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
173 static int disable_apic_timer __initdata;
174 /* Local APIC timer works in C2 */
175 int local_apic_timer_c2_ok;
176 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
178 int first_system_vector = FIRST_SYSTEM_VECTOR;
181 * Debug level, exported for io_apic.c
183 unsigned int apic_verbosity;
187 /* Have we found an MP table */
188 int smp_found_config;
190 static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 unsigned int lapic_timer_frequency = 0;
197 static void apic_pm_activate(void);
199 static unsigned long apic_phys;
202 * Get the LAPIC version
204 static inline int lapic_get_version(void)
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
210 * Check, if the APIC is integrated or a separate chip
212 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
222 * Check, whether this is a modern or a first generation APIC
224 static int modern_apic(void)
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
228 boot_cpu_data.x86 >= 0xf)
230 return lapic_get_version() >= 0x14;
234 * right after this call apic become NOOP driven
235 * so apic->write/read doesn't do anything
237 static void __init apic_disable(void)
239 pr_info("APIC: switched to apic NOOP\n");
243 void native_apic_wait_icr_idle(void)
245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
249 u32 native_safe_apic_wait_icr_idle(void)
256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
259 inc_irq_stat(icr_read_retry_count);
261 } while (timeout++ < 1000);
266 void native_apic_icr_write(u32 low, u32 id)
270 local_irq_save(flags);
271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272 apic_write(APIC_ICR, low);
273 local_irq_restore(flags);
276 u64 native_apic_icr_read(void)
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
283 return icr1 | ((u64)icr2 << 32);
288 * get_physical_broadcast - Get number of physical broadcast IDs
290 int get_physical_broadcast(void)
292 return modern_apic() ? 0xff : 0xf;
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 int lapic_get_maxlvt(void)
303 v = apic_read(APIC_LVR);
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR 8
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 unsigned int lvtt_value, tmp_value;
333 lvtt_value = LOCAL_TIMER_VECTOR;
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 if (!lapic_is_integrated())
340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343 lvtt_value |= APIC_LVT_MASKED;
345 apic_write(APIC_LVTT, lvtt_value);
347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
353 asm volatile("mfence" : : : "memory");
355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372 * Setup extended LVT, AMD specific
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 return (old & APIC_EILVT_MASKED)
396 || (new == APIC_EILVT_MASKED)
397 || ((new & ~APIC_EILVT_MASKED) == old);
400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 unsigned int rsvd, vector;
404 if (offset >= APIC_EILVT_NR_MAX)
407 rsvd = atomic_read(&eilvt_offsets[offset]);
409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
410 if (vector && !eilvt_entry_is_changeable(vector, new))
411 /* may not change if vectors are different */
413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
414 } while (rsvd != new);
416 rsvd &= ~APIC_EILVT_MASKED;
417 if (rsvd && rsvd != vector)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 unsigned long reg = APIC_EILVTn(offset);
433 unsigned int new, old, reserved;
435 new = (mask << 16) | (msg_type << 8) | vector;
436 old = apic_read(reg);
437 reserved = reserve_eilvt_offset(offset, new);
439 if (reserved != new) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg, offset, new, reserved);
447 if (!eilvt_entry_is_changeable(old, new)) {
448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg, offset, new, old);
455 apic_write(reg, new);
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
462 * Program the next event, relative to now
464 static int lapic_next_event(unsigned long delta,
465 struct clock_event_device *evt)
467 apic_write(APIC_TMICT, delta);
471 static int lapic_next_deadline(unsigned long delta,
472 struct clock_event_device *evt)
477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
481 static int lapic_timer_shutdown(struct clock_event_device *evt)
485 /* Lapic used as dummy for broadcast ? */
486 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
489 v = apic_read(APIC_LVTT);
490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
491 apic_write(APIC_LVTT, v);
492 apic_write(APIC_TMICT, 0);
497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499 /* Lapic used as dummy for broadcast ? */
500 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
507 static int lapic_timer_set_periodic(struct clock_event_device *evt)
509 return lapic_timer_set_periodic_oneshot(evt, false);
512 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514 return lapic_timer_set_periodic_oneshot(evt, true);
518 * Local APIC timer broadcast function
520 static void lapic_timer_broadcast(const struct cpumask *mask)
523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
529 * The local apic timer can be used for any function which is CPU local.
531 static struct clock_event_device lapic_clockevent = {
533 .features = CLOCK_EVT_FEAT_PERIODIC |
534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
535 | CLOCK_EVT_FEAT_DUMMY,
537 .set_state_shutdown = lapic_timer_shutdown,
538 .set_state_periodic = lapic_timer_set_periodic,
539 .set_state_oneshot = lapic_timer_set_oneshot,
540 .set_next_event = lapic_next_event,
541 .broadcast = lapic_timer_broadcast,
545 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
548 * Setup the local APIC timer for this CPU. Copy the initialized values
549 * of the boot CPU and register the clock event in the framework.
551 static void setup_APIC_timer(void)
553 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
555 if (this_cpu_has(X86_FEATURE_ARAT)) {
556 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
557 /* Make LAPIC timer preferrable over percpu HPET */
558 lapic_clockevent.rating = 150;
561 memcpy(levt, &lapic_clockevent, sizeof(*levt));
562 levt->cpumask = cpumask_of(smp_processor_id());
564 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
565 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
566 CLOCK_EVT_FEAT_DUMMY);
567 levt->set_next_event = lapic_next_deadline;
568 clockevents_config_and_register(levt,
569 tsc_khz * (1000 / TSC_DIVISOR),
572 clockevents_register_device(levt);
576 * Install the updated TSC frequency from recalibration at the TSC
577 * deadline clockevent devices.
579 static void __lapic_update_tsc_freq(void *info)
581 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
583 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
586 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
589 void lapic_update_tsc_freq(void)
592 * The clockevent device's ->mult and ->shift can both be
593 * changed. In order to avoid races, schedule the frequency
594 * update code on each CPU.
596 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
600 * In this functions we calibrate APIC bus clocks to the external timer.
602 * We want to do the calibration only once since we want to have local timer
603 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
606 * This was previously done by reading the PIT/HPET and waiting for a wrap
607 * around to find out, that a tick has elapsed. I have a box, where the PIT
608 * readout is broken, so it never gets out of the wait loop again. This was
609 * also reported by others.
611 * Monitoring the jiffies value is inaccurate and the clockevents
612 * infrastructure allows us to do a simple substitution of the interrupt
615 * The calibration routine also uses the pm_timer when possible, as the PIT
616 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
617 * back to normal later in the boot process).
620 #define LAPIC_CAL_LOOPS (HZ/10)
622 static __initdata int lapic_cal_loops = -1;
623 static __initdata long lapic_cal_t1, lapic_cal_t2;
624 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
625 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
626 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
629 * Temporary interrupt handler.
631 static void __init lapic_cal_handler(struct clock_event_device *dev)
633 unsigned long long tsc = 0;
634 long tapic = apic_read(APIC_TMCCT);
635 unsigned long pm = acpi_pm_read_early();
637 if (boot_cpu_has(X86_FEATURE_TSC))
640 switch (lapic_cal_loops++) {
642 lapic_cal_t1 = tapic;
643 lapic_cal_tsc1 = tsc;
645 lapic_cal_j1 = jiffies;
648 case LAPIC_CAL_LOOPS:
649 lapic_cal_t2 = tapic;
650 lapic_cal_tsc2 = tsc;
651 if (pm < lapic_cal_pm1)
652 pm += ACPI_PM_OVRRUN;
654 lapic_cal_j2 = jiffies;
660 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
662 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
663 const long pm_thresh = pm_100ms / 100;
667 #ifndef CONFIG_X86_PM_TIMER
671 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
673 /* Check, if the PM timer is available */
677 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
679 if (deltapm > (pm_100ms - pm_thresh) &&
680 deltapm < (pm_100ms + pm_thresh)) {
681 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
685 res = (((u64)deltapm) * mult) >> 22;
686 do_div(res, 1000000);
687 pr_warning("APIC calibration not consistent "
688 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
690 /* Correct the lapic counter value */
691 res = (((u64)(*delta)) * pm_100ms);
692 do_div(res, deltapm);
693 pr_info("APIC delta adjusted to PM-Timer: "
694 "%lu (%ld)\n", (unsigned long)res, *delta);
697 /* Correct the tsc counter value */
698 if (boot_cpu_has(X86_FEATURE_TSC)) {
699 res = (((u64)(*deltatsc)) * pm_100ms);
700 do_div(res, deltapm);
701 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
702 "PM-Timer: %lu (%ld)\n",
703 (unsigned long)res, *deltatsc);
704 *deltatsc = (long)res;
710 static int __init calibrate_APIC_clock(void)
712 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
713 void (*real_handler)(struct clock_event_device *dev);
714 unsigned long deltaj;
715 long delta, deltatsc;
716 int pm_referenced = 0;
719 * check if lapic timer has already been calibrated by platform
720 * specific routine, such as tsc calibration code. if so, we just fill
721 * in the clockevent structure and return.
724 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
726 } else if (lapic_timer_frequency) {
727 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
728 lapic_timer_frequency);
729 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
730 TICK_NSEC, lapic_clockevent.shift);
731 lapic_clockevent.max_delta_ns =
732 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
733 lapic_clockevent.min_delta_ns =
734 clockevent_delta2ns(0xF, &lapic_clockevent);
735 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
739 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
740 "calibrating APIC timer ...\n");
744 /* Replace the global interrupt handler */
745 real_handler = global_clock_event->event_handler;
746 global_clock_event->event_handler = lapic_cal_handler;
749 * Setup the APIC counter to maximum. There is no way the lapic
750 * can underflow in the 100ms detection time frame
752 __setup_APIC_LVTT(0xffffffff, 0, 0);
754 /* Let the interrupts run */
757 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
762 /* Restore the real event handler */
763 global_clock_event->event_handler = real_handler;
765 /* Build delta t1-t2 as apic timer counts down */
766 delta = lapic_cal_t1 - lapic_cal_t2;
767 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
769 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
771 /* we trust the PM based calibration if possible */
772 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
775 /* Calculate the scaled math multiplication factor */
776 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
777 lapic_clockevent.shift);
778 lapic_clockevent.max_delta_ns =
779 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
780 lapic_clockevent.min_delta_ns =
781 clockevent_delta2ns(0xF, &lapic_clockevent);
783 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
785 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
786 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
787 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
788 lapic_timer_frequency);
790 if (boot_cpu_has(X86_FEATURE_TSC)) {
791 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
793 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
794 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
797 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
799 lapic_timer_frequency / (1000000 / HZ),
800 lapic_timer_frequency % (1000000 / HZ));
803 * Do a sanity check on the APIC calibration result
805 if (lapic_timer_frequency < (1000000 / HZ)) {
807 pr_warning("APIC frequency too slow, disabling apic timer\n");
811 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
814 * PM timer calibration failed or not turned on
815 * so lets try APIC timer based calibration
817 if (!pm_referenced) {
818 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
821 * Setup the apic timer manually
823 levt->event_handler = lapic_cal_handler;
824 lapic_timer_set_periodic(levt);
825 lapic_cal_loops = -1;
827 /* Let the interrupts run */
830 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
833 /* Stop the lapic timer */
835 lapic_timer_shutdown(levt);
838 deltaj = lapic_cal_j2 - lapic_cal_j1;
839 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
841 /* Check, if the jiffies result is consistent */
842 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
843 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
845 levt->features |= CLOCK_EVT_FEAT_DUMMY;
849 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
850 pr_warning("APIC timer disabled due to verification failure\n");
858 * Setup the boot APIC
860 * Calibrate and verify the result.
862 void __init setup_boot_APIC_clock(void)
865 * The local apic timer can be disabled via the kernel
866 * commandline or from the CPU detection code. Register the lapic
867 * timer as a dummy clock event source on SMP systems, so the
868 * broadcast mechanism is used. On UP systems simply ignore it.
870 if (disable_apic_timer) {
871 pr_info("Disabling APIC timer\n");
872 /* No broadcast on UP ! */
873 if (num_possible_cpus() > 1) {
874 lapic_clockevent.mult = 1;
880 if (calibrate_APIC_clock()) {
881 /* No broadcast on UP ! */
882 if (num_possible_cpus() > 1)
888 * If nmi_watchdog is set to IO_APIC, we need the
889 * PIT/HPET going. Otherwise register lapic as a dummy
892 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
894 /* Setup the lapic or request the broadcast */
896 amd_e400_c1e_apic_setup();
899 void setup_secondary_APIC_clock(void)
902 amd_e400_c1e_apic_setup();
906 * The guts of the apic timer interrupt
908 static void local_apic_timer_interrupt(void)
910 int cpu = smp_processor_id();
911 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
914 * Normally we should not be here till LAPIC has been initialized but
915 * in some cases like kdump, its possible that there is a pending LAPIC
916 * timer interrupt from previous kernel's context and is delivered in
917 * new kernel the moment interrupts are enabled.
919 * Interrupts are enabled early and LAPIC is setup much later, hence
920 * its possible that when we get here evt->event_handler is NULL.
921 * Check for event_handler being NULL and discard the interrupt as
924 if (!evt->event_handler) {
925 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
927 lapic_timer_shutdown(evt);
932 * the NMI deadlock-detector uses this.
934 inc_irq_stat(apic_timer_irqs);
936 evt->event_handler(evt);
940 * Local APIC timer interrupt. This is the most natural way for doing
941 * local interrupts, but local timer interrupts can be emulated by
942 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
944 * [ if a single-CPU system runs an SMP kernel then we call the local
945 * interrupt as well. Thus we cannot inline the local irq ... ]
947 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
949 struct pt_regs *old_regs = set_irq_regs(regs);
952 * NOTE! We'd better ACK the irq immediately,
953 * because timer handling can be slow.
955 * update_process_times() expects us to have done irq_enter().
956 * Besides, if we don't timer interrupts ignore the global
957 * interrupt lock, which is the WrongThing (tm) to do.
960 local_apic_timer_interrupt();
963 set_irq_regs(old_regs);
966 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
968 struct pt_regs *old_regs = set_irq_regs(regs);
971 * NOTE! We'd better ACK the irq immediately,
972 * because timer handling can be slow.
974 * update_process_times() expects us to have done irq_enter().
975 * Besides, if we don't timer interrupts ignore the global
976 * interrupt lock, which is the WrongThing (tm) to do.
979 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
980 local_apic_timer_interrupt();
981 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
984 set_irq_regs(old_regs);
987 int setup_profiling_timer(unsigned int multiplier)
993 * Local APIC start and shutdown
997 * clear_local_APIC - shutdown the local APIC
999 * This is called, when a CPU is disabled and before rebooting, so the state of
1000 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1001 * leftovers during boot.
1003 void clear_local_APIC(void)
1008 /* APIC hasn't been mapped yet */
1009 if (!x2apic_mode && !apic_phys)
1012 maxlvt = lapic_get_maxlvt();
1014 * Masking an LVT entry can trigger a local APIC error
1015 * if the vector is zero. Mask LVTERR first to prevent this.
1018 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1019 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1022 * Careful: we have to set masks only first to deassert
1023 * any level-triggered sources.
1025 v = apic_read(APIC_LVTT);
1026 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1027 v = apic_read(APIC_LVT0);
1028 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1029 v = apic_read(APIC_LVT1);
1030 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1032 v = apic_read(APIC_LVTPC);
1033 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1036 /* lets not touch this if we didn't frob it */
1037 #ifdef CONFIG_X86_THERMAL_VECTOR
1039 v = apic_read(APIC_LVTTHMR);
1040 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1043 #ifdef CONFIG_X86_MCE_INTEL
1045 v = apic_read(APIC_LVTCMCI);
1046 if (!(v & APIC_LVT_MASKED))
1047 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1052 * Clean APIC state for other OSs:
1054 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1055 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1056 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1058 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1060 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1062 /* Integrated APIC (!82489DX) ? */
1063 if (lapic_is_integrated()) {
1065 /* Clear ESR due to Pentium errata 3AP and 11AP */
1066 apic_write(APIC_ESR, 0);
1067 apic_read(APIC_ESR);
1072 * disable_local_APIC - clear and disable the local APIC
1074 void disable_local_APIC(void)
1078 /* APIC hasn't been mapped yet */
1079 if (!x2apic_mode && !apic_phys)
1085 * Disable APIC (implies clearing of registers
1088 value = apic_read(APIC_SPIV);
1089 value &= ~APIC_SPIV_APIC_ENABLED;
1090 apic_write(APIC_SPIV, value);
1092 #ifdef CONFIG_X86_32
1094 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1095 * restore the disabled state.
1097 if (enabled_via_apicbase) {
1100 rdmsr(MSR_IA32_APICBASE, l, h);
1101 l &= ~MSR_IA32_APICBASE_ENABLE;
1102 wrmsr(MSR_IA32_APICBASE, l, h);
1108 * If Linux enabled the LAPIC against the BIOS default disable it down before
1109 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1110 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1111 * for the case where Linux didn't enable the LAPIC.
1113 void lapic_shutdown(void)
1115 unsigned long flags;
1117 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1120 local_irq_save(flags);
1122 #ifdef CONFIG_X86_32
1123 if (!enabled_via_apicbase)
1127 disable_local_APIC();
1130 local_irq_restore(flags);
1134 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1136 void __init sync_Arb_IDs(void)
1139 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1142 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1148 apic_wait_icr_idle();
1150 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1151 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1152 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1156 * An initial setup of the virtual wire mode.
1158 void __init init_bsp_APIC(void)
1163 * Don't do the setup now if we have a SMP BIOS as the
1164 * through-I/O-APIC virtual wire mode might be active.
1166 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1170 * Do not trust the local APIC being empty at bootup.
1177 value = apic_read(APIC_SPIV);
1178 value &= ~APIC_VECTOR_MASK;
1179 value |= APIC_SPIV_APIC_ENABLED;
1181 #ifdef CONFIG_X86_32
1182 /* This bit is reserved on P4/Xeon and should be cleared */
1183 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1184 (boot_cpu_data.x86 == 15))
1185 value &= ~APIC_SPIV_FOCUS_DISABLED;
1188 value |= APIC_SPIV_FOCUS_DISABLED;
1189 value |= SPURIOUS_APIC_VECTOR;
1190 apic_write(APIC_SPIV, value);
1193 * Set up the virtual wire mode.
1195 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1196 value = APIC_DM_NMI;
1197 if (!lapic_is_integrated()) /* 82489DX */
1198 value |= APIC_LVT_LEVEL_TRIGGER;
1199 if (apic_extnmi == APIC_EXTNMI_NONE)
1200 value |= APIC_LVT_MASKED;
1201 apic_write(APIC_LVT1, value);
1204 static void lapic_setup_esr(void)
1206 unsigned int oldvalue, value, maxlvt;
1208 if (!lapic_is_integrated()) {
1209 pr_info("No ESR for 82489DX.\n");
1213 if (apic->disable_esr) {
1215 * Something untraceable is creating bad interrupts on
1216 * secondary quads ... for the moment, just leave the
1217 * ESR disabled - we can't do anything useful with the
1218 * errors anyway - mbligh
1220 pr_info("Leaving ESR disabled.\n");
1224 maxlvt = lapic_get_maxlvt();
1225 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1226 apic_write(APIC_ESR, 0);
1227 oldvalue = apic_read(APIC_ESR);
1229 /* enables sending errors */
1230 value = ERROR_APIC_VECTOR;
1231 apic_write(APIC_LVTERR, value);
1234 * spec says clear errors after enabling vector.
1237 apic_write(APIC_ESR, 0);
1238 value = apic_read(APIC_ESR);
1239 if (value != oldvalue)
1240 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1241 "vector: 0x%08x after: 0x%08x\n",
1246 * setup_local_APIC - setup the local APIC
1248 * Used to setup local APIC while initializing BSP or bringin up APs.
1249 * Always called with preemption disabled.
1251 void setup_local_APIC(void)
1253 int cpu = smp_processor_id();
1254 unsigned int value, queued;
1255 int i, j, acked = 0;
1256 unsigned long long tsc = 0, ntsc;
1257 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1259 if (boot_cpu_has(X86_FEATURE_TSC))
1263 disable_ioapic_support();
1267 #ifdef CONFIG_X86_32
1268 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1269 if (lapic_is_integrated() && apic->disable_esr) {
1270 apic_write(APIC_ESR, 0);
1271 apic_write(APIC_ESR, 0);
1272 apic_write(APIC_ESR, 0);
1273 apic_write(APIC_ESR, 0);
1276 perf_events_lapic_init();
1279 * Double-check whether this APIC is really registered.
1280 * This is meaningless in clustered apic mode, so we skip it.
1282 BUG_ON(!apic->apic_id_registered());
1285 * Intel recommends to set DFR, LDR and TPR before enabling
1286 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1287 * document number 292116). So here it goes...
1289 apic->init_apic_ldr();
1291 #ifdef CONFIG_X86_32
1293 * APIC LDR is initialized. If logical_apicid mapping was
1294 * initialized during get_smp_config(), make sure it matches the
1297 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1298 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1299 /* always use the value from LDR */
1300 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1301 logical_smp_processor_id();
1305 * Set Task Priority to 'accept all'. We never change this
1308 value = apic_read(APIC_TASKPRI);
1309 value &= ~APIC_TPRI_MASK;
1310 apic_write(APIC_TASKPRI, value);
1313 * After a crash, we no longer service the interrupts and a pending
1314 * interrupt from previous kernel might still have ISR bit set.
1316 * Most probably by now CPU has serviced that pending interrupt and
1317 * it might not have done the ack_APIC_irq() because it thought,
1318 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1319 * does not clear the ISR bit and cpu thinks it has already serivced
1320 * the interrupt. Hence a vector might get locked. It was noticed
1321 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1325 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1326 queued |= apic_read(APIC_IRR + i*0x10);
1328 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1329 value = apic_read(APIC_ISR + i*0x10);
1330 for (j = 31; j >= 0; j--) {
1331 if (value & (1<<j)) {
1338 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1343 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1345 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1349 } while (queued && max_loops > 0);
1350 WARN_ON(max_loops <= 0);
1353 * Now that we are all set up, enable the APIC
1355 value = apic_read(APIC_SPIV);
1356 value &= ~APIC_VECTOR_MASK;
1360 value |= APIC_SPIV_APIC_ENABLED;
1362 #ifdef CONFIG_X86_32
1364 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1365 * certain networking cards. If high frequency interrupts are
1366 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1367 * entry is masked/unmasked at a high rate as well then sooner or
1368 * later IOAPIC line gets 'stuck', no more interrupts are received
1369 * from the device. If focus CPU is disabled then the hang goes
1372 * [ This bug can be reproduced easily with a level-triggered
1373 * PCI Ne2000 networking cards and PII/PIII processors, dual
1377 * Actually disabling the focus CPU check just makes the hang less
1378 * frequent as it makes the interrupt distributon model be more
1379 * like LRU than MRU (the short-term load is more even across CPUs).
1383 * - enable focus processor (bit==0)
1384 * - 64bit mode always use processor focus
1385 * so no need to set it
1387 value &= ~APIC_SPIV_FOCUS_DISABLED;
1391 * Set spurious IRQ vector
1393 value |= SPURIOUS_APIC_VECTOR;
1394 apic_write(APIC_SPIV, value);
1397 * Set up LVT0, LVT1:
1399 * set up through-local-APIC on the BP's LINT0. This is not
1400 * strictly necessary in pure symmetric-IO mode, but sometimes
1401 * we delegate interrupts to the 8259A.
1404 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1406 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1407 if (!cpu && (pic_mode || !value)) {
1408 value = APIC_DM_EXTINT;
1409 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1411 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1412 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1414 apic_write(APIC_LVT0, value);
1417 * Only the BSP sees the LINT1 NMI signal by default. This can be
1418 * modified by apic_extnmi= boot option.
1420 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1421 apic_extnmi == APIC_EXTNMI_ALL)
1422 value = APIC_DM_NMI;
1424 value = APIC_DM_NMI | APIC_LVT_MASKED;
1425 if (!lapic_is_integrated()) /* 82489DX */
1426 value |= APIC_LVT_LEVEL_TRIGGER;
1427 apic_write(APIC_LVT1, value);
1429 #ifdef CONFIG_X86_MCE_INTEL
1430 /* Recheck CMCI information after local APIC is up on CPU #0 */
1436 static void end_local_APIC_setup(void)
1440 #ifdef CONFIG_X86_32
1443 /* Disable the local apic timer */
1444 value = apic_read(APIC_LVTT);
1445 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1446 apic_write(APIC_LVTT, value);
1454 * APIC setup function for application processors. Called from smpboot.c
1456 void apic_ap_setup(void)
1459 end_local_APIC_setup();
1462 #ifdef CONFIG_X86_X2APIC
1470 static int x2apic_state;
1472 static void __x2apic_disable(void)
1476 if (!boot_cpu_has(X86_FEATURE_APIC))
1479 rdmsrl(MSR_IA32_APICBASE, msr);
1480 if (!(msr & X2APIC_ENABLE))
1482 /* Disable xapic and x2apic first and then reenable xapic mode */
1483 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1484 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1485 printk_once(KERN_INFO "x2apic disabled\n");
1488 static void __x2apic_enable(void)
1492 rdmsrl(MSR_IA32_APICBASE, msr);
1493 if (msr & X2APIC_ENABLE)
1495 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1496 printk_once(KERN_INFO "x2apic enabled\n");
1499 static int __init setup_nox2apic(char *str)
1501 if (x2apic_enabled()) {
1502 int apicid = native_apic_msr_read(APIC_ID);
1504 if (apicid >= 255) {
1505 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1509 pr_warning("x2apic already enabled.\n");
1512 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1513 x2apic_state = X2APIC_DISABLED;
1517 early_param("nox2apic", setup_nox2apic);
1519 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1520 void x2apic_setup(void)
1523 * If x2apic is not in ON state, disable it if already enabled
1526 if (x2apic_state != X2APIC_ON) {
1533 static __init void x2apic_disable(void)
1535 u32 x2apic_id, state = x2apic_state;
1538 x2apic_state = X2APIC_DISABLED;
1540 if (state != X2APIC_ON)
1543 x2apic_id = read_apic_id();
1544 if (x2apic_id >= 255)
1545 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1548 register_lapic_address(mp_lapic_addr);
1551 static __init void x2apic_enable(void)
1553 if (x2apic_state != X2APIC_OFF)
1557 x2apic_state = X2APIC_ON;
1561 static __init void try_to_enable_x2apic(int remap_mode)
1563 if (x2apic_state == X2APIC_DISABLED)
1566 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1567 /* IR is required if there is APIC ID > 255 even when running
1570 if (max_physical_apicid > 255 ||
1571 !hypervisor_x2apic_available()) {
1572 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1578 * without IR all CPUs can be addressed by IOAPIC/MSI
1579 * only in physical mode
1586 void __init check_x2apic(void)
1588 if (x2apic_enabled()) {
1589 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1591 x2apic_state = X2APIC_ON;
1592 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1593 x2apic_state = X2APIC_DISABLED;
1596 #else /* CONFIG_X86_X2APIC */
1597 static int __init validate_x2apic(void)
1599 if (!apic_is_x2apic_enabled())
1602 * Checkme: Can we simply turn off x2apic here instead of panic?
1604 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1606 early_initcall(validate_x2apic);
1608 static inline void try_to_enable_x2apic(int remap_mode) { }
1609 static inline void __x2apic_enable(void) { }
1610 #endif /* !CONFIG_X86_X2APIC */
1612 static int __init try_to_enable_IR(void)
1614 #ifdef CONFIG_X86_IO_APIC
1615 if (!x2apic_enabled() && skip_ioapic_setup) {
1616 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1620 return irq_remapping_enable();
1623 void __init enable_IR_x2apic(void)
1625 unsigned long flags;
1628 if (skip_ioapic_setup)
1631 ir_stat = irq_remapping_prepare();
1632 if (ir_stat < 0 && !x2apic_supported())
1635 ret = save_ioapic_entries();
1637 pr_info("Saving IO-APIC state failed: %d\n", ret);
1641 local_irq_save(flags);
1642 legacy_pic->mask_all();
1643 mask_ioapic_entries();
1645 /* If irq_remapping_prepare() succeeded, try to enable it */
1647 ir_stat = try_to_enable_IR();
1648 /* ir_stat contains the remap mode or an error code */
1649 try_to_enable_x2apic(ir_stat);
1652 restore_ioapic_entries();
1653 legacy_pic->restore_mask();
1654 local_irq_restore(flags);
1657 #ifdef CONFIG_X86_64
1659 * Detect and enable local APICs on non-SMP boards.
1660 * Original code written by Keir Fraser.
1661 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1662 * not correctly set up (usually the APIC timer won't work etc.)
1664 static int __init detect_init_APIC(void)
1666 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1667 pr_info("No local APIC present\n");
1671 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1676 static int __init apic_verify(void)
1681 * The APIC feature bit should now be enabled
1684 features = cpuid_edx(1);
1685 if (!(features & (1 << X86_FEATURE_APIC))) {
1686 pr_warning("Could not enable APIC!\n");
1689 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1690 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1692 /* The BIOS may have set up the APIC at some other address */
1693 if (boot_cpu_data.x86 >= 6) {
1694 rdmsr(MSR_IA32_APICBASE, l, h);
1695 if (l & MSR_IA32_APICBASE_ENABLE)
1696 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1699 pr_info("Found and enabled local APIC!\n");
1703 int __init apic_force_enable(unsigned long addr)
1711 * Some BIOSes disable the local APIC in the APIC_BASE
1712 * MSR. This can only be done in software for Intel P6 or later
1713 * and AMD K7 (Model > 1) or later.
1715 if (boot_cpu_data.x86 >= 6) {
1716 rdmsr(MSR_IA32_APICBASE, l, h);
1717 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1718 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1719 l &= ~MSR_IA32_APICBASE_BASE;
1720 l |= MSR_IA32_APICBASE_ENABLE | addr;
1721 wrmsr(MSR_IA32_APICBASE, l, h);
1722 enabled_via_apicbase = 1;
1725 return apic_verify();
1729 * Detect and initialize APIC
1731 static int __init detect_init_APIC(void)
1733 /* Disabled by kernel option? */
1737 switch (boot_cpu_data.x86_vendor) {
1738 case X86_VENDOR_AMD:
1739 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1740 (boot_cpu_data.x86 >= 15))
1743 case X86_VENDOR_INTEL:
1744 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1745 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1752 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1754 * Over-ride BIOS and try to enable the local APIC only if
1755 * "lapic" specified.
1757 if (!force_enable_local_apic) {
1758 pr_info("Local APIC disabled by BIOS -- "
1759 "you can enable it with \"lapic\"\n");
1762 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1774 pr_info("No local APIC present or hardware disabled\n");
1780 * init_apic_mappings - initialize APIC mappings
1782 void __init init_apic_mappings(void)
1784 unsigned int new_apicid;
1787 boot_cpu_physical_apicid = read_apic_id();
1791 /* If no local APIC can be found return early */
1792 if (!smp_found_config && detect_init_APIC()) {
1793 /* lets NOP'ify apic operations */
1794 pr_info("APIC: disable apic facility\n");
1797 apic_phys = mp_lapic_addr;
1800 * acpi lapic path already maps that address in
1801 * acpi_register_lapic_address()
1803 if (!acpi_lapic && !smp_found_config)
1804 register_lapic_address(apic_phys);
1808 * Fetch the APIC ID of the BSP in case we have a
1809 * default configuration (or the MP table is broken).
1811 new_apicid = read_apic_id();
1812 if (boot_cpu_physical_apicid != new_apicid) {
1813 boot_cpu_physical_apicid = new_apicid;
1815 * yeah -- we lie about apic_version
1816 * in case if apic was disabled via boot option
1817 * but it's not a problem for SMP compiled kernel
1818 * since smp_sanity_check is prepared for such a case
1819 * and disable smp mode
1821 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1825 void __init register_lapic_address(unsigned long address)
1827 mp_lapic_addr = address;
1830 set_fixmap_nocache(FIX_APIC_BASE, address);
1831 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1832 APIC_BASE, address);
1834 if (boot_cpu_physical_apicid == -1U) {
1835 boot_cpu_physical_apicid = read_apic_id();
1836 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1841 * Local APIC interrupts
1845 * This interrupt should _never_ happen with our APIC/SMP architecture
1847 static void __smp_spurious_interrupt(u8 vector)
1852 * Check if this really is a spurious interrupt and ACK it
1853 * if it is a vectored one. Just in case...
1854 * Spurious interrupts should not be ACKed.
1856 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1857 if (v & (1 << (vector & 0x1f)))
1860 inc_irq_stat(irq_spurious_count);
1862 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1863 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1864 "should never happen.\n", vector, smp_processor_id());
1867 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1870 __smp_spurious_interrupt(~regs->orig_ax);
1874 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1876 u8 vector = ~regs->orig_ax;
1879 trace_spurious_apic_entry(vector);
1880 __smp_spurious_interrupt(vector);
1881 trace_spurious_apic_exit(vector);
1886 * This interrupt should never happen with our APIC/SMP architecture
1888 static void __smp_error_interrupt(struct pt_regs *regs)
1892 static const char * const error_interrupt_reason[] = {
1893 "Send CS error", /* APIC Error Bit 0 */
1894 "Receive CS error", /* APIC Error Bit 1 */
1895 "Send accept error", /* APIC Error Bit 2 */
1896 "Receive accept error", /* APIC Error Bit 3 */
1897 "Redirectable IPI", /* APIC Error Bit 4 */
1898 "Send illegal vector", /* APIC Error Bit 5 */
1899 "Received illegal vector", /* APIC Error Bit 6 */
1900 "Illegal register address", /* APIC Error Bit 7 */
1903 /* First tickle the hardware, only then report what went on. -- REW */
1904 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1905 apic_write(APIC_ESR, 0);
1906 v = apic_read(APIC_ESR);
1908 atomic_inc(&irq_err_count);
1910 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1911 smp_processor_id(), v);
1916 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1921 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1925 __visible void smp_error_interrupt(struct pt_regs *regs)
1928 __smp_error_interrupt(regs);
1932 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
1935 trace_error_apic_entry(ERROR_APIC_VECTOR);
1936 __smp_error_interrupt(regs);
1937 trace_error_apic_exit(ERROR_APIC_VECTOR);
1942 * connect_bsp_APIC - attach the APIC to the interrupt system
1944 static void __init connect_bsp_APIC(void)
1946 #ifdef CONFIG_X86_32
1949 * Do not trust the local APIC being empty at bootup.
1953 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1954 * local APIC to INT and NMI lines.
1956 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1957 "enabling APIC mode.\n");
1964 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1965 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1967 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1970 void disconnect_bsp_APIC(int virt_wire_setup)
1974 #ifdef CONFIG_X86_32
1977 * Put the board back into PIC mode (has an effect only on
1978 * certain older boards). Note that APIC interrupts, including
1979 * IPIs, won't work beyond this point! The only exception are
1982 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1983 "entering PIC mode.\n");
1989 /* Go back to Virtual Wire compatibility mode */
1991 /* For the spurious interrupt use vector F, and enable it */
1992 value = apic_read(APIC_SPIV);
1993 value &= ~APIC_VECTOR_MASK;
1994 value |= APIC_SPIV_APIC_ENABLED;
1996 apic_write(APIC_SPIV, value);
1998 if (!virt_wire_setup) {
2000 * For LVT0 make it edge triggered, active high,
2001 * external and enabled
2003 value = apic_read(APIC_LVT0);
2004 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2005 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2006 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2007 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2008 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2009 apic_write(APIC_LVT0, value);
2012 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2016 * For LVT1 make it edge triggered, active high,
2019 value = apic_read(APIC_LVT1);
2020 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2021 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2022 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2023 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2024 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2025 apic_write(APIC_LVT1, value);
2029 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2030 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2031 * All allocated CPU ID should be in [0, nr_logical_cpuidi), so the maximum of
2032 * nr_logical_cpuids is nr_cpu_ids.
2034 * NOTE: Reserve 0 for BSP.
2036 static int nr_logical_cpuids = 1;
2039 * Used to store mapping between logical CPU IDs and APIC IDs.
2041 static int cpuid_to_apicid[] = {
2042 [0 ... NR_CPUS - 1] = -1,
2046 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2047 * and cpuid_to_apicid[] synchronized.
2049 static int allocate_logical_cpuid(int apicid)
2054 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2055 * check if the kernel has allocated a cpuid for it.
2057 for (i = 0; i < nr_logical_cpuids; i++) {
2058 if (cpuid_to_apicid[i] == apicid)
2062 /* Allocate a new cpuid. */
2063 if (nr_logical_cpuids >= nr_cpu_ids) {
2064 WARN_ONCE(1, "Only %d processors supported."
2065 "Processor %d/0x%x and the rest are ignored.\n",
2066 nr_cpu_ids - 1, nr_logical_cpuids, apicid);
2070 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2071 return nr_logical_cpuids++;
2074 int __generic_processor_info(int apicid, int version, bool enabled)
2076 int cpu, max = nr_cpu_ids;
2077 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2078 phys_cpu_present_map);
2081 * boot_cpu_physical_apicid is designed to have the apicid
2082 * returned by read_apic_id(), i.e, the apicid of the
2083 * currently booting-up processor. However, on some platforms,
2084 * it is temporarily modified by the apicid reported as BSP
2085 * through MP table. Concretely:
2087 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2088 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2090 * This function is executed with the modified
2091 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2092 * parameter doesn't work to disable APs on kdump 2nd kernel.
2094 * Since fixing handling of boot_cpu_physical_apicid requires
2095 * another discussion and tests on each platform, we leave it
2096 * for now and here we use read_apic_id() directly in this
2097 * function, generic_processor_info().
2099 if (disabled_cpu_apicid != BAD_APICID &&
2100 disabled_cpu_apicid != read_apic_id() &&
2101 disabled_cpu_apicid == apicid) {
2102 int thiscpu = num_processors + disabled_cpus;
2104 pr_warning("APIC: Disabling requested cpu."
2105 " Processor %d/0x%x ignored.\n",
2113 * If boot cpu has not been detected yet, then only allow upto
2114 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2116 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2117 apicid != boot_cpu_physical_apicid) {
2118 int thiscpu = max + disabled_cpus - 1;
2121 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2122 " reached. Keeping one slot for boot cpu."
2123 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2129 if (num_processors >= nr_cpu_ids) {
2130 int thiscpu = max + disabled_cpus;
2133 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2134 "reached. Processor %d/0x%x ignored.\n",
2135 max, thiscpu, apicid);
2142 if (apicid == boot_cpu_physical_apicid) {
2144 * x86_bios_cpu_apicid is required to have processors listed
2145 * in same order as logical cpu numbers. Hence the first
2146 * entry is BSP, and so on.
2147 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2152 /* Logical cpuid 0 is reserved for BSP. */
2153 cpuid_to_apicid[0] = apicid;
2155 cpu = allocate_logical_cpuid(apicid);
2165 if (version == 0x0) {
2166 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2171 if (version != boot_cpu_apic_version) {
2172 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2173 boot_cpu_apic_version, cpu, version);
2176 if (apicid > max_physical_apicid)
2177 max_physical_apicid = apicid;
2179 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2180 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2181 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2183 #ifdef CONFIG_X86_32
2184 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2185 apic->x86_32_early_logical_apicid(cpu);
2187 set_cpu_possible(cpu, true);
2191 physid_set(apicid, phys_cpu_present_map);
2192 set_cpu_present(cpu, true);
2200 int generic_processor_info(int apicid, int version)
2202 return __generic_processor_info(apicid, version, true);
2205 int hard_smp_processor_id(void)
2207 return read_apic_id();
2210 void default_init_apic_ldr(void)
2214 apic_write(APIC_DFR, APIC_DFR_VALUE);
2215 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2216 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2217 apic_write(APIC_LDR, val);
2220 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2221 const struct cpumask *andmask,
2222 unsigned int *apicid)
2226 for_each_cpu_and(cpu, cpumask, andmask) {
2227 if (cpumask_test_cpu(cpu, cpu_online_mask))
2231 if (likely(cpu < nr_cpu_ids)) {
2232 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2240 * Override the generic EOI implementation with an optimized version.
2241 * Only called during early boot when only one CPU is active and with
2242 * interrupts disabled, so we know this does not race with actual APIC driver
2245 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2249 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2250 /* Should happen once for each apic */
2251 WARN_ON((*drv)->eoi_write == eoi_write);
2252 (*drv)->native_eoi_write = (*drv)->eoi_write;
2253 (*drv)->eoi_write = eoi_write;
2257 static void __init apic_bsp_up_setup(void)
2259 #ifdef CONFIG_X86_64
2260 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2263 * Hack: In case of kdump, after a crash, kernel might be booting
2264 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2265 * might be zero if read from MP tables. Get it from LAPIC.
2267 # ifdef CONFIG_CRASH_DUMP
2268 boot_cpu_physical_apicid = read_apic_id();
2271 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2275 * apic_bsp_setup - Setup function for local apic and io-apic
2276 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2279 * apic_id of BSP APIC
2281 int __init apic_bsp_setup(bool upmode)
2287 apic_bsp_up_setup();
2291 id = apic_read(APIC_LDR);
2293 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2296 end_local_APIC_setup();
2297 irq_remap_enable_fault_handling();
2299 /* Setup local timer */
2300 x86_init.timers.setup_percpu_clockev();
2305 * This initializes the IO-APIC and APIC hardware if this is
2308 int __init APIC_init_uniprocessor(void)
2311 pr_info("Apic disabled\n");
2314 #ifdef CONFIG_X86_64
2315 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2317 pr_info("Apic disabled by BIOS\n");
2321 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2325 * Complain if the BIOS pretends there is one.
2327 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2328 APIC_INTEGRATED(boot_cpu_apic_version)) {
2329 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2330 boot_cpu_physical_apicid);
2335 if (!smp_found_config)
2336 disable_ioapic_support();
2338 default_setup_apic_routing();
2339 apic_bsp_setup(true);
2343 #ifdef CONFIG_UP_LATE_INIT
2344 void __init up_late_init(void)
2346 APIC_init_uniprocessor();
2357 * 'active' is true if the local APIC was enabled by us and
2358 * not the BIOS; this signifies that we are also responsible
2359 * for disabling it before entering apm/acpi suspend
2362 /* r/w apic fields */
2363 unsigned int apic_id;
2364 unsigned int apic_taskpri;
2365 unsigned int apic_ldr;
2366 unsigned int apic_dfr;
2367 unsigned int apic_spiv;
2368 unsigned int apic_lvtt;
2369 unsigned int apic_lvtpc;
2370 unsigned int apic_lvt0;
2371 unsigned int apic_lvt1;
2372 unsigned int apic_lvterr;
2373 unsigned int apic_tmict;
2374 unsigned int apic_tdcr;
2375 unsigned int apic_thmr;
2376 unsigned int apic_cmci;
2379 static int lapic_suspend(void)
2381 unsigned long flags;
2384 if (!apic_pm_state.active)
2387 maxlvt = lapic_get_maxlvt();
2389 apic_pm_state.apic_id = apic_read(APIC_ID);
2390 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2391 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2392 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2393 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2394 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2396 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2397 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2398 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2399 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2400 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2401 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2402 #ifdef CONFIG_X86_THERMAL_VECTOR
2404 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2406 #ifdef CONFIG_X86_MCE_INTEL
2408 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2411 local_irq_save(flags);
2412 disable_local_APIC();
2414 irq_remapping_disable();
2416 local_irq_restore(flags);
2420 static void lapic_resume(void)
2423 unsigned long flags;
2426 if (!apic_pm_state.active)
2429 local_irq_save(flags);
2432 * IO-APIC and PIC have their own resume routines.
2433 * We just mask them here to make sure the interrupt
2434 * subsystem is completely quiet while we enable x2apic
2435 * and interrupt-remapping.
2437 mask_ioapic_entries();
2438 legacy_pic->mask_all();
2444 * Make sure the APICBASE points to the right address
2446 * FIXME! This will be wrong if we ever support suspend on
2447 * SMP! We'll need to do this as part of the CPU restore!
2449 if (boot_cpu_data.x86 >= 6) {
2450 rdmsr(MSR_IA32_APICBASE, l, h);
2451 l &= ~MSR_IA32_APICBASE_BASE;
2452 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2453 wrmsr(MSR_IA32_APICBASE, l, h);
2457 maxlvt = lapic_get_maxlvt();
2458 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2459 apic_write(APIC_ID, apic_pm_state.apic_id);
2460 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2461 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2462 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2463 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2464 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2465 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2466 #ifdef CONFIG_X86_THERMAL_VECTOR
2468 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2470 #ifdef CONFIG_X86_MCE_INTEL
2472 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2475 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2476 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2477 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2478 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2479 apic_write(APIC_ESR, 0);
2480 apic_read(APIC_ESR);
2481 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2482 apic_write(APIC_ESR, 0);
2483 apic_read(APIC_ESR);
2485 irq_remapping_reenable(x2apic_mode);
2487 local_irq_restore(flags);
2491 * This device has no shutdown method - fully functioning local APICs
2492 * are needed on every CPU up until machine_halt/restart/poweroff.
2495 static struct syscore_ops lapic_syscore_ops = {
2496 .resume = lapic_resume,
2497 .suspend = lapic_suspend,
2500 static void apic_pm_activate(void)
2502 apic_pm_state.active = 1;
2505 static int __init init_lapic_sysfs(void)
2507 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2508 if (boot_cpu_has(X86_FEATURE_APIC))
2509 register_syscore_ops(&lapic_syscore_ops);
2514 /* local apic needs to resume before other devices access its registers. */
2515 core_initcall(init_lapic_sysfs);
2517 #else /* CONFIG_PM */
2519 static void apic_pm_activate(void) { }
2521 #endif /* CONFIG_PM */
2523 #ifdef CONFIG_X86_64
2525 static int multi_checked;
2528 static int set_multi(const struct dmi_system_id *d)
2532 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2537 static const struct dmi_system_id multi_dmi_table[] = {
2539 .callback = set_multi,
2540 .ident = "IBM System Summit2",
2542 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2543 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2549 static void dmi_check_multi(void)
2554 dmi_check_system(multi_dmi_table);
2559 * apic_is_clustered_box() -- Check if we can expect good TSC
2561 * Thus far, the major user of this is IBM's Summit2 series:
2562 * Clustered boxes may have unsynced TSC problems if they are
2564 * Use DMI to check them
2566 int apic_is_clustered_box(void)
2574 * APIC command line parameters
2576 static int __init setup_disableapic(char *arg)
2579 setup_clear_cpu_cap(X86_FEATURE_APIC);
2582 early_param("disableapic", setup_disableapic);
2584 /* same as disableapic, for compatibility */
2585 static int __init setup_nolapic(char *arg)
2587 return setup_disableapic(arg);
2589 early_param("nolapic", setup_nolapic);
2591 static int __init parse_lapic_timer_c2_ok(char *arg)
2593 local_apic_timer_c2_ok = 1;
2596 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2598 static int __init parse_disable_apic_timer(char *arg)
2600 disable_apic_timer = 1;
2603 early_param("noapictimer", parse_disable_apic_timer);
2605 static int __init parse_nolapic_timer(char *arg)
2607 disable_apic_timer = 1;
2610 early_param("nolapic_timer", parse_nolapic_timer);
2612 static int __init apic_set_verbosity(char *arg)
2615 #ifdef CONFIG_X86_64
2616 skip_ioapic_setup = 0;
2622 if (strcmp("debug", arg) == 0)
2623 apic_verbosity = APIC_DEBUG;
2624 else if (strcmp("verbose", arg) == 0)
2625 apic_verbosity = APIC_VERBOSE;
2627 pr_warning("APIC Verbosity level %s not recognised"
2628 " use apic=verbose or apic=debug\n", arg);
2634 early_param("apic", apic_set_verbosity);
2636 static int __init lapic_insert_resource(void)
2641 /* Put local APIC into the resource map. */
2642 lapic_resource.start = apic_phys;
2643 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2644 insert_resource(&iomem_resource, &lapic_resource);
2650 * need call insert after e820_reserve_resources()
2651 * that is using request_resource
2653 late_initcall(lapic_insert_resource);
2655 static int __init apic_set_disabled_cpu_apicid(char *arg)
2657 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2662 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2664 static int __init apic_set_extnmi(char *arg)
2669 if (!strncmp("all", arg, 3))
2670 apic_extnmi = APIC_EXTNMI_ALL;
2671 else if (!strncmp("none", arg, 4))
2672 apic_extnmi = APIC_EXTNMI_NONE;
2673 else if (!strncmp("bsp", arg, 3))
2674 apic_extnmi = APIC_EXTNMI_BSP;
2676 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2682 early_param("apic_extnmi", apic_set_extnmi);