2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
60 unsigned int num_processors;
62 unsigned disabled_cpus;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_physical_apicid = -1U;
66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68 u8 boot_cpu_apic_version;
71 * The highest APIC ID seen during enumeration.
73 static unsigned int max_physical_apicid;
76 * Bitmask of physically existing CPUs:
78 physid_mask_t phys_cpu_present_map;
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
91 static int apic_extnmi = APIC_EXTNMI_BSP;
94 * Map cpu index to physical APIC ID
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
124 static inline void imcr_pic_to_apic(void)
126 /* select IMCR register */
128 /* NMI and 8259 INTR go through APIC */
132 static inline void imcr_apic_to_pic(void)
134 /* select IMCR register */
136 /* NMI and 8259 INTR go directly to BSP */
142 * Knob to control our willingness to enable the local APIC.
146 static int force_enable_local_apic __initdata;
149 * APIC command line parameters
151 static int __init parse_lapic(char *arg)
153 if (IS_ENABLED(CONFIG_X86_32) && !arg)
154 force_enable_local_apic = 1;
155 else if (arg && !strncmp(arg, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
159 early_param("lapic", parse_lapic);
162 static int apic_calibrate_pmtmr __initdata;
163 static __init int setup_apicpmtimer(char *s)
165 apic_calibrate_pmtmr = 1;
169 __setup("apicpmtimer", setup_apicpmtimer);
172 unsigned long mp_lapic_addr;
174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
175 static int disable_apic_timer __initdata;
176 /* Local APIC timer works in C2 */
177 int local_apic_timer_c2_ok;
178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
180 int first_system_vector = FIRST_SYSTEM_VECTOR;
183 * Debug level, exported for io_apic.c
185 unsigned int apic_verbosity;
189 /* Have we found an MP table */
190 int smp_found_config;
192 static struct resource lapic_resource = {
193 .name = "Local APIC",
194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
197 unsigned int lapic_timer_frequency = 0;
199 static void apic_pm_activate(void);
201 static unsigned long apic_phys;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
219 return APIC_INTEGRATED(lapic_get_version());
224 * Check, whether this is a modern or a first generation APIC
226 static int modern_apic(void)
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
230 boot_cpu_data.x86 >= 0xf)
232 return lapic_get_version() >= 0x14;
236 * right after this call apic become NOOP driven
237 * so apic->write/read doesn't do anything
239 static void __init apic_disable(void)
241 pr_info("APIC: switched to apic NOOP\n");
245 void native_apic_wait_icr_idle(void)
247 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
251 u32 native_safe_apic_wait_icr_idle(void)
258 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
261 inc_irq_stat(icr_read_retry_count);
263 } while (timeout++ < 1000);
268 void native_apic_icr_write(u32 low, u32 id)
272 local_irq_save(flags);
273 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
274 apic_write(APIC_ICR, low);
275 local_irq_restore(flags);
278 u64 native_apic_icr_read(void)
282 icr2 = apic_read(APIC_ICR2);
283 icr1 = apic_read(APIC_ICR);
285 return icr1 | ((u64)icr2 << 32);
290 * get_physical_broadcast - Get number of physical broadcast IDs
292 int get_physical_broadcast(void)
294 return modern_apic() ? 0xff : 0xf;
299 * lapic_get_maxlvt - get the maximum number of local vector table entries
301 int lapic_get_maxlvt(void)
305 v = apic_read(APIC_LVR);
307 * - we always have APIC integrated on 64bit mode
308 * - 82489DXs do not report # of LVT entries
310 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
318 #define APIC_DIVISOR 16
319 #define TSC_DIVISOR 8
322 * This function sets up the local APIC timer, with a timeout of
323 * 'clocks' APIC bus clock. During calibration we actually call
324 * this function twice on the boot CPU, once with a bogus timeout
325 * value, second time for real. The other (noncalibrating) CPUs
326 * call this function only once, with the real, calibrated value.
328 * We do reads before writes even if unnecessary, to get around the
329 * P5 APIC double write bug.
331 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
333 unsigned int lvtt_value, tmp_value;
335 lvtt_value = LOCAL_TIMER_VECTOR;
337 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
338 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
339 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
341 if (!lapic_is_integrated())
342 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
345 lvtt_value |= APIC_LVT_MASKED;
347 apic_write(APIC_LVTT, lvtt_value);
349 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
351 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
352 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
353 * According to Intel, MFENCE can do the serialization here.
355 asm volatile("mfence" : : : "memory");
357 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
364 tmp_value = apic_read(APIC_TDCR);
365 apic_write(APIC_TDCR,
366 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
370 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
374 * Setup extended LVT, AMD specific
376 * Software should use the LVT offsets the BIOS provides. The offsets
377 * are determined by the subsystems using it like those for MCE
378 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
379 * are supported. Beginning with family 10h at least 4 offsets are
382 * Since the offsets must be consistent for all cores, we keep track
383 * of the LVT offsets in software and reserve the offset for the same
384 * vector also to be used on other cores. An offset is freed by
385 * setting the entry to APIC_EILVT_MASKED.
387 * If the BIOS is right, there should be no conflicts. Otherwise a
388 * "[Firmware Bug]: ..." error message is generated. However, if
389 * software does not properly determines the offsets, it is not
390 * necessarily a BIOS bug.
393 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
395 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
397 return (old & APIC_EILVT_MASKED)
398 || (new == APIC_EILVT_MASKED)
399 || ((new & ~APIC_EILVT_MASKED) == old);
402 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
404 unsigned int rsvd, vector;
406 if (offset >= APIC_EILVT_NR_MAX)
409 rsvd = atomic_read(&eilvt_offsets[offset]);
411 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
412 if (vector && !eilvt_entry_is_changeable(vector, new))
413 /* may not change if vectors are different */
415 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
416 } while (rsvd != new);
418 rsvd &= ~APIC_EILVT_MASKED;
419 if (rsvd && rsvd != vector)
420 pr_info("LVT offset %d assigned for vector 0x%02x\n",
427 * If mask=1, the LVT entry does not generate interrupts while mask=0
428 * enables the vector. See also the BKDGs. Must be called with
429 * preemption disabled.
432 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
434 unsigned long reg = APIC_EILVTn(offset);
435 unsigned int new, old, reserved;
437 new = (mask << 16) | (msg_type << 8) | vector;
438 old = apic_read(reg);
439 reserved = reserve_eilvt_offset(offset, new);
441 if (reserved != new) {
442 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
443 "vector 0x%x, but the register is already in use for "
444 "vector 0x%x on another cpu\n",
445 smp_processor_id(), reg, offset, new, reserved);
449 if (!eilvt_entry_is_changeable(old, new)) {
450 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
451 "vector 0x%x, but the register is already in use for "
452 "vector 0x%x on this cpu\n",
453 smp_processor_id(), reg, offset, new, old);
457 apic_write(reg, new);
461 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
464 * Program the next event, relative to now
466 static int lapic_next_event(unsigned long delta,
467 struct clock_event_device *evt)
469 apic_write(APIC_TMICT, delta);
473 static int lapic_next_deadline(unsigned long delta,
474 struct clock_event_device *evt)
479 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
483 static int lapic_timer_shutdown(struct clock_event_device *evt)
487 /* Lapic used as dummy for broadcast ? */
488 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
491 v = apic_read(APIC_LVTT);
492 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
493 apic_write(APIC_LVTT, v);
494 apic_write(APIC_TMICT, 0);
499 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
501 /* Lapic used as dummy for broadcast ? */
502 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
505 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
509 static int lapic_timer_set_periodic(struct clock_event_device *evt)
511 return lapic_timer_set_periodic_oneshot(evt, false);
514 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
516 return lapic_timer_set_periodic_oneshot(evt, true);
520 * Local APIC timer broadcast function
522 static void lapic_timer_broadcast(const struct cpumask *mask)
525 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
531 * The local apic timer can be used for any function which is CPU local.
533 static struct clock_event_device lapic_clockevent = {
535 .features = CLOCK_EVT_FEAT_PERIODIC |
536 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
537 | CLOCK_EVT_FEAT_DUMMY,
539 .set_state_shutdown = lapic_timer_shutdown,
540 .set_state_periodic = lapic_timer_set_periodic,
541 .set_state_oneshot = lapic_timer_set_oneshot,
542 .set_state_oneshot_stopped = lapic_timer_shutdown,
543 .set_next_event = lapic_next_event,
544 .broadcast = lapic_timer_broadcast,
548 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
550 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
551 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
553 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
554 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
556 static u32 hsx_deadline_rev(void)
558 switch (boot_cpu_data.x86_mask) {
559 case 0x02: return 0x3a; /* EP */
560 case 0x04: return 0x0f; /* EX */
566 static u32 bdx_deadline_rev(void)
568 switch (boot_cpu_data.x86_mask) {
569 case 0x02: return 0x00000011;
570 case 0x03: return 0x0700000e;
571 case 0x04: return 0x0f00000c;
572 case 0x05: return 0x0e000003;
578 static const struct x86_cpu_id deadline_match[] = {
579 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
580 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
581 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
582 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014),
584 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
588 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
600 static void apic_check_deadline_errata(void)
602 const struct x86_cpu_id *m = x86_match_cpu(deadline_match);
609 * Function pointers will have the MSB set due to address layout,
610 * immediate revisions will not.
612 if ((long)m->driver_data < 0)
613 rev = ((u32 (*)(void))(m->driver_data))();
615 rev = (u32)m->driver_data;
617 if (boot_cpu_data.microcode >= rev)
620 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
621 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
622 "please update microcode to version: 0x%x (or later)\n", rev);
626 * Setup the local APIC timer for this CPU. Copy the initialized values
627 * of the boot CPU and register the clock event in the framework.
629 static void setup_APIC_timer(void)
631 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
633 if (this_cpu_has(X86_FEATURE_ARAT)) {
634 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
635 /* Make LAPIC timer preferrable over percpu HPET */
636 lapic_clockevent.rating = 150;
639 memcpy(levt, &lapic_clockevent, sizeof(*levt));
640 levt->cpumask = cpumask_of(smp_processor_id());
642 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
643 levt->name = "lapic-deadline";
644 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
645 CLOCK_EVT_FEAT_DUMMY);
646 levt->set_next_event = lapic_next_deadline;
647 clockevents_config_and_register(levt,
648 tsc_khz * (1000 / TSC_DIVISOR),
651 clockevents_register_device(levt);
655 * Install the updated TSC frequency from recalibration at the TSC
656 * deadline clockevent devices.
658 static void __lapic_update_tsc_freq(void *info)
660 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
662 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
665 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
668 void lapic_update_tsc_freq(void)
671 * The clockevent device's ->mult and ->shift can both be
672 * changed. In order to avoid races, schedule the frequency
673 * update code on each CPU.
675 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
679 * In this functions we calibrate APIC bus clocks to the external timer.
681 * We want to do the calibration only once since we want to have local timer
682 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
685 * This was previously done by reading the PIT/HPET and waiting for a wrap
686 * around to find out, that a tick has elapsed. I have a box, where the PIT
687 * readout is broken, so it never gets out of the wait loop again. This was
688 * also reported by others.
690 * Monitoring the jiffies value is inaccurate and the clockevents
691 * infrastructure allows us to do a simple substitution of the interrupt
694 * The calibration routine also uses the pm_timer when possible, as the PIT
695 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
696 * back to normal later in the boot process).
699 #define LAPIC_CAL_LOOPS (HZ/10)
701 static __initdata int lapic_cal_loops = -1;
702 static __initdata long lapic_cal_t1, lapic_cal_t2;
703 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
704 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
705 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
708 * Temporary interrupt handler.
710 static void __init lapic_cal_handler(struct clock_event_device *dev)
712 unsigned long long tsc = 0;
713 long tapic = apic_read(APIC_TMCCT);
714 unsigned long pm = acpi_pm_read_early();
716 if (boot_cpu_has(X86_FEATURE_TSC))
719 switch (lapic_cal_loops++) {
721 lapic_cal_t1 = tapic;
722 lapic_cal_tsc1 = tsc;
724 lapic_cal_j1 = jiffies;
727 case LAPIC_CAL_LOOPS:
728 lapic_cal_t2 = tapic;
729 lapic_cal_tsc2 = tsc;
730 if (pm < lapic_cal_pm1)
731 pm += ACPI_PM_OVRRUN;
733 lapic_cal_j2 = jiffies;
739 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
741 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
742 const long pm_thresh = pm_100ms / 100;
746 #ifndef CONFIG_X86_PM_TIMER
750 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
752 /* Check, if the PM timer is available */
756 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
758 if (deltapm > (pm_100ms - pm_thresh) &&
759 deltapm < (pm_100ms + pm_thresh)) {
760 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
764 res = (((u64)deltapm) * mult) >> 22;
765 do_div(res, 1000000);
766 pr_warning("APIC calibration not consistent "
767 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
769 /* Correct the lapic counter value */
770 res = (((u64)(*delta)) * pm_100ms);
771 do_div(res, deltapm);
772 pr_info("APIC delta adjusted to PM-Timer: "
773 "%lu (%ld)\n", (unsigned long)res, *delta);
776 /* Correct the tsc counter value */
777 if (boot_cpu_has(X86_FEATURE_TSC)) {
778 res = (((u64)(*deltatsc)) * pm_100ms);
779 do_div(res, deltapm);
780 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
781 "PM-Timer: %lu (%ld)\n",
782 (unsigned long)res, *deltatsc);
783 *deltatsc = (long)res;
789 static int __init calibrate_APIC_clock(void)
791 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
792 void (*real_handler)(struct clock_event_device *dev);
793 unsigned long deltaj;
794 long delta, deltatsc;
795 int pm_referenced = 0;
798 * check if lapic timer has already been calibrated by platform
799 * specific routine, such as tsc calibration code. if so, we just fill
800 * in the clockevent structure and return.
803 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
805 } else if (lapic_timer_frequency) {
806 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
807 lapic_timer_frequency);
808 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
809 TICK_NSEC, lapic_clockevent.shift);
810 lapic_clockevent.max_delta_ns =
811 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
812 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
813 lapic_clockevent.min_delta_ns =
814 clockevent_delta2ns(0xF, &lapic_clockevent);
815 lapic_clockevent.min_delta_ticks = 0xF;
816 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
820 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
821 "calibrating APIC timer ...\n");
825 /* Replace the global interrupt handler */
826 real_handler = global_clock_event->event_handler;
827 global_clock_event->event_handler = lapic_cal_handler;
830 * Setup the APIC counter to maximum. There is no way the lapic
831 * can underflow in the 100ms detection time frame
833 __setup_APIC_LVTT(0xffffffff, 0, 0);
835 /* Let the interrupts run */
838 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
843 /* Restore the real event handler */
844 global_clock_event->event_handler = real_handler;
846 /* Build delta t1-t2 as apic timer counts down */
847 delta = lapic_cal_t1 - lapic_cal_t2;
848 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
850 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
852 /* we trust the PM based calibration if possible */
853 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
856 /* Calculate the scaled math multiplication factor */
857 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
858 lapic_clockevent.shift);
859 lapic_clockevent.max_delta_ns =
860 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
861 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
862 lapic_clockevent.min_delta_ns =
863 clockevent_delta2ns(0xF, &lapic_clockevent);
864 lapic_clockevent.min_delta_ticks = 0xF;
866 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
868 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
869 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
870 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
871 lapic_timer_frequency);
873 if (boot_cpu_has(X86_FEATURE_TSC)) {
874 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
876 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
877 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
880 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
882 lapic_timer_frequency / (1000000 / HZ),
883 lapic_timer_frequency % (1000000 / HZ));
886 * Do a sanity check on the APIC calibration result
888 if (lapic_timer_frequency < (1000000 / HZ)) {
890 pr_warning("APIC frequency too slow, disabling apic timer\n");
894 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
897 * PM timer calibration failed or not turned on
898 * so lets try APIC timer based calibration
900 if (!pm_referenced) {
901 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
904 * Setup the apic timer manually
906 levt->event_handler = lapic_cal_handler;
907 lapic_timer_set_periodic(levt);
908 lapic_cal_loops = -1;
910 /* Let the interrupts run */
913 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
916 /* Stop the lapic timer */
918 lapic_timer_shutdown(levt);
921 deltaj = lapic_cal_j2 - lapic_cal_j1;
922 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
924 /* Check, if the jiffies result is consistent */
925 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
926 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
928 levt->features |= CLOCK_EVT_FEAT_DUMMY;
932 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
933 pr_warning("APIC timer disabled due to verification failure\n");
941 * Setup the boot APIC
943 * Calibrate and verify the result.
945 void __init setup_boot_APIC_clock(void)
948 * The local apic timer can be disabled via the kernel
949 * commandline or from the CPU detection code. Register the lapic
950 * timer as a dummy clock event source on SMP systems, so the
951 * broadcast mechanism is used. On UP systems simply ignore it.
953 if (disable_apic_timer) {
954 pr_info("Disabling APIC timer\n");
955 /* No broadcast on UP ! */
956 if (num_possible_cpus() > 1) {
957 lapic_clockevent.mult = 1;
963 if (calibrate_APIC_clock()) {
964 /* No broadcast on UP ! */
965 if (num_possible_cpus() > 1)
971 * If nmi_watchdog is set to IO_APIC, we need the
972 * PIT/HPET going. Otherwise register lapic as a dummy
975 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
977 /* Setup the lapic or request the broadcast */
979 amd_e400_c1e_apic_setup();
982 void setup_secondary_APIC_clock(void)
985 amd_e400_c1e_apic_setup();
989 * The guts of the apic timer interrupt
991 static void local_apic_timer_interrupt(void)
993 int cpu = smp_processor_id();
994 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
997 * Normally we should not be here till LAPIC has been initialized but
998 * in some cases like kdump, its possible that there is a pending LAPIC
999 * timer interrupt from previous kernel's context and is delivered in
1000 * new kernel the moment interrupts are enabled.
1002 * Interrupts are enabled early and LAPIC is setup much later, hence
1003 * its possible that when we get here evt->event_handler is NULL.
1004 * Check for event_handler being NULL and discard the interrupt as
1007 if (!evt->event_handler) {
1008 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
1010 lapic_timer_shutdown(evt);
1015 * the NMI deadlock-detector uses this.
1017 inc_irq_stat(apic_timer_irqs);
1019 evt->event_handler(evt);
1023 * Local APIC timer interrupt. This is the most natural way for doing
1024 * local interrupts, but local timer interrupts can be emulated by
1025 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1027 * [ if a single-CPU system runs an SMP kernel then we call the local
1028 * interrupt as well. Thus we cannot inline the local irq ... ]
1030 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1032 struct pt_regs *old_regs = set_irq_regs(regs);
1035 * NOTE! We'd better ACK the irq immediately,
1036 * because timer handling can be slow.
1038 * update_process_times() expects us to have done irq_enter().
1039 * Besides, if we don't timer interrupts ignore the global
1040 * interrupt lock, which is the WrongThing (tm) to do.
1043 local_apic_timer_interrupt();
1046 set_irq_regs(old_regs);
1049 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
1051 struct pt_regs *old_regs = set_irq_regs(regs);
1054 * NOTE! We'd better ACK the irq immediately,
1055 * because timer handling can be slow.
1057 * update_process_times() expects us to have done irq_enter().
1058 * Besides, if we don't timer interrupts ignore the global
1059 * interrupt lock, which is the WrongThing (tm) to do.
1062 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1063 local_apic_timer_interrupt();
1064 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1067 set_irq_regs(old_regs);
1070 int setup_profiling_timer(unsigned int multiplier)
1076 * Local APIC start and shutdown
1080 * clear_local_APIC - shutdown the local APIC
1082 * This is called, when a CPU is disabled and before rebooting, so the state of
1083 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1084 * leftovers during boot.
1086 void clear_local_APIC(void)
1091 /* APIC hasn't been mapped yet */
1092 if (!x2apic_mode && !apic_phys)
1095 maxlvt = lapic_get_maxlvt();
1097 * Masking an LVT entry can trigger a local APIC error
1098 * if the vector is zero. Mask LVTERR first to prevent this.
1101 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1102 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1105 * Careful: we have to set masks only first to deassert
1106 * any level-triggered sources.
1108 v = apic_read(APIC_LVTT);
1109 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1110 v = apic_read(APIC_LVT0);
1111 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1112 v = apic_read(APIC_LVT1);
1113 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1115 v = apic_read(APIC_LVTPC);
1116 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1119 /* lets not touch this if we didn't frob it */
1120 #ifdef CONFIG_X86_THERMAL_VECTOR
1122 v = apic_read(APIC_LVTTHMR);
1123 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1126 #ifdef CONFIG_X86_MCE_INTEL
1128 v = apic_read(APIC_LVTCMCI);
1129 if (!(v & APIC_LVT_MASKED))
1130 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1135 * Clean APIC state for other OSs:
1137 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1138 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1139 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1141 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1143 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1145 /* Integrated APIC (!82489DX) ? */
1146 if (lapic_is_integrated()) {
1148 /* Clear ESR due to Pentium errata 3AP and 11AP */
1149 apic_write(APIC_ESR, 0);
1150 apic_read(APIC_ESR);
1155 * disable_local_APIC - clear and disable the local APIC
1157 void disable_local_APIC(void)
1161 /* APIC hasn't been mapped yet */
1162 if (!x2apic_mode && !apic_phys)
1168 * Disable APIC (implies clearing of registers
1171 value = apic_read(APIC_SPIV);
1172 value &= ~APIC_SPIV_APIC_ENABLED;
1173 apic_write(APIC_SPIV, value);
1175 #ifdef CONFIG_X86_32
1177 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1178 * restore the disabled state.
1180 if (enabled_via_apicbase) {
1183 rdmsr(MSR_IA32_APICBASE, l, h);
1184 l &= ~MSR_IA32_APICBASE_ENABLE;
1185 wrmsr(MSR_IA32_APICBASE, l, h);
1191 * If Linux enabled the LAPIC against the BIOS default disable it down before
1192 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1193 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1194 * for the case where Linux didn't enable the LAPIC.
1196 void lapic_shutdown(void)
1198 unsigned long flags;
1200 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1203 local_irq_save(flags);
1205 #ifdef CONFIG_X86_32
1206 if (!enabled_via_apicbase)
1210 disable_local_APIC();
1213 local_irq_restore(flags);
1217 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1219 void __init sync_Arb_IDs(void)
1222 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1225 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1231 apic_wait_icr_idle();
1233 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1234 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1235 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1239 * An initial setup of the virtual wire mode.
1241 void __init init_bsp_APIC(void)
1246 * Don't do the setup now if we have a SMP BIOS as the
1247 * through-I/O-APIC virtual wire mode might be active.
1249 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1253 * Do not trust the local APIC being empty at bootup.
1260 value = apic_read(APIC_SPIV);
1261 value &= ~APIC_VECTOR_MASK;
1262 value |= APIC_SPIV_APIC_ENABLED;
1264 #ifdef CONFIG_X86_32
1265 /* This bit is reserved on P4/Xeon and should be cleared */
1266 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1267 (boot_cpu_data.x86 == 15))
1268 value &= ~APIC_SPIV_FOCUS_DISABLED;
1271 value |= APIC_SPIV_FOCUS_DISABLED;
1272 value |= SPURIOUS_APIC_VECTOR;
1273 apic_write(APIC_SPIV, value);
1276 * Set up the virtual wire mode.
1278 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1279 value = APIC_DM_NMI;
1280 if (!lapic_is_integrated()) /* 82489DX */
1281 value |= APIC_LVT_LEVEL_TRIGGER;
1282 if (apic_extnmi == APIC_EXTNMI_NONE)
1283 value |= APIC_LVT_MASKED;
1284 apic_write(APIC_LVT1, value);
1287 static void lapic_setup_esr(void)
1289 unsigned int oldvalue, value, maxlvt;
1291 if (!lapic_is_integrated()) {
1292 pr_info("No ESR for 82489DX.\n");
1296 if (apic->disable_esr) {
1298 * Something untraceable is creating bad interrupts on
1299 * secondary quads ... for the moment, just leave the
1300 * ESR disabled - we can't do anything useful with the
1301 * errors anyway - mbligh
1303 pr_info("Leaving ESR disabled.\n");
1307 maxlvt = lapic_get_maxlvt();
1308 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1309 apic_write(APIC_ESR, 0);
1310 oldvalue = apic_read(APIC_ESR);
1312 /* enables sending errors */
1313 value = ERROR_APIC_VECTOR;
1314 apic_write(APIC_LVTERR, value);
1317 * spec says clear errors after enabling vector.
1320 apic_write(APIC_ESR, 0);
1321 value = apic_read(APIC_ESR);
1322 if (value != oldvalue)
1323 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1324 "vector: 0x%08x after: 0x%08x\n",
1329 * setup_local_APIC - setup the local APIC
1331 * Used to setup local APIC while initializing BSP or bringing up APs.
1332 * Always called with preemption disabled.
1334 void setup_local_APIC(void)
1336 int cpu = smp_processor_id();
1337 unsigned int value, queued;
1338 int i, j, acked = 0;
1339 unsigned long long tsc = 0, ntsc;
1340 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1342 if (boot_cpu_has(X86_FEATURE_TSC))
1346 disable_ioapic_support();
1350 #ifdef CONFIG_X86_32
1351 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1352 if (lapic_is_integrated() && apic->disable_esr) {
1353 apic_write(APIC_ESR, 0);
1354 apic_write(APIC_ESR, 0);
1355 apic_write(APIC_ESR, 0);
1356 apic_write(APIC_ESR, 0);
1359 perf_events_lapic_init();
1362 * Double-check whether this APIC is really registered.
1363 * This is meaningless in clustered apic mode, so we skip it.
1365 BUG_ON(!apic->apic_id_registered());
1368 * Intel recommends to set DFR, LDR and TPR before enabling
1369 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1370 * document number 292116). So here it goes...
1372 apic->init_apic_ldr();
1374 #ifdef CONFIG_X86_32
1376 * APIC LDR is initialized. If logical_apicid mapping was
1377 * initialized during get_smp_config(), make sure it matches the
1380 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1381 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1382 /* always use the value from LDR */
1383 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1384 logical_smp_processor_id();
1388 * Set Task Priority to 'accept all'. We never change this
1391 value = apic_read(APIC_TASKPRI);
1392 value &= ~APIC_TPRI_MASK;
1393 apic_write(APIC_TASKPRI, value);
1396 * After a crash, we no longer service the interrupts and a pending
1397 * interrupt from previous kernel might still have ISR bit set.
1399 * Most probably by now CPU has serviced that pending interrupt and
1400 * it might not have done the ack_APIC_irq() because it thought,
1401 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1402 * does not clear the ISR bit and cpu thinks it has already serivced
1403 * the interrupt. Hence a vector might get locked. It was noticed
1404 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1408 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1409 queued |= apic_read(APIC_IRR + i*0x10);
1411 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1412 value = apic_read(APIC_ISR + i*0x10);
1413 for (j = 31; j >= 0; j--) {
1414 if (value & (1<<j)) {
1421 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1426 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1428 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1432 } while (queued && max_loops > 0);
1433 WARN_ON(max_loops <= 0);
1436 * Now that we are all set up, enable the APIC
1438 value = apic_read(APIC_SPIV);
1439 value &= ~APIC_VECTOR_MASK;
1443 value |= APIC_SPIV_APIC_ENABLED;
1445 #ifdef CONFIG_X86_32
1447 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1448 * certain networking cards. If high frequency interrupts are
1449 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1450 * entry is masked/unmasked at a high rate as well then sooner or
1451 * later IOAPIC line gets 'stuck', no more interrupts are received
1452 * from the device. If focus CPU is disabled then the hang goes
1455 * [ This bug can be reproduced easily with a level-triggered
1456 * PCI Ne2000 networking cards and PII/PIII processors, dual
1460 * Actually disabling the focus CPU check just makes the hang less
1461 * frequent as it makes the interrupt distributon model be more
1462 * like LRU than MRU (the short-term load is more even across CPUs).
1466 * - enable focus processor (bit==0)
1467 * - 64bit mode always use processor focus
1468 * so no need to set it
1470 value &= ~APIC_SPIV_FOCUS_DISABLED;
1474 * Set spurious IRQ vector
1476 value |= SPURIOUS_APIC_VECTOR;
1477 apic_write(APIC_SPIV, value);
1480 * Set up LVT0, LVT1:
1482 * set up through-local-APIC on the BP's LINT0. This is not
1483 * strictly necessary in pure symmetric-IO mode, but sometimes
1484 * we delegate interrupts to the 8259A.
1487 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1489 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1490 if (!cpu && (pic_mode || !value)) {
1491 value = APIC_DM_EXTINT;
1492 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1494 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1495 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1497 apic_write(APIC_LVT0, value);
1500 * Only the BSP sees the LINT1 NMI signal by default. This can be
1501 * modified by apic_extnmi= boot option.
1503 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1504 apic_extnmi == APIC_EXTNMI_ALL)
1505 value = APIC_DM_NMI;
1507 value = APIC_DM_NMI | APIC_LVT_MASKED;
1508 if (!lapic_is_integrated()) /* 82489DX */
1509 value |= APIC_LVT_LEVEL_TRIGGER;
1510 apic_write(APIC_LVT1, value);
1512 #ifdef CONFIG_X86_MCE_INTEL
1513 /* Recheck CMCI information after local APIC is up on CPU #0 */
1519 static void end_local_APIC_setup(void)
1523 #ifdef CONFIG_X86_32
1526 /* Disable the local apic timer */
1527 value = apic_read(APIC_LVTT);
1528 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1529 apic_write(APIC_LVTT, value);
1537 * APIC setup function for application processors. Called from smpboot.c
1539 void apic_ap_setup(void)
1542 end_local_APIC_setup();
1545 #ifdef CONFIG_X86_X2APIC
1553 static int x2apic_state;
1555 static void __x2apic_disable(void)
1559 if (!boot_cpu_has(X86_FEATURE_APIC))
1562 rdmsrl(MSR_IA32_APICBASE, msr);
1563 if (!(msr & X2APIC_ENABLE))
1565 /* Disable xapic and x2apic first and then reenable xapic mode */
1566 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1567 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1568 printk_once(KERN_INFO "x2apic disabled\n");
1571 static void __x2apic_enable(void)
1575 rdmsrl(MSR_IA32_APICBASE, msr);
1576 if (msr & X2APIC_ENABLE)
1578 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1579 printk_once(KERN_INFO "x2apic enabled\n");
1582 static int __init setup_nox2apic(char *str)
1584 if (x2apic_enabled()) {
1585 int apicid = native_apic_msr_read(APIC_ID);
1587 if (apicid >= 255) {
1588 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1592 pr_warning("x2apic already enabled.\n");
1595 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1596 x2apic_state = X2APIC_DISABLED;
1600 early_param("nox2apic", setup_nox2apic);
1602 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1603 void x2apic_setup(void)
1606 * If x2apic is not in ON state, disable it if already enabled
1609 if (x2apic_state != X2APIC_ON) {
1616 static __init void x2apic_disable(void)
1618 u32 x2apic_id, state = x2apic_state;
1621 x2apic_state = X2APIC_DISABLED;
1623 if (state != X2APIC_ON)
1626 x2apic_id = read_apic_id();
1627 if (x2apic_id >= 255)
1628 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1631 register_lapic_address(mp_lapic_addr);
1634 static __init void x2apic_enable(void)
1636 if (x2apic_state != X2APIC_OFF)
1640 x2apic_state = X2APIC_ON;
1644 static __init void try_to_enable_x2apic(int remap_mode)
1646 if (x2apic_state == X2APIC_DISABLED)
1649 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1650 /* IR is required if there is APIC ID > 255 even when running
1653 if (max_physical_apicid > 255 ||
1654 !hypervisor_x2apic_available()) {
1655 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1661 * without IR all CPUs can be addressed by IOAPIC/MSI
1662 * only in physical mode
1669 void __init check_x2apic(void)
1671 if (x2apic_enabled()) {
1672 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1674 x2apic_state = X2APIC_ON;
1675 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1676 x2apic_state = X2APIC_DISABLED;
1679 #else /* CONFIG_X86_X2APIC */
1680 static int __init validate_x2apic(void)
1682 if (!apic_is_x2apic_enabled())
1685 * Checkme: Can we simply turn off x2apic here instead of panic?
1687 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1689 early_initcall(validate_x2apic);
1691 static inline void try_to_enable_x2apic(int remap_mode) { }
1692 static inline void __x2apic_enable(void) { }
1693 #endif /* !CONFIG_X86_X2APIC */
1695 void __init enable_IR_x2apic(void)
1697 unsigned long flags;
1700 if (skip_ioapic_setup) {
1701 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1705 ir_stat = irq_remapping_prepare();
1706 if (ir_stat < 0 && !x2apic_supported())
1709 ret = save_ioapic_entries();
1711 pr_info("Saving IO-APIC state failed: %d\n", ret);
1715 local_irq_save(flags);
1716 legacy_pic->mask_all();
1717 mask_ioapic_entries();
1719 /* If irq_remapping_prepare() succeeded, try to enable it */
1721 ir_stat = irq_remapping_enable();
1722 /* ir_stat contains the remap mode or an error code */
1723 try_to_enable_x2apic(ir_stat);
1726 restore_ioapic_entries();
1727 legacy_pic->restore_mask();
1728 local_irq_restore(flags);
1731 #ifdef CONFIG_X86_64
1733 * Detect and enable local APICs on non-SMP boards.
1734 * Original code written by Keir Fraser.
1735 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1736 * not correctly set up (usually the APIC timer won't work etc.)
1738 static int __init detect_init_APIC(void)
1740 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1741 pr_info("No local APIC present\n");
1745 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1750 static int __init apic_verify(void)
1755 * The APIC feature bit should now be enabled
1758 features = cpuid_edx(1);
1759 if (!(features & (1 << X86_FEATURE_APIC))) {
1760 pr_warning("Could not enable APIC!\n");
1763 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1764 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1766 /* The BIOS may have set up the APIC at some other address */
1767 if (boot_cpu_data.x86 >= 6) {
1768 rdmsr(MSR_IA32_APICBASE, l, h);
1769 if (l & MSR_IA32_APICBASE_ENABLE)
1770 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1773 pr_info("Found and enabled local APIC!\n");
1777 int __init apic_force_enable(unsigned long addr)
1785 * Some BIOSes disable the local APIC in the APIC_BASE
1786 * MSR. This can only be done in software for Intel P6 or later
1787 * and AMD K7 (Model > 1) or later.
1789 if (boot_cpu_data.x86 >= 6) {
1790 rdmsr(MSR_IA32_APICBASE, l, h);
1791 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1792 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1793 l &= ~MSR_IA32_APICBASE_BASE;
1794 l |= MSR_IA32_APICBASE_ENABLE | addr;
1795 wrmsr(MSR_IA32_APICBASE, l, h);
1796 enabled_via_apicbase = 1;
1799 return apic_verify();
1803 * Detect and initialize APIC
1805 static int __init detect_init_APIC(void)
1807 /* Disabled by kernel option? */
1811 switch (boot_cpu_data.x86_vendor) {
1812 case X86_VENDOR_AMD:
1813 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1814 (boot_cpu_data.x86 >= 15))
1817 case X86_VENDOR_INTEL:
1818 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1819 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1826 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1828 * Over-ride BIOS and try to enable the local APIC only if
1829 * "lapic" specified.
1831 if (!force_enable_local_apic) {
1832 pr_info("Local APIC disabled by BIOS -- "
1833 "you can enable it with \"lapic\"\n");
1836 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1848 pr_info("No local APIC present or hardware disabled\n");
1854 * init_apic_mappings - initialize APIC mappings
1856 void __init init_apic_mappings(void)
1858 unsigned int new_apicid;
1860 apic_check_deadline_errata();
1863 boot_cpu_physical_apicid = read_apic_id();
1867 /* If no local APIC can be found return early */
1868 if (!smp_found_config && detect_init_APIC()) {
1869 /* lets NOP'ify apic operations */
1870 pr_info("APIC: disable apic facility\n");
1873 apic_phys = mp_lapic_addr;
1876 * If the system has ACPI MADT tables or MP info, the LAPIC
1877 * address is already registered.
1879 if (!acpi_lapic && !smp_found_config)
1880 register_lapic_address(apic_phys);
1884 * Fetch the APIC ID of the BSP in case we have a
1885 * default configuration (or the MP table is broken).
1887 new_apicid = read_apic_id();
1888 if (boot_cpu_physical_apicid != new_apicid) {
1889 boot_cpu_physical_apicid = new_apicid;
1891 * yeah -- we lie about apic_version
1892 * in case if apic was disabled via boot option
1893 * but it's not a problem for SMP compiled kernel
1894 * since smp_sanity_check is prepared for such a case
1895 * and disable smp mode
1897 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1901 void __init register_lapic_address(unsigned long address)
1903 mp_lapic_addr = address;
1906 set_fixmap_nocache(FIX_APIC_BASE, address);
1907 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1908 APIC_BASE, address);
1910 if (boot_cpu_physical_apicid == -1U) {
1911 boot_cpu_physical_apicid = read_apic_id();
1912 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1917 * Local APIC interrupts
1921 * This interrupt should _never_ happen with our APIC/SMP architecture
1923 static void __smp_spurious_interrupt(u8 vector)
1928 * Check if this really is a spurious interrupt and ACK it
1929 * if it is a vectored one. Just in case...
1930 * Spurious interrupts should not be ACKed.
1932 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1933 if (v & (1 << (vector & 0x1f)))
1936 inc_irq_stat(irq_spurious_count);
1938 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1939 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1940 "should never happen.\n", vector, smp_processor_id());
1943 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1946 __smp_spurious_interrupt(~regs->orig_ax);
1950 __visible void __irq_entry smp_trace_spurious_interrupt(struct pt_regs *regs)
1952 u8 vector = ~regs->orig_ax;
1955 trace_spurious_apic_entry(vector);
1956 __smp_spurious_interrupt(vector);
1957 trace_spurious_apic_exit(vector);
1962 * This interrupt should never happen with our APIC/SMP architecture
1964 static void __smp_error_interrupt(struct pt_regs *regs)
1968 static const char * const error_interrupt_reason[] = {
1969 "Send CS error", /* APIC Error Bit 0 */
1970 "Receive CS error", /* APIC Error Bit 1 */
1971 "Send accept error", /* APIC Error Bit 2 */
1972 "Receive accept error", /* APIC Error Bit 3 */
1973 "Redirectable IPI", /* APIC Error Bit 4 */
1974 "Send illegal vector", /* APIC Error Bit 5 */
1975 "Received illegal vector", /* APIC Error Bit 6 */
1976 "Illegal register address", /* APIC Error Bit 7 */
1979 /* First tickle the hardware, only then report what went on. -- REW */
1980 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1981 apic_write(APIC_ESR, 0);
1982 v = apic_read(APIC_ESR);
1984 atomic_inc(&irq_err_count);
1986 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1987 smp_processor_id(), v);
1992 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1997 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2001 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2004 __smp_error_interrupt(regs);
2008 __visible void __irq_entry smp_trace_error_interrupt(struct pt_regs *regs)
2011 trace_error_apic_entry(ERROR_APIC_VECTOR);
2012 __smp_error_interrupt(regs);
2013 trace_error_apic_exit(ERROR_APIC_VECTOR);
2018 * connect_bsp_APIC - attach the APIC to the interrupt system
2020 static void __init connect_bsp_APIC(void)
2022 #ifdef CONFIG_X86_32
2025 * Do not trust the local APIC being empty at bootup.
2029 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2030 * local APIC to INT and NMI lines.
2032 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2033 "enabling APIC mode.\n");
2040 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2041 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2043 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2046 void disconnect_bsp_APIC(int virt_wire_setup)
2050 #ifdef CONFIG_X86_32
2053 * Put the board back into PIC mode (has an effect only on
2054 * certain older boards). Note that APIC interrupts, including
2055 * IPIs, won't work beyond this point! The only exception are
2058 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2059 "entering PIC mode.\n");
2065 /* Go back to Virtual Wire compatibility mode */
2067 /* For the spurious interrupt use vector F, and enable it */
2068 value = apic_read(APIC_SPIV);
2069 value &= ~APIC_VECTOR_MASK;
2070 value |= APIC_SPIV_APIC_ENABLED;
2072 apic_write(APIC_SPIV, value);
2074 if (!virt_wire_setup) {
2076 * For LVT0 make it edge triggered, active high,
2077 * external and enabled
2079 value = apic_read(APIC_LVT0);
2080 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2081 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2082 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2083 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2084 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2085 apic_write(APIC_LVT0, value);
2088 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2092 * For LVT1 make it edge triggered, active high,
2095 value = apic_read(APIC_LVT1);
2096 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2097 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2098 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2099 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2100 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2101 apic_write(APIC_LVT1, value);
2105 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2106 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2107 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2108 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2110 * NOTE: Reserve 0 for BSP.
2112 static int nr_logical_cpuids = 1;
2115 * Used to store mapping between logical CPU IDs and APIC IDs.
2117 static int cpuid_to_apicid[] = {
2118 [0 ... NR_CPUS - 1] = -1,
2122 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2123 * and cpuid_to_apicid[] synchronized.
2125 static int allocate_logical_cpuid(int apicid)
2130 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2131 * check if the kernel has allocated a cpuid for it.
2133 for (i = 0; i < nr_logical_cpuids; i++) {
2134 if (cpuid_to_apicid[i] == apicid)
2138 /* Allocate a new cpuid. */
2139 if (nr_logical_cpuids >= nr_cpu_ids) {
2140 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %i reached. "
2141 "Processor %d/0x%x and the rest are ignored.\n",
2142 nr_cpu_ids, nr_logical_cpuids, apicid);
2146 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2147 return nr_logical_cpuids++;
2150 int generic_processor_info(int apicid, int version)
2152 int cpu, max = nr_cpu_ids;
2153 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2154 phys_cpu_present_map);
2157 * boot_cpu_physical_apicid is designed to have the apicid
2158 * returned by read_apic_id(), i.e, the apicid of the
2159 * currently booting-up processor. However, on some platforms,
2160 * it is temporarily modified by the apicid reported as BSP
2161 * through MP table. Concretely:
2163 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2164 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2166 * This function is executed with the modified
2167 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2168 * parameter doesn't work to disable APs on kdump 2nd kernel.
2170 * Since fixing handling of boot_cpu_physical_apicid requires
2171 * another discussion and tests on each platform, we leave it
2172 * for now and here we use read_apic_id() directly in this
2173 * function, __generic_processor_info().
2175 if (disabled_cpu_apicid != BAD_APICID &&
2176 disabled_cpu_apicid != read_apic_id() &&
2177 disabled_cpu_apicid == apicid) {
2178 int thiscpu = num_processors + disabled_cpus;
2180 pr_warning("APIC: Disabling requested cpu."
2181 " Processor %d/0x%x ignored.\n",
2189 * If boot cpu has not been detected yet, then only allow upto
2190 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2192 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2193 apicid != boot_cpu_physical_apicid) {
2194 int thiscpu = max + disabled_cpus - 1;
2197 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2198 " reached. Keeping one slot for boot cpu."
2199 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2205 if (num_processors >= nr_cpu_ids) {
2206 int thiscpu = max + disabled_cpus;
2208 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2209 "reached. Processor %d/0x%x ignored.\n",
2210 max, thiscpu, apicid);
2216 if (apicid == boot_cpu_physical_apicid) {
2218 * x86_bios_cpu_apicid is required to have processors listed
2219 * in same order as logical cpu numbers. Hence the first
2220 * entry is BSP, and so on.
2221 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2226 /* Logical cpuid 0 is reserved for BSP. */
2227 cpuid_to_apicid[0] = apicid;
2229 cpu = allocate_logical_cpuid(apicid);
2239 if (version == 0x0) {
2240 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2245 if (version != boot_cpu_apic_version) {
2246 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2247 boot_cpu_apic_version, cpu, version);
2250 if (apicid > max_physical_apicid)
2251 max_physical_apicid = apicid;
2253 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2254 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2255 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2257 #ifdef CONFIG_X86_32
2258 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2259 apic->x86_32_early_logical_apicid(cpu);
2261 set_cpu_possible(cpu, true);
2262 physid_set(apicid, phys_cpu_present_map);
2263 set_cpu_present(cpu, true);
2269 int hard_smp_processor_id(void)
2271 return read_apic_id();
2274 void default_init_apic_ldr(void)
2278 apic_write(APIC_DFR, APIC_DFR_VALUE);
2279 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2280 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2281 apic_write(APIC_LDR, val);
2284 int default_cpu_mask_to_apicid(const struct cpumask *mask,
2285 struct irq_data *irqdata,
2286 unsigned int *apicid)
2288 unsigned int cpu = cpumask_first(mask);
2290 if (cpu >= nr_cpu_ids)
2292 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2293 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2297 int flat_cpu_mask_to_apicid(const struct cpumask *mask,
2298 struct irq_data *irqdata,
2299 unsigned int *apicid)
2302 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2303 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2307 *apicid = (unsigned int)cpu_mask;
2308 cpumask_bits(effmsk)[0] = cpu_mask;
2313 * Override the generic EOI implementation with an optimized version.
2314 * Only called during early boot when only one CPU is active and with
2315 * interrupts disabled, so we know this does not race with actual APIC driver
2318 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2322 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2323 /* Should happen once for each apic */
2324 WARN_ON((*drv)->eoi_write == eoi_write);
2325 (*drv)->native_eoi_write = (*drv)->eoi_write;
2326 (*drv)->eoi_write = eoi_write;
2330 static void __init apic_bsp_up_setup(void)
2332 #ifdef CONFIG_X86_64
2333 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2336 * Hack: In case of kdump, after a crash, kernel might be booting
2337 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2338 * might be zero if read from MP tables. Get it from LAPIC.
2340 # ifdef CONFIG_CRASH_DUMP
2341 boot_cpu_physical_apicid = read_apic_id();
2344 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2348 * apic_bsp_setup - Setup function for local apic and io-apic
2349 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2352 * apic_id of BSP APIC
2354 int __init apic_bsp_setup(bool upmode)
2360 apic_bsp_up_setup();
2364 id = apic_read(APIC_LDR);
2366 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2369 end_local_APIC_setup();
2370 irq_remap_enable_fault_handling();
2372 /* Setup local timer */
2373 x86_init.timers.setup_percpu_clockev();
2378 * This initializes the IO-APIC and APIC hardware if this is
2381 int __init APIC_init_uniprocessor(void)
2384 pr_info("Apic disabled\n");
2387 #ifdef CONFIG_X86_64
2388 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2390 pr_info("Apic disabled by BIOS\n");
2394 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2398 * Complain if the BIOS pretends there is one.
2400 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2401 APIC_INTEGRATED(boot_cpu_apic_version)) {
2402 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2403 boot_cpu_physical_apicid);
2408 if (!smp_found_config)
2409 disable_ioapic_support();
2411 default_setup_apic_routing();
2412 apic_bsp_setup(true);
2416 #ifdef CONFIG_UP_LATE_INIT
2417 void __init up_late_init(void)
2419 APIC_init_uniprocessor();
2430 * 'active' is true if the local APIC was enabled by us and
2431 * not the BIOS; this signifies that we are also responsible
2432 * for disabling it before entering apm/acpi suspend
2435 /* r/w apic fields */
2436 unsigned int apic_id;
2437 unsigned int apic_taskpri;
2438 unsigned int apic_ldr;
2439 unsigned int apic_dfr;
2440 unsigned int apic_spiv;
2441 unsigned int apic_lvtt;
2442 unsigned int apic_lvtpc;
2443 unsigned int apic_lvt0;
2444 unsigned int apic_lvt1;
2445 unsigned int apic_lvterr;
2446 unsigned int apic_tmict;
2447 unsigned int apic_tdcr;
2448 unsigned int apic_thmr;
2449 unsigned int apic_cmci;
2452 static int lapic_suspend(void)
2454 unsigned long flags;
2457 if (!apic_pm_state.active)
2460 maxlvt = lapic_get_maxlvt();
2462 apic_pm_state.apic_id = apic_read(APIC_ID);
2463 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2464 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2465 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2466 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2467 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2469 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2470 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2471 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2472 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2473 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2474 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2475 #ifdef CONFIG_X86_THERMAL_VECTOR
2477 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2479 #ifdef CONFIG_X86_MCE_INTEL
2481 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2484 local_irq_save(flags);
2485 disable_local_APIC();
2487 irq_remapping_disable();
2489 local_irq_restore(flags);
2493 static void lapic_resume(void)
2496 unsigned long flags;
2499 if (!apic_pm_state.active)
2502 local_irq_save(flags);
2505 * IO-APIC and PIC have their own resume routines.
2506 * We just mask them here to make sure the interrupt
2507 * subsystem is completely quiet while we enable x2apic
2508 * and interrupt-remapping.
2510 mask_ioapic_entries();
2511 legacy_pic->mask_all();
2517 * Make sure the APICBASE points to the right address
2519 * FIXME! This will be wrong if we ever support suspend on
2520 * SMP! We'll need to do this as part of the CPU restore!
2522 if (boot_cpu_data.x86 >= 6) {
2523 rdmsr(MSR_IA32_APICBASE, l, h);
2524 l &= ~MSR_IA32_APICBASE_BASE;
2525 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2526 wrmsr(MSR_IA32_APICBASE, l, h);
2530 maxlvt = lapic_get_maxlvt();
2531 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2532 apic_write(APIC_ID, apic_pm_state.apic_id);
2533 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2534 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2535 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2536 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2537 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2538 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2539 #ifdef CONFIG_X86_THERMAL_VECTOR
2541 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2543 #ifdef CONFIG_X86_MCE_INTEL
2545 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2548 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2549 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2550 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2551 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2552 apic_write(APIC_ESR, 0);
2553 apic_read(APIC_ESR);
2554 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2555 apic_write(APIC_ESR, 0);
2556 apic_read(APIC_ESR);
2558 irq_remapping_reenable(x2apic_mode);
2560 local_irq_restore(flags);
2564 * This device has no shutdown method - fully functioning local APICs
2565 * are needed on every CPU up until machine_halt/restart/poweroff.
2568 static struct syscore_ops lapic_syscore_ops = {
2569 .resume = lapic_resume,
2570 .suspend = lapic_suspend,
2573 static void apic_pm_activate(void)
2575 apic_pm_state.active = 1;
2578 static int __init init_lapic_sysfs(void)
2580 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2581 if (boot_cpu_has(X86_FEATURE_APIC))
2582 register_syscore_ops(&lapic_syscore_ops);
2587 /* local apic needs to resume before other devices access its registers. */
2588 core_initcall(init_lapic_sysfs);
2590 #else /* CONFIG_PM */
2592 static void apic_pm_activate(void) { }
2594 #endif /* CONFIG_PM */
2596 #ifdef CONFIG_X86_64
2598 static int multi_checked;
2601 static int set_multi(const struct dmi_system_id *d)
2605 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2610 static const struct dmi_system_id multi_dmi_table[] = {
2612 .callback = set_multi,
2613 .ident = "IBM System Summit2",
2615 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2616 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2622 static void dmi_check_multi(void)
2627 dmi_check_system(multi_dmi_table);
2632 * apic_is_clustered_box() -- Check if we can expect good TSC
2634 * Thus far, the major user of this is IBM's Summit2 series:
2635 * Clustered boxes may have unsynced TSC problems if they are
2637 * Use DMI to check them
2639 int apic_is_clustered_box(void)
2647 * APIC command line parameters
2649 static int __init setup_disableapic(char *arg)
2652 setup_clear_cpu_cap(X86_FEATURE_APIC);
2655 early_param("disableapic", setup_disableapic);
2657 /* same as disableapic, for compatibility */
2658 static int __init setup_nolapic(char *arg)
2660 return setup_disableapic(arg);
2662 early_param("nolapic", setup_nolapic);
2664 static int __init parse_lapic_timer_c2_ok(char *arg)
2666 local_apic_timer_c2_ok = 1;
2669 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2671 static int __init parse_disable_apic_timer(char *arg)
2673 disable_apic_timer = 1;
2676 early_param("noapictimer", parse_disable_apic_timer);
2678 static int __init parse_nolapic_timer(char *arg)
2680 disable_apic_timer = 1;
2683 early_param("nolapic_timer", parse_nolapic_timer);
2685 static int __init apic_set_verbosity(char *arg)
2688 #ifdef CONFIG_X86_64
2689 skip_ioapic_setup = 0;
2695 if (strcmp("debug", arg) == 0)
2696 apic_verbosity = APIC_DEBUG;
2697 else if (strcmp("verbose", arg) == 0)
2698 apic_verbosity = APIC_VERBOSE;
2700 pr_warning("APIC Verbosity level %s not recognised"
2701 " use apic=verbose or apic=debug\n", arg);
2707 early_param("apic", apic_set_verbosity);
2709 static int __init lapic_insert_resource(void)
2714 /* Put local APIC into the resource map. */
2715 lapic_resource.start = apic_phys;
2716 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2717 insert_resource(&iomem_resource, &lapic_resource);
2723 * need call insert after e820__reserve_resources()
2724 * that is using request_resource
2726 late_initcall(lapic_insert_resource);
2728 static int __init apic_set_disabled_cpu_apicid(char *arg)
2730 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2735 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2737 static int __init apic_set_extnmi(char *arg)
2742 if (!strncmp("all", arg, 3))
2743 apic_extnmi = APIC_EXTNMI_ALL;
2744 else if (!strncmp("none", arg, 4))
2745 apic_extnmi = APIC_EXTNMI_NONE;
2746 else if (!strncmp("bsp", arg, 3))
2747 apic_extnmi = APIC_EXTNMI_BSP;
2749 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2755 early_param("apic_extnmi", apic_set_extnmi);