2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
22 * Historical information which is worth to be preserved:
26 * We used to have a workaround for a bug in SiS chips which
27 * required to rewrite the index register for a read-modify-write
28 * operation as the chip lost the index information which was
29 * setup for the read already. We cache the data now, so that
30 * workaround has been removed.
34 #include <linux/interrupt.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/sched.h>
38 #include <linux/pci.h>
39 #include <linux/mc146818rtc.h>
40 #include <linux/compiler.h>
41 #include <linux/acpi.h>
42 #include <linux/export.h>
43 #include <linux/syscore_ops.h>
44 #include <linux/freezer.h>
45 #include <linux/kthread.h>
46 #include <linux/jiffies.h> /* time_after() */
47 #include <linux/slab.h>
48 #include <linux/bootmem.h>
50 #include <asm/irqdomain.h>
55 #include <asm/proto.h>
58 #include <asm/timer.h>
59 #include <asm/i8259.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define for_each_ioapic(idx) \
67 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
68 #define for_each_ioapic_reverse(idx) \
69 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
70 #define for_each_pin(idx, pin) \
71 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
72 #define for_each_ioapic_pin(idx, pin) \
73 for_each_ioapic((idx)) \
74 for_each_pin((idx), (pin))
75 #define for_each_irq_pin(entry, head) \
76 list_for_each_entry(entry, &head, list)
78 static DEFINE_RAW_SPINLOCK(ioapic_lock);
79 static DEFINE_MUTEX(ioapic_mutex);
80 static unsigned int ioapic_dynirq_base;
81 static int ioapic_initialized;
84 struct list_head list;
89 struct list_head irq_2_pin;
90 struct IO_APIC_route_entry entry;
97 struct mp_ioapic_gsi {
102 static struct ioapic {
104 * # of IRQ routing registers
108 * Saved state during suspend/resume, or while enabling intr-remap.
110 struct IO_APIC_route_entry *saved_registers;
111 /* I/O APIC config */
112 struct mpc_ioapic mp_config;
113 /* IO APIC gsi routing info */
114 struct mp_ioapic_gsi gsi_config;
115 struct ioapic_domain_cfg irqdomain_cfg;
116 struct irq_domain *irqdomain;
117 struct resource *iomem_res;
118 } ioapics[MAX_IO_APICS];
120 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
122 int mpc_ioapic_id(int ioapic_idx)
124 return ioapics[ioapic_idx].mp_config.apicid;
127 unsigned int mpc_ioapic_addr(int ioapic_idx)
129 return ioapics[ioapic_idx].mp_config.apicaddr;
132 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134 return &ioapics[ioapic_idx].gsi_config;
137 static inline int mp_ioapic_pin_count(int ioapic)
139 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
144 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
149 static inline bool mp_is_legacy_irq(int irq)
151 return irq >= 0 && irq < nr_legacy_irqs();
155 * Initialize all legacy IRQs and all pins on the first IOAPIC
156 * if we have legacy interrupt controller. Kernel boot option "pirq="
157 * may rely on non-legacy pins on the first IOAPIC.
159 static inline int mp_init_irq_at_boot(int ioapic, int irq)
161 if (!nr_legacy_irqs())
164 return ioapic == 0 || mp_is_legacy_irq(irq);
167 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
169 return ioapics[ioapic].irqdomain;
174 /* The one past the highest gsi number used */
177 /* MP IRQ source entries */
178 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
180 /* # of MP IRQ source entries */
184 int mp_bus_id_to_type[MAX_MP_BUSSES];
187 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
189 int skip_ioapic_setup;
192 * disable_ioapic_support() - disables ioapic support at runtime
194 void disable_ioapic_support(void)
198 noioapicreroute = -1;
200 skip_ioapic_setup = 1;
203 static int __init parse_noapic(char *str)
205 /* disable IO-APIC */
206 disable_ioapic_support();
209 early_param("noapic", parse_noapic);
211 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
212 void mp_save_irq(struct mpc_intsrc *m)
216 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
217 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
218 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
219 m->srcbusirq, m->dstapic, m->dstirq);
221 for (i = 0; i < mp_irq_entries; i++) {
222 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
226 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
227 if (++mp_irq_entries == MAX_IRQ_SOURCES)
228 panic("Max # of irq sources exceeded!!\n");
231 static void alloc_ioapic_saved_registers(int idx)
235 if (ioapics[idx].saved_registers)
238 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
239 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
240 if (!ioapics[idx].saved_registers)
241 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
244 static void free_ioapic_saved_registers(int idx)
246 kfree(ioapics[idx].saved_registers);
247 ioapics[idx].saved_registers = NULL;
250 int __init arch_early_ioapic_init(void)
254 if (!nr_legacy_irqs())
258 alloc_ioapic_saved_registers(i);
265 unsigned int unused[3];
267 unsigned int unused2[11];
271 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
273 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
274 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
277 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
279 struct io_apic __iomem *io_apic = io_apic_base(apic);
280 writel(vector, &io_apic->eoi);
283 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
285 struct io_apic __iomem *io_apic = io_apic_base(apic);
286 writel(reg, &io_apic->index);
287 return readl(&io_apic->data);
290 static void io_apic_write(unsigned int apic, unsigned int reg,
293 struct io_apic __iomem *io_apic = io_apic_base(apic);
295 writel(reg, &io_apic->index);
296 writel(value, &io_apic->data);
300 struct { u32 w1, w2; };
301 struct IO_APIC_route_entry entry;
304 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
306 union entry_union eu;
308 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
309 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
314 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
316 union entry_union eu;
319 raw_spin_lock_irqsave(&ioapic_lock, flags);
320 eu.entry = __ioapic_read_entry(apic, pin);
321 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
327 * When we write a new IO APIC routing entry, we need to write the high
328 * word first! If the mask bit in the low word is clear, we will enable
329 * the interrupt, and we need to make sure the entry is fully populated
330 * before that happens.
332 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
334 union entry_union eu = {{0, 0}};
337 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
338 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
341 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
345 raw_spin_lock_irqsave(&ioapic_lock, flags);
346 __ioapic_write_entry(apic, pin, e);
347 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
351 * When we mask an IO APIC routing entry, we need to write the low
352 * word first, in order to set the mask bit before we change the
355 static void ioapic_mask_entry(int apic, int pin)
358 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
360 raw_spin_lock_irqsave(&ioapic_lock, flags);
361 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
362 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
363 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
367 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
368 * shared ISA-space IRQs, so we have to support them. We are super
369 * fast in the common case, and fast for shared ISA-space IRQs.
371 static int __add_pin_to_irq_node(struct mp_chip_data *data,
372 int node, int apic, int pin)
374 struct irq_pin_list *entry;
376 /* don't allow duplicates */
377 for_each_irq_pin(entry, data->irq_2_pin)
378 if (entry->apic == apic && entry->pin == pin)
381 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
383 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
389 list_add_tail(&entry->list, &data->irq_2_pin);
394 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
396 struct irq_pin_list *tmp, *entry;
398 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
399 if (entry->apic == apic && entry->pin == pin) {
400 list_del(&entry->list);
406 static void add_pin_to_irq_node(struct mp_chip_data *data,
407 int node, int apic, int pin)
409 if (__add_pin_to_irq_node(data, node, apic, pin))
410 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
414 * Reroute an IRQ to a different pin.
416 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
417 int oldapic, int oldpin,
418 int newapic, int newpin)
420 struct irq_pin_list *entry;
422 for_each_irq_pin(entry, data->irq_2_pin) {
423 if (entry->apic == oldapic && entry->pin == oldpin) {
424 entry->apic = newapic;
426 /* every one is different, right? */
431 /* old apic/pin didn't exist, so just add new ones */
432 add_pin_to_irq_node(data, node, newapic, newpin);
435 static void io_apic_modify_irq(struct mp_chip_data *data,
436 int mask_and, int mask_or,
437 void (*final)(struct irq_pin_list *entry))
439 union entry_union eu;
440 struct irq_pin_list *entry;
442 eu.entry = data->entry;
445 data->entry = eu.entry;
447 for_each_irq_pin(entry, data->irq_2_pin) {
448 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
454 static void io_apic_sync(struct irq_pin_list *entry)
457 * Synchronize the IO-APIC and the CPU by doing
458 * a dummy read from the IO-APIC
460 struct io_apic __iomem *io_apic;
462 io_apic = io_apic_base(entry->apic);
463 readl(&io_apic->data);
466 static void mask_ioapic_irq(struct irq_data *irq_data)
468 struct mp_chip_data *data = irq_data->chip_data;
471 raw_spin_lock_irqsave(&ioapic_lock, flags);
472 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
473 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
476 static void __unmask_ioapic(struct mp_chip_data *data)
478 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
481 static void unmask_ioapic_irq(struct irq_data *irq_data)
483 struct mp_chip_data *data = irq_data->chip_data;
486 raw_spin_lock_irqsave(&ioapic_lock, flags);
487 __unmask_ioapic(data);
488 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
492 * IO-APIC versions below 0x20 don't support EOI register.
493 * For the record, here is the information about various versions:
495 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
496 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
499 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
500 * version as 0x2. This is an error with documentation and these ICH chips
501 * use io-apic's of version 0x20.
503 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
504 * Otherwise, we simulate the EOI message manually by changing the trigger
505 * mode to edge and then back to level, with RTE being masked during this.
507 static void __eoi_ioapic_pin(int apic, int pin, int vector)
509 if (mpc_ioapic_ver(apic) >= 0x20) {
510 io_apic_eoi(apic, vector);
512 struct IO_APIC_route_entry entry, entry1;
514 entry = entry1 = __ioapic_read_entry(apic, pin);
517 * Mask the entry and change the trigger mode to edge.
519 entry1.mask = IOAPIC_MASKED;
520 entry1.trigger = IOAPIC_EDGE;
522 __ioapic_write_entry(apic, pin, entry1);
525 * Restore the previous level triggered entry.
527 __ioapic_write_entry(apic, pin, entry);
531 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
534 struct irq_pin_list *entry;
536 raw_spin_lock_irqsave(&ioapic_lock, flags);
537 for_each_irq_pin(entry, data->irq_2_pin)
538 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
539 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
542 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
544 struct IO_APIC_route_entry entry;
546 /* Check delivery_mode to be sure we're not clearing an SMI pin */
547 entry = ioapic_read_entry(apic, pin);
548 if (entry.delivery_mode == dest_SMI)
552 * Make sure the entry is masked and re-read the contents to check
553 * if it is a level triggered pin and if the remote-IRR is set.
555 if (entry.mask == IOAPIC_UNMASKED) {
556 entry.mask = IOAPIC_MASKED;
557 ioapic_write_entry(apic, pin, entry);
558 entry = ioapic_read_entry(apic, pin);
565 * Make sure the trigger mode is set to level. Explicit EOI
566 * doesn't clear the remote-IRR if the trigger mode is not
569 if (entry.trigger == IOAPIC_EDGE) {
570 entry.trigger = IOAPIC_LEVEL;
571 ioapic_write_entry(apic, pin, entry);
573 raw_spin_lock_irqsave(&ioapic_lock, flags);
574 __eoi_ioapic_pin(apic, pin, entry.vector);
575 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
579 * Clear the rest of the bits in the IO-APIC RTE except for the mask
582 ioapic_mask_entry(apic, pin);
583 entry = ioapic_read_entry(apic, pin);
585 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
586 mpc_ioapic_id(apic), pin);
589 static void clear_IO_APIC (void)
593 for_each_ioapic_pin(apic, pin)
594 clear_IO_APIC_pin(apic, pin);
599 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
600 * specific CPU-side IRQs.
604 static int pirq_entries[MAX_PIRQS] = {
605 [0 ... MAX_PIRQS - 1] = -1
608 static int __init ioapic_pirq_setup(char *str)
611 int ints[MAX_PIRQS+1];
613 get_options(str, ARRAY_SIZE(ints), ints);
615 apic_printk(APIC_VERBOSE, KERN_INFO
616 "PIRQ redirection, working around broken MP-BIOS.\n");
618 if (ints[0] < MAX_PIRQS)
621 for (i = 0; i < max; i++) {
622 apic_printk(APIC_VERBOSE, KERN_DEBUG
623 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
625 * PIRQs are mapped upside down, usually.
627 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
632 __setup("pirq=", ioapic_pirq_setup);
633 #endif /* CONFIG_X86_32 */
636 * Saves all the IO-APIC RTE's
638 int save_ioapic_entries(void)
643 for_each_ioapic(apic) {
644 if (!ioapics[apic].saved_registers) {
649 for_each_pin(apic, pin)
650 ioapics[apic].saved_registers[pin] =
651 ioapic_read_entry(apic, pin);
658 * Mask all IO APIC entries.
660 void mask_ioapic_entries(void)
664 for_each_ioapic(apic) {
665 if (!ioapics[apic].saved_registers)
668 for_each_pin(apic, pin) {
669 struct IO_APIC_route_entry entry;
671 entry = ioapics[apic].saved_registers[pin];
672 if (entry.mask == IOAPIC_UNMASKED) {
673 entry.mask = IOAPIC_MASKED;
674 ioapic_write_entry(apic, pin, entry);
681 * Restore IO APIC entries which was saved in the ioapic structure.
683 int restore_ioapic_entries(void)
687 for_each_ioapic(apic) {
688 if (!ioapics[apic].saved_registers)
691 for_each_pin(apic, pin)
692 ioapic_write_entry(apic, pin,
693 ioapics[apic].saved_registers[pin]);
699 * Find the IRQ entry number of a certain pin.
701 static int find_irq_entry(int ioapic_idx, int pin, int type)
705 for (i = 0; i < mp_irq_entries; i++)
706 if (mp_irqs[i].irqtype == type &&
707 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
708 mp_irqs[i].dstapic == MP_APIC_ALL) &&
709 mp_irqs[i].dstirq == pin)
716 * Find the pin to which IRQ[irq] (ISA) is connected
718 static int __init find_isa_irq_pin(int irq, int type)
722 for (i = 0; i < mp_irq_entries; i++) {
723 int lbus = mp_irqs[i].srcbus;
725 if (test_bit(lbus, mp_bus_not_pci) &&
726 (mp_irqs[i].irqtype == type) &&
727 (mp_irqs[i].srcbusirq == irq))
729 return mp_irqs[i].dstirq;
734 static int __init find_isa_irq_apic(int irq, int type)
738 for (i = 0; i < mp_irq_entries; i++) {
739 int lbus = mp_irqs[i].srcbus;
741 if (test_bit(lbus, mp_bus_not_pci) &&
742 (mp_irqs[i].irqtype == type) &&
743 (mp_irqs[i].srcbusirq == irq))
747 if (i < mp_irq_entries) {
750 for_each_ioapic(ioapic_idx)
751 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
760 * EISA Edge/Level control register, ELCR
762 static int EISA_ELCR(unsigned int irq)
764 if (irq < nr_legacy_irqs()) {
765 unsigned int port = 0x4d0 + (irq >> 3);
766 return (inb(port) >> (irq & 7)) & 1;
768 apic_printk(APIC_VERBOSE, KERN_INFO
769 "Broken MPtable reports ISA irq %d\n", irq);
775 /* ISA interrupts are always active high edge triggered,
776 * when listed as conforming in the MP table. */
778 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
779 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
781 /* EISA interrupts are always polarity zero and can be edge or level
782 * trigger depending on the ELCR value. If an interrupt is listed as
783 * EISA conforming in the MP table, that means its trigger type must
784 * be read in from the ELCR */
786 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
787 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
789 /* PCI interrupts are always active low level triggered,
790 * when listed as conforming in the MP table. */
792 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
793 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
795 static int irq_polarity(int idx)
797 int bus = mp_irqs[idx].srcbus;
800 * Determine IRQ line polarity (high active or low active):
802 switch (mp_irqs[idx].irqflag & 0x03) {
804 /* conforms to spec, ie. bus-type dependent polarity */
805 if (test_bit(bus, mp_bus_not_pci))
806 return default_ISA_polarity(idx);
808 return default_PCI_polarity(idx);
810 return IOAPIC_POL_HIGH;
812 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
814 default: /* Pointless default required due to do gcc stupidity */
815 return IOAPIC_POL_LOW;
820 static int eisa_irq_trigger(int idx, int bus, int trigger)
822 switch (mp_bus_id_to_type[bus]) {
827 return default_EISA_trigger(idx);
829 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
833 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
839 static int irq_trigger(int idx)
841 int bus = mp_irqs[idx].srcbus;
845 * Determine IRQ trigger mode (edge or level sensitive):
847 switch ((mp_irqs[idx].irqflag >> 2) & 0x03) {
849 /* conforms to spec, ie. bus-type dependent trigger mode */
850 if (test_bit(bus, mp_bus_not_pci))
851 trigger = default_ISA_trigger(idx);
853 trigger = default_PCI_trigger(idx);
854 /* Take EISA into account */
855 return eisa_irq_trigger(idx, bus, trigger);
859 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
861 default: /* Pointless default required due to do gcc stupidity */
866 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
867 int trigger, int polarity)
869 init_irq_alloc_info(info, NULL);
870 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
871 info->ioapic_node = node;
872 info->ioapic_trigger = trigger;
873 info->ioapic_polarity = polarity;
874 info->ioapic_valid = 1;
878 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
881 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
882 struct irq_alloc_info *src,
883 u32 gsi, int ioapic_idx, int pin)
885 int trigger, polarity;
887 copy_irq_alloc_info(dst, src);
888 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
889 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
890 dst->ioapic_pin = pin;
891 dst->ioapic_valid = 1;
892 if (src && src->ioapic_valid) {
893 dst->ioapic_node = src->ioapic_node;
894 dst->ioapic_trigger = src->ioapic_trigger;
895 dst->ioapic_polarity = src->ioapic_polarity;
897 dst->ioapic_node = NUMA_NO_NODE;
898 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
899 dst->ioapic_trigger = trigger;
900 dst->ioapic_polarity = polarity;
903 * PCI interrupts are always active low level
906 dst->ioapic_trigger = IOAPIC_LEVEL;
907 dst->ioapic_polarity = IOAPIC_POL_LOW;
912 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
914 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
917 static void mp_register_handler(unsigned int irq, unsigned long trigger)
919 irq_flow_handler_t hdl;
923 irq_set_status_flags(irq, IRQ_LEVEL);
926 irq_clear_status_flags(irq, IRQ_LEVEL);
930 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
931 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
934 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
936 struct mp_chip_data *data = irq_get_chip_data(irq);
939 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
940 * and polarity attirbutes. So allow the first user to reprogram the
941 * pin with real trigger and polarity attributes.
943 if (irq < nr_legacy_irqs() && data->count == 1) {
944 if (info->ioapic_trigger != data->trigger)
945 mp_register_handler(irq, info->ioapic_trigger);
946 data->entry.trigger = data->trigger = info->ioapic_trigger;
947 data->entry.polarity = data->polarity = info->ioapic_polarity;
950 return data->trigger == info->ioapic_trigger &&
951 data->polarity == info->ioapic_polarity;
954 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
955 struct irq_alloc_info *info)
959 int type = ioapics[ioapic].irqdomain_cfg.type;
962 case IOAPIC_DOMAIN_LEGACY:
964 * Dynamically allocate IRQ number for non-ISA IRQs in the first
965 * 16 GSIs on some weird platforms.
967 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
969 legacy = mp_is_legacy_irq(irq);
971 case IOAPIC_DOMAIN_STRICT:
974 case IOAPIC_DOMAIN_DYNAMIC:
977 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
981 return __irq_domain_alloc_irqs(domain, irq, 1,
982 ioapic_alloc_attr_node(info),
987 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
988 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
989 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
990 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
991 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
992 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
993 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
994 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
996 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
997 int irq, int ioapic, int pin,
998 struct irq_alloc_info *info)
1000 struct mp_chip_data *data;
1001 struct irq_data *irq_data = irq_get_irq_data(irq);
1002 int node = ioapic_alloc_attr_node(info);
1005 * Legacy ISA IRQ has already been allocated, just add pin to
1006 * the pin list assoicated with this IRQ and program the IOAPIC
1007 * entry. The IOAPIC entry
1009 if (irq_data && irq_data->parent_data) {
1010 if (!mp_check_pin_attr(irq, info))
1012 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1016 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1019 irq_data = irq_domain_get_irq_data(domain, irq);
1020 data = irq_data->chip_data;
1021 data->isa_irq = true;
1028 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1029 unsigned int flags, struct irq_alloc_info *info)
1032 bool legacy = false;
1033 struct irq_alloc_info tmp;
1034 struct mp_chip_data *data;
1035 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1040 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1041 irq = mp_irqs[idx].srcbusirq;
1042 legacy = mp_is_legacy_irq(irq);
1045 mutex_lock(&ioapic_mutex);
1046 if (!(flags & IOAPIC_MAP_ALLOC)) {
1048 irq = irq_find_mapping(domain, pin);
1053 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1055 irq = alloc_isa_irq_from_domain(domain, irq,
1057 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1058 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1059 else if (!mp_check_pin_attr(irq, &tmp))
1062 data = irq_get_chip_data(irq);
1066 mutex_unlock(&ioapic_mutex);
1071 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1073 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1076 * Debugging check, we are in big trouble if this message pops up!
1078 if (mp_irqs[idx].dstirq != pin)
1079 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1081 #ifdef CONFIG_X86_32
1083 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1085 if ((pin >= 16) && (pin <= 23)) {
1086 if (pirq_entries[pin-16] != -1) {
1087 if (!pirq_entries[pin-16]) {
1088 apic_printk(APIC_VERBOSE, KERN_DEBUG
1089 "disabling PIRQ%d\n", pin-16);
1091 int irq = pirq_entries[pin-16];
1092 apic_printk(APIC_VERBOSE, KERN_DEBUG
1093 "using PIRQ%d -> IRQ %d\n",
1101 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1104 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1106 int ioapic, pin, idx;
1108 ioapic = mp_find_ioapic(gsi);
1112 pin = mp_find_ioapic_pin(ioapic, gsi);
1113 idx = find_irq_entry(ioapic, pin, mp_INT);
1114 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1117 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1120 void mp_unmap_irq(int irq)
1122 struct irq_data *irq_data = irq_get_irq_data(irq);
1123 struct mp_chip_data *data;
1125 if (!irq_data || !irq_data->domain)
1128 data = irq_data->chip_data;
1129 if (!data || data->isa_irq)
1132 mutex_lock(&ioapic_mutex);
1133 if (--data->count == 0)
1134 irq_domain_free_irqs(irq, 1);
1135 mutex_unlock(&ioapic_mutex);
1139 * Find a specific PCI IRQ entry.
1140 * Not an __init, possibly needed by modules
1142 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1144 int irq, i, best_ioapic = -1, best_idx = -1;
1146 apic_printk(APIC_DEBUG,
1147 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1149 if (test_bit(bus, mp_bus_not_pci)) {
1150 apic_printk(APIC_VERBOSE,
1151 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1155 for (i = 0; i < mp_irq_entries; i++) {
1156 int lbus = mp_irqs[i].srcbus;
1157 int ioapic_idx, found = 0;
1159 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1160 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1163 for_each_ioapic(ioapic_idx)
1164 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1165 mp_irqs[i].dstapic == MP_APIC_ALL) {
1173 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1174 if (irq > 0 && !IO_APIC_IRQ(irq))
1177 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1179 best_ioapic = ioapic_idx;
1184 * Use the first all-but-pin matching entry as a
1185 * best-guess fuzzy result for broken mptables.
1189 best_ioapic = ioapic_idx;
1196 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1199 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1201 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1203 #ifdef CONFIG_X86_32
1204 static inline int IO_APIC_irq_trigger(int irq)
1208 for_each_ioapic_pin(apic, pin) {
1209 idx = find_irq_entry(apic, pin, mp_INT);
1210 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1211 return irq_trigger(idx);
1214 * nonexistent IRQs are edge default
1219 static inline int IO_APIC_irq_trigger(int irq)
1225 static void __init setup_IO_APIC_irqs(void)
1227 unsigned int ioapic, pin;
1230 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1232 for_each_ioapic_pin(ioapic, pin) {
1233 idx = find_irq_entry(ioapic, pin, mp_INT);
1235 apic_printk(APIC_VERBOSE,
1236 KERN_DEBUG " apic %d pin %d not connected\n",
1237 mpc_ioapic_id(ioapic), pin);
1239 pin_2_irq(idx, ioapic, pin,
1240 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1244 void ioapic_zap_locks(void)
1246 raw_spin_lock_init(&ioapic_lock);
1249 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1253 struct IO_APIC_route_entry entry;
1254 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1256 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1257 for (i = 0; i <= nr_entries; i++) {
1258 entry = ioapic_read_entry(apic, i);
1259 snprintf(buf, sizeof(buf),
1260 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1262 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1263 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1264 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1265 entry.vector, entry.irr, entry.delivery_status);
1266 if (ir_entry->format)
1267 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1268 buf, (ir_entry->index << 15) | ir_entry->index,
1271 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1273 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1274 "logical " : "physical",
1275 entry.dest, entry.delivery_mode);
1279 static void __init print_IO_APIC(int ioapic_idx)
1281 union IO_APIC_reg_00 reg_00;
1282 union IO_APIC_reg_01 reg_01;
1283 union IO_APIC_reg_02 reg_02;
1284 union IO_APIC_reg_03 reg_03;
1285 unsigned long flags;
1287 raw_spin_lock_irqsave(&ioapic_lock, flags);
1288 reg_00.raw = io_apic_read(ioapic_idx, 0);
1289 reg_01.raw = io_apic_read(ioapic_idx, 1);
1290 if (reg_01.bits.version >= 0x10)
1291 reg_02.raw = io_apic_read(ioapic_idx, 2);
1292 if (reg_01.bits.version >= 0x20)
1293 reg_03.raw = io_apic_read(ioapic_idx, 3);
1294 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1296 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1297 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1298 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1299 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1300 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1302 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1303 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1304 reg_01.bits.entries);
1306 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1307 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1308 reg_01.bits.version);
1311 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1312 * but the value of reg_02 is read as the previous read register
1313 * value, so ignore it if reg_02 == reg_01.
1315 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1316 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1317 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1321 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1322 * or reg_03, but the value of reg_0[23] is read as the previous read
1323 * register value, so ignore it if reg_03 == reg_0[12].
1325 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1326 reg_03.raw != reg_01.raw) {
1327 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1328 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1331 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1332 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1335 void __init print_IO_APICs(void)
1340 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1341 for_each_ioapic(ioapic_idx)
1342 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1343 mpc_ioapic_id(ioapic_idx),
1344 ioapics[ioapic_idx].nr_registers);
1347 * We are a bit conservative about what we expect. We have to
1348 * know about every hardware change ASAP.
1350 printk(KERN_INFO "testing the IO APIC.......................\n");
1352 for_each_ioapic(ioapic_idx)
1353 print_IO_APIC(ioapic_idx);
1355 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1356 for_each_active_irq(irq) {
1357 struct irq_pin_list *entry;
1358 struct irq_chip *chip;
1359 struct mp_chip_data *data;
1361 chip = irq_get_chip(irq);
1362 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1364 data = irq_get_chip_data(irq);
1367 if (list_empty(&data->irq_2_pin))
1370 printk(KERN_DEBUG "IRQ%d ", irq);
1371 for_each_irq_pin(entry, data->irq_2_pin)
1372 pr_cont("-> %d:%d", entry->apic, entry->pin);
1376 printk(KERN_INFO ".................................... done.\n");
1379 /* Where if anywhere is the i8259 connect in external int mode */
1380 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1382 void __init enable_IO_APIC(void)
1384 int i8259_apic, i8259_pin;
1387 if (skip_ioapic_setup)
1390 if (!nr_legacy_irqs() || !nr_ioapics)
1393 for_each_ioapic_pin(apic, pin) {
1394 /* See if any of the pins is in ExtINT mode */
1395 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1397 /* If the interrupt line is enabled and in ExtInt mode
1398 * I have found the pin where the i8259 is connected.
1400 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1401 ioapic_i8259.apic = apic;
1402 ioapic_i8259.pin = pin;
1407 /* Look to see what if the MP table has reported the ExtINT */
1408 /* If we could not find the appropriate pin by looking at the ioapic
1409 * the i8259 probably is not connected the ioapic but give the
1410 * mptable a chance anyway.
1412 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1413 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1414 /* Trust the MP table if nothing is setup in the hardware */
1415 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1416 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1417 ioapic_i8259.pin = i8259_pin;
1418 ioapic_i8259.apic = i8259_apic;
1420 /* Complain if the MP table and the hardware disagree */
1421 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1422 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1424 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1428 * Do not trust the IO-APIC being empty at bootup
1433 void native_disable_io_apic(void)
1436 * If the i8259 is routed through an IOAPIC
1437 * Put that IOAPIC in virtual wire mode
1438 * so legacy interrupts can be delivered.
1440 if (ioapic_i8259.pin != -1) {
1441 struct IO_APIC_route_entry entry;
1443 memset(&entry, 0, sizeof(entry));
1444 entry.mask = IOAPIC_UNMASKED;
1445 entry.trigger = IOAPIC_EDGE;
1446 entry.polarity = IOAPIC_POL_HIGH;
1447 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1448 entry.delivery_mode = dest_ExtINT;
1449 entry.dest = read_apic_id();
1452 * Add it to the IO-APIC irq-routing table:
1454 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1457 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1458 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1462 * Not an __init, needed by the reboot code
1464 void disable_IO_APIC(void)
1467 * Clear the IO-APIC before rebooting:
1471 if (!nr_legacy_irqs())
1474 x86_io_apic_ops.disable();
1477 #ifdef CONFIG_X86_32
1479 * function to set the IO-APIC physical IDs based on the
1480 * values stored in the MPC table.
1482 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1484 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1486 union IO_APIC_reg_00 reg_00;
1487 physid_mask_t phys_id_present_map;
1490 unsigned char old_id;
1491 unsigned long flags;
1494 * This is broken; anything with a real cpu count has to
1495 * circumvent this idiocy regardless.
1497 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1500 * Set the IOAPIC ID to the value stored in the MPC table.
1502 for_each_ioapic(ioapic_idx) {
1503 /* Read the register 0 value */
1504 raw_spin_lock_irqsave(&ioapic_lock, flags);
1505 reg_00.raw = io_apic_read(ioapic_idx, 0);
1506 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1508 old_id = mpc_ioapic_id(ioapic_idx);
1510 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1511 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1512 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1513 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1515 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1519 * Sanity check, is the ID really free? Every APIC in a
1520 * system must have a unique ID or we get lots of nice
1521 * 'stuck on smp_invalidate_needed IPI wait' messages.
1523 if (apic->check_apicid_used(&phys_id_present_map,
1524 mpc_ioapic_id(ioapic_idx))) {
1525 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1526 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1527 for (i = 0; i < get_physical_broadcast(); i++)
1528 if (!physid_isset(i, phys_id_present_map))
1530 if (i >= get_physical_broadcast())
1531 panic("Max APIC ID exceeded!\n");
1532 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1534 physid_set(i, phys_id_present_map);
1535 ioapics[ioapic_idx].mp_config.apicid = i;
1538 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1540 apic_printk(APIC_VERBOSE, "Setting %d in the "
1541 "phys_id_present_map\n",
1542 mpc_ioapic_id(ioapic_idx));
1543 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1547 * We need to adjust the IRQ routing table
1548 * if the ID changed.
1550 if (old_id != mpc_ioapic_id(ioapic_idx))
1551 for (i = 0; i < mp_irq_entries; i++)
1552 if (mp_irqs[i].dstapic == old_id)
1554 = mpc_ioapic_id(ioapic_idx);
1557 * Update the ID register according to the right value
1558 * from the MPC table if they are different.
1560 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1563 apic_printk(APIC_VERBOSE, KERN_INFO
1564 "...changing IO-APIC physical APIC ID to %d ...",
1565 mpc_ioapic_id(ioapic_idx));
1567 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1568 raw_spin_lock_irqsave(&ioapic_lock, flags);
1569 io_apic_write(ioapic_idx, 0, reg_00.raw);
1570 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1575 raw_spin_lock_irqsave(&ioapic_lock, flags);
1576 reg_00.raw = io_apic_read(ioapic_idx, 0);
1577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1578 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1579 pr_cont("could not set ID!\n");
1581 apic_printk(APIC_VERBOSE, " ok.\n");
1585 void __init setup_ioapic_ids_from_mpc(void)
1591 * Don't check I/O APIC IDs for xAPIC systems. They have
1592 * no meaning without the serial APIC bus.
1594 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1595 || APIC_XAPIC(boot_cpu_apic_version))
1597 setup_ioapic_ids_from_mpc_nocheck();
1601 int no_timer_check __initdata;
1603 static int __init notimercheck(char *s)
1608 __setup("no_timer_check", notimercheck);
1611 * There is a nasty bug in some older SMP boards, their mptable lies
1612 * about the timer IRQ. We do the following to work around the situation:
1614 * - timer IRQ defaults to IO-APIC IRQ
1615 * - if this function detects that timer IRQs are defunct, then we fall
1616 * back to ISA timer IRQs
1618 static int __init timer_irq_works(void)
1620 unsigned long t1 = jiffies;
1621 unsigned long flags;
1626 local_save_flags(flags);
1628 /* Let ten ticks pass... */
1629 mdelay((10 * 1000) / HZ);
1630 local_irq_restore(flags);
1633 * Expect a few ticks at least, to be sure some possible
1634 * glue logic does not lock up after one or two first
1635 * ticks in a non-ExtINT mode. Also the local APIC
1636 * might have cached one ExtINT interrupt. Finally, at
1637 * least one tick may be lost due to delays.
1641 if (time_after(jiffies, t1 + 4))
1647 * In the SMP+IOAPIC case it might happen that there are an unspecified
1648 * number of pending IRQ events unhandled. These cases are very rare,
1649 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1650 * better to do it this way as thus we do not have to be aware of
1651 * 'pending' interrupts in the IRQ path, except at this point.
1654 * Edge triggered needs to resend any interrupt
1655 * that was delayed but this is now handled in the device
1660 * Starting up a edge-triggered IO-APIC interrupt is
1661 * nasty - we need to make sure that we get the edge.
1662 * If it is already asserted for some reason, we need
1663 * return 1 to indicate that is was pending.
1665 * This is not complete - we should be able to fake
1666 * an edge even if it isn't on the 8259A...
1668 static unsigned int startup_ioapic_irq(struct irq_data *data)
1670 int was_pending = 0, irq = data->irq;
1671 unsigned long flags;
1673 raw_spin_lock_irqsave(&ioapic_lock, flags);
1674 if (irq < nr_legacy_irqs()) {
1675 legacy_pic->mask(irq);
1676 if (legacy_pic->irq_pending(irq))
1679 __unmask_ioapic(data->chip_data);
1680 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1685 atomic_t irq_mis_count;
1687 #ifdef CONFIG_GENERIC_PENDING_IRQ
1688 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1690 struct irq_pin_list *entry;
1691 unsigned long flags;
1693 raw_spin_lock_irqsave(&ioapic_lock, flags);
1694 for_each_irq_pin(entry, data->irq_2_pin) {
1699 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1700 /* Is the remote IRR bit set? */
1701 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1702 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1706 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1711 static inline bool ioapic_irqd_mask(struct irq_data *data)
1713 /* If we are moving the irq we need to mask it */
1714 if (unlikely(irqd_is_setaffinity_pending(data))) {
1715 mask_ioapic_irq(data);
1721 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1723 if (unlikely(masked)) {
1724 /* Only migrate the irq if the ack has been received.
1726 * On rare occasions the broadcast level triggered ack gets
1727 * delayed going to ioapics, and if we reprogram the
1728 * vector while Remote IRR is still set the irq will never
1731 * To prevent this scenario we read the Remote IRR bit
1732 * of the ioapic. This has two effects.
1733 * - On any sane system the read of the ioapic will
1734 * flush writes (and acks) going to the ioapic from
1736 * - We get to see if the ACK has actually been delivered.
1738 * Based on failed experiments of reprogramming the
1739 * ioapic entry from outside of irq context starting
1740 * with masking the ioapic entry and then polling until
1741 * Remote IRR was clear before reprogramming the
1742 * ioapic I don't trust the Remote IRR bit to be
1743 * completey accurate.
1745 * However there appears to be no other way to plug
1746 * this race, so if the Remote IRR bit is not
1747 * accurate and is causing problems then it is a hardware bug
1748 * and you can go talk to the chipset vendor about it.
1750 if (!io_apic_level_ack_pending(data->chip_data))
1751 irq_move_masked_irq(data);
1752 unmask_ioapic_irq(data);
1756 static inline bool ioapic_irqd_mask(struct irq_data *data)
1760 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1765 static void ioapic_ack_level(struct irq_data *irq_data)
1767 struct irq_cfg *cfg = irqd_cfg(irq_data);
1772 irq_complete_move(cfg);
1773 masked = ioapic_irqd_mask(irq_data);
1776 * It appears there is an erratum which affects at least version 0x11
1777 * of I/O APIC (that's the 82093AA and cores integrated into various
1778 * chipsets). Under certain conditions a level-triggered interrupt is
1779 * erroneously delivered as edge-triggered one but the respective IRR
1780 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1781 * message but it will never arrive and further interrupts are blocked
1782 * from the source. The exact reason is so far unknown, but the
1783 * phenomenon was observed when two consecutive interrupt requests
1784 * from a given source get delivered to the same CPU and the source is
1785 * temporarily disabled in between.
1787 * A workaround is to simulate an EOI message manually. We achieve it
1788 * by setting the trigger mode to edge and then to level when the edge
1789 * trigger mode gets detected in the TMR of a local APIC for a
1790 * level-triggered interrupt. We mask the source for the time of the
1791 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1792 * The idea is from Manfred Spraul. --macro
1794 * Also in the case when cpu goes offline, fixup_irqs() will forward
1795 * any unhandled interrupt on the offlined cpu to the new cpu
1796 * destination that is handling the corresponding interrupt. This
1797 * interrupt forwarding is done via IPI's. Hence, in this case also
1798 * level-triggered io-apic interrupt will be seen as an edge
1799 * interrupt in the IRR. And we can't rely on the cpu's EOI
1800 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1801 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1802 * supporting EOI register, we do an explicit EOI to clear the
1803 * remote IRR and on IO-APIC's which don't have an EOI register,
1804 * we use the above logic (mask+edge followed by unmask+level) from
1805 * Manfred Spraul to clear the remote IRR.
1808 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1811 * We must acknowledge the irq before we move it or the acknowledge will
1812 * not propagate properly.
1817 * Tail end of clearing remote IRR bit (either by delivering the EOI
1818 * message via io-apic EOI register write or simulating it using
1819 * mask+edge followed by unnask+level logic) manually when the
1820 * level triggered interrupt is seen as the edge triggered interrupt
1823 if (!(v & (1 << (i & 0x1f)))) {
1824 atomic_inc(&irq_mis_count);
1825 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1828 ioapic_irqd_unmask(irq_data, masked);
1831 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1833 struct mp_chip_data *data = irq_data->chip_data;
1836 * Intr-remapping uses pin number as the virtual vector
1837 * in the RTE. Actual vector is programmed in
1838 * intr-remapping table entry. Hence for the io-apic
1839 * EOI we use the pin number.
1842 eoi_ioapic_pin(data->entry.vector, data);
1845 static int ioapic_set_affinity(struct irq_data *irq_data,
1846 const struct cpumask *mask, bool force)
1848 struct irq_data *parent = irq_data->parent_data;
1849 struct mp_chip_data *data = irq_data->chip_data;
1850 struct irq_pin_list *entry;
1851 struct irq_cfg *cfg;
1852 unsigned long flags;
1855 ret = parent->chip->irq_set_affinity(parent, mask, force);
1856 raw_spin_lock_irqsave(&ioapic_lock, flags);
1857 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1858 cfg = irqd_cfg(irq_data);
1859 data->entry.dest = cfg->dest_apicid;
1860 data->entry.vector = cfg->vector;
1861 for_each_irq_pin(entry, data->irq_2_pin)
1862 __ioapic_write_entry(entry->apic, entry->pin,
1865 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1870 static struct irq_chip ioapic_chip __read_mostly = {
1872 .irq_startup = startup_ioapic_irq,
1873 .irq_mask = mask_ioapic_irq,
1874 .irq_unmask = unmask_ioapic_irq,
1875 .irq_ack = irq_chip_ack_parent,
1876 .irq_eoi = ioapic_ack_level,
1877 .irq_set_affinity = ioapic_set_affinity,
1878 .flags = IRQCHIP_SKIP_SET_WAKE,
1881 static struct irq_chip ioapic_ir_chip __read_mostly = {
1882 .name = "IR-IO-APIC",
1883 .irq_startup = startup_ioapic_irq,
1884 .irq_mask = mask_ioapic_irq,
1885 .irq_unmask = unmask_ioapic_irq,
1886 .irq_ack = irq_chip_ack_parent,
1887 .irq_eoi = ioapic_ir_ack_level,
1888 .irq_set_affinity = ioapic_set_affinity,
1889 .flags = IRQCHIP_SKIP_SET_WAKE,
1892 static inline void init_IO_APIC_traps(void)
1894 struct irq_cfg *cfg;
1897 for_each_active_irq(irq) {
1899 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1901 * Hmm.. We don't have an entry for this,
1902 * so default to an old-fashioned 8259
1903 * interrupt if we can..
1905 if (irq < nr_legacy_irqs())
1906 legacy_pic->make_irq(irq);
1908 /* Strange. Oh, well.. */
1909 irq_set_chip(irq, &no_irq_chip);
1915 * The local APIC irq-chip implementation:
1918 static void mask_lapic_irq(struct irq_data *data)
1922 v = apic_read(APIC_LVT0);
1923 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1926 static void unmask_lapic_irq(struct irq_data *data)
1930 v = apic_read(APIC_LVT0);
1931 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1934 static void ack_lapic_irq(struct irq_data *data)
1939 static struct irq_chip lapic_chip __read_mostly = {
1940 .name = "local-APIC",
1941 .irq_mask = mask_lapic_irq,
1942 .irq_unmask = unmask_lapic_irq,
1943 .irq_ack = ack_lapic_irq,
1946 static void lapic_register_intr(int irq)
1948 irq_clear_status_flags(irq, IRQ_LEVEL);
1949 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1954 * This looks a bit hackish but it's about the only one way of sending
1955 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1956 * not support the ExtINT mode, unfortunately. We need to send these
1957 * cycles as some i82489DX-based boards have glue logic that keeps the
1958 * 8259A interrupt line asserted until INTA. --macro
1960 static inline void __init unlock_ExtINT_logic(void)
1963 struct IO_APIC_route_entry entry0, entry1;
1964 unsigned char save_control, save_freq_select;
1966 pin = find_isa_irq_pin(8, mp_INT);
1971 apic = find_isa_irq_apic(8, mp_INT);
1977 entry0 = ioapic_read_entry(apic, pin);
1978 clear_IO_APIC_pin(apic, pin);
1980 memset(&entry1, 0, sizeof(entry1));
1982 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1983 entry1.mask = IOAPIC_UNMASKED;
1984 entry1.dest = hard_smp_processor_id();
1985 entry1.delivery_mode = dest_ExtINT;
1986 entry1.polarity = entry0.polarity;
1987 entry1.trigger = IOAPIC_EDGE;
1990 ioapic_write_entry(apic, pin, entry1);
1992 save_control = CMOS_READ(RTC_CONTROL);
1993 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1994 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1996 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2001 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2005 CMOS_WRITE(save_control, RTC_CONTROL);
2006 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2007 clear_IO_APIC_pin(apic, pin);
2009 ioapic_write_entry(apic, pin, entry0);
2012 static int disable_timer_pin_1 __initdata;
2013 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2014 static int __init disable_timer_pin_setup(char *arg)
2016 disable_timer_pin_1 = 1;
2019 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2021 static int mp_alloc_timer_irq(int ioapic, int pin)
2024 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2027 struct irq_alloc_info info;
2029 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2030 info.ioapic_id = mpc_ioapic_id(ioapic);
2031 info.ioapic_pin = pin;
2032 mutex_lock(&ioapic_mutex);
2033 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2034 mutex_unlock(&ioapic_mutex);
2041 * This code may look a bit paranoid, but it's supposed to cooperate with
2042 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2043 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2044 * fanatically on his truly buggy board.
2046 * FIXME: really need to revamp this for all platforms.
2048 static inline void __init check_timer(void)
2050 struct irq_data *irq_data = irq_get_irq_data(0);
2051 struct mp_chip_data *data = irq_data->chip_data;
2052 struct irq_cfg *cfg = irqd_cfg(irq_data);
2053 int node = cpu_to_node(0);
2054 int apic1, pin1, apic2, pin2;
2055 unsigned long flags;
2058 local_irq_save(flags);
2061 * get/set the timer IRQ vector:
2063 legacy_pic->mask(0);
2066 * As IRQ0 is to be enabled in the 8259A, the virtual
2067 * wire has to be disabled in the local APIC. Also
2068 * timer interrupts need to be acknowledged manually in
2069 * the 8259A for the i82489DX when using the NMI
2070 * watchdog as that APIC treats NMIs as level-triggered.
2071 * The AEOI mode will finish them in the 8259A
2074 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2075 legacy_pic->init(1);
2077 pin1 = find_isa_irq_pin(0, mp_INT);
2078 apic1 = find_isa_irq_apic(0, mp_INT);
2079 pin2 = ioapic_i8259.pin;
2080 apic2 = ioapic_i8259.apic;
2082 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2083 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2084 cfg->vector, apic1, pin1, apic2, pin2);
2087 * Some BIOS writers are clueless and report the ExtINTA
2088 * I/O APIC input from the cascaded 8259A as the timer
2089 * interrupt input. So just in case, if only one pin
2090 * was found above, try it both directly and through the
2094 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2098 } else if (pin2 == -1) {
2104 /* Ok, does IRQ0 through the IOAPIC work? */
2106 mp_alloc_timer_irq(apic1, pin1);
2109 * for edge trigger, it's already unmasked,
2110 * so only need to unmask if it is level-trigger
2111 * do we really have level trigger timer?
2114 idx = find_irq_entry(apic1, pin1, mp_INT);
2115 if (idx != -1 && irq_trigger(idx))
2116 unmask_ioapic_irq(irq_get_chip_data(0));
2118 irq_domain_deactivate_irq(irq_data);
2119 irq_domain_activate_irq(irq_data);
2120 if (timer_irq_works()) {
2121 if (disable_timer_pin_1 > 0)
2122 clear_IO_APIC_pin(0, pin1);
2125 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2126 local_irq_disable();
2127 clear_IO_APIC_pin(apic1, pin1);
2129 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2130 "8254 timer not connected to IO-APIC\n");
2132 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2133 "(IRQ0) through the 8259A ...\n");
2134 apic_printk(APIC_QUIET, KERN_INFO
2135 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2137 * legacy devices should be connected to IO APIC #0
2139 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2140 irq_domain_deactivate_irq(irq_data);
2141 irq_domain_activate_irq(irq_data);
2142 legacy_pic->unmask(0);
2143 if (timer_irq_works()) {
2144 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2148 * Cleanup, just in case ...
2150 local_irq_disable();
2151 legacy_pic->mask(0);
2152 clear_IO_APIC_pin(apic2, pin2);
2153 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2156 apic_printk(APIC_QUIET, KERN_INFO
2157 "...trying to set up timer as Virtual Wire IRQ...\n");
2159 lapic_register_intr(0);
2160 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2161 legacy_pic->unmask(0);
2163 if (timer_irq_works()) {
2164 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2167 local_irq_disable();
2168 legacy_pic->mask(0);
2169 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2170 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2172 apic_printk(APIC_QUIET, KERN_INFO
2173 "...trying to set up timer as ExtINT IRQ...\n");
2175 legacy_pic->init(0);
2176 legacy_pic->make_irq(0);
2177 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2179 unlock_ExtINT_logic();
2181 if (timer_irq_works()) {
2182 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2185 local_irq_disable();
2186 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2187 if (apic_is_x2apic_enabled())
2188 apic_printk(APIC_QUIET, KERN_INFO
2189 "Perhaps problem with the pre-enabled x2apic mode\n"
2190 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2191 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2192 "report. Then try booting with the 'noapic' option.\n");
2194 local_irq_restore(flags);
2198 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2199 * to devices. However there may be an I/O APIC pin available for
2200 * this interrupt regardless. The pin may be left unconnected, but
2201 * typically it will be reused as an ExtINT cascade interrupt for
2202 * the master 8259A. In the MPS case such a pin will normally be
2203 * reported as an ExtINT interrupt in the MP table. With ACPI
2204 * there is no provision for ExtINT interrupts, and in the absence
2205 * of an override it would be treated as an ordinary ISA I/O APIC
2206 * interrupt, that is edge-triggered and unmasked by default. We
2207 * used to do this, but it caused problems on some systems because
2208 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2209 * the same ExtINT cascade interrupt to drive the local APIC of the
2210 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2211 * the I/O APIC in all cases now. No actual device should request
2212 * it anyway. --macro
2214 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2216 static int mp_irqdomain_create(int ioapic)
2218 struct irq_alloc_info info;
2219 struct irq_domain *parent;
2220 int hwirqs = mp_ioapic_pin_count(ioapic);
2221 struct ioapic *ip = &ioapics[ioapic];
2222 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2223 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2225 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2228 init_irq_alloc_info(&info, NULL);
2229 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2230 info.ioapic_id = mpc_ioapic_id(ioapic);
2231 parent = irq_remapping_get_ir_irq_domain(&info);
2233 parent = x86_vector_domain;
2235 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2236 (void *)(long)ioapic);
2240 ip->irqdomain->parent = parent;
2242 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2243 cfg->type == IOAPIC_DOMAIN_STRICT)
2244 ioapic_dynirq_base = max(ioapic_dynirq_base,
2245 gsi_cfg->gsi_end + 1);
2250 static void ioapic_destroy_irqdomain(int idx)
2252 if (ioapics[idx].irqdomain) {
2253 irq_domain_remove(ioapics[idx].irqdomain);
2254 ioapics[idx].irqdomain = NULL;
2258 void __init setup_IO_APIC(void)
2262 if (skip_ioapic_setup || !nr_ioapics)
2265 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2267 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2268 for_each_ioapic(ioapic)
2269 BUG_ON(mp_irqdomain_create(ioapic));
2272 * Set up IO-APIC IRQ routing.
2274 x86_init.mpparse.setup_ioapic_ids();
2277 setup_IO_APIC_irqs();
2278 init_IO_APIC_traps();
2279 if (nr_legacy_irqs())
2282 ioapic_initialized = 1;
2285 static void resume_ioapic_id(int ioapic_idx)
2287 unsigned long flags;
2288 union IO_APIC_reg_00 reg_00;
2290 raw_spin_lock_irqsave(&ioapic_lock, flags);
2291 reg_00.raw = io_apic_read(ioapic_idx, 0);
2292 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2293 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2294 io_apic_write(ioapic_idx, 0, reg_00.raw);
2296 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2299 static void ioapic_resume(void)
2303 for_each_ioapic_reverse(ioapic_idx)
2304 resume_ioapic_id(ioapic_idx);
2306 restore_ioapic_entries();
2309 static struct syscore_ops ioapic_syscore_ops = {
2310 .suspend = save_ioapic_entries,
2311 .resume = ioapic_resume,
2314 static int __init ioapic_init_ops(void)
2316 register_syscore_ops(&ioapic_syscore_ops);
2321 device_initcall(ioapic_init_ops);
2323 static int io_apic_get_redir_entries(int ioapic)
2325 union IO_APIC_reg_01 reg_01;
2326 unsigned long flags;
2328 raw_spin_lock_irqsave(&ioapic_lock, flags);
2329 reg_01.raw = io_apic_read(ioapic, 1);
2330 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2332 /* The register returns the maximum index redir index
2333 * supported, which is one less than the total number of redir
2336 return reg_01.bits.entries + 1;
2339 unsigned int arch_dynirq_lower_bound(unsigned int from)
2342 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2343 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2345 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2348 #ifdef CONFIG_X86_32
2349 static int io_apic_get_unique_id(int ioapic, int apic_id)
2351 union IO_APIC_reg_00 reg_00;
2352 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2354 unsigned long flags;
2358 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2359 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2360 * supports up to 16 on one shared APIC bus.
2362 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2363 * advantage of new APIC bus architecture.
2366 if (physids_empty(apic_id_map))
2367 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2369 raw_spin_lock_irqsave(&ioapic_lock, flags);
2370 reg_00.raw = io_apic_read(ioapic, 0);
2371 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2373 if (apic_id >= get_physical_broadcast()) {
2374 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2375 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2376 apic_id = reg_00.bits.ID;
2380 * Every APIC in a system must have a unique ID or we get lots of nice
2381 * 'stuck on smp_invalidate_needed IPI wait' messages.
2383 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2385 for (i = 0; i < get_physical_broadcast(); i++) {
2386 if (!apic->check_apicid_used(&apic_id_map, i))
2390 if (i == get_physical_broadcast())
2391 panic("Max apic_id exceeded!\n");
2393 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2394 "trying %d\n", ioapic, apic_id, i);
2399 apic->apicid_to_cpu_present(apic_id, &tmp);
2400 physids_or(apic_id_map, apic_id_map, tmp);
2402 if (reg_00.bits.ID != apic_id) {
2403 reg_00.bits.ID = apic_id;
2405 raw_spin_lock_irqsave(&ioapic_lock, flags);
2406 io_apic_write(ioapic, 0, reg_00.raw);
2407 reg_00.raw = io_apic_read(ioapic, 0);
2408 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2411 if (reg_00.bits.ID != apic_id) {
2412 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2418 apic_printk(APIC_VERBOSE, KERN_INFO
2419 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2424 static u8 io_apic_unique_id(int idx, u8 id)
2426 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2427 !APIC_XAPIC(boot_cpu_apic_version))
2428 return io_apic_get_unique_id(idx, id);
2433 static u8 io_apic_unique_id(int idx, u8 id)
2435 union IO_APIC_reg_00 reg_00;
2436 DECLARE_BITMAP(used, 256);
2437 unsigned long flags;
2441 bitmap_zero(used, 256);
2443 __set_bit(mpc_ioapic_id(i), used);
2445 /* Hand out the requested id if available */
2446 if (!test_bit(id, used))
2450 * Read the current id from the ioapic and keep it if
2453 raw_spin_lock_irqsave(&ioapic_lock, flags);
2454 reg_00.raw = io_apic_read(idx, 0);
2455 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2456 new_id = reg_00.bits.ID;
2457 if (!test_bit(new_id, used)) {
2458 apic_printk(APIC_VERBOSE, KERN_INFO
2459 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2465 * Get the next free id and write it to the ioapic.
2467 new_id = find_first_zero_bit(used, 256);
2468 reg_00.bits.ID = new_id;
2469 raw_spin_lock_irqsave(&ioapic_lock, flags);
2470 io_apic_write(idx, 0, reg_00.raw);
2471 reg_00.raw = io_apic_read(idx, 0);
2472 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2474 BUG_ON(reg_00.bits.ID != new_id);
2480 static int io_apic_get_version(int ioapic)
2482 union IO_APIC_reg_01 reg_01;
2483 unsigned long flags;
2485 raw_spin_lock_irqsave(&ioapic_lock, flags);
2486 reg_01.raw = io_apic_read(ioapic, 1);
2487 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2489 return reg_01.bits.version;
2492 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2494 int ioapic, pin, idx;
2496 if (skip_ioapic_setup)
2499 ioapic = mp_find_ioapic(gsi);
2503 pin = mp_find_ioapic_pin(ioapic, gsi);
2507 idx = find_irq_entry(ioapic, pin, mp_INT);
2511 *trigger = irq_trigger(idx);
2512 *polarity = irq_polarity(idx);
2517 * This function currently is only a helper for the i386 smp boot process where
2518 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2519 * so mask in all cases should simply be apic->target_cpus()
2522 void __init setup_ioapic_dest(void)
2524 int pin, ioapic, irq, irq_entry;
2525 const struct cpumask *mask;
2526 struct irq_desc *desc;
2527 struct irq_data *idata;
2528 struct irq_chip *chip;
2530 if (skip_ioapic_setup == 1)
2533 for_each_ioapic_pin(ioapic, pin) {
2534 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2535 if (irq_entry == -1)
2538 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2539 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2542 desc = irq_to_desc(irq);
2543 raw_spin_lock_irq(&desc->lock);
2544 idata = irq_desc_get_irq_data(desc);
2547 * Honour affinities which have been set in early boot
2549 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2550 mask = irq_data_get_affinity_mask(idata);
2552 mask = apic->target_cpus();
2554 chip = irq_data_get_irq_chip(idata);
2555 /* Might be lapic_chip for irq 0 */
2556 if (chip->irq_set_affinity)
2557 chip->irq_set_affinity(idata, mask, false);
2558 raw_spin_unlock_irq(&desc->lock);
2563 #define IOAPIC_RESOURCE_NAME_SIZE 11
2565 static struct resource *ioapic_resources;
2567 static struct resource * __init ioapic_setup_resources(void)
2570 struct resource *res;
2574 if (nr_ioapics == 0)
2577 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2580 mem = alloc_bootmem(n);
2583 mem += sizeof(struct resource) * nr_ioapics;
2585 for_each_ioapic(i) {
2587 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2588 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2589 mem += IOAPIC_RESOURCE_NAME_SIZE;
2590 ioapics[i].iomem_res = &res[i];
2593 ioapic_resources = res;
2598 void __init io_apic_init_mappings(void)
2600 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2601 struct resource *ioapic_res;
2604 ioapic_res = ioapic_setup_resources();
2605 for_each_ioapic(i) {
2606 if (smp_found_config) {
2607 ioapic_phys = mpc_ioapic_addr(i);
2608 #ifdef CONFIG_X86_32
2611 "WARNING: bogus zero IO-APIC "
2612 "address found in MPTABLE, "
2613 "disabling IO/APIC support!\n");
2614 smp_found_config = 0;
2615 skip_ioapic_setup = 1;
2616 goto fake_ioapic_page;
2620 #ifdef CONFIG_X86_32
2623 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2624 ioapic_phys = __pa(ioapic_phys);
2626 set_fixmap_nocache(idx, ioapic_phys);
2627 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2628 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2632 ioapic_res->start = ioapic_phys;
2633 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2638 void __init ioapic_insert_resources(void)
2641 struct resource *r = ioapic_resources;
2646 "IO APIC resources couldn't be allocated.\n");
2650 for_each_ioapic(i) {
2651 insert_resource(&iomem_resource, r);
2656 int mp_find_ioapic(u32 gsi)
2660 if (nr_ioapics == 0)
2663 /* Find the IOAPIC that manages this GSI. */
2664 for_each_ioapic(i) {
2665 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2666 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2670 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2674 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2676 struct mp_ioapic_gsi *gsi_cfg;
2678 if (WARN_ON(ioapic < 0))
2681 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2682 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2685 return gsi - gsi_cfg->gsi_base;
2688 static int bad_ioapic_register(int idx)
2690 union IO_APIC_reg_00 reg_00;
2691 union IO_APIC_reg_01 reg_01;
2692 union IO_APIC_reg_02 reg_02;
2694 reg_00.raw = io_apic_read(idx, 0);
2695 reg_01.raw = io_apic_read(idx, 1);
2696 reg_02.raw = io_apic_read(idx, 2);
2698 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2699 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2700 mpc_ioapic_addr(idx));
2707 static int find_free_ioapic_entry(void)
2711 for (idx = 0; idx < MAX_IO_APICS; idx++)
2712 if (ioapics[idx].nr_registers == 0)
2715 return MAX_IO_APICS;
2719 * mp_register_ioapic - Register an IOAPIC device
2720 * @id: hardware IOAPIC ID
2721 * @address: physical address of IOAPIC register area
2722 * @gsi_base: base of GSI associated with the IOAPIC
2723 * @cfg: configuration information for the IOAPIC
2725 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2726 struct ioapic_domain_cfg *cfg)
2728 bool hotplug = !!ioapic_initialized;
2729 struct mp_ioapic_gsi *gsi_cfg;
2730 int idx, ioapic, entries;
2734 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2737 for_each_ioapic(ioapic)
2738 if (ioapics[ioapic].mp_config.apicaddr == address) {
2739 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2744 idx = find_free_ioapic_entry();
2745 if (idx >= MAX_IO_APICS) {
2746 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2751 ioapics[idx].mp_config.type = MP_IOAPIC;
2752 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2753 ioapics[idx].mp_config.apicaddr = address;
2755 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2756 if (bad_ioapic_register(idx)) {
2757 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2761 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2762 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2765 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2766 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2768 entries = io_apic_get_redir_entries(idx);
2769 gsi_end = gsi_base + entries - 1;
2770 for_each_ioapic(ioapic) {
2771 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2772 if ((gsi_base >= gsi_cfg->gsi_base &&
2773 gsi_base <= gsi_cfg->gsi_end) ||
2774 (gsi_end >= gsi_cfg->gsi_base &&
2775 gsi_end <= gsi_cfg->gsi_end)) {
2776 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2778 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2779 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2783 gsi_cfg = mp_ioapic_gsi_routing(idx);
2784 gsi_cfg->gsi_base = gsi_base;
2785 gsi_cfg->gsi_end = gsi_end;
2787 ioapics[idx].irqdomain = NULL;
2788 ioapics[idx].irqdomain_cfg = *cfg;
2791 * If mp_register_ioapic() is called during early boot stage when
2792 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2793 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2796 if (mp_irqdomain_create(idx)) {
2797 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2800 alloc_ioapic_saved_registers(idx);
2803 if (gsi_cfg->gsi_end >= gsi_top)
2804 gsi_top = gsi_cfg->gsi_end + 1;
2805 if (nr_ioapics <= idx)
2806 nr_ioapics = idx + 1;
2808 /* Set nr_registers to mark entry present */
2809 ioapics[idx].nr_registers = entries;
2811 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2812 idx, mpc_ioapic_id(idx),
2813 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2814 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2819 int mp_unregister_ioapic(u32 gsi_base)
2824 for_each_ioapic(ioapic)
2825 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2830 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2834 for_each_pin(ioapic, pin) {
2835 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2836 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2837 struct mp_chip_data *data;
2840 data = irq_get_chip_data(irq);
2841 if (data && data->count) {
2842 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2849 /* Mark entry not present */
2850 ioapics[ioapic].nr_registers = 0;
2851 ioapic_destroy_irqdomain(ioapic);
2852 free_ioapic_saved_registers(ioapic);
2853 if (ioapics[ioapic].iomem_res)
2854 release_resource(ioapics[ioapic].iomem_res);
2855 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2856 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2861 int mp_ioapic_registered(u32 gsi_base)
2865 for_each_ioapic(ioapic)
2866 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2872 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2873 struct irq_alloc_info *info)
2875 if (info && info->ioapic_valid) {
2876 data->trigger = info->ioapic_trigger;
2877 data->polarity = info->ioapic_polarity;
2878 } else if (acpi_get_override_irq(gsi, &data->trigger,
2879 &data->polarity) < 0) {
2880 /* PCI interrupts are always active low level triggered. */
2881 data->trigger = IOAPIC_LEVEL;
2882 data->polarity = IOAPIC_POL_LOW;
2886 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2887 struct IO_APIC_route_entry *entry)
2889 memset(entry, 0, sizeof(*entry));
2890 entry->delivery_mode = apic->irq_delivery_mode;
2891 entry->dest_mode = apic->irq_dest_mode;
2892 entry->dest = cfg->dest_apicid;
2893 entry->vector = cfg->vector;
2894 entry->trigger = data->trigger;
2895 entry->polarity = data->polarity;
2897 * Mask level triggered irqs. Edge triggered irqs are masked
2898 * by the irq core code in case they fire.
2900 if (data->trigger == IOAPIC_LEVEL)
2901 entry->mask = IOAPIC_MASKED;
2903 entry->mask = IOAPIC_UNMASKED;
2906 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2907 unsigned int nr_irqs, void *arg)
2909 int ret, ioapic, pin;
2910 struct irq_cfg *cfg;
2911 struct irq_data *irq_data;
2912 struct mp_chip_data *data;
2913 struct irq_alloc_info *info = arg;
2914 unsigned long flags;
2916 if (!info || nr_irqs > 1)
2918 irq_data = irq_domain_get_irq_data(domain, virq);
2922 ioapic = mp_irqdomain_ioapic_idx(domain);
2923 pin = info->ioapic_pin;
2924 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2927 data = kzalloc(sizeof(*data), GFP_KERNEL);
2931 info->ioapic_entry = &data->entry;
2932 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2938 INIT_LIST_HEAD(&data->irq_2_pin);
2939 irq_data->hwirq = info->ioapic_pin;
2940 irq_data->chip = (domain->parent == x86_vector_domain) ?
2941 &ioapic_chip : &ioapic_ir_chip;
2942 irq_data->chip_data = data;
2943 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2945 cfg = irqd_cfg(irq_data);
2946 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2948 local_irq_save(flags);
2949 if (info->ioapic_entry)
2950 mp_setup_entry(cfg, data, info->ioapic_entry);
2951 mp_register_handler(virq, data->trigger);
2952 if (virq < nr_legacy_irqs())
2953 legacy_pic->mask(virq);
2954 local_irq_restore(flags);
2956 apic_printk(APIC_VERBOSE, KERN_DEBUG
2957 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2958 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2959 virq, data->trigger, data->polarity, cfg->dest_apicid);
2964 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2965 unsigned int nr_irqs)
2967 struct irq_data *irq_data;
2968 struct mp_chip_data *data;
2970 BUG_ON(nr_irqs != 1);
2971 irq_data = irq_domain_get_irq_data(domain, virq);
2972 if (irq_data && irq_data->chip_data) {
2973 data = irq_data->chip_data;
2974 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2975 (int)irq_data->hwirq);
2976 WARN_ON(!list_empty(&data->irq_2_pin));
2977 kfree(irq_data->chip_data);
2979 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2982 void mp_irqdomain_activate(struct irq_domain *domain,
2983 struct irq_data *irq_data)
2985 unsigned long flags;
2986 struct irq_pin_list *entry;
2987 struct mp_chip_data *data = irq_data->chip_data;
2989 raw_spin_lock_irqsave(&ioapic_lock, flags);
2990 for_each_irq_pin(entry, data->irq_2_pin)
2991 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
2992 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2995 void mp_irqdomain_deactivate(struct irq_domain *domain,
2996 struct irq_data *irq_data)
2998 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2999 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3000 (int)irq_data->hwirq);
3003 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3005 return (int)(long)domain->host_data;
3008 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3009 .alloc = mp_irqdomain_alloc,
3010 .free = mp_irqdomain_free,
3011 .activate = mp_irqdomain_activate,
3012 .deactivate = mp_irqdomain_deactivate,