2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
30 #include <asm/uv/uv_mmrs.h>
31 #include <asm/uv/uv_hub.h>
32 #include <asm/current.h>
33 #include <asm/pgtable.h>
34 #include <asm/uv/bios.h>
35 #include <asm/uv/uv.h>
39 #include <asm/x86_init.h>
42 DEFINE_PER_CPU(int, x2apic_extra_bits);
44 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
46 static enum uv_system_type uv_system_type;
47 static u64 gru_start_paddr, gru_end_paddr;
48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49 static u64 gru_dist_lmask, gru_dist_umask;
50 static union uvh_apicid uvh_apicid;
52 /* info derived from CPUID */
54 unsigned int apicid_shift;
55 unsigned int apicid_mask;
56 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
57 unsigned int pnode_mask;
58 unsigned int gpa_shift;
59 unsigned int gnode_shift;
62 int uv_min_hub_revision_id;
63 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
64 unsigned int uv_apicid_hibits;
65 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
67 static struct apic apic_x2apic_uv_x;
68 static struct uv_hub_info_s uv_hub_info_node0;
70 /* Set this to use hardware error handler instead of kernel panic */
71 static int disable_uv_undefined_panic = 1;
72 unsigned long uv_undefined(char *str)
74 if (likely(!disable_uv_undefined_panic))
75 panic("UV: error: undefined MMR: %s\n", str);
77 pr_crit("UV: error: undefined MMR: %s\n", str);
78 return ~0ul; /* cause a machine fault */
80 EXPORT_SYMBOL(uv_undefined);
82 static unsigned long __init uv_early_read_mmr(unsigned long addr)
84 unsigned long val, *mmr;
86 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
88 early_iounmap(mmr, sizeof(*mmr));
92 static inline bool is_GRU_range(u64 start, u64 end)
95 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
96 u64 sl = start & gru_dist_lmask; /* base offset bits */
97 u64 eu = end & gru_dist_umask;
98 u64 el = end & gru_dist_lmask;
100 /* Must reside completely within a single GRU range */
101 return (sl == gru_dist_base && el == gru_dist_base &&
102 su >= gru_first_node_paddr &&
103 su <= gru_last_node_paddr &&
106 return start >= gru_start_paddr && end <= gru_end_paddr;
110 static bool uv_is_untracked_pat_range(u64 start, u64 end)
112 return is_ISA_range(start, end) || is_GRU_range(start, end);
115 static int __init early_get_pnodeid(void)
117 union uvh_node_id_u node_id;
118 union uvh_rh_gam_config_mmr_u m_n_config;
121 /* Currently, all blades have same revision number */
122 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
123 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
124 uv_min_hub_revision_id = node_id.s.revision;
126 switch (node_id.s.part_number) {
127 case UV2_HUB_PART_NUMBER:
128 case UV2_HUB_PART_NUMBER_X:
129 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
131 case UV3_HUB_PART_NUMBER:
132 case UV3_HUB_PART_NUMBER_X:
133 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
135 case UV4_HUB_PART_NUMBER:
136 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
137 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
141 uv_hub_info->hub_revision = uv_min_hub_revision_id;
142 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
143 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
144 uv_cpuid.gpa_shift = 46; /* default unless changed */
146 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
147 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
148 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
152 /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
153 #define SMT_LEVEL 0 /* leaf 0xb SMT level */
154 #define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */
157 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
158 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
160 static void set_x2apic_bits(void)
162 unsigned int eax, ebx, ecx, edx, sub_index;
163 unsigned int sid_shift;
165 cpuid(0, &eax, &ebx, &ecx, &edx);
167 pr_info("UV: CPU does not have CPUID.11\n");
170 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
171 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
172 pr_info("UV: CPUID.11 not implemented\n");
175 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
178 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
179 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
180 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
184 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
185 uv_cpuid.apicid_shift = 0;
186 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
187 uv_cpuid.socketid_shift = sid_shift;
190 static void __init early_get_apic_socketid_shift(void)
192 if (is_uv2_hub() || is_uv3_hub())
193 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
197 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
198 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
199 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
200 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
204 * Add an extra bit as dictated by bios to the destination apicid of
205 * interrupts potentially passing through the UV HUB. This prevents
206 * a deadlock between interrupts and IO port operations.
208 static void __init uv_set_apicid_hibit(void)
210 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
214 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
216 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
220 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
225 if (strncmp(oem_id, "SGI", 3) != 0)
229 pr_err("UV: NUMA is off, disabling UV support\n");
233 /* Setup early hub type field in uv_hub_info for Node 0 */
234 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
237 * Determine UV arch type.
240 * SGI3: UV300 (truncated to 4 chars because of different varieties)
241 * SGI4: UV400 (truncated to 4 chars because of different varieties)
243 uv_hub_info->hub_revision =
244 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
245 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
246 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
247 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
249 if (uv_hub_info->hub_revision == 0)
252 pnodeid = early_get_pnodeid();
253 early_get_apic_socketid_shift();
254 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
255 x86_platform.nmi_init = uv_nmi_init;
257 if (!strcmp(oem_table_id, "UVX")) { /* most common */
258 uv_system_type = UV_X2APIC;
261 } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
262 uv_system_type = UV_NON_UNIQUE_APIC;
263 __this_cpu_write(x2apic_extra_bits,
264 pnodeid << uvh_apicid.s.pnode_shift);
265 uv_set_apicid_hibit();
268 } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
269 uv_system_type = UV_LEGACY_APIC; /* very small systems */
276 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
277 oem_id, oem_table_id, uv_system_type,
278 uv_min_hub_revision_id, uv_apic);
283 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
284 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
288 enum uv_system_type get_uv_system_type(void)
290 return uv_system_type;
293 int is_uv_system(void)
295 return uv_system_type != UV_NONE;
297 EXPORT_SYMBOL_GPL(is_uv_system);
299 void **__uv_hub_info_list;
300 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
302 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
303 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
305 short uv_possible_blades;
306 EXPORT_SYMBOL_GPL(uv_possible_blades);
308 unsigned long sn_rtc_cycles_per_second;
309 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
311 /* the following values are used for the per node hub info struct */
312 static __initdata unsigned short *_node_to_pnode;
313 static __initdata unsigned short _min_socket, _max_socket;
314 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
315 static __initdata struct uv_gam_range_entry *uv_gre_table;
316 static __initdata struct uv_gam_parameters *uv_gp_table;
317 static __initdata unsigned short *_socket_to_node;
318 static __initdata unsigned short *_socket_to_pnode;
319 static __initdata unsigned short *_pnode_to_socket;
320 static __initdata struct uv_gam_range_s *_gr_table;
321 #define SOCK_EMPTY ((unsigned short)~0)
323 extern int uv_hub_info_version(void)
325 return UV_HUB_INFO_VERSION;
327 EXPORT_SYMBOL(uv_hub_info_version);
329 /* Build GAM range lookup table */
330 static __init void build_uv_gr_table(void)
332 struct uv_gam_range_entry *gre = uv_gre_table;
333 struct uv_gam_range_s *grt;
334 unsigned long last_limit = 0, ram_limit = 0;
335 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
340 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
341 grt = kzalloc(bytes, GFP_KERNEL);
345 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
346 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
347 if (!ram_limit) { /* mark hole between ram/non-ram */
348 ram_limit = last_limit;
349 last_limit = gre->limit;
353 last_limit = gre->limit;
354 pr_info("UV: extra hole in GAM RE table @%d\n",
355 (int)(gre - uv_gre_table));
358 if (_max_socket < gre->sockid) {
359 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
360 gre->sockid, _max_socket,
361 (int)(gre - uv_gre_table));
364 sid = gre->sockid - _min_socket;
365 if (lsid < sid) { /* new range */
366 grt = &_gr_table[indx];
368 grt->nasid = gre->nasid;
369 grt->limit = last_limit = gre->limit;
374 if (lsid == sid && !ram_limit) { /* update range */
375 if (grt->limit == last_limit) { /* .. if contiguous */
376 grt->limit = last_limit = gre->limit;
380 if (!ram_limit) { /* non-contiguous ram range */
383 grt->nasid = gre->nasid;
384 grt->limit = last_limit = gre->limit;
387 grt++; /* non-contiguous/non-ram */
388 grt->base = grt - _gr_table; /* base is this entry */
389 grt->nasid = gre->nasid;
390 grt->limit = last_limit = gre->limit;
394 /* shorten table if possible */
397 if (i < _gr_table_len) {
400 bytes = i * sizeof(struct uv_gam_range_s);
401 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
408 /* display resultant gam range table */
409 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
411 unsigned long start = gb < 0 ? 0 :
412 (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
414 (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
416 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
417 i, grt->nasid, start, end, gb);
421 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
426 pnode = uv_apicid_to_pnode(phys_apicid);
427 phys_apicid |= uv_apicid_hibits;
428 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
429 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
430 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
432 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
434 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
435 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
436 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
438 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
443 static void uv_send_IPI_one(int cpu, int vector)
445 unsigned long apicid;
448 apicid = per_cpu(x86_cpu_to_apicid, cpu);
449 pnode = uv_apicid_to_pnode(apicid);
450 uv_hub_send_ipi(pnode, apicid, vector);
453 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
457 for_each_cpu(cpu, mask)
458 uv_send_IPI_one(cpu, vector);
461 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
463 unsigned int this_cpu = smp_processor_id();
466 for_each_cpu(cpu, mask) {
468 uv_send_IPI_one(cpu, vector);
472 static void uv_send_IPI_allbutself(int vector)
474 unsigned int this_cpu = smp_processor_id();
477 for_each_online_cpu(cpu) {
479 uv_send_IPI_one(cpu, vector);
483 static void uv_send_IPI_all(int vector)
485 uv_send_IPI_mask(cpu_online_mask, vector);
488 static int uv_apic_id_valid(int apicid)
493 static int uv_apic_id_registered(void)
498 static void uv_init_apic_ldr(void)
503 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
504 const struct cpumask *andmask,
505 unsigned int *apicid)
510 * We're using fixed IRQ delivery, can only return one phys APIC ID.
511 * May as well be the first.
513 for_each_cpu_and(cpu, cpumask, andmask) {
514 if (cpumask_test_cpu(cpu, cpu_online_mask))
518 if (likely(cpu < nr_cpu_ids)) {
519 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
526 static unsigned int x2apic_get_apic_id(unsigned long x)
530 WARN_ON(preemptible() && num_online_cpus() > 1);
531 id = x | __this_cpu_read(x2apic_extra_bits);
536 static unsigned long set_apic_id(unsigned int id)
538 /* CHECKME: Do we need to mask out the xapic extra bits? */
542 static unsigned int uv_read_apic_id(void)
544 return x2apic_get_apic_id(apic_read(APIC_ID));
547 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
549 return uv_read_apic_id() >> index_msb;
552 static void uv_send_IPI_self(int vector)
554 apic_write(APIC_SELF_IPI, vector);
557 static int uv_probe(void)
559 return apic == &apic_x2apic_uv_x;
562 static struct apic apic_x2apic_uv_x __ro_after_init = {
564 .name = "UV large system",
566 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
567 .apic_id_valid = uv_apic_id_valid,
568 .apic_id_registered = uv_apic_id_registered,
570 .irq_delivery_mode = dest_Fixed,
571 .irq_dest_mode = 0, /* physical */
573 .target_cpus = online_target_cpus,
575 .dest_logical = APIC_DEST_LOGICAL,
576 .check_apicid_used = NULL,
578 .vector_allocation_domain = default_vector_allocation_domain,
579 .init_apic_ldr = uv_init_apic_ldr,
581 .ioapic_phys_id_map = NULL,
582 .setup_apic_routing = NULL,
583 .cpu_present_to_apicid = default_cpu_present_to_apicid,
584 .apicid_to_cpu_present = NULL,
585 .check_phys_apicid_present = default_check_phys_apicid_present,
586 .phys_pkg_id = uv_phys_pkg_id,
588 .get_apic_id = x2apic_get_apic_id,
589 .set_apic_id = set_apic_id,
591 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
593 .send_IPI = uv_send_IPI_one,
594 .send_IPI_mask = uv_send_IPI_mask,
595 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
596 .send_IPI_allbutself = uv_send_IPI_allbutself,
597 .send_IPI_all = uv_send_IPI_all,
598 .send_IPI_self = uv_send_IPI_self,
600 .wakeup_secondary_cpu = uv_wakeup_secondary,
601 .inquire_remote_apic = NULL,
603 .read = native_apic_msr_read,
604 .write = native_apic_msr_write,
605 .eoi_write = native_apic_msr_eoi_write,
606 .icr_read = native_x2apic_icr_read,
607 .icr_write = native_x2apic_icr_write,
608 .wait_icr_idle = native_x2apic_wait_icr_idle,
609 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
612 static void set_x2apic_extra_bits(int pnode)
614 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
617 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
618 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
620 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
622 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
623 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
624 unsigned long m_redirect;
625 unsigned long m_overlay;
628 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
631 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
632 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
635 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
636 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
639 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
640 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
643 alias.v = uv_read_local_mmr(m_overlay);
644 if (alias.s.enable && alias.s.base == 0) {
645 *size = (1UL << alias.s.m_alias);
646 redirect.v = uv_read_local_mmr(m_redirect);
647 *base = (unsigned long)redirect.s.dest_base
655 enum map_type {map_wb, map_uc};
657 static __init void map_high(char *id, unsigned long base, int pshift,
658 int bshift, int max_pnode, enum map_type map_type)
660 unsigned long bytes, paddr;
662 paddr = base << pshift;
663 bytes = (1UL << bshift) * (max_pnode + 1);
665 pr_info("UV: Map %s_HI base address NULL\n", id);
668 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
669 if (map_type == map_uc)
670 init_extra_mapping_uc(paddr, bytes);
672 init_extra_mapping_wb(paddr, bytes);
675 static __init void map_gru_distributed(unsigned long c)
677 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
683 /* only base bits 42:28 relevant in dist mode */
684 gru_dist_base = gru.v & 0x000007fff0000000UL;
685 if (!gru_dist_base) {
686 pr_info("UV: Map GRU_DIST base address NULL\n");
689 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
690 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
691 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
692 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
693 for_each_online_node(nid) {
694 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
696 init_extra_mapping_wb(paddr, bytes);
697 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
698 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
700 /* Save upper (63:M) bits of address only for is_GRU_range */
701 gru_first_node_paddr &= gru_dist_umask;
702 gru_last_node_paddr &= gru_dist_umask;
703 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
704 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
707 static __init void map_gru_high(int max_pnode)
709 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
710 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
711 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
714 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
716 pr_info("UV: GRU disabled\n");
720 if (is_uv3_hub() && gru.s3.mode) {
721 map_gru_distributed(gru.v);
724 base = (gru.v & mask) >> shift;
725 map_high("GRU", base, shift, shift, max_pnode, map_wb);
726 gru_start_paddr = ((u64)base << shift);
727 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
730 static __init void map_mmr_high(int max_pnode)
732 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
733 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
735 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
737 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
739 pr_info("UV: MMR disabled\n");
743 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
744 * and REDIRECT MMR regs are exactly the same on UV3.
746 struct mmioh_config {
747 unsigned long overlay;
748 unsigned long redirect;
752 static __initdata struct mmioh_config mmiohs[] = {
754 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
755 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
759 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
760 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
765 /* UV3 & UV4 have identical MMIOH overlay configs */
766 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
768 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
771 int i, n, shift, m_io, max_io;
772 int nasid, lnasid, fi, li;
775 id = mmiohs[index].id;
776 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
777 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
778 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
779 if (!overlay.s3.enable) {
780 pr_info("UV: %s disabled\n", id);
784 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
785 base = (unsigned long)overlay.s3.base;
786 m_io = overlay.s3.m_io;
787 mmr = mmiohs[index].redirect;
788 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
789 min_pnode *= 2; /* convert to NASID */
791 max_io = lnasid = fi = li = -1;
793 for (i = 0; i < n; i++) {
794 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
796 redirect.v = uv_read_local_mmr(mmr + i * 8);
797 nasid = redirect.s3.nasid;
798 if (nasid < min_pnode || max_pnode < nasid)
799 nasid = -1; /* invalid NASID */
801 if (nasid == lnasid) {
803 if (i != n-1) /* last entry check */
807 /* check if we have a cached (or last) redirect to print */
808 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
809 unsigned long addr1, addr2;
819 addr1 = (base << shift) +
821 addr2 = (base << shift) +
822 (l + 1) * (1ULL << m_io);
823 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
824 id, fi, li, lnasid, addr1, addr2);
832 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
833 id, base, shift, m_io, max_io);
836 map_high(id, base, shift, m_io, max_io, map_uc);
839 static __init void map_mmioh_high(int min_pnode, int max_pnode)
841 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
842 unsigned long mmr, base;
843 int shift, enable, m_io, n_io;
845 if (is_uv3_hub() || is_uv4_hub()) {
846 /* Map both MMIOH Regions */
847 map_mmioh_high_uv3(0, min_pnode, max_pnode);
848 map_mmioh_high_uv3(1, min_pnode, max_pnode);
853 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
854 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
855 mmioh.v = uv_read_local_mmr(mmr);
856 enable = !!mmioh.s1.enable;
857 base = mmioh.s1.base;
858 m_io = mmioh.s1.m_io;
859 n_io = mmioh.s1.n_io;
860 } else if (is_uv2_hub()) {
861 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
862 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
863 mmioh.v = uv_read_local_mmr(mmr);
864 enable = !!mmioh.s2.enable;
865 base = mmioh.s2.base;
866 m_io = mmioh.s2.m_io;
867 n_io = mmioh.s2.n_io;
872 max_pnode &= (1 << n_io) - 1;
874 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
875 base, shift, m_io, n_io, max_pnode);
876 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
878 pr_info("UV: MMIOH disabled\n");
882 static __init void map_low_mmrs(void)
884 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
885 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
888 static __init void uv_rtc_init(void)
893 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
895 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
897 "unable to determine platform RTC clock frequency, "
899 /* BIOS gives wrong value for clock freq. so guess */
900 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
902 sn_rtc_cycles_per_second = ticks_per_sec;
906 * percpu heartbeat timer
908 static void uv_heartbeat(unsigned long ignored)
910 struct timer_list *timer = &uv_scir_info->timer;
911 unsigned char bits = uv_scir_info->state;
913 /* flip heartbeat bit */
914 bits ^= SCIR_CPU_HEARTBEAT;
916 /* is this cpu idle? */
917 if (idle_cpu(raw_smp_processor_id()))
918 bits &= ~SCIR_CPU_ACTIVITY;
920 bits |= SCIR_CPU_ACTIVITY;
922 /* update system controller interface reg */
923 uv_set_scir_bits(bits);
925 /* enable next timer period */
926 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
929 static int uv_heartbeat_enable(unsigned int cpu)
931 while (!uv_cpu_scir_info(cpu)->enabled) {
932 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
934 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
935 setup_pinned_timer(timer, uv_heartbeat, cpu);
936 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
937 add_timer_on(timer, cpu);
938 uv_cpu_scir_info(cpu)->enabled = 1;
940 /* also ensure that boot cpu is enabled */
946 #ifdef CONFIG_HOTPLUG_CPU
947 static int uv_heartbeat_disable(unsigned int cpu)
949 if (uv_cpu_scir_info(cpu)->enabled) {
950 uv_cpu_scir_info(cpu)->enabled = 0;
951 del_timer(&uv_cpu_scir_info(cpu)->timer);
953 uv_set_cpu_scir_bits(cpu, 0xff);
957 static __init void uv_scir_register_cpu_notifier(void)
959 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
960 uv_heartbeat_enable, uv_heartbeat_disable);
963 #else /* !CONFIG_HOTPLUG_CPU */
965 static __init void uv_scir_register_cpu_notifier(void)
969 static __init int uv_init_heartbeat(void)
974 for_each_online_cpu(cpu)
975 uv_heartbeat_enable(cpu);
979 late_initcall(uv_init_heartbeat);
981 #endif /* !CONFIG_HOTPLUG_CPU */
983 /* Direct Legacy VGA I/O traffic to designated IOH */
984 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
985 unsigned int command_bits, u32 flags)
989 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
990 pdev->devfn, decode, command_bits, flags);
992 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
995 if ((command_bits & PCI_COMMAND_IO) == 0)
998 domain = pci_domain_nr(pdev->bus);
999 bus = pdev->bus->number;
1001 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1002 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
1008 * Called on each cpu to initialize the per_cpu UV data area.
1009 * FIXME: hotplug not supported yet
1011 void uv_cpu_init(void)
1013 /* CPU 0 initialization will be done via uv_system_init. */
1014 if (smp_processor_id() == 0)
1017 uv_hub_info->nr_online_cpus++;
1019 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1020 set_x2apic_extra_bits(uv_hub_info->pnode);
1024 unsigned char m_val;
1025 unsigned char n_val;
1026 unsigned char m_shift;
1027 unsigned char n_lshift;
1030 static void get_mn(struct mn *mnp)
1032 union uvh_rh_gam_config_mmr_u m_n_config;
1033 union uv3h_gr0_gam_gr_config_u m_gr_config;
1035 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1036 mnp->n_val = m_n_config.s.n_skt;
1040 } else if (is_uv3_hub()) {
1041 mnp->m_val = m_n_config.s3.m_skt;
1042 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1043 mnp->n_lshift = m_gr_config.s3.m_skt;
1044 } else if (is_uv2_hub()) {
1045 mnp->m_val = m_n_config.s2.m_skt;
1046 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1047 } else if (is_uv1_hub()) {
1048 mnp->m_val = m_n_config.s1.m_skt;
1049 mnp->n_lshift = mnp->m_val;
1051 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1054 void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
1056 struct mn mn = {0}; /* avoid unitialized warnings */
1057 union uvh_node_id_u node_id;
1060 hub_info->m_val = mn.m_val;
1061 hub_info->n_val = mn.n_val;
1062 hub_info->m_shift = mn.m_shift;
1063 hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1065 hub_info->hub_revision = uv_hub_info->hub_revision;
1066 hub_info->pnode_mask = uv_cpuid.pnode_mask;
1067 hub_info->min_pnode = _min_pnode;
1068 hub_info->min_socket = _min_socket;
1069 hub_info->pnode_to_socket = _pnode_to_socket;
1070 hub_info->socket_to_node = _socket_to_node;
1071 hub_info->socket_to_pnode = _socket_to_pnode;
1072 hub_info->gr_table_len = _gr_table_len;
1073 hub_info->gr_table = _gr_table;
1074 hub_info->gpa_mask = mn.m_val ?
1075 (1UL << (mn.m_val + mn.n_val)) - 1 :
1076 (1UL << uv_cpuid.gpa_shift) - 1;
1078 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1079 uv_cpuid.gnode_shift = max_t(unsigned int,
1080 uv_cpuid.gnode_shift, mn.n_val);
1081 hub_info->gnode_extra =
1082 (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1084 hub_info->gnode_upper =
1085 ((unsigned long)hub_info->gnode_extra << mn.m_val);
1088 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1089 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1090 hub_info->global_gru_base = uv_gp_table->gru_base;
1091 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1092 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1093 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1095 hub_info->global_mmr_base =
1096 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1098 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1101 get_lowmem_redirect(
1102 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
1104 hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
1106 /* show system specific info */
1107 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1108 hub_info->n_val, hub_info->m_val,
1109 hub_info->m_shift, hub_info->n_lshift);
1111 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
1112 hub_info->gpa_mask, hub_info->gpa_shift,
1113 hub_info->pnode_mask, hub_info->apic_pnode_shift);
1115 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
1116 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1117 hub_info->global_gru_base, hub_info->global_gru_shift);
1119 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1120 hub_info->gnode_upper, hub_info->gnode_extra);
1123 static void __init decode_gam_params(unsigned long ptr)
1125 uv_gp_table = (struct uv_gam_parameters *)ptr;
1127 pr_info("UV: GAM Params...\n");
1128 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1129 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1130 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1131 uv_gp_table->gpa_shift);
1134 static void __init decode_gam_rng_tbl(unsigned long ptr)
1136 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1137 unsigned long lgre = 0;
1139 int sock_min = 999999, pnode_min = 99999;
1140 int sock_max = -1, pnode_max = -1;
1143 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1145 pr_info("UV: GAM Range Table...\n");
1146 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n",
1147 "Range", "", "Size", "Type", "NASID",
1151 "UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n",
1153 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1154 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1155 ((unsigned long)(gre->limit - lgre)) >>
1156 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1157 gre->type, gre->nasid, gre->sockid, gre->pnode);
1160 if (sock_min > gre->sockid)
1161 sock_min = gre->sockid;
1162 if (sock_max < gre->sockid)
1163 sock_max = gre->sockid;
1164 if (pnode_min > gre->pnode)
1165 pnode_min = gre->pnode;
1166 if (pnode_max < gre->pnode)
1167 pnode_max = gre->pnode;
1169 _min_socket = sock_min;
1170 _max_socket = sock_max;
1171 _min_pnode = pnode_min;
1172 _max_pnode = pnode_max;
1173 _gr_table_len = index;
1175 "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1176 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1179 static int __init decode_uv_systab(void)
1181 struct uv_systab *st;
1184 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1185 return 0; /* No extended UVsystab required */
1188 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1189 int rev = st ? st->revision : 0;
1192 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1193 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1195 "UV: Cannot support UV operations, switching to generic PC\n");
1196 uv_system_type = UV_NONE;
1200 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1201 unsigned long ptr = st->entry[i].offset;
1206 ptr = ptr + (unsigned long)st;
1208 switch (st->entry[i].type) {
1209 case UV_SYSTAB_TYPE_GAM_PARAMS:
1210 decode_gam_params(ptr);
1213 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1214 decode_gam_rng_tbl(ptr);
1222 * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
1223 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1224 * .. being replaced by GAM Range Table
1226 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1230 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1231 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1234 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1236 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1238 uv_pb += hweight64(np);
1240 if (uv_possible_blades != uv_pb)
1241 uv_possible_blades = uv_pb;
1244 static void __init build_socket_tables(void)
1246 struct uv_gam_range_entry *gre = uv_gre_table;
1249 int minsock = _min_socket;
1250 int maxsock = _max_socket;
1251 int minpnode = _min_pnode;
1252 int maxpnode = _max_pnode;
1256 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1257 pr_info("UV: No UVsystab socket table, ignoring\n");
1258 return; /* not required */
1261 "UV: Error: UVsystab address translations not available!\n");
1265 /* build socket id -> node id, pnode */
1266 num = maxsock - minsock + 1;
1267 bytes = num * sizeof(_socket_to_node[0]);
1268 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1269 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1271 nump = maxpnode - minpnode + 1;
1272 bytes = nump * sizeof(_pnode_to_socket[0]);
1273 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1274 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1276 for (i = 0; i < num; i++)
1277 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1279 for (i = 0; i < nump; i++)
1280 _pnode_to_socket[i] = SOCK_EMPTY;
1282 /* fill in pnode/node/addr conversion list values */
1283 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1284 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1285 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1287 i = gre->sockid - minsock;
1288 if (_socket_to_pnode[i] != SOCK_EMPTY)
1289 continue; /* duplicate */
1290 _socket_to_pnode[i] = gre->pnode;
1292 i = gre->pnode - minpnode;
1293 _pnode_to_socket[i] = gre->sockid;
1296 "UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1297 gre->sockid, gre->type, gre->nasid,
1298 _socket_to_pnode[gre->sockid - minsock],
1299 _pnode_to_socket[gre->pnode - minpnode]);
1302 /* Set socket -> node values */
1304 for_each_present_cpu(cpu) {
1305 int nid = cpu_to_node(cpu);
1311 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1312 sockid = apicid >> uv_cpuid.socketid_shift;
1313 _socket_to_node[sockid - minsock] = nid;
1314 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1315 sockid, apicid, nid);
1318 /* Setup physical blade to pnode translation from GAM Range Table */
1319 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1320 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1321 BUG_ON(!_node_to_pnode);
1323 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1324 unsigned short sockid;
1326 for (sockid = minsock; sockid <= maxsock; sockid++) {
1327 if (lnid == _socket_to_node[sockid - minsock]) {
1328 _node_to_pnode[lnid] =
1329 _socket_to_pnode[sockid - minsock];
1333 if (sockid > maxsock) {
1334 pr_err("UV: socket for node %d not found!\n", lnid);
1340 * If socket id == pnode or socket id == node for all nodes,
1341 * system runs faster by removing corresponding conversion table.
1343 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1345 for (i = 0; i < num; i++)
1346 if (_socket_to_node[i] == SOCK_EMPTY ||
1347 i != _socket_to_node[i])
1350 kfree(_socket_to_node);
1351 _socket_to_node = NULL;
1352 pr_info("UV: 1:1 socket_to_node table removed\n");
1355 if (minsock == minpnode) {
1356 for (i = 0; i < num; i++)
1357 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1358 _socket_to_pnode[i] != i + minpnode)
1361 kfree(_socket_to_pnode);
1362 _socket_to_pnode = NULL;
1363 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1368 void __init uv_system_init(void)
1370 struct uv_hub_info_s hub_info = {0};
1371 int bytes, cpu, nodeid;
1372 unsigned short min_pnode = 9999, max_pnode = 0;
1373 char *hub = is_uv4_hub() ? "UV400" :
1374 is_uv3_hub() ? "UV300" :
1375 is_uv2_hub() ? "UV2000/3000" :
1376 is_uv1_hub() ? "UV100/1000" : NULL;
1379 pr_err("UV: Unknown/unsupported UV hub\n");
1382 pr_info("UV: Found %s hub\n", hub);
1386 uv_bios_init(); /* get uv_systab for decoding */
1387 if (decode_uv_systab() < 0)
1388 return; /* UVsystab problem, abort UV init */
1389 build_socket_tables();
1390 build_uv_gr_table();
1391 uv_init_hub_info(&hub_info);
1392 uv_possible_blades = num_possible_nodes();
1393 if (!_node_to_pnode)
1394 boot_init_possible_blades(&hub_info);
1396 /* uv_num_possible_blades() is really the hub count */
1397 pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1398 uv_num_possible_blades(),
1399 num_possible_nodes(),
1400 num_possible_cpus());
1402 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1403 &sn_region_size, &system_serial_number);
1404 hub_info.coherency_domain_number = sn_coherency_id;
1407 bytes = sizeof(void *) * uv_num_possible_blades();
1408 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1409 BUG_ON(!__uv_hub_info_list);
1411 bytes = sizeof(struct uv_hub_info_s);
1412 for_each_node(nodeid) {
1413 struct uv_hub_info_s *new_hub;
1415 if (__uv_hub_info_list[nodeid]) {
1416 pr_err("UV: Node %d UV HUB already initialized!?\n",
1421 /* Allocate new per hub info list */
1422 new_hub = (nodeid == 0) ?
1423 &uv_hub_info_node0 :
1424 kzalloc_node(bytes, GFP_KERNEL, nodeid);
1426 __uv_hub_info_list[nodeid] = new_hub;
1427 new_hub = uv_hub_info_list(nodeid);
1429 *new_hub = hub_info;
1431 /* Use information from GAM table if available */
1433 new_hub->pnode = _node_to_pnode[nodeid];
1434 else /* Fill in during cpu loop */
1435 new_hub->pnode = 0xffff;
1436 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1437 new_hub->memory_nid = -1;
1438 new_hub->nr_possible_cpus = 0;
1439 new_hub->nr_online_cpus = 0;
1442 /* Initialize per cpu info */
1443 for_each_possible_cpu(cpu) {
1444 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1446 unsigned short pnode;
1448 nodeid = cpu_to_node(cpu);
1449 numa_node_id = numa_cpu_node(cpu);
1450 pnode = uv_apicid_to_pnode(apicid);
1452 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1453 uv_cpu_info_per(cpu)->blade_cpu_id =
1454 uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1455 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1456 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1457 if (nodeid != numa_node_id && /* init memoryless node */
1458 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1459 uv_hub_info_list(numa_node_id)->pnode = pnode;
1460 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1461 uv_cpu_hub_info(cpu)->pnode = pnode;
1462 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1465 for_each_node(nodeid) {
1466 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1468 /* Add pnode info for pre-GAM list nodes without cpus */
1469 if (pnode == 0xffff) {
1470 unsigned long paddr;
1472 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1473 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1474 uv_hub_info_list(nodeid)->pnode = pnode;
1476 min_pnode = min(pnode, min_pnode);
1477 max_pnode = max(pnode, max_pnode);
1478 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1480 uv_hub_info_list(nodeid)->pnode,
1481 uv_hub_info_list(nodeid)->nr_possible_cpus);
1484 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1485 map_gru_high(max_pnode);
1486 map_mmr_high(max_pnode);
1487 map_mmioh_high(min_pnode, max_pnode);
1491 uv_scir_register_cpu_notifier();
1492 proc_mkdir("sgi_uv", NULL);
1494 /* register Legacy VGA I/O redirection handler */
1495 pci_register_set_vga_state(uv_set_vga_state);
1498 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1499 * EFI is not enabled in the kdump kernel.
1501 if (is_kdump_kernel())
1502 reboot_type = BOOT_ACPI;
1505 apic_driver(apic_x2apic_uv_x);