arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/export.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 static enum uv_system_type      uv_system_type;
  45 static u64                      gru_start_paddr, gru_end_paddr;
  46 static u64                      gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  47 static u64                      gru_dist_lmask, gru_dist_umask;
  48 static union uvh_apicid         uvh_apicid;
  49
  50 /* Information derived from CPUID: */
  51 static struct {
  52         unsigned int apicid_shift;
  53         unsigned int apicid_mask;
  54         unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
  55         unsigned int pnode_mask;
  56         unsigned int gpa_shift;
  57         unsigned int gnode_shift;
  58 } uv_cpuid;
  59
  60 int uv_min_hub_revision_id;
  61 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  62
  63 unsigned int uv_apicid_hibits;
  64 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  65
  66 static struct apic apic_x2apic_uv_x;
  67 static struct uv_hub_info_s uv_hub_info_node0;
  68
  69 /* Set this to use hardware error handler instead of kernel panic: */
  70 static int disable_uv_undefined_panic = 1;
  71
  72 unsigned long uv_undefined(char *str)
  73 {
  74         if (likely(!disable_uv_undefined_panic))
  75                 panic("UV: error: undefined MMR: %s\n", str);
  76         else
  77                 pr_crit("UV: error: undefined MMR: %s\n", str);
  78
  79         /* Cause a machine fault: */
  80         return ~0ul;
  81 }
  82 EXPORT_SYMBOL(uv_undefined);
  83
  84 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  85 {
  86         unsigned long val, *mmr;
  87
  88         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  89         val = *mmr;
  90         early_iounmap(mmr, sizeof(*mmr));
  91
  92         return val;
  93 }
  94
  95 static inline bool is_GRU_range(u64 start, u64 end)
  96 {
  97         if (gru_dist_base) {
  98                 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
  99                 u64 sl = start & gru_dist_lmask; /* Base offset bits */
 100                 u64 eu = end & gru_dist_umask;
 101                 u64 el = end & gru_dist_lmask;
 102
 103                 /* Must reside completely within a single GRU range: */
 104                 return (sl == gru_dist_base && el == gru_dist_base &&
 105                         su >= gru_first_node_paddr &&
 106                         su <= gru_last_node_paddr &&
 107                         eu == su);
 108         } else {
 109                 return start >= gru_start_paddr && end <= gru_end_paddr;
 110         }
 111 }
 112
 113 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 114 {
 115         return is_ISA_range(start, end) || is_GRU_range(start, end);
 116 }
 117
 118 static int __init early_get_pnodeid(void)
 119 {
 120         union uvh_node_id_u node_id;
 121         union uvh_rh_gam_config_mmr_u  m_n_config;
 122         int pnode;
 123
 124         /* Currently, all blades have same revision number */
 125         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 126         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 127         uv_min_hub_revision_id = node_id.s.revision;
 128
 129         switch (node_id.s.part_number) {
 130         case UV2_HUB_PART_NUMBER:
 131         case UV2_HUB_PART_NUMBER_X:
 132                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 133                 break;
 134         case UV3_HUB_PART_NUMBER:
 135         case UV3_HUB_PART_NUMBER_X:
 136                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 137                 break;
 138         case UV4_HUB_PART_NUMBER:
 139                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 140                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
 141                 break;
 142         }
 143
 144         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 145         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 146         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 147         uv_cpuid.gpa_shift = 46;        /* Default unless changed */
 148
 149         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 150                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 151                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 152         return pnode;
 153 }
 154
 155 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 156
 157 #define SMT_LEVEL                       0       /* Leaf 0xb SMT level */
 158 #define INVALID_TYPE                    0       /* Leaf 0xb sub-leaf types */
 159 #define SMT_TYPE                        1
 160 #define CORE_TYPE                       2
 161 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 162 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 163
 164 static void set_x2apic_bits(void)
 165 {
 166         unsigned int eax, ebx, ecx, edx, sub_index;
 167         unsigned int sid_shift;
 168
 169         cpuid(0, &eax, &ebx, &ecx, &edx);
 170         if (eax < 0xb) {
 171                 pr_info("UV: CPU does not have CPUID.11\n");
 172                 return;
 173         }
 174
 175         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 176         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 177                 pr_info("UV: CPUID.11 not implemented\n");
 178                 return;
 179         }
 180
 181         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 182         sub_index = 1;
 183         do {
 184                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 185                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 186                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 187                         break;
 188                 }
 189                 sub_index++;
 190         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 191
 192         uv_cpuid.apicid_shift   = 0;
 193         uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
 194         uv_cpuid.socketid_shift = sid_shift;
 195 }
 196
 197 static void __init early_get_apic_socketid_shift(void)
 198 {
 199         if (is_uv2_hub() || is_uv3_hub())
 200                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 201
 202         set_x2apic_bits();
 203
 204         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 205         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 206 }
 207
 208 /*
 209  * Add an extra bit as dictated by bios to the destination apicid of
 210  * interrupts potentially passing through the UV HUB.  This prevents
 211  * a deadlock between interrupts and IO port operations.
 212  */
 213 static void __init uv_set_apicid_hibit(void)
 214 {
 215         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 216
 217         if (is_uv1_hub()) {
 218                 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 219                 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 220         }
 221 }
 222
 223 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 224 {
 225         int pnodeid;
 226         int uv_apic;
 227
 228         if (strncmp(oem_id, "SGI", 3) != 0)
 229                 return 0;
 230
 231         if (numa_off) {
 232                 pr_err("UV: NUMA is off, disabling UV support\n");
 233                 return 0;
 234         }
 235
 236         /* Set up early hub type field in uv_hub_info for Node 0 */
 237         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 238
 239         /*
 240          * Determine UV arch type.
 241          *   SGI:  UV100/1000
 242          *   SGI2: UV2000/3000
 243          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 244          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 245          */
 246         uv_hub_info->hub_revision =
 247                 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 248                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 249                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 250                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 251
 252         if (uv_hub_info->hub_revision == 0)
 253                 goto badbios;
 254
 255         pnodeid = early_get_pnodeid();
 256         early_get_apic_socketid_shift();
 257
 258         x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
 259         x86_platform.nmi_init = uv_nmi_init;
 260
 261         if (!strcmp(oem_table_id, "UVX")) {
 262                 /* This is the most common hardware variant: */
 263                 uv_system_type = UV_X2APIC;
 264                 uv_apic = 0;
 265
 266         } else if (!strcmp(oem_table_id, "UVH")) {
 267                 /* Only UV1 systems: */
 268                 uv_system_type = UV_NON_UNIQUE_APIC;
 269                 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
 270                 uv_set_apicid_hibit();
 271                 uv_apic = 1;
 272
 273         } else if (!strcmp(oem_table_id, "UVL")) {
 274                 /* Only used for very small systems:  */
 275                 uv_system_type = UV_LEGACY_APIC;
 276                 uv_apic = 0;
 277
 278         } else {
 279                 goto badbios;
 280         }
 281
 282         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
 283
 284         return uv_apic;
 285
 286 badbios:
 287         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 288         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 289         BUG();
 290 }
 291
 292 enum uv_system_type get_uv_system_type(void)
 293 {
 294         return uv_system_type;
 295 }
 296
 297 int is_uv_system(void)
 298 {
 299         return uv_system_type != UV_NONE;
 300 }
 301 EXPORT_SYMBOL_GPL(is_uv_system);
 302
 303 void **__uv_hub_info_list;
 304 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 305
 306 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 307 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 308
 309 short uv_possible_blades;
 310 EXPORT_SYMBOL_GPL(uv_possible_blades);
 311
 312 unsigned long sn_rtc_cycles_per_second;
 313 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 314
 315 /* The following values are used for the per node hub info struct */
 316 static __initdata unsigned short                *_node_to_pnode;
 317 static __initdata unsigned short                _min_socket, _max_socket;
 318 static __initdata unsigned short                _min_pnode, _max_pnode, _gr_table_len;
 319 static __initdata struct uv_gam_range_entry     *uv_gre_table;
 320 static __initdata struct uv_gam_parameters      *uv_gp_table;
 321 static __initdata unsigned short                *_socket_to_node;
 322 static __initdata unsigned short                *_socket_to_pnode;
 323 static __initdata unsigned short                *_pnode_to_socket;
 324
 325 static __initdata struct uv_gam_range_s         *_gr_table;
 326
 327 #define SOCK_EMPTY      ((unsigned short)~0)
 328
 329 extern int uv_hub_info_version(void)
 330 {
 331         return UV_HUB_INFO_VERSION;
 332 }
 333 EXPORT_SYMBOL(uv_hub_info_version);
 334
 335 /* Build GAM range lookup table: */
 336 static __init void build_uv_gr_table(void)
 337 {
 338         struct uv_gam_range_entry *gre = uv_gre_table;
 339         struct uv_gam_range_s *grt;
 340         unsigned long last_limit = 0, ram_limit = 0;
 341         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
 342
 343         if (!gre)
 344                 return;
 345
 346         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 347         grt = kzalloc(bytes, GFP_KERNEL);
 348         BUG_ON(!grt);
 349         _gr_table = grt;
 350
 351         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 352                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 353                         if (!ram_limit) {
 354                                 /* Mark hole between RAM/non-RAM: */
 355                                 ram_limit = last_limit;
 356                                 last_limit = gre->limit;
 357                                 lsid++;
 358                                 continue;
 359                         }
 360                         last_limit = gre->limit;
 361                         pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
 362                         continue;
 363                 }
 364                 if (_max_socket < gre->sockid) {
 365                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
 366                         continue;
 367                 }
 368                 sid = gre->sockid - _min_socket;
 369                 if (lsid < sid) {
 370                         /* New range: */
 371                         grt = &_gr_table[indx];
 372                         grt->base = lindx;
 373                         grt->nasid = gre->nasid;
 374                         grt->limit = last_limit = gre->limit;
 375                         lsid = sid;
 376                         lindx = indx++;
 377                         continue;
 378                 }
 379                 /* Update range: */
 380                 if (lsid == sid && !ram_limit) {
 381                         /* .. if contiguous: */
 382                         if (grt->limit == last_limit) {
 383                                 grt->limit = last_limit = gre->limit;
 384                                 continue;
 385                         }
 386                 }
 387                 /* Non-contiguous RAM range: */
 388                 if (!ram_limit) {
 389                         grt++;
 390                         grt->base = lindx;
 391                         grt->nasid = gre->nasid;
 392                         grt->limit = last_limit = gre->limit;
 393                         continue;
 394                 }
 395                 /* Non-contiguous/non-RAM: */
 396                 grt++;
 397                 /* base is this entry */
 398                 grt->base = grt - _gr_table;
 399                 grt->nasid = gre->nasid;
 400                 grt->limit = last_limit = gre->limit;
 401                 lsid++;
 402         }
 403
 404         /* Shorten table if possible */
 405         grt++;
 406         i = grt - _gr_table;
 407         if (i < _gr_table_len) {
 408                 void *ret;
 409
 410                 bytes = i * sizeof(struct uv_gam_range_s);
 411                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 412                 if (ret) {
 413                         _gr_table = ret;
 414                         _gr_table_len = i;
 415                 }
 416         }
 417
 418         /* Display resultant GAM range table: */
 419         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 420                 unsigned long start, end;
 421                 int gb = grt->base;
 422
 423                 start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 424                 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 425
 426                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
 427         }
 428 }
 429
 430 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 431 {
 432         unsigned long val;
 433         int pnode;
 434
 435         pnode = uv_apicid_to_pnode(phys_apicid);
 436         phys_apicid |= uv_apicid_hibits;
 437
 438         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 439             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 440             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 441             APIC_DM_INIT;
 442
 443         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 444
 445         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 446             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 447             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 448             APIC_DM_STARTUP;
 449
 450         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 451
 452         return 0;
 453 }
 454
 455 static void uv_send_IPI_one(int cpu, int vector)
 456 {
 457         unsigned long apicid;
 458         int pnode;
 459
 460         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 461         pnode = uv_apicid_to_pnode(apicid);
 462         uv_hub_send_ipi(pnode, apicid, vector);
 463 }
 464
 465 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 466 {
 467         unsigned int cpu;
 468
 469         for_each_cpu(cpu, mask)
 470                 uv_send_IPI_one(cpu, vector);
 471 }
 472
 473 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 474 {
 475         unsigned int this_cpu = smp_processor_id();
 476         unsigned int cpu;
 477
 478         for_each_cpu(cpu, mask) {
 479                 if (cpu != this_cpu)
 480                         uv_send_IPI_one(cpu, vector);
 481         }
 482 }
 483
 484 static void uv_send_IPI_allbutself(int vector)
 485 {
 486         unsigned int this_cpu = smp_processor_id();
 487         unsigned int cpu;
 488
 489         for_each_online_cpu(cpu) {
 490                 if (cpu != this_cpu)
 491                         uv_send_IPI_one(cpu, vector);
 492         }
 493 }
 494
 495 static void uv_send_IPI_all(int vector)
 496 {
 497         uv_send_IPI_mask(cpu_online_mask, vector);
 498 }
 499
 500 static int uv_apic_id_valid(int apicid)
 501 {
 502         return 1;
 503 }
 504
 505 static int uv_apic_id_registered(void)
 506 {
 507         return 1;
 508 }
 509
 510 static void uv_init_apic_ldr(void)
 511 {
 512 }
 513
 514 static int
 515 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 516                           const struct cpumask *andmask,
 517                           unsigned int *apicid)
 518 {
 519         int unsigned cpu;
 520
 521         /*
 522          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 523          * May as well be the first.
 524          */
 525         for_each_cpu_and(cpu, cpumask, andmask) {
 526                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 527                         break;
 528         }
 529
 530         if (likely(cpu < nr_cpu_ids)) {
 531                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 532                 return 0;
 533         }
 534
 535         return -EINVAL;
 536 }
 537
 538 static unsigned int x2apic_get_apic_id(unsigned long x)
 539 {
 540         unsigned int id;
 541
 542         WARN_ON(preemptible() && num_online_cpus() > 1);
 543         id = x | __this_cpu_read(x2apic_extra_bits);
 544
 545         return id;
 546 }
 547
 548 static unsigned long set_apic_id(unsigned int id)
 549 {
 550         /* CHECKME: Do we need to mask out the xapic extra bits? */
 551         return id;
 552 }
 553
 554 static unsigned int uv_read_apic_id(void)
 555 {
 556         return x2apic_get_apic_id(apic_read(APIC_ID));
 557 }
 558
 559 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 560 {
 561         return uv_read_apic_id() >> index_msb;
 562 }
 563
 564 static void uv_send_IPI_self(int vector)
 565 {
 566         apic_write(APIC_SELF_IPI, vector);
 567 }
 568
 569 static int uv_probe(void)
 570 {
 571         return apic == &apic_x2apic_uv_x;
 572 }
 573
 574 static struct apic apic_x2apic_uv_x __ro_after_init = {
 575
 576         .name                           = "UV large system",
 577         .probe                          = uv_probe,
 578         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 579         .apic_id_valid                  = uv_apic_id_valid,
 580         .apic_id_registered             = uv_apic_id_registered,
 581
 582         .irq_delivery_mode              = dest_Fixed,
 583         .irq_dest_mode                  = 0, /* Physical */
 584
 585         .target_cpus                    = online_target_cpus,
 586         .disable_esr                    = 0,
 587         .dest_logical                   = APIC_DEST_LOGICAL,
 588         .check_apicid_used              = NULL,
 589
 590         .vector_allocation_domain       = default_vector_allocation_domain,
 591         .init_apic_ldr                  = uv_init_apic_ldr,
 592
 593         .ioapic_phys_id_map             = NULL,
 594         .setup_apic_routing             = NULL,
 595         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 596         .apicid_to_cpu_present          = NULL,
 597         .check_phys_apicid_present      = default_check_phys_apicid_present,
 598         .phys_pkg_id                    = uv_phys_pkg_id,
 599
 600         .get_apic_id                    = x2apic_get_apic_id,
 601         .set_apic_id                    = set_apic_id,
 602
 603         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 604
 605         .send_IPI                       = uv_send_IPI_one,
 606         .send_IPI_mask                  = uv_send_IPI_mask,
 607         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 608         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 609         .send_IPI_all                   = uv_send_IPI_all,
 610         .send_IPI_self                  = uv_send_IPI_self,
 611
 612         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 613         .inquire_remote_apic            = NULL,
 614
 615         .read                           = native_apic_msr_read,
 616         .write                          = native_apic_msr_write,
 617         .eoi_write                      = native_apic_msr_eoi_write,
 618         .icr_read                       = native_x2apic_icr_read,
 619         .icr_write                      = native_x2apic_icr_write,
 620         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 621         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 622 };
 623
 624 static void set_x2apic_extra_bits(int pnode)
 625 {
 626         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 627 }
 628
 629 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 630 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 631
 632 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 633 {
 634         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 635         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 636         unsigned long m_redirect;
 637         unsigned long m_overlay;
 638         int i;
 639
 640         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 641                 switch (i) {
 642                 case 0:
 643                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 644                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 645                         break;
 646                 case 1:
 647                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 648                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 649                         break;
 650                 case 2:
 651                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 652                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 653                         break;
 654                 }
 655                 alias.v = uv_read_local_mmr(m_overlay);
 656                 if (alias.s.enable && alias.s.base == 0) {
 657                         *size = (1UL << alias.s.m_alias);
 658                         redirect.v = uv_read_local_mmr(m_redirect);
 659                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 660                         return;
 661                 }
 662         }
 663         *base = *size = 0;
 664 }
 665
 666 enum map_type {map_wb, map_uc};
 667
 668 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
 669 {
 670         unsigned long bytes, paddr;
 671
 672         paddr = base << pshift;
 673         bytes = (1UL << bshift) * (max_pnode + 1);
 674         if (!paddr) {
 675                 pr_info("UV: Map %s_HI base address NULL\n", id);
 676                 return;
 677         }
 678         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 679         if (map_type == map_uc)
 680                 init_extra_mapping_uc(paddr, bytes);
 681         else
 682                 init_extra_mapping_wb(paddr, bytes);
 683 }
 684
 685 static __init void map_gru_distributed(unsigned long c)
 686 {
 687         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 688         u64 paddr;
 689         unsigned long bytes;
 690         int nid;
 691
 692         gru.v = c;
 693
 694         /* Only base bits 42:28 relevant in dist mode */
 695         gru_dist_base = gru.v & 0x000007fff0000000UL;
 696         if (!gru_dist_base) {
 697                 pr_info("UV: Map GRU_DIST base address NULL\n");
 698                 return;
 699         }
 700
 701         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 702         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 703         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 704         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 705
 706         for_each_online_node(nid) {
 707                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 708                                 gru_dist_base;
 709                 init_extra_mapping_wb(paddr, bytes);
 710                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 711                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 712         }
 713
 714         /* Save upper (63:M) bits of address only for is_GRU_range */
 715         gru_first_node_paddr &= gru_dist_umask;
 716         gru_last_node_paddr &= gru_dist_umask;
 717
 718         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 719 }
 720
 721 static __init void map_gru_high(int max_pnode)
 722 {
 723         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 724         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 725         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 726         unsigned long base;
 727
 728         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 729         if (!gru.s.enable) {
 730                 pr_info("UV: GRU disabled\n");
 731                 return;
 732         }
 733
 734         if (is_uv3_hub() && gru.s3.mode) {
 735                 map_gru_distributed(gru.v);
 736                 return;
 737         }
 738
 739         base = (gru.v & mask) >> shift;
 740         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 741         gru_start_paddr = ((u64)base << shift);
 742         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 743 }
 744
 745 static __init void map_mmr_high(int max_pnode)
 746 {
 747         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 748         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 749
 750         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 751         if (mmr.s.enable)
 752                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 753         else
 754                 pr_info("UV: MMR disabled\n");
 755 }
 756
 757 /*
 758  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 759  * and REDIRECT MMR regs are exactly the same on UV3.
 760  */
 761 struct mmioh_config {
 762         unsigned long overlay;
 763         unsigned long redirect;
 764         char *id;
 765 };
 766
 767 static __initdata struct mmioh_config mmiohs[] = {
 768         {
 769                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 770                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 771                 "MMIOH0"
 772         },
 773         {
 774                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 775                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 776                 "MMIOH1"
 777         },
 778 };
 779
 780 /* UV3 & UV4 have identical MMIOH overlay configs */
 781 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 782 {
 783         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 784         unsigned long mmr;
 785         unsigned long base;
 786         int i, n, shift, m_io, max_io;
 787         int nasid, lnasid, fi, li;
 788         char *id;
 789
 790         id = mmiohs[index].id;
 791         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 792
 793         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 794         if (!overlay.s3.enable) {
 795                 pr_info("UV: %s disabled\n", id);
 796                 return;
 797         }
 798
 799         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 800         base = (unsigned long)overlay.s3.base;
 801         m_io = overlay.s3.m_io;
 802         mmr = mmiohs[index].redirect;
 803         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 804         /* Convert to NASID: */
 805         min_pnode *= 2;
 806         max_pnode *= 2;
 807         max_io = lnasid = fi = li = -1;
 808
 809         for (i = 0; i < n; i++) {
 810                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 811
 812                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 813                 nasid = redirect.s3.nasid;
 814                 /* Invalid NASID: */
 815                 if (nasid < min_pnode || max_pnode < nasid)
 816                         nasid = -1;
 817
 818                 if (nasid == lnasid) {
 819                         li = i;
 820                         /* Last entry check: */
 821                         if (i != n-1)
 822                                 continue;
 823                 }
 824
 825                 /* Check if we have a cached (or last) redirect to print: */
 826                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 827                         unsigned long addr1, addr2;
 828                         int f, l;
 829
 830                         if (lnasid == -1) {
 831                                 f = l = i;
 832                                 lnasid = nasid;
 833                         } else {
 834                                 f = fi;
 835                                 l = li;
 836                         }
 837                         addr1 = (base << shift) + f * (1ULL << m_io);
 838                         addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
 839                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
 840                         if (max_io < l)
 841                                 max_io = l;
 842                 }
 843                 fi = li = i;
 844                 lnasid = nasid;
 845         }
 846
 847         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
 848
 849         if (max_io >= 0)
 850                 map_high(id, base, shift, m_io, max_io, map_uc);
 851 }
 852
 853 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 854 {
 855         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 856         unsigned long mmr, base;
 857         int shift, enable, m_io, n_io;
 858
 859         if (is_uv3_hub() || is_uv4_hub()) {
 860                 /* Map both MMIOH regions: */
 861                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 862                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 863                 return;
 864         }
 865
 866         if (is_uv1_hub()) {
 867                 mmr     = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 868                 shift   = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 869                 mmioh.v = uv_read_local_mmr(mmr);
 870                 enable  = !!mmioh.s1.enable;
 871                 base    = mmioh.s1.base;
 872                 m_io    = mmioh.s1.m_io;
 873                 n_io    = mmioh.s1.n_io;
 874         } else if (is_uv2_hub()) {
 875                 mmr     = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 876                 shift   = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 877                 mmioh.v = uv_read_local_mmr(mmr);
 878                 enable  = !!mmioh.s2.enable;
 879                 base    = mmioh.s2.base;
 880                 m_io    = mmioh.s2.m_io;
 881                 n_io    = mmioh.s2.n_io;
 882         } else {
 883                 return;
 884         }
 885
 886         if (enable) {
 887                 max_pnode &= (1 << n_io) - 1;
 888                 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
 889                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 890         } else {
 891                 pr_info("UV: MMIOH disabled\n");
 892         }
 893 }
 894
 895 static __init void map_low_mmrs(void)
 896 {
 897         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 898         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 899 }
 900
 901 static __init void uv_rtc_init(void)
 902 {
 903         long status;
 904         u64 ticks_per_sec;
 905
 906         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
 907
 908         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 909                 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
 910
 911                 /* BIOS gives wrong value for clock frequency, so guess: */
 912                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 913         } else {
 914                 sn_rtc_cycles_per_second = ticks_per_sec;
 915         }
 916 }
 917
 918 /*
 919  * percpu heartbeat timer
 920  */
 921 static void uv_heartbeat(unsigned long ignored)
 922 {
 923         struct timer_list *timer = &uv_scir_info->timer;
 924         unsigned char bits = uv_scir_info->state;
 925
 926         /* Flip heartbeat bit: */
 927         bits ^= SCIR_CPU_HEARTBEAT;
 928
 929         /* Is this CPU idle? */
 930         if (idle_cpu(raw_smp_processor_id()))
 931                 bits &= ~SCIR_CPU_ACTIVITY;
 932         else
 933                 bits |= SCIR_CPU_ACTIVITY;
 934
 935         /* Update system controller interface reg: */
 936         uv_set_scir_bits(bits);
 937
 938         /* Enable next timer period: */
 939         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 940 }
 941
 942 static int uv_heartbeat_enable(unsigned int cpu)
 943 {
 944         while (!uv_cpu_scir_info(cpu)->enabled) {
 945                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 946
 947                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 948                 setup_pinned_timer(timer, uv_heartbeat, cpu);
 949                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 950                 add_timer_on(timer, cpu);
 951                 uv_cpu_scir_info(cpu)->enabled = 1;
 952
 953                 /* Also ensure that boot CPU is enabled: */
 954                 cpu = 0;
 955         }
 956         return 0;
 957 }
 958
 959 #ifdef CONFIG_HOTPLUG_CPU
 960 static int uv_heartbeat_disable(unsigned int cpu)
 961 {
 962         if (uv_cpu_scir_info(cpu)->enabled) {
 963                 uv_cpu_scir_info(cpu)->enabled = 0;
 964                 del_timer(&uv_cpu_scir_info(cpu)->timer);
 965         }
 966         uv_set_cpu_scir_bits(cpu, 0xff);
 967         return 0;
 968 }
 969
 970 static __init void uv_scir_register_cpu_notifier(void)
 971 {
 972         cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
 973                                   uv_heartbeat_enable, uv_heartbeat_disable);
 974 }
 975
 976 #else /* !CONFIG_HOTPLUG_CPU */
 977
 978 static __init void uv_scir_register_cpu_notifier(void)
 979 {
 980 }
 981
 982 static __init int uv_init_heartbeat(void)
 983 {
 984         int cpu;
 985
 986         if (is_uv_system()) {
 987                 for_each_online_cpu(cpu)
 988                         uv_heartbeat_enable(cpu);
 989         }
 990
 991         return 0;
 992 }
 993
 994 late_initcall(uv_init_heartbeat);
 995
 996 #endif /* !CONFIG_HOTPLUG_CPU */
 997
 998 /* Direct Legacy VGA I/O traffic to designated IOH */
 999 int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1000 {
1001         int domain, bus, rc;
1002
1003         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1004                 return 0;
1005
1006         if ((command_bits & PCI_COMMAND_IO) == 0)
1007                 return 0;
1008
1009         domain = pci_domain_nr(pdev->bus);
1010         bus = pdev->bus->number;
1011
1012         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1013
1014         return rc;
1015 }
1016
1017 /*
1018  * Called on each CPU to initialize the per_cpu UV data area.
1019  * FIXME: hotplug not supported yet
1020  */
1021 void uv_cpu_init(void)
1022 {
1023         /* CPU 0 initialization will be done via uv_system_init. */
1024         if (smp_processor_id() == 0)
1025                 return;
1026
1027         uv_hub_info->nr_online_cpus++;
1028
1029         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1030                 set_x2apic_extra_bits(uv_hub_info->pnode);
1031 }
1032
1033 struct mn {
1034         unsigned char   m_val;
1035         unsigned char   n_val;
1036         unsigned char   m_shift;
1037         unsigned char   n_lshift;
1038 };
1039
1040 static void get_mn(struct mn *mnp)
1041 {
1042         union uvh_rh_gam_config_mmr_u m_n_config;
1043         union uv3h_gr0_gam_gr_config_u m_gr_config;
1044
1045         /* Make sure the whole structure is well initialized: */
1046         memset(mnp, 0, sizeof(*mnp));
1047
1048         m_n_config.v    = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1049         mnp->n_val      = m_n_config.s.n_skt;
1050
1051         if (is_uv4_hub()) {
1052                 mnp->m_val      = 0;
1053                 mnp->n_lshift   = 0;
1054         } else if (is_uv3_hub()) {
1055                 mnp->m_val      = m_n_config.s3.m_skt;
1056                 m_gr_config.v   = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1057                 mnp->n_lshift   = m_gr_config.s3.m_skt;
1058         } else if (is_uv2_hub()) {
1059                 mnp->m_val      = m_n_config.s2.m_skt;
1060                 mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1061         } else if (is_uv1_hub()) {
1062                 mnp->m_val      = m_n_config.s1.m_skt;
1063                 mnp->n_lshift   = mnp->m_val;
1064         }
1065         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1066 }
1067
1068 void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1069 {
1070         union uvh_node_id_u node_id;
1071         struct mn mn;
1072
1073         get_mn(&mn);
1074         hi->gpa_mask = mn.m_val ?
1075                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1076                 (1UL << uv_cpuid.gpa_shift) - 1;
1077
1078         hi->m_val               = mn.m_val;
1079         hi->n_val               = mn.n_val;
1080         hi->m_shift             = mn.m_shift;
1081         hi->n_lshift            = mn.n_lshift ? mn.n_lshift : 0;
1082         hi->hub_revision        = uv_hub_info->hub_revision;
1083         hi->pnode_mask          = uv_cpuid.pnode_mask;
1084         hi->min_pnode           = _min_pnode;
1085         hi->min_socket          = _min_socket;
1086         hi->pnode_to_socket     = _pnode_to_socket;
1087         hi->socket_to_node      = _socket_to_node;
1088         hi->socket_to_pnode     = _socket_to_pnode;
1089         hi->gr_table_len        = _gr_table_len;
1090         hi->gr_table            = _gr_table;
1091
1092         node_id.v               = uv_read_local_mmr(UVH_NODE_ID);
1093         uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1094         hi->gnode_extra         = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1095         hi->gnode_upper         = (unsigned long)hi->gnode_extra << mn.m_val;
1096
1097         if (uv_gp_table) {
1098                 hi->global_mmr_base     = uv_gp_table->mmr_base;
1099                 hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1100                 hi->global_gru_base     = uv_gp_table->gru_base;
1101                 hi->global_gru_shift    = uv_gp_table->gru_shift;
1102                 hi->gpa_shift           = uv_gp_table->gpa_shift;
1103                 hi->gpa_mask            = (1UL << hi->gpa_shift) - 1;
1104         } else {
1105                 hi->global_mmr_base     = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1106                 hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1107         }
1108
1109         get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1110
1111         hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1112
1113         /* Show system specific info: */
1114         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1115         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1116         pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1117         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1118 }
1119
1120 static void __init decode_gam_params(unsigned long ptr)
1121 {
1122         uv_gp_table = (struct uv_gam_parameters *)ptr;
1123
1124         pr_info("UV: GAM Params...\n");
1125         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1126                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1127                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1128                 uv_gp_table->gpa_shift);
1129 }
1130
1131 static void __init decode_gam_rng_tbl(unsigned long ptr)
1132 {
1133         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1134         unsigned long lgre = 0;
1135         int index = 0;
1136         int sock_min = 999999, pnode_min = 99999;
1137         int sock_max = -1, pnode_max = -1;
1138
1139         uv_gre_table = gre;
1140         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1141                 if (!index) {
1142                         pr_info("UV: GAM Range Table...\n");
1143                         pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1144                 }
1145                 pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x\n",
1146                         index++,
1147                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1148                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1149                         ((unsigned long)(gre->limit - lgre)) >>
1150                                 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1151                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1152
1153                 lgre = gre->limit;
1154                 if (sock_min > gre->sockid)
1155                         sock_min = gre->sockid;
1156                 if (sock_max < gre->sockid)
1157                         sock_max = gre->sockid;
1158                 if (pnode_min > gre->pnode)
1159                         pnode_min = gre->pnode;
1160                 if (pnode_max < gre->pnode)
1161                         pnode_max = gre->pnode;
1162         }
1163         _min_socket     = sock_min;
1164         _max_socket     = sock_max;
1165         _min_pnode      = pnode_min;
1166         _max_pnode      = pnode_max;
1167         _gr_table_len   = index;
1168
1169         pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1170 }
1171
1172 static int __init decode_uv_systab(void)
1173 {
1174         struct uv_systab *st;
1175         int i;
1176
1177         if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1178                 return 0;       /* No extended UVsystab required */
1179
1180         st = uv_systab;
1181         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1182                 int rev = st ? st->revision : 0;
1183
1184                 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1185                 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1186                 uv_system_type = UV_NONE;
1187
1188                 return -EINVAL;
1189         }
1190
1191         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1192                 unsigned long ptr = st->entry[i].offset;
1193
1194                 if (!ptr)
1195                         continue;
1196
1197                 ptr = ptr + (unsigned long)st;
1198
1199                 switch (st->entry[i].type) {
1200                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1201                         decode_gam_params(ptr);
1202                         break;
1203
1204                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1205                         decode_gam_rng_tbl(ptr);
1206                         break;
1207                 }
1208         }
1209         return 0;
1210 }
1211
1212 /*
1213  * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1214  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1215  * .. being replaced by GAM Range Table
1216  */
1217 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1218 {
1219         int i, uv_pb = 0;
1220
1221         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1222         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1223                 unsigned long np;
1224
1225                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1226                 if (np)
1227                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1228
1229                 uv_pb += hweight64(np);
1230         }
1231         if (uv_possible_blades != uv_pb)
1232                 uv_possible_blades = uv_pb;
1233 }
1234
1235 static void __init build_socket_tables(void)
1236 {
1237         struct uv_gam_range_entry *gre = uv_gre_table;
1238         int num, nump;
1239         int cpu, i, lnid;
1240         int minsock = _min_socket;
1241         int maxsock = _max_socket;
1242         int minpnode = _min_pnode;
1243         int maxpnode = _max_pnode;
1244         size_t bytes;
1245
1246         if (!gre) {
1247                 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1248                         pr_info("UV: No UVsystab socket table, ignoring\n");
1249                         return;
1250                 }
1251                 pr_crit("UV: Error: UVsystab address translations not available!\n");
1252                 BUG();
1253         }
1254
1255         /* Build socket id -> node id, pnode */
1256         num = maxsock - minsock + 1;
1257         bytes = num * sizeof(_socket_to_node[0]);
1258         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1259         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1260
1261         nump = maxpnode - minpnode + 1;
1262         bytes = nump * sizeof(_pnode_to_socket[0]);
1263         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1264         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1265
1266         for (i = 0; i < num; i++)
1267                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1268
1269         for (i = 0; i < nump; i++)
1270                 _pnode_to_socket[i] = SOCK_EMPTY;
1271
1272         /* Fill in pnode/node/addr conversion list values: */
1273         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1274         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1275                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1276                         continue;
1277                 i = gre->sockid - minsock;
1278                 /* Duplicate: */
1279                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1280                         continue;
1281                 _socket_to_pnode[i] = gre->pnode;
1282
1283                 i = gre->pnode - minpnode;
1284                 _pnode_to_socket[i] = gre->sockid;
1285
1286                 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1287                         gre->sockid, gre->type, gre->nasid,
1288                         _socket_to_pnode[gre->sockid - minsock],
1289                         _pnode_to_socket[gre->pnode - minpnode]);
1290         }
1291
1292         /* Set socket -> node values: */
1293         lnid = -1;
1294         for_each_present_cpu(cpu) {
1295                 int nid = cpu_to_node(cpu);
1296                 int apicid, sockid;
1297
1298                 if (lnid == nid)
1299                         continue;
1300                 lnid = nid;
1301                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1302                 sockid = apicid >> uv_cpuid.socketid_shift;
1303                 _socket_to_node[sockid - minsock] = nid;
1304                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1305                         sockid, apicid, nid);
1306         }
1307
1308         /* Set up physical blade to pnode translation from GAM Range Table: */
1309         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1310         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1311         BUG_ON(!_node_to_pnode);
1312
1313         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1314                 unsigned short sockid;
1315
1316                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1317                         if (lnid == _socket_to_node[sockid - minsock]) {
1318                                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1319                                 break;
1320                         }
1321                 }
1322                 if (sockid > maxsock) {
1323                         pr_err("UV: socket for node %d not found!\n", lnid);
1324                         BUG();
1325                 }
1326         }
1327
1328         /*
1329          * If socket id == pnode or socket id == node for all nodes,
1330          *   system runs faster by removing corresponding conversion table.
1331          */
1332         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1333         if (minsock == 0) {
1334                 for (i = 0; i < num; i++)
1335                         if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1336                                 break;
1337                 if (i >= num) {
1338                         kfree(_socket_to_node);
1339                         _socket_to_node = NULL;
1340                         pr_info("UV: 1:1 socket_to_node table removed\n");
1341                 }
1342         }
1343         if (minsock == minpnode) {
1344                 for (i = 0; i < num; i++)
1345                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1346                                 _socket_to_pnode[i] != i + minpnode)
1347                                 break;
1348                 if (i >= num) {
1349                         kfree(_socket_to_pnode);
1350                         _socket_to_pnode = NULL;
1351                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1352                 }
1353         }
1354 }
1355
1356 void __init uv_system_init(void)
1357 {
1358         struct uv_hub_info_s hub_info = {0};
1359         int bytes, cpu, nodeid;
1360         unsigned short min_pnode = 9999, max_pnode = 0;
1361         char *hub = is_uv4_hub() ? "UV400" :
1362                     is_uv3_hub() ? "UV300" :
1363                     is_uv2_hub() ? "UV2000/3000" :
1364                     is_uv1_hub() ? "UV100/1000" : NULL;
1365
1366         if (!hub) {
1367                 pr_err("UV: Unknown/unsupported UV hub\n");
1368                 return;
1369         }
1370         pr_info("UV: Found %s hub\n", hub);
1371
1372         map_low_mmrs();
1373
1374         /* Get uv_systab for decoding: */
1375         uv_bios_init();
1376
1377         /* If there's an UVsystab problem then abort UV init: */
1378         if (decode_uv_systab() < 0)
1379                 return;
1380
1381         build_socket_tables();
1382         build_uv_gr_table();
1383         uv_init_hub_info(&hub_info);
1384         uv_possible_blades = num_possible_nodes();
1385         if (!_node_to_pnode)
1386                 boot_init_possible_blades(&hub_info);
1387
1388         /* uv_num_possible_blades() is really the hub count: */
1389         pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1390
1391         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1392         hub_info.coherency_domain_number = sn_coherency_id;
1393         uv_rtc_init();
1394
1395         bytes = sizeof(void *) * uv_num_possible_blades();
1396         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1397         BUG_ON(!__uv_hub_info_list);
1398
1399         bytes = sizeof(struct uv_hub_info_s);
1400         for_each_node(nodeid) {
1401                 struct uv_hub_info_s *new_hub;
1402
1403                 if (__uv_hub_info_list[nodeid]) {
1404                         pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1405                         BUG();
1406                 }
1407
1408                 /* Allocate new per hub info list */
1409                 new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1410                 BUG_ON(!new_hub);
1411                 __uv_hub_info_list[nodeid] = new_hub;
1412                 new_hub = uv_hub_info_list(nodeid);
1413                 BUG_ON(!new_hub);
1414                 *new_hub = hub_info;
1415
1416                 /* Use information from GAM table if available: */
1417                 if (_node_to_pnode)
1418                         new_hub->pnode = _node_to_pnode[nodeid];
1419                 else /* Or fill in during CPU loop: */
1420                         new_hub->pnode = 0xffff;
1421
1422                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1423                 new_hub->memory_nid = -1;
1424                 new_hub->nr_possible_cpus = 0;
1425                 new_hub->nr_online_cpus = 0;
1426         }
1427
1428         /* Initialize per CPU info: */
1429         for_each_possible_cpu(cpu) {
1430                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1431                 int numa_node_id;
1432                 unsigned short pnode;
1433
1434                 nodeid = cpu_to_node(cpu);
1435                 numa_node_id = numa_cpu_node(cpu);
1436                 pnode = uv_apicid_to_pnode(apicid);
1437
1438                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1439                 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1440                 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1441                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1442
1443                 /* Init memoryless node: */
1444                 if (nodeid != numa_node_id &&
1445                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1446                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1447                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1448                         uv_cpu_hub_info(cpu)->pnode = pnode;
1449
1450                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1451         }
1452
1453         for_each_node(nodeid) {
1454                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1455
1456                 /* Add pnode info for pre-GAM list nodes without CPUs: */
1457                 if (pnode == 0xffff) {
1458                         unsigned long paddr;
1459
1460                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1461                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1462                         uv_hub_info_list(nodeid)->pnode = pnode;
1463                 }
1464                 min_pnode = min(pnode, min_pnode);
1465                 max_pnode = max(pnode, max_pnode);
1466                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1467                         nodeid,
1468                         uv_hub_info_list(nodeid)->pnode,
1469                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1470         }
1471
1472         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1473         map_gru_high(max_pnode);
1474         map_mmr_high(max_pnode);
1475         map_mmioh_high(min_pnode, max_pnode);
1476
1477         uv_nmi_setup();
1478         uv_cpu_init();
1479         uv_scir_register_cpu_notifier();
1480         proc_mkdir("sgi_uv", NULL);
1481
1482         /* Register Legacy VGA I/O redirection handler: */
1483         pci_register_set_vga_state(uv_set_vga_state);
1484
1485         /*
1486          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1487          * EFI is not enabled in the kdump kernel:
1488          */
1489         if (is_kdump_kernel())
1490                 reboot_type = BOOT_ACPI;
1491 }
1492
1493 apic_driver(apic_x2apic_uv_x);