arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/export.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51
  52 /* info derived from CPUID */
  53 static struct {
  54         unsigned int apicid_shift;
  55         unsigned int apicid_mask;
  56         unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
  57         unsigned int pnode_mask;
  58         unsigned int gpa_shift;
  59         unsigned int gnode_shift;
  60 } uv_cpuid;
  61
  62 int uv_min_hub_revision_id;
  63 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  64 unsigned int uv_apicid_hibits;
  65 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  66
  67 static struct apic apic_x2apic_uv_x;
  68 static struct uv_hub_info_s uv_hub_info_node0;
  69
  70 /* Set this to use hardware error handler instead of kernel panic */
  71 static int disable_uv_undefined_panic = 1;
  72 unsigned long uv_undefined(char *str)
  73 {
  74         if (likely(!disable_uv_undefined_panic))
  75                 panic("UV: error: undefined MMR: %s\n", str);
  76         else
  77                 pr_crit("UV: error: undefined MMR: %s\n", str);
  78         return ~0ul;    /* cause a machine fault  */
  79 }
  80 EXPORT_SYMBOL(uv_undefined);
  81
  82 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  83 {
  84         unsigned long val, *mmr;
  85
  86         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  87         val = *mmr;
  88         early_iounmap(mmr, sizeof(*mmr));
  89         return val;
  90 }
  91
  92 static inline bool is_GRU_range(u64 start, u64 end)
  93 {
  94         if (gru_dist_base) {
  95                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  96                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  97                 u64 eu = end & gru_dist_umask;
  98                 u64 el = end & gru_dist_lmask;
  99
 100                 /* Must reside completely within a single GRU range */
 101                 return (sl == gru_dist_base && el == gru_dist_base &&
 102                         su >= gru_first_node_paddr &&
 103                         su <= gru_last_node_paddr &&
 104                         eu == su);
 105         } else {
 106                 return start >= gru_start_paddr && end <= gru_end_paddr;
 107         }
 108 }
 109
 110 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 111 {
 112         return is_ISA_range(start, end) || is_GRU_range(start, end);
 113 }
 114
 115 static int __init early_get_pnodeid(void)
 116 {
 117         union uvh_node_id_u node_id;
 118         union uvh_rh_gam_config_mmr_u  m_n_config;
 119         int pnode;
 120
 121         /* Currently, all blades have same revision number */
 122         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 123         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 124         uv_min_hub_revision_id = node_id.s.revision;
 125
 126         switch (node_id.s.part_number) {
 127         case UV2_HUB_PART_NUMBER:
 128         case UV2_HUB_PART_NUMBER_X:
 129                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 130                 break;
 131         case UV3_HUB_PART_NUMBER:
 132         case UV3_HUB_PART_NUMBER_X:
 133                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 134                 break;
 135         case UV4_HUB_PART_NUMBER:
 136                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 137                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
 138                 break;
 139         }
 140
 141         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 142         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 143         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 144         uv_cpuid.gpa_shift = 46;        /* default unless changed */
 145
 146         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 147                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 148                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 149         return pnode;
 150 }
 151
 152 /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 153 #define SMT_LEVEL       0       /* leaf 0xb SMT level */
 154 #define INVALID_TYPE    0       /* leaf 0xb sub-leaf types */
 155 #define SMT_TYPE        1
 156 #define CORE_TYPE       2
 157 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 158 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 159
 160 static void set_x2apic_bits(void)
 161 {
 162         unsigned int eax, ebx, ecx, edx, sub_index;
 163         unsigned int sid_shift;
 164
 165         cpuid(0, &eax, &ebx, &ecx, &edx);
 166         if (eax < 0xb) {
 167                 pr_info("UV: CPU does not have CPUID.11\n");
 168                 return;
 169         }
 170         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 171         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 172                 pr_info("UV: CPUID.11 not implemented\n");
 173                 return;
 174         }
 175         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 176         sub_index = 1;
 177         do {
 178                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 179                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 180                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 181                         break;
 182                 }
 183                 sub_index++;
 184         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 185         uv_cpuid.apicid_shift = 0;
 186         uv_cpuid.apicid_mask = (~(-1 << sid_shift));
 187         uv_cpuid.socketid_shift = sid_shift;
 188 }
 189
 190 static void __init early_get_apic_socketid_shift(void)
 191 {
 192         if (is_uv2_hub() || is_uv3_hub())
 193                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 194
 195         set_x2apic_bits();
 196
 197         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
 198                 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 199         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
 200                 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 201 }
 202
 203 /*
 204  * Add an extra bit as dictated by bios to the destination apicid of
 205  * interrupts potentially passing through the UV HUB.  This prevents
 206  * a deadlock between interrupts and IO port operations.
 207  */
 208 static void __init uv_set_apicid_hibit(void)
 209 {
 210         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 211
 212         if (is_uv1_hub()) {
 213                 apicid_mask.v =
 214                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 215                 uv_apicid_hibits =
 216                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 217         }
 218 }
 219
 220 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 221 {
 222         int pnodeid;
 223         int uv_apic;
 224
 225         if (strncmp(oem_id, "SGI", 3) != 0)
 226                 return 0;
 227
 228         if (numa_off) {
 229                 pr_err("UV: NUMA is off, disabling UV support\n");
 230                 return 0;
 231         }
 232
 233         /* Setup early hub type field in uv_hub_info for Node 0 */
 234         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 235
 236         /*
 237          * Determine UV arch type.
 238          *   SGI: UV100/1000
 239          *   SGI2: UV2000/3000
 240          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 241          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 242          */
 243         uv_hub_info->hub_revision =
 244                 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 245                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 246                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 247                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 248
 249         if (uv_hub_info->hub_revision == 0)
 250                 goto badbios;
 251
 252         pnodeid = early_get_pnodeid();
 253         early_get_apic_socketid_shift();
 254         x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 255         x86_platform.nmi_init = uv_nmi_init;
 256
 257         if (!strcmp(oem_table_id, "UVX")) {             /* most common */
 258                 uv_system_type = UV_X2APIC;
 259                 uv_apic = 0;
 260
 261         } else if (!strcmp(oem_table_id, "UVH")) {      /* only UV1 systems */
 262                 uv_system_type = UV_NON_UNIQUE_APIC;
 263                 __this_cpu_write(x2apic_extra_bits,
 264                         pnodeid << uvh_apicid.s.pnode_shift);
 265                 uv_set_apicid_hibit();
 266                 uv_apic = 1;
 267
 268         } else  if (!strcmp(oem_table_id, "UVL")) {     /* only used for */
 269                 uv_system_type = UV_LEGACY_APIC;        /* very small systems */
 270                 uv_apic = 0;
 271
 272         } else {
 273                 goto badbios;
 274         }
 275
 276         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
 277                 oem_id, oem_table_id, uv_system_type,
 278                 uv_min_hub_revision_id, uv_apic);
 279
 280         return uv_apic;
 281
 282 badbios:
 283         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 284         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 285         BUG();
 286 }
 287
 288 enum uv_system_type get_uv_system_type(void)
 289 {
 290         return uv_system_type;
 291 }
 292
 293 int is_uv_system(void)
 294 {
 295         return uv_system_type != UV_NONE;
 296 }
 297 EXPORT_SYMBOL_GPL(is_uv_system);
 298
 299 void **__uv_hub_info_list;
 300 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 301
 302 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 303 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 304
 305 short uv_possible_blades;
 306 EXPORT_SYMBOL_GPL(uv_possible_blades);
 307
 308 unsigned long sn_rtc_cycles_per_second;
 309 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 310
 311 /* the following values are used for the per node hub info struct */
 312 static __initdata unsigned short *_node_to_pnode;
 313 static __initdata unsigned short _min_socket, _max_socket;
 314 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
 315 static __initdata struct uv_gam_range_entry *uv_gre_table;
 316 static __initdata struct uv_gam_parameters *uv_gp_table;
 317 static __initdata unsigned short *_socket_to_node;
 318 static __initdata unsigned short *_socket_to_pnode;
 319 static __initdata unsigned short *_pnode_to_socket;
 320 static __initdata struct uv_gam_range_s *_gr_table;
 321 #define SOCK_EMPTY      ((unsigned short)~0)
 322
 323 extern int uv_hub_info_version(void)
 324 {
 325         return UV_HUB_INFO_VERSION;
 326 }
 327 EXPORT_SYMBOL(uv_hub_info_version);
 328
 329 /* Build GAM range lookup table */
 330 static __init void build_uv_gr_table(void)
 331 {
 332         struct uv_gam_range_entry *gre = uv_gre_table;
 333         struct uv_gam_range_s *grt;
 334         unsigned long last_limit = 0, ram_limit = 0;
 335         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
 336
 337         if (!gre)
 338                 return;
 339
 340         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 341         grt = kzalloc(bytes, GFP_KERNEL);
 342         BUG_ON(!grt);
 343         _gr_table = grt;
 344
 345         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 346                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 347                         if (!ram_limit) {   /* mark hole between ram/non-ram */
 348                                 ram_limit = last_limit;
 349                                 last_limit = gre->limit;
 350                                 lsid++;
 351                                 continue;
 352                         }
 353                         last_limit = gre->limit;
 354                         pr_info("UV: extra hole in GAM RE table @%d\n",
 355                                 (int)(gre - uv_gre_table));
 356                         continue;
 357                 }
 358                 if (_max_socket < gre->sockid) {
 359                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
 360                                 gre->sockid, _max_socket,
 361                                 (int)(gre - uv_gre_table));
 362                         continue;
 363                 }
 364                 sid = gre->sockid - _min_socket;
 365                 if (lsid < sid) {               /* new range */
 366                         grt = &_gr_table[indx];
 367                         grt->base = lindx;
 368                         grt->nasid = gre->nasid;
 369                         grt->limit = last_limit = gre->limit;
 370                         lsid = sid;
 371                         lindx = indx++;
 372                         continue;
 373                 }
 374                 if (lsid == sid && !ram_limit) {        /* update range */
 375                         if (grt->limit == last_limit) { /* .. if contiguous */
 376                                 grt->limit = last_limit = gre->limit;
 377                                 continue;
 378                         }
 379                 }
 380                 if (!ram_limit) {               /* non-contiguous ram range */
 381                         grt++;
 382                         grt->base = lindx;
 383                         grt->nasid = gre->nasid;
 384                         grt->limit = last_limit = gre->limit;
 385                         continue;
 386                 }
 387                 grt++;                          /* non-contiguous/non-ram */
 388                 grt->base = grt - _gr_table;    /* base is this entry */
 389                 grt->nasid = gre->nasid;
 390                 grt->limit = last_limit = gre->limit;
 391                 lsid++;
 392         }
 393
 394         /* shorten table if possible */
 395         grt++;
 396         i = grt - _gr_table;
 397         if (i < _gr_table_len) {
 398                 void *ret;
 399
 400                 bytes = i * sizeof(struct uv_gam_range_s);
 401                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 402                 if (ret) {
 403                         _gr_table = ret;
 404                         _gr_table_len = i;
 405                 }
 406         }
 407
 408         /* display resultant gam range table */
 409         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 410                 int gb = grt->base;
 411                 unsigned long start = gb < 0 ?  0 :
 412                         (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 413                 unsigned long end =
 414                         (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 415
 416                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
 417                         i, grt->nasid, start, end, gb);
 418         }
 419 }
 420
 421 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 422 {
 423         unsigned long val;
 424         int pnode;
 425
 426         pnode = uv_apicid_to_pnode(phys_apicid);
 427         phys_apicid |= uv_apicid_hibits;
 428         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 429             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 430             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 431             APIC_DM_INIT;
 432         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 433
 434         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 435             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 436             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 437             APIC_DM_STARTUP;
 438         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 439
 440         return 0;
 441 }
 442
 443 static void uv_send_IPI_one(int cpu, int vector)
 444 {
 445         unsigned long apicid;
 446         int pnode;
 447
 448         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 449         pnode = uv_apicid_to_pnode(apicid);
 450         uv_hub_send_ipi(pnode, apicid, vector);
 451 }
 452
 453 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 454 {
 455         unsigned int cpu;
 456
 457         for_each_cpu(cpu, mask)
 458                 uv_send_IPI_one(cpu, vector);
 459 }
 460
 461 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 462 {
 463         unsigned int this_cpu = smp_processor_id();
 464         unsigned int cpu;
 465
 466         for_each_cpu(cpu, mask) {
 467                 if (cpu != this_cpu)
 468                         uv_send_IPI_one(cpu, vector);
 469         }
 470 }
 471
 472 static void uv_send_IPI_allbutself(int vector)
 473 {
 474         unsigned int this_cpu = smp_processor_id();
 475         unsigned int cpu;
 476
 477         for_each_online_cpu(cpu) {
 478                 if (cpu != this_cpu)
 479                         uv_send_IPI_one(cpu, vector);
 480         }
 481 }
 482
 483 static void uv_send_IPI_all(int vector)
 484 {
 485         uv_send_IPI_mask(cpu_online_mask, vector);
 486 }
 487
 488 static int uv_apic_id_valid(int apicid)
 489 {
 490         return 1;
 491 }
 492
 493 static int uv_apic_id_registered(void)
 494 {
 495         return 1;
 496 }
 497
 498 static void uv_init_apic_ldr(void)
 499 {
 500 }
 501
 502 static int
 503 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 504                           const struct cpumask *andmask,
 505                           unsigned int *apicid)
 506 {
 507         int unsigned cpu;
 508
 509         /*
 510          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 511          * May as well be the first.
 512          */
 513         for_each_cpu_and(cpu, cpumask, andmask) {
 514                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 515                         break;
 516         }
 517
 518         if (likely(cpu < nr_cpu_ids)) {
 519                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 520                 return 0;
 521         }
 522
 523         return -EINVAL;
 524 }
 525
 526 static unsigned int x2apic_get_apic_id(unsigned long x)
 527 {
 528         unsigned int id;
 529
 530         WARN_ON(preemptible() && num_online_cpus() > 1);
 531         id = x | __this_cpu_read(x2apic_extra_bits);
 532
 533         return id;
 534 }
 535
 536 static unsigned long set_apic_id(unsigned int id)
 537 {
 538         /* CHECKME: Do we need to mask out the xapic extra bits? */
 539         return id;
 540 }
 541
 542 static unsigned int uv_read_apic_id(void)
 543 {
 544         return x2apic_get_apic_id(apic_read(APIC_ID));
 545 }
 546
 547 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 548 {
 549         return uv_read_apic_id() >> index_msb;
 550 }
 551
 552 static void uv_send_IPI_self(int vector)
 553 {
 554         apic_write(APIC_SELF_IPI, vector);
 555 }
 556
 557 static int uv_probe(void)
 558 {
 559         return apic == &apic_x2apic_uv_x;
 560 }
 561
 562 static struct apic apic_x2apic_uv_x __ro_after_init = {
 563
 564         .name                           = "UV large system",
 565         .probe                          = uv_probe,
 566         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 567         .apic_id_valid                  = uv_apic_id_valid,
 568         .apic_id_registered             = uv_apic_id_registered,
 569
 570         .irq_delivery_mode              = dest_Fixed,
 571         .irq_dest_mode                  = 0, /* physical */
 572
 573         .target_cpus                    = online_target_cpus,
 574         .disable_esr                    = 0,
 575         .dest_logical                   = APIC_DEST_LOGICAL,
 576         .check_apicid_used              = NULL,
 577
 578         .vector_allocation_domain       = default_vector_allocation_domain,
 579         .init_apic_ldr                  = uv_init_apic_ldr,
 580
 581         .ioapic_phys_id_map             = NULL,
 582         .setup_apic_routing             = NULL,
 583         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 584         .apicid_to_cpu_present          = NULL,
 585         .check_phys_apicid_present      = default_check_phys_apicid_present,
 586         .phys_pkg_id                    = uv_phys_pkg_id,
 587
 588         .get_apic_id                    = x2apic_get_apic_id,
 589         .set_apic_id                    = set_apic_id,
 590
 591         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 592
 593         .send_IPI                       = uv_send_IPI_one,
 594         .send_IPI_mask                  = uv_send_IPI_mask,
 595         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 596         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 597         .send_IPI_all                   = uv_send_IPI_all,
 598         .send_IPI_self                  = uv_send_IPI_self,
 599
 600         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 601         .inquire_remote_apic            = NULL,
 602
 603         .read                           = native_apic_msr_read,
 604         .write                          = native_apic_msr_write,
 605         .eoi_write                      = native_apic_msr_eoi_write,
 606         .icr_read                       = native_x2apic_icr_read,
 607         .icr_write                      = native_x2apic_icr_write,
 608         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 609         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 610 };
 611
 612 static void set_x2apic_extra_bits(int pnode)
 613 {
 614         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 615 }
 616
 617 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 618 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 619
 620 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 621 {
 622         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 623         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 624         unsigned long m_redirect;
 625         unsigned long m_overlay;
 626         int i;
 627
 628         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 629                 switch (i) {
 630                 case 0:
 631                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 632                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 633                         break;
 634                 case 1:
 635                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 636                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 637                         break;
 638                 case 2:
 639                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 640                         m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 641                         break;
 642                 }
 643                 alias.v = uv_read_local_mmr(m_overlay);
 644                 if (alias.s.enable && alias.s.base == 0) {
 645                         *size = (1UL << alias.s.m_alias);
 646                         redirect.v = uv_read_local_mmr(m_redirect);
 647                         *base = (unsigned long)redirect.s.dest_base
 648                                                         << DEST_SHIFT;
 649                         return;
 650                 }
 651         }
 652         *base = *size = 0;
 653 }
 654
 655 enum map_type {map_wb, map_uc};
 656
 657 static __init void map_high(char *id, unsigned long base, int pshift,
 658                         int bshift, int max_pnode, enum map_type map_type)
 659 {
 660         unsigned long bytes, paddr;
 661
 662         paddr = base << pshift;
 663         bytes = (1UL << bshift) * (max_pnode + 1);
 664         if (!paddr) {
 665                 pr_info("UV: Map %s_HI base address NULL\n", id);
 666                 return;
 667         }
 668         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 669         if (map_type == map_uc)
 670                 init_extra_mapping_uc(paddr, bytes);
 671         else
 672                 init_extra_mapping_wb(paddr, bytes);
 673 }
 674
 675 static __init void map_gru_distributed(unsigned long c)
 676 {
 677         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 678         u64 paddr;
 679         unsigned long bytes;
 680         int nid;
 681
 682         gru.v = c;
 683         /* only base bits 42:28 relevant in dist mode */
 684         gru_dist_base = gru.v & 0x000007fff0000000UL;
 685         if (!gru_dist_base) {
 686                 pr_info("UV: Map GRU_DIST base address NULL\n");
 687                 return;
 688         }
 689         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 690         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 691         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 692         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 693         for_each_online_node(nid) {
 694                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 695                                 gru_dist_base;
 696                 init_extra_mapping_wb(paddr, bytes);
 697                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 698                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 699         }
 700         /* Save upper (63:M) bits of address only for is_GRU_range */
 701         gru_first_node_paddr &= gru_dist_umask;
 702         gru_last_node_paddr &= gru_dist_umask;
 703         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 704                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 705 }
 706
 707 static __init void map_gru_high(int max_pnode)
 708 {
 709         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 710         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 711         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 712         unsigned long base;
 713
 714         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 715         if (!gru.s.enable) {
 716                 pr_info("UV: GRU disabled\n");
 717                 return;
 718         }
 719
 720         if (is_uv3_hub() && gru.s3.mode) {
 721                 map_gru_distributed(gru.v);
 722                 return;
 723         }
 724         base = (gru.v & mask) >> shift;
 725         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 726         gru_start_paddr = ((u64)base << shift);
 727         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 728 }
 729
 730 static __init void map_mmr_high(int max_pnode)
 731 {
 732         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 733         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 734
 735         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 736         if (mmr.s.enable)
 737                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 738         else
 739                 pr_info("UV: MMR disabled\n");
 740 }
 741
 742 /*
 743  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 744  * and REDIRECT MMR regs are exactly the same on UV3.
 745  */
 746 struct mmioh_config {
 747         unsigned long overlay;
 748         unsigned long redirect;
 749         char *id;
 750 };
 751
 752 static __initdata struct mmioh_config mmiohs[] = {
 753         {
 754                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 755                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 756                 "MMIOH0"
 757         },
 758         {
 759                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 760                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 761                 "MMIOH1"
 762         },
 763 };
 764
 765 /* UV3 & UV4 have identical MMIOH overlay configs */
 766 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 767 {
 768         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 769         unsigned long mmr;
 770         unsigned long base;
 771         int i, n, shift, m_io, max_io;
 772         int nasid, lnasid, fi, li;
 773         char *id;
 774
 775         id = mmiohs[index].id;
 776         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 777         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 778                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 779         if (!overlay.s3.enable) {
 780                 pr_info("UV: %s disabled\n", id);
 781                 return;
 782         }
 783
 784         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 785         base = (unsigned long)overlay.s3.base;
 786         m_io = overlay.s3.m_io;
 787         mmr = mmiohs[index].redirect;
 788         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 789         min_pnode *= 2;                         /* convert to NASID */
 790         max_pnode *= 2;
 791         max_io = lnasid = fi = li = -1;
 792
 793         for (i = 0; i < n; i++) {
 794                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 795
 796                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 797                 nasid = redirect.s3.nasid;
 798                 if (nasid < min_pnode || max_pnode < nasid)
 799                         nasid = -1;             /* invalid NASID */
 800
 801                 if (nasid == lnasid) {
 802                         li = i;
 803                         if (i != n-1)           /* last entry check */
 804                                 continue;
 805                 }
 806
 807                 /* check if we have a cached (or last) redirect to print */
 808                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 809                         unsigned long addr1, addr2;
 810                         int f, l;
 811
 812                         if (lnasid == -1) {
 813                                 f = l = i;
 814                                 lnasid = nasid;
 815                         } else {
 816                                 f = fi;
 817                                 l = li;
 818                         }
 819                         addr1 = (base << shift) +
 820                                 f * (1ULL << m_io);
 821                         addr2 = (base << shift) +
 822                                 (l + 1) * (1ULL << m_io);
 823                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 824                                 id, fi, li, lnasid, addr1, addr2);
 825                         if (max_io < l)
 826                                 max_io = l;
 827                 }
 828                 fi = li = i;
 829                 lnasid = nasid;
 830         }
 831
 832         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 833                 id, base, shift, m_io, max_io);
 834
 835         if (max_io >= 0)
 836                 map_high(id, base, shift, m_io, max_io, map_uc);
 837 }
 838
 839 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 840 {
 841         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 842         unsigned long mmr, base;
 843         int shift, enable, m_io, n_io;
 844
 845         if (is_uv3_hub() || is_uv4_hub()) {
 846                 /* Map both MMIOH Regions */
 847                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 848                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 849                 return;
 850         }
 851
 852         if (is_uv1_hub()) {
 853                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 854                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 855                 mmioh.v = uv_read_local_mmr(mmr);
 856                 enable = !!mmioh.s1.enable;
 857                 base = mmioh.s1.base;
 858                 m_io = mmioh.s1.m_io;
 859                 n_io = mmioh.s1.n_io;
 860         } else if (is_uv2_hub()) {
 861                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 862                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 863                 mmioh.v = uv_read_local_mmr(mmr);
 864                 enable = !!mmioh.s2.enable;
 865                 base = mmioh.s2.base;
 866                 m_io = mmioh.s2.m_io;
 867                 n_io = mmioh.s2.n_io;
 868         } else
 869                 return;
 870
 871         if (enable) {
 872                 max_pnode &= (1 << n_io) - 1;
 873                 pr_info(
 874                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 875                         base, shift, m_io, n_io, max_pnode);
 876                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 877         } else {
 878                 pr_info("UV: MMIOH disabled\n");
 879         }
 880 }
 881
 882 static __init void map_low_mmrs(void)
 883 {
 884         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 885         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 886 }
 887
 888 static __init void uv_rtc_init(void)
 889 {
 890         long status;
 891         u64 ticks_per_sec;
 892
 893         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 894                                         &ticks_per_sec);
 895         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 896                 printk(KERN_WARNING
 897                         "unable to determine platform RTC clock frequency, "
 898                         "guessing.\n");
 899                 /* BIOS gives wrong value for clock freq. so guess */
 900                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 901         } else
 902                 sn_rtc_cycles_per_second = ticks_per_sec;
 903 }
 904
 905 /*
 906  * percpu heartbeat timer
 907  */
 908 static void uv_heartbeat(unsigned long ignored)
 909 {
 910         struct timer_list *timer = &uv_scir_info->timer;
 911         unsigned char bits = uv_scir_info->state;
 912
 913         /* flip heartbeat bit */
 914         bits ^= SCIR_CPU_HEARTBEAT;
 915
 916         /* is this cpu idle? */
 917         if (idle_cpu(raw_smp_processor_id()))
 918                 bits &= ~SCIR_CPU_ACTIVITY;
 919         else
 920                 bits |= SCIR_CPU_ACTIVITY;
 921
 922         /* update system controller interface reg */
 923         uv_set_scir_bits(bits);
 924
 925         /* enable next timer period */
 926         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 927 }
 928
 929 static int uv_heartbeat_enable(unsigned int cpu)
 930 {
 931         while (!uv_cpu_scir_info(cpu)->enabled) {
 932                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 933
 934                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 935                 setup_pinned_timer(timer, uv_heartbeat, cpu);
 936                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 937                 add_timer_on(timer, cpu);
 938                 uv_cpu_scir_info(cpu)->enabled = 1;
 939
 940                 /* also ensure that boot cpu is enabled */
 941                 cpu = 0;
 942         }
 943         return 0;
 944 }
 945
 946 #ifdef CONFIG_HOTPLUG_CPU
 947 static int uv_heartbeat_disable(unsigned int cpu)
 948 {
 949         if (uv_cpu_scir_info(cpu)->enabled) {
 950                 uv_cpu_scir_info(cpu)->enabled = 0;
 951                 del_timer(&uv_cpu_scir_info(cpu)->timer);
 952         }
 953         uv_set_cpu_scir_bits(cpu, 0xff);
 954         return 0;
 955 }
 956
 957 static __init void uv_scir_register_cpu_notifier(void)
 958 {
 959         cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
 960                                   uv_heartbeat_enable, uv_heartbeat_disable);
 961 }
 962
 963 #else /* !CONFIG_HOTPLUG_CPU */
 964
 965 static __init void uv_scir_register_cpu_notifier(void)
 966 {
 967 }
 968
 969 static __init int uv_init_heartbeat(void)
 970 {
 971         int cpu;
 972
 973         if (is_uv_system())
 974                 for_each_online_cpu(cpu)
 975                         uv_heartbeat_enable(cpu);
 976         return 0;
 977 }
 978
 979 late_initcall(uv_init_heartbeat);
 980
 981 #endif /* !CONFIG_HOTPLUG_CPU */
 982
 983 /* Direct Legacy VGA I/O traffic to designated IOH */
 984 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 985                       unsigned int command_bits, u32 flags)
 986 {
 987         int domain, bus, rc;
 988
 989         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
 990                         pdev->devfn, decode, command_bits, flags);
 991
 992         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 993                 return 0;
 994
 995         if ((command_bits & PCI_COMMAND_IO) == 0)
 996                 return 0;
 997
 998         domain = pci_domain_nr(pdev->bus);
 999         bus = pdev->bus->number;
1000
1001         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1002         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
1003
1004         return rc;
1005 }
1006
1007 /*
1008  * Called on each cpu to initialize the per_cpu UV data area.
1009  * FIXME: hotplug not supported yet
1010  */
1011 void uv_cpu_init(void)
1012 {
1013         /* CPU 0 initialization will be done via uv_system_init. */
1014         if (smp_processor_id() == 0)
1015                 return;
1016
1017         uv_hub_info->nr_online_cpus++;
1018
1019         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1020                 set_x2apic_extra_bits(uv_hub_info->pnode);
1021 }
1022
1023 struct mn {
1024         unsigned char   m_val;
1025         unsigned char   n_val;
1026         unsigned char   m_shift;
1027         unsigned char   n_lshift;
1028 };
1029
1030 static void get_mn(struct mn *mnp)
1031 {
1032         union uvh_rh_gam_config_mmr_u m_n_config;
1033         union uv3h_gr0_gam_gr_config_u m_gr_config;
1034
1035         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1036         mnp->n_val = m_n_config.s.n_skt;
1037         if (is_uv4_hub()) {
1038                 mnp->m_val = 0;
1039                 mnp->n_lshift = 0;
1040         } else if (is_uv3_hub()) {
1041                 mnp->m_val = m_n_config.s3.m_skt;
1042                 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1043                 mnp->n_lshift = m_gr_config.s3.m_skt;
1044         } else if (is_uv2_hub()) {
1045                 mnp->m_val = m_n_config.s2.m_skt;
1046                 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1047         } else if (is_uv1_hub()) {
1048                 mnp->m_val = m_n_config.s1.m_skt;
1049                 mnp->n_lshift = mnp->m_val;
1050         }
1051         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1052 }
1053
1054 void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
1055 {
1056         struct mn mn = {0};     /* avoid unitialized warnings */
1057         union uvh_node_id_u node_id;
1058
1059         get_mn(&mn);
1060         hub_info->m_val = mn.m_val;
1061         hub_info->n_val = mn.n_val;
1062         hub_info->m_shift = mn.m_shift;
1063         hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1064
1065         hub_info->hub_revision = uv_hub_info->hub_revision;
1066         hub_info->pnode_mask = uv_cpuid.pnode_mask;
1067         hub_info->min_pnode = _min_pnode;
1068         hub_info->min_socket = _min_socket;
1069         hub_info->pnode_to_socket = _pnode_to_socket;
1070         hub_info->socket_to_node = _socket_to_node;
1071         hub_info->socket_to_pnode = _socket_to_pnode;
1072         hub_info->gr_table_len = _gr_table_len;
1073         hub_info->gr_table = _gr_table;
1074         hub_info->gpa_mask = mn.m_val ?
1075                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1076                 (1UL << uv_cpuid.gpa_shift) - 1;
1077
1078         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1079         uv_cpuid.gnode_shift = max_t(unsigned int,
1080                                         uv_cpuid.gnode_shift, mn.n_val);
1081         hub_info->gnode_extra =
1082                 (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1083
1084         hub_info->gnode_upper =
1085                 ((unsigned long)hub_info->gnode_extra << mn.m_val);
1086
1087         if (uv_gp_table) {
1088                 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1089                 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1090                 hub_info->global_gru_base = uv_gp_table->gru_base;
1091                 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1092                 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1093                 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1094         } else {
1095                 hub_info->global_mmr_base =
1096                         uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1097                                         ~UV_MMR_ENABLE;
1098                 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1099         }
1100
1101         get_lowmem_redirect(
1102                 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
1103
1104         hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
1105
1106         /* show system specific info */
1107         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1108                 hub_info->n_val, hub_info->m_val,
1109                 hub_info->m_shift, hub_info->n_lshift);
1110
1111         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
1112                 hub_info->gpa_mask, hub_info->gpa_shift,
1113                 hub_info->pnode_mask, hub_info->apic_pnode_shift);
1114
1115         pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
1116                 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1117                 hub_info->global_gru_base, hub_info->global_gru_shift);
1118
1119         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1120                 hub_info->gnode_upper, hub_info->gnode_extra);
1121 }
1122
1123 static void __init decode_gam_params(unsigned long ptr)
1124 {
1125         uv_gp_table = (struct uv_gam_parameters *)ptr;
1126
1127         pr_info("UV: GAM Params...\n");
1128         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1129                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1130                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1131                 uv_gp_table->gpa_shift);
1132 }
1133
1134 static void __init decode_gam_rng_tbl(unsigned long ptr)
1135 {
1136         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1137         unsigned long lgre = 0;
1138         int index = 0;
1139         int sock_min = 999999, pnode_min = 99999;
1140         int sock_max = -1, pnode_max = -1;
1141
1142         uv_gre_table = gre;
1143         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1144                 if (!index) {
1145                         pr_info("UV: GAM Range Table...\n");
1146                         pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s\n",
1147                                 "Range", "", "Size", "Type", "NASID",
1148                                 "SID", "PN");
1149                 }
1150                 pr_info(
1151                 "UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x\n",
1152                         index++,
1153                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1154                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1155                         ((unsigned long)(gre->limit - lgre)) >>
1156                                 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1157                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1158
1159                 lgre = gre->limit;
1160                 if (sock_min > gre->sockid)
1161                         sock_min = gre->sockid;
1162                 if (sock_max < gre->sockid)
1163                         sock_max = gre->sockid;
1164                 if (pnode_min > gre->pnode)
1165                         pnode_min = gre->pnode;
1166                 if (pnode_max < gre->pnode)
1167                         pnode_max = gre->pnode;
1168         }
1169         _min_socket = sock_min;
1170         _max_socket = sock_max;
1171         _min_pnode = pnode_min;
1172         _max_pnode = pnode_max;
1173         _gr_table_len = index;
1174         pr_info(
1175         "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1176                 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1177 }
1178
1179 static int __init decode_uv_systab(void)
1180 {
1181         struct uv_systab *st;
1182         int i;
1183
1184         if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1185                 return 0;       /* No extended UVsystab required */
1186
1187         st = uv_systab;
1188         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1189                 int rev = st ? st->revision : 0;
1190
1191                 pr_err(
1192                 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1193                         rev, UV_SYSTAB_VERSION_UV4_LATEST);
1194                 pr_err(
1195                 "UV: Cannot support UV operations, switching to generic PC\n");
1196                 uv_system_type = UV_NONE;
1197                 return -EINVAL;
1198         }
1199
1200         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1201                 unsigned long ptr = st->entry[i].offset;
1202
1203                 if (!ptr)
1204                         continue;
1205
1206                 ptr = ptr + (unsigned long)st;
1207
1208                 switch (st->entry[i].type) {
1209                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1210                         decode_gam_params(ptr);
1211                         break;
1212
1213                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1214                         decode_gam_rng_tbl(ptr);
1215                         break;
1216                 }
1217         }
1218         return 0;
1219 }
1220
1221 /*
1222  * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
1223  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1224  * .. being replaced by GAM Range Table
1225  */
1226 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1227 {
1228         int i, uv_pb = 0;
1229
1230         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1231         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1232                 unsigned long np;
1233
1234                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1235                 if (np)
1236                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1237
1238                 uv_pb += hweight64(np);
1239         }
1240         if (uv_possible_blades != uv_pb)
1241                 uv_possible_blades = uv_pb;
1242 }
1243
1244 static void __init build_socket_tables(void)
1245 {
1246         struct uv_gam_range_entry *gre = uv_gre_table;
1247         int num, nump;
1248         int cpu, i, lnid;
1249         int minsock = _min_socket;
1250         int maxsock = _max_socket;
1251         int minpnode = _min_pnode;
1252         int maxpnode = _max_pnode;
1253         size_t bytes;
1254
1255         if (!gre) {
1256                 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1257                         pr_info("UV: No UVsystab socket table, ignoring\n");
1258                         return;         /* not required */
1259                 }
1260                 pr_crit(
1261                 "UV: Error: UVsystab address translations not available!\n");
1262                 BUG();
1263         }
1264
1265         /* build socket id -> node id, pnode */
1266         num = maxsock - minsock + 1;
1267         bytes = num * sizeof(_socket_to_node[0]);
1268         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1269         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1270
1271         nump = maxpnode - minpnode + 1;
1272         bytes = nump * sizeof(_pnode_to_socket[0]);
1273         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1274         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1275
1276         for (i = 0; i < num; i++)
1277                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1278
1279         for (i = 0; i < nump; i++)
1280                 _pnode_to_socket[i] = SOCK_EMPTY;
1281
1282         /* fill in pnode/node/addr conversion list values */
1283         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1284         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1285                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1286                         continue;
1287                 i = gre->sockid - minsock;
1288                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1289                         continue;       /* duplicate */
1290                 _socket_to_pnode[i] = gre->pnode;
1291
1292                 i = gre->pnode - minpnode;
1293                 _pnode_to_socket[i] = gre->sockid;
1294
1295                 pr_info(
1296                 "UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1297                         gre->sockid, gre->type, gre->nasid,
1298                         _socket_to_pnode[gre->sockid - minsock],
1299                         _pnode_to_socket[gre->pnode - minpnode]);
1300         }
1301
1302         /* Set socket -> node values */
1303         lnid = -1;
1304         for_each_present_cpu(cpu) {
1305                 int nid = cpu_to_node(cpu);
1306                 int apicid, sockid;
1307
1308                 if (lnid == nid)
1309                         continue;
1310                 lnid = nid;
1311                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1312                 sockid = apicid >> uv_cpuid.socketid_shift;
1313                 _socket_to_node[sockid - minsock] = nid;
1314                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1315                         sockid, apicid, nid);
1316         }
1317
1318         /* Setup physical blade to pnode translation from GAM Range Table */
1319         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1320         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1321         BUG_ON(!_node_to_pnode);
1322
1323         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1324                 unsigned short sockid;
1325
1326                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1327                         if (lnid == _socket_to_node[sockid - minsock]) {
1328                                 _node_to_pnode[lnid] =
1329                                         _socket_to_pnode[sockid - minsock];
1330                                 break;
1331                         }
1332                 }
1333                 if (sockid > maxsock) {
1334                         pr_err("UV: socket for node %d not found!\n", lnid);
1335                         BUG();
1336                 }
1337         }
1338
1339         /*
1340          * If socket id == pnode or socket id == node for all nodes,
1341          *   system runs faster by removing corresponding conversion table.
1342          */
1343         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1344         if (minsock == 0) {
1345                 for (i = 0; i < num; i++)
1346                         if (_socket_to_node[i] == SOCK_EMPTY ||
1347                                 i != _socket_to_node[i])
1348                                 break;
1349                 if (i >= num) {
1350                         kfree(_socket_to_node);
1351                         _socket_to_node = NULL;
1352                         pr_info("UV: 1:1 socket_to_node table removed\n");
1353                 }
1354         }
1355         if (minsock == minpnode) {
1356                 for (i = 0; i < num; i++)
1357                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1358                                 _socket_to_pnode[i] != i + minpnode)
1359                                 break;
1360                 if (i >= num) {
1361                         kfree(_socket_to_pnode);
1362                         _socket_to_pnode = NULL;
1363                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1364                 }
1365         }
1366 }
1367
1368 void __init uv_system_init(void)
1369 {
1370         struct uv_hub_info_s hub_info = {0};
1371         int bytes, cpu, nodeid;
1372         unsigned short min_pnode = 9999, max_pnode = 0;
1373         char *hub = is_uv4_hub() ? "UV400" :
1374                     is_uv3_hub() ? "UV300" :
1375                     is_uv2_hub() ? "UV2000/3000" :
1376                     is_uv1_hub() ? "UV100/1000" : NULL;
1377
1378         if (!hub) {
1379                 pr_err("UV: Unknown/unsupported UV hub\n");
1380                 return;
1381         }
1382         pr_info("UV: Found %s hub\n", hub);
1383
1384         map_low_mmrs();
1385
1386         uv_bios_init();                 /* get uv_systab for decoding */
1387         if (decode_uv_systab() < 0)
1388                 return;                 /* UVsystab problem, abort UV init */
1389         build_socket_tables();
1390         build_uv_gr_table();
1391         uv_init_hub_info(&hub_info);
1392         uv_possible_blades = num_possible_nodes();
1393         if (!_node_to_pnode)
1394                 boot_init_possible_blades(&hub_info);
1395
1396         /* uv_num_possible_blades() is really the hub count */
1397         pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1398                         uv_num_possible_blades(),
1399                         num_possible_nodes(),
1400                         num_possible_cpus());
1401
1402         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1403                             &sn_region_size, &system_serial_number);
1404         hub_info.coherency_domain_number = sn_coherency_id;
1405         uv_rtc_init();
1406
1407         bytes = sizeof(void *) * uv_num_possible_blades();
1408         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1409         BUG_ON(!__uv_hub_info_list);
1410
1411         bytes = sizeof(struct uv_hub_info_s);
1412         for_each_node(nodeid) {
1413                 struct uv_hub_info_s *new_hub;
1414
1415                 if (__uv_hub_info_list[nodeid]) {
1416                         pr_err("UV: Node %d UV HUB already initialized!?\n",
1417                                 nodeid);
1418                         BUG();
1419                 }
1420
1421                 /* Allocate new per hub info list */
1422                 new_hub = (nodeid == 0) ?
1423                         &uv_hub_info_node0 :
1424                         kzalloc_node(bytes, GFP_KERNEL, nodeid);
1425                 BUG_ON(!new_hub);
1426                 __uv_hub_info_list[nodeid] = new_hub;
1427                 new_hub = uv_hub_info_list(nodeid);
1428                 BUG_ON(!new_hub);
1429                 *new_hub = hub_info;
1430
1431                 /* Use information from GAM table if available */
1432                 if (_node_to_pnode)
1433                         new_hub->pnode = _node_to_pnode[nodeid];
1434                 else    /* Fill in during cpu loop */
1435                         new_hub->pnode = 0xffff;
1436                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1437                 new_hub->memory_nid = -1;
1438                 new_hub->nr_possible_cpus = 0;
1439                 new_hub->nr_online_cpus = 0;
1440         }
1441
1442         /* Initialize per cpu info */
1443         for_each_possible_cpu(cpu) {
1444                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1445                 int numa_node_id;
1446                 unsigned short pnode;
1447
1448                 nodeid = cpu_to_node(cpu);
1449                 numa_node_id = numa_cpu_node(cpu);
1450                 pnode = uv_apicid_to_pnode(apicid);
1451
1452                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1453                 uv_cpu_info_per(cpu)->blade_cpu_id =
1454                         uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1455                 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1456                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1457                 if (nodeid != numa_node_id &&   /* init memoryless node */
1458                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1459                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1460                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1461                         uv_cpu_hub_info(cpu)->pnode = pnode;
1462                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1463         }
1464
1465         for_each_node(nodeid) {
1466                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1467
1468                 /* Add pnode info for pre-GAM list nodes without cpus */
1469                 if (pnode == 0xffff) {
1470                         unsigned long paddr;
1471
1472                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1473                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1474                         uv_hub_info_list(nodeid)->pnode = pnode;
1475                 }
1476                 min_pnode = min(pnode, min_pnode);
1477                 max_pnode = max(pnode, max_pnode);
1478                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1479                         nodeid,
1480                         uv_hub_info_list(nodeid)->pnode,
1481                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1482         }
1483
1484         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1485         map_gru_high(max_pnode);
1486         map_mmr_high(max_pnode);
1487         map_mmioh_high(min_pnode, max_pnode);
1488
1489         uv_nmi_setup();
1490         uv_cpu_init();
1491         uv_scir_register_cpu_notifier();
1492         proc_mkdir("sgi_uv", NULL);
1493
1494         /* register Legacy VGA I/O redirection handler */
1495         pci_register_set_vga_state(uv_set_vga_state);
1496
1497         /*
1498          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1499          * EFI is not enabled in the kdump kernel.
1500          */
1501         if (is_kdump_kernel())
1502                 reboot_type = BOOT_ACPI;
1503 }
1504
1505 apic_driver(apic_x2apic_uv_x);