arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/crash_dump.h>
  11 #include <linux/cpuhotplug.h>
  12 #include <linux/cpumask.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/memory.h>
  15 #include <linux/export.h>
  16 #include <linux/pci.h>
  17 #include <linux/acpi.h>
  18 #include <linux/efi.h>
  19
  20 #include <asm/e820/api.h>
  21 #include <asm/uv/uv_mmrs.h>
  22 #include <asm/uv/uv_hub.h>
  23 #include <asm/uv/bios.h>
  24 #include <asm/uv/uv.h>
  25 #include <asm/apic.h>
  26
  27 static DEFINE_PER_CPU(int, x2apic_extra_bits);
  28
  29 static enum uv_system_type      uv_system_type;
  30 static int                      uv_hubbed_system;
  31 static int                      uv_hubless_system;
  32 static u64                      gru_start_paddr, gru_end_paddr;
  33 static u64                      gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  34 static u64                      gru_dist_lmask, gru_dist_umask;
  35 static union uvh_apicid         uvh_apicid;
  36
  37 /* Unpack OEM/TABLE ID's to be NULL terminated strings */
  38 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
  39 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  40
  41 /* Information derived from CPUID: */
  42 static struct {
  43         unsigned int apicid_shift;
  44         unsigned int apicid_mask;
  45         unsigned int socketid_shift;    /* aka pnode_shift for UV1/2/3 */
  46         unsigned int pnode_mask;
  47         unsigned int gpa_shift;
  48         unsigned int gnode_shift;
  49 } uv_cpuid;
  50
  51 int uv_min_hub_revision_id;
  52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  53
  54 unsigned int uv_apicid_hibits;
  55 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  56
  57 static struct apic apic_x2apic_uv_x;
  58 static struct uv_hub_info_s uv_hub_info_node0;
  59
  60 /* Set this to use hardware error handler instead of kernel panic: */
  61 static int disable_uv_undefined_panic = 1;
  62
  63 unsigned long uv_undefined(char *str)
  64 {
  65         if (likely(!disable_uv_undefined_panic))
  66                 panic("UV: error: undefined MMR: %s\n", str);
  67         else
  68                 pr_crit("UV: error: undefined MMR: %s\n", str);
  69
  70         /* Cause a machine fault: */
  71         return ~0ul;
  72 }
  73 EXPORT_SYMBOL(uv_undefined);
  74
  75 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  76 {
  77         unsigned long val, *mmr;
  78
  79         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  80         val = *mmr;
  81         early_iounmap(mmr, sizeof(*mmr));
  82
  83         return val;
  84 }
  85
  86 static inline bool is_GRU_range(u64 start, u64 end)
  87 {
  88         if (gru_dist_base) {
  89                 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
  90                 u64 sl = start & gru_dist_lmask; /* Base offset bits */
  91                 u64 eu = end & gru_dist_umask;
  92                 u64 el = end & gru_dist_lmask;
  93
  94                 /* Must reside completely within a single GRU range: */
  95                 return (sl == gru_dist_base && el == gru_dist_base &&
  96                         su >= gru_first_node_paddr &&
  97                         su <= gru_last_node_paddr &&
  98                         eu == su);
  99         } else {
 100                 return start >= gru_start_paddr && end <= gru_end_paddr;
 101         }
 102 }
 103
 104 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 105 {
 106         return is_ISA_range(start, end) || is_GRU_range(start, end);
 107 }
 108
 109 static int __init early_get_pnodeid(void)
 110 {
 111         union uvh_node_id_u node_id;
 112         union uvh_rh_gam_config_mmr_u  m_n_config;
 113         int pnode;
 114
 115         /* Currently, all blades have same revision number */
 116         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 117         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 118         uv_min_hub_revision_id = node_id.s.revision;
 119
 120         switch (node_id.s.part_number) {
 121         case UV2_HUB_PART_NUMBER:
 122         case UV2_HUB_PART_NUMBER_X:
 123                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 124                 break;
 125         case UV3_HUB_PART_NUMBER:
 126         case UV3_HUB_PART_NUMBER_X:
 127                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 128                 break;
 129
 130         /* Update: UV4A has only a modified revision to indicate HUB fixes */
 131         case UV4_HUB_PART_NUMBER:
 132                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 133                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
 134                 break;
 135         }
 136
 137         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 138         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 139         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 140         uv_cpuid.gpa_shift = 46;        /* Default unless changed */
 141
 142         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 143                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 144                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 145         return pnode;
 146 }
 147
 148 static void __init uv_tsc_check_sync(void)
 149 {
 150         u64 mmr;
 151         int sync_state;
 152         int mmr_shift;
 153         char *state;
 154         bool valid;
 155
 156         /* Accommodate different UV arch BIOSes */
 157         mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
 158         mmr_shift =
 159                 is_uv1_hub() ? 0 :
 160                 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
 161         if (mmr_shift)
 162                 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
 163         else
 164                 sync_state = 0;
 165
 166         switch (sync_state) {
 167         case UVH_TSC_SYNC_VALID:
 168                 state = "in sync";
 169                 valid = true;
 170                 break;
 171
 172         case UVH_TSC_SYNC_INVALID:
 173                 state = "unstable";
 174                 valid = false;
 175                 break;
 176         default:
 177                 state = "unknown: assuming valid";
 178                 valid = true;
 179                 break;
 180         }
 181         pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
 182
 183         /* Mark flag that says TSC != 0 is valid for socket 0 */
 184         if (valid)
 185                 mark_tsc_async_resets("UV BIOS");
 186         else
 187                 mark_tsc_unstable("UV BIOS");
 188 }
 189
 190 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 191
 192 #define SMT_LEVEL                       0       /* Leaf 0xb SMT level */
 193 #define INVALID_TYPE                    0       /* Leaf 0xb sub-leaf types */
 194 #define SMT_TYPE                        1
 195 #define CORE_TYPE                       2
 196 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 197 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 198
 199 static void set_x2apic_bits(void)
 200 {
 201         unsigned int eax, ebx, ecx, edx, sub_index;
 202         unsigned int sid_shift;
 203
 204         cpuid(0, &eax, &ebx, &ecx, &edx);
 205         if (eax < 0xb) {
 206                 pr_info("UV: CPU does not have CPUID.11\n");
 207                 return;
 208         }
 209
 210         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 211         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 212                 pr_info("UV: CPUID.11 not implemented\n");
 213                 return;
 214         }
 215
 216         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 217         sub_index = 1;
 218         do {
 219                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 220                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 221                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 222                         break;
 223                 }
 224                 sub_index++;
 225         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 226
 227         uv_cpuid.apicid_shift   = 0;
 228         uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
 229         uv_cpuid.socketid_shift = sid_shift;
 230 }
 231
 232 static void __init early_get_apic_socketid_shift(void)
 233 {
 234         if (is_uv2_hub() || is_uv3_hub())
 235                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 236
 237         set_x2apic_bits();
 238
 239         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 240         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 241 }
 242
 243 /*
 244  * Add an extra bit as dictated by bios to the destination apicid of
 245  * interrupts potentially passing through the UV HUB.  This prevents
 246  * a deadlock between interrupts and IO port operations.
 247  */
 248 static void __init uv_set_apicid_hibit(void)
 249 {
 250         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 251
 252         if (is_uv1_hub()) {
 253                 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 254                 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 255         }
 256 }
 257
 258 static void __init uv_stringify(int len, char *to, char *from)
 259 {
 260         /* Relies on 'to' being NULL chars so result will be NULL terminated */
 261         strncpy(to, from, len-1);
 262 }
 263
 264 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
 265 {
 266         int pnodeid;
 267         int uv_apic;
 268
 269         uv_stringify(sizeof(oem_id), oem_id, _oem_id);
 270         uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
 271
 272         if (strncmp(oem_id, "SGI", 3) != 0) {
 273                 if (strncmp(oem_id, "NSGI", 4) != 0)
 274                         return 0;
 275
 276                 /* UV4 Hubless, CH, (0x11:UV4+Any) */
 277                 if (strncmp(oem_id, "NSGI4", 5) == 0)
 278                         uv_hubless_system = 0x11;
 279
 280                 /* UV3 Hubless, UV300/MC990X w/o hub (0x9:UV3+Any) */
 281                 else
 282                         uv_hubless_system = 0x9;
 283
 284                 pr_info("UV: OEM IDs %s/%s, HUBLESS(0x%x)\n",
 285                         oem_id, oem_table_id, uv_hubless_system);
 286
 287                 return 0;
 288         }
 289
 290         if (numa_off) {
 291                 pr_err("UV: NUMA is off, disabling UV support\n");
 292                 return 0;
 293         }
 294
 295         /* Set up early hub type field in uv_hub_info for Node 0 */
 296         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 297
 298         /*
 299          * Determine UV arch type.
 300          *   SGI:  UV100/1000
 301          *   SGI2: UV2000/3000
 302          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 303          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 304          */
 305         uv_hub_info->hub_revision =
 306                 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 307                 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 308                 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
 309                 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
 310
 311         if (uv_hub_info->hub_revision == 0)
 312                 goto badbios;
 313
 314         switch (uv_hub_info->hub_revision) {
 315         case UV4_HUB_REVISION_BASE:
 316                 uv_hubbed_system = 0x11;
 317                 break;
 318
 319         case UV3_HUB_REVISION_BASE:
 320                 uv_hubbed_system = 0x9;
 321                 break;
 322
 323         case UV2_HUB_REVISION_BASE:
 324                 uv_hubbed_system = 0x5;
 325                 break;
 326
 327         case UV1_HUB_REVISION_BASE:
 328                 uv_hubbed_system = 0x3;
 329                 break;
 330         }
 331
 332         pnodeid = early_get_pnodeid();
 333         early_get_apic_socketid_shift();
 334
 335         x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
 336         x86_platform.nmi_init = uv_nmi_init;
 337
 338         if (!strcmp(oem_table_id, "UVX")) {
 339                 /* This is the most common hardware variant: */
 340                 uv_system_type = UV_X2APIC;
 341                 uv_apic = 0;
 342
 343         } else if (!strcmp(oem_table_id, "UVH")) {
 344                 /* Only UV1 systems: */
 345                 uv_system_type = UV_NON_UNIQUE_APIC;
 346                 x86_platform.legacy.warm_reset = 0;
 347                 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
 348                 uv_set_apicid_hibit();
 349                 uv_apic = 1;
 350
 351         } else if (!strcmp(oem_table_id, "UVL")) {
 352                 /* Only used for very small systems:  */
 353                 uv_system_type = UV_LEGACY_APIC;
 354                 uv_apic = 0;
 355
 356         } else {
 357                 goto badbios;
 358         }
 359
 360         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
 361         uv_tsc_check_sync();
 362
 363         return uv_apic;
 364
 365 badbios:
 366         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 367         pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
 368         BUG();
 369 }
 370
 371 enum uv_system_type get_uv_system_type(void)
 372 {
 373         return uv_system_type;
 374 }
 375
 376 int is_uv_system(void)
 377 {
 378         return uv_system_type != UV_NONE;
 379 }
 380 EXPORT_SYMBOL_GPL(is_uv_system);
 381
 382 int is_uv_hubbed(int uvtype)
 383 {
 384         return (uv_hubbed_system & uvtype);
 385 }
 386 EXPORT_SYMBOL_GPL(is_uv_hubbed);
 387
 388 int is_uv_hubless(int uvtype)
 389 {
 390         return (uv_hubless_system & uvtype);
 391 }
 392 EXPORT_SYMBOL_GPL(is_uv_hubless);
 393
 394 void **__uv_hub_info_list;
 395 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 396
 397 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 398 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 399
 400 short uv_possible_blades;
 401 EXPORT_SYMBOL_GPL(uv_possible_blades);
 402
 403 unsigned long sn_rtc_cycles_per_second;
 404 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 405
 406 /* The following values are used for the per node hub info struct */
 407 static __initdata unsigned short                *_node_to_pnode;
 408 static __initdata unsigned short                _min_socket, _max_socket;
 409 static __initdata unsigned short                _min_pnode, _max_pnode, _gr_table_len;
 410 static __initdata struct uv_gam_range_entry     *uv_gre_table;
 411 static __initdata struct uv_gam_parameters      *uv_gp_table;
 412 static __initdata unsigned short                *_socket_to_node;
 413 static __initdata unsigned short                *_socket_to_pnode;
 414 static __initdata unsigned short                *_pnode_to_socket;
 415
 416 static __initdata struct uv_gam_range_s         *_gr_table;
 417
 418 #define SOCK_EMPTY      ((unsigned short)~0)
 419
 420 extern int uv_hub_info_version(void)
 421 {
 422         return UV_HUB_INFO_VERSION;
 423 }
 424 EXPORT_SYMBOL(uv_hub_info_version);
 425
 426 /* Default UV memory block size is 2GB */
 427 static unsigned long mem_block_size __initdata = (2UL << 30);
 428
 429 /* Kernel parameter to specify UV mem block size */
 430 static int __init parse_mem_block_size(char *ptr)
 431 {
 432         unsigned long size = memparse(ptr, NULL);
 433
 434         /* Size will be rounded down by set_block_size() below */
 435         mem_block_size = size;
 436         return 0;
 437 }
 438 early_param("uv_memblksize", parse_mem_block_size);
 439
 440 static __init int adj_blksize(u32 lgre)
 441 {
 442         unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
 443         unsigned long size;
 444
 445         for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
 446                 if (IS_ALIGNED(base, size))
 447                         break;
 448
 449         if (size >= mem_block_size)
 450                 return 0;
 451
 452         mem_block_size = size;
 453         return 1;
 454 }
 455
 456 static __init void set_block_size(void)
 457 {
 458         unsigned int order = ffs(mem_block_size);
 459
 460         if (order) {
 461                 /* adjust for ffs return of 1..64 */
 462                 set_memory_block_size_order(order - 1);
 463                 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
 464         } else {
 465                 /* bad or zero value, default to 1UL << 31 (2GB) */
 466                 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
 467                 set_memory_block_size_order(31);
 468         }
 469 }
 470
 471 /* Build GAM range lookup table: */
 472 static __init void build_uv_gr_table(void)
 473 {
 474         struct uv_gam_range_entry *gre = uv_gre_table;
 475         struct uv_gam_range_s *grt;
 476         unsigned long last_limit = 0, ram_limit = 0;
 477         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
 478
 479         if (!gre)
 480                 return;
 481
 482         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 483         grt = kzalloc(bytes, GFP_KERNEL);
 484         BUG_ON(!grt);
 485         _gr_table = grt;
 486
 487         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 488                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 489                         if (!ram_limit) {
 490                                 /* Mark hole between RAM/non-RAM: */
 491                                 ram_limit = last_limit;
 492                                 last_limit = gre->limit;
 493                                 lsid++;
 494                                 continue;
 495                         }
 496                         last_limit = gre->limit;
 497                         pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
 498                         continue;
 499                 }
 500                 if (_max_socket < gre->sockid) {
 501                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
 502                         continue;
 503                 }
 504                 sid = gre->sockid - _min_socket;
 505                 if (lsid < sid) {
 506                         /* New range: */
 507                         grt = &_gr_table[indx];
 508                         grt->base = lindx;
 509                         grt->nasid = gre->nasid;
 510                         grt->limit = last_limit = gre->limit;
 511                         lsid = sid;
 512                         lindx = indx++;
 513                         continue;
 514                 }
 515                 /* Update range: */
 516                 if (lsid == sid && !ram_limit) {
 517                         /* .. if contiguous: */
 518                         if (grt->limit == last_limit) {
 519                                 grt->limit = last_limit = gre->limit;
 520                                 continue;
 521                         }
 522                 }
 523                 /* Non-contiguous RAM range: */
 524                 if (!ram_limit) {
 525                         grt++;
 526                         grt->base = lindx;
 527                         grt->nasid = gre->nasid;
 528                         grt->limit = last_limit = gre->limit;
 529                         continue;
 530                 }
 531                 /* Non-contiguous/non-RAM: */
 532                 grt++;
 533                 /* base is this entry */
 534                 grt->base = grt - _gr_table;
 535                 grt->nasid = gre->nasid;
 536                 grt->limit = last_limit = gre->limit;
 537                 lsid++;
 538         }
 539
 540         /* Shorten table if possible */
 541         grt++;
 542         i = grt - _gr_table;
 543         if (i < _gr_table_len) {
 544                 void *ret;
 545
 546                 bytes = i * sizeof(struct uv_gam_range_s);
 547                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 548                 if (ret) {
 549                         _gr_table = ret;
 550                         _gr_table_len = i;
 551                 }
 552         }
 553
 554         /* Display resultant GAM range table: */
 555         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 556                 unsigned long start, end;
 557                 int gb = grt->base;
 558
 559                 start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 560                 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 561
 562                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
 563         }
 564 }
 565
 566 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 567 {
 568         unsigned long val;
 569         int pnode;
 570
 571         pnode = uv_apicid_to_pnode(phys_apicid);
 572         phys_apicid |= uv_apicid_hibits;
 573
 574         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 575             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 576             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 577             APIC_DM_INIT;
 578
 579         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 580
 581         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 582             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 583             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 584             APIC_DM_STARTUP;
 585
 586         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 587
 588         return 0;
 589 }
 590
 591 static void uv_send_IPI_one(int cpu, int vector)
 592 {
 593         unsigned long apicid;
 594         int pnode;
 595
 596         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 597         pnode = uv_apicid_to_pnode(apicid);
 598         uv_hub_send_ipi(pnode, apicid, vector);
 599 }
 600
 601 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 602 {
 603         unsigned int cpu;
 604
 605         for_each_cpu(cpu, mask)
 606                 uv_send_IPI_one(cpu, vector);
 607 }
 608
 609 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 610 {
 611         unsigned int this_cpu = smp_processor_id();
 612         unsigned int cpu;
 613
 614         for_each_cpu(cpu, mask) {
 615                 if (cpu != this_cpu)
 616                         uv_send_IPI_one(cpu, vector);
 617         }
 618 }
 619
 620 static void uv_send_IPI_allbutself(int vector)
 621 {
 622         unsigned int this_cpu = smp_processor_id();
 623         unsigned int cpu;
 624
 625         for_each_online_cpu(cpu) {
 626                 if (cpu != this_cpu)
 627                         uv_send_IPI_one(cpu, vector);
 628         }
 629 }
 630
 631 static void uv_send_IPI_all(int vector)
 632 {
 633         uv_send_IPI_mask(cpu_online_mask, vector);
 634 }
 635
 636 static int uv_apic_id_valid(u32 apicid)
 637 {
 638         return 1;
 639 }
 640
 641 static int uv_apic_id_registered(void)
 642 {
 643         return 1;
 644 }
 645
 646 static void uv_init_apic_ldr(void)
 647 {
 648 }
 649
 650 static u32 apic_uv_calc_apicid(unsigned int cpu)
 651 {
 652         return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
 653 }
 654
 655 static unsigned int x2apic_get_apic_id(unsigned long x)
 656 {
 657         unsigned int id;
 658
 659         WARN_ON(preemptible() && num_online_cpus() > 1);
 660         id = x | __this_cpu_read(x2apic_extra_bits);
 661
 662         return id;
 663 }
 664
 665 static u32 set_apic_id(unsigned int id)
 666 {
 667         /* CHECKME: Do we need to mask out the xapic extra bits? */
 668         return id;
 669 }
 670
 671 static unsigned int uv_read_apic_id(void)
 672 {
 673         return x2apic_get_apic_id(apic_read(APIC_ID));
 674 }
 675
 676 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 677 {
 678         return uv_read_apic_id() >> index_msb;
 679 }
 680
 681 static void uv_send_IPI_self(int vector)
 682 {
 683         apic_write(APIC_SELF_IPI, vector);
 684 }
 685
 686 static int uv_probe(void)
 687 {
 688         return apic == &apic_x2apic_uv_x;
 689 }
 690
 691 static struct apic apic_x2apic_uv_x __ro_after_init = {
 692
 693         .name                           = "UV large system",
 694         .probe                          = uv_probe,
 695         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 696         .apic_id_valid                  = uv_apic_id_valid,
 697         .apic_id_registered             = uv_apic_id_registered,
 698
 699         .irq_delivery_mode              = dest_Fixed,
 700         .irq_dest_mode                  = 0, /* Physical */
 701
 702         .disable_esr                    = 0,
 703         .dest_logical                   = APIC_DEST_LOGICAL,
 704         .check_apicid_used              = NULL,
 705
 706         .init_apic_ldr                  = uv_init_apic_ldr,
 707
 708         .ioapic_phys_id_map             = NULL,
 709         .setup_apic_routing             = NULL,
 710         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 711         .apicid_to_cpu_present          = NULL,
 712         .check_phys_apicid_present      = default_check_phys_apicid_present,
 713         .phys_pkg_id                    = uv_phys_pkg_id,
 714
 715         .get_apic_id                    = x2apic_get_apic_id,
 716         .set_apic_id                    = set_apic_id,
 717
 718         .calc_dest_apicid               = apic_uv_calc_apicid,
 719
 720         .send_IPI                       = uv_send_IPI_one,
 721         .send_IPI_mask                  = uv_send_IPI_mask,
 722         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 723         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 724         .send_IPI_all                   = uv_send_IPI_all,
 725         .send_IPI_self                  = uv_send_IPI_self,
 726
 727         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 728         .inquire_remote_apic            = NULL,
 729
 730         .read                           = native_apic_msr_read,
 731         .write                          = native_apic_msr_write,
 732         .eoi_write                      = native_apic_msr_eoi_write,
 733         .icr_read                       = native_x2apic_icr_read,
 734         .icr_write                      = native_x2apic_icr_write,
 735         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 736         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 737 };
 738
 739 static void set_x2apic_extra_bits(int pnode)
 740 {
 741         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 742 }
 743
 744 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 745 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 746
 747 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 748 {
 749         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 750         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 751         unsigned long m_redirect;
 752         unsigned long m_overlay;
 753         int i;
 754
 755         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 756                 switch (i) {
 757                 case 0:
 758                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 759                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 760                         break;
 761                 case 1:
 762                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 763                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 764                         break;
 765                 case 2:
 766                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 767                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 768                         break;
 769                 }
 770                 alias.v = uv_read_local_mmr(m_overlay);
 771                 if (alias.s.enable && alias.s.base == 0) {
 772                         *size = (1UL << alias.s.m_alias);
 773                         redirect.v = uv_read_local_mmr(m_redirect);
 774                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 775                         return;
 776                 }
 777         }
 778         *base = *size = 0;
 779 }
 780
 781 enum map_type {map_wb, map_uc};
 782
 783 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
 784 {
 785         unsigned long bytes, paddr;
 786
 787         paddr = base << pshift;
 788         bytes = (1UL << bshift) * (max_pnode + 1);
 789         if (!paddr) {
 790                 pr_info("UV: Map %s_HI base address NULL\n", id);
 791                 return;
 792         }
 793         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 794         if (map_type == map_uc)
 795                 init_extra_mapping_uc(paddr, bytes);
 796         else
 797                 init_extra_mapping_wb(paddr, bytes);
 798 }
 799
 800 static __init void map_gru_distributed(unsigned long c)
 801 {
 802         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 803         u64 paddr;
 804         unsigned long bytes;
 805         int nid;
 806
 807         gru.v = c;
 808
 809         /* Only base bits 42:28 relevant in dist mode */
 810         gru_dist_base = gru.v & 0x000007fff0000000UL;
 811         if (!gru_dist_base) {
 812                 pr_info("UV: Map GRU_DIST base address NULL\n");
 813                 return;
 814         }
 815
 816         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 817         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 818         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 819         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 820
 821         for_each_online_node(nid) {
 822                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 823                                 gru_dist_base;
 824                 init_extra_mapping_wb(paddr, bytes);
 825                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 826                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 827         }
 828
 829         /* Save upper (63:M) bits of address only for is_GRU_range */
 830         gru_first_node_paddr &= gru_dist_umask;
 831         gru_last_node_paddr &= gru_dist_umask;
 832
 833         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 834 }
 835
 836 static __init void map_gru_high(int max_pnode)
 837 {
 838         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 839         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 840         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 841         unsigned long base;
 842
 843         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 844         if (!gru.s.enable) {
 845                 pr_info("UV: GRU disabled\n");
 846                 return;
 847         }
 848
 849         /* Only UV3 has distributed GRU mode */
 850         if (is_uv3_hub() && gru.s3.mode) {
 851                 map_gru_distributed(gru.v);
 852                 return;
 853         }
 854
 855         base = (gru.v & mask) >> shift;
 856         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 857         gru_start_paddr = ((u64)base << shift);
 858         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 859 }
 860
 861 static __init void map_mmr_high(int max_pnode)
 862 {
 863         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 864         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 865
 866         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 867         if (mmr.s.enable)
 868                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 869         else
 870                 pr_info("UV: MMR disabled\n");
 871 }
 872
 873 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
 874 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
 875 {
 876         unsigned long overlay;
 877         unsigned long mmr;
 878         unsigned long base;
 879         unsigned long nasid_mask;
 880         unsigned long m_overlay;
 881         int i, n, shift, m_io, max_io;
 882         int nasid, lnasid, fi, li;
 883         char *id;
 884
 885         if (index == 0) {
 886                 id = "MMIOH0";
 887                 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
 888                 overlay = uv_read_local_mmr(m_overlay);
 889                 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
 890                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
 891                 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
 892                         >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
 893                 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
 894                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 895                 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
 896         } else {
 897                 id = "MMIOH1";
 898                 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
 899                 overlay = uv_read_local_mmr(m_overlay);
 900                 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
 901                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
 902                 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
 903                         >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
 904                 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
 905                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
 906                 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
 907         }
 908         pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
 909         if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
 910                 pr_info("UV: %s disabled\n", id);
 911                 return;
 912         }
 913
 914         /* Convert to NASID: */
 915         min_pnode *= 2;
 916         max_pnode *= 2;
 917         max_io = lnasid = fi = li = -1;
 918
 919         for (i = 0; i < n; i++) {
 920                 unsigned long m_redirect = mmr + i * 8;
 921                 unsigned long redirect = uv_read_local_mmr(m_redirect);
 922
 923                 nasid = redirect & nasid_mask;
 924                 if (i == 0)
 925                         pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
 926                                 id, redirect, m_redirect, nasid);
 927
 928                 /* Invalid NASID: */
 929                 if (nasid < min_pnode || max_pnode < nasid)
 930                         nasid = -1;
 931
 932                 if (nasid == lnasid) {
 933                         li = i;
 934                         /* Last entry check: */
 935                         if (i != n-1)
 936                                 continue;
 937                 }
 938
 939                 /* Check if we have a cached (or last) redirect to print: */
 940                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 941                         unsigned long addr1, addr2;
 942                         int f, l;
 943
 944                         if (lnasid == -1) {
 945                                 f = l = i;
 946                                 lnasid = nasid;
 947                         } else {
 948                                 f = fi;
 949                                 l = li;
 950                         }
 951                         addr1 = (base << shift) + f * (1ULL << m_io);
 952                         addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
 953                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
 954                         if (max_io < l)
 955                                 max_io = l;
 956                 }
 957                 fi = li = i;
 958                 lnasid = nasid;
 959         }
 960
 961         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
 962
 963         if (max_io >= 0)
 964                 map_high(id, base, shift, m_io, max_io, map_uc);
 965 }
 966
 967 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 968 {
 969         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 970         unsigned long mmr, base;
 971         int shift, enable, m_io, n_io;
 972
 973         if (is_uv3_hub() || is_uv4_hub()) {
 974                 /* Map both MMIOH regions: */
 975                 map_mmioh_high_uv34(0, min_pnode, max_pnode);
 976                 map_mmioh_high_uv34(1, min_pnode, max_pnode);
 977                 return;
 978         }
 979
 980         if (is_uv1_hub()) {
 981                 mmr     = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 982                 shift   = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 983                 mmioh.v = uv_read_local_mmr(mmr);
 984                 enable  = !!mmioh.s1.enable;
 985                 base    = mmioh.s1.base;
 986                 m_io    = mmioh.s1.m_io;
 987                 n_io    = mmioh.s1.n_io;
 988         } else if (is_uv2_hub()) {
 989                 mmr     = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 990                 shift   = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 991                 mmioh.v = uv_read_local_mmr(mmr);
 992                 enable  = !!mmioh.s2.enable;
 993                 base    = mmioh.s2.base;
 994                 m_io    = mmioh.s2.m_io;
 995                 n_io    = mmioh.s2.n_io;
 996         } else {
 997                 return;
 998         }
 999
1000         if (enable) {
1001                 max_pnode &= (1 << n_io) - 1;
1002                 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
1003                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
1004         } else {
1005                 pr_info("UV: MMIOH disabled\n");
1006         }
1007 }
1008
1009 static __init void map_low_mmrs(void)
1010 {
1011         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1012         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1013 }
1014
1015 static __init void uv_rtc_init(void)
1016 {
1017         long status;
1018         u64 ticks_per_sec;
1019
1020         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1021
1022         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1023                 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1024
1025                 /* BIOS gives wrong value for clock frequency, so guess: */
1026                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1027         } else {
1028                 sn_rtc_cycles_per_second = ticks_per_sec;
1029         }
1030 }
1031
1032 /*
1033  * percpu heartbeat timer
1034  */
1035 static void uv_heartbeat(struct timer_list *timer)
1036 {
1037         unsigned char bits = uv_scir_info->state;
1038
1039         /* Flip heartbeat bit: */
1040         bits ^= SCIR_CPU_HEARTBEAT;
1041
1042         /* Is this CPU idle? */
1043         if (idle_cpu(raw_smp_processor_id()))
1044                 bits &= ~SCIR_CPU_ACTIVITY;
1045         else
1046                 bits |= SCIR_CPU_ACTIVITY;
1047
1048         /* Update system controller interface reg: */
1049         uv_set_scir_bits(bits);
1050
1051         /* Enable next timer period: */
1052         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1053 }
1054
1055 static int uv_heartbeat_enable(unsigned int cpu)
1056 {
1057         while (!uv_cpu_scir_info(cpu)->enabled) {
1058                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1059
1060                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1061                 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
1062                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1063                 add_timer_on(timer, cpu);
1064                 uv_cpu_scir_info(cpu)->enabled = 1;
1065
1066                 /* Also ensure that boot CPU is enabled: */
1067                 cpu = 0;
1068         }
1069         return 0;
1070 }
1071
1072 #ifdef CONFIG_HOTPLUG_CPU
1073 static int uv_heartbeat_disable(unsigned int cpu)
1074 {
1075         if (uv_cpu_scir_info(cpu)->enabled) {
1076                 uv_cpu_scir_info(cpu)->enabled = 0;
1077                 del_timer(&uv_cpu_scir_info(cpu)->timer);
1078         }
1079         uv_set_cpu_scir_bits(cpu, 0xff);
1080         return 0;
1081 }
1082
1083 static __init void uv_scir_register_cpu_notifier(void)
1084 {
1085         cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1086                                   uv_heartbeat_enable, uv_heartbeat_disable);
1087 }
1088
1089 #else /* !CONFIG_HOTPLUG_CPU */
1090
1091 static __init void uv_scir_register_cpu_notifier(void)
1092 {
1093 }
1094
1095 static __init int uv_init_heartbeat(void)
1096 {
1097         int cpu;
1098
1099         if (is_uv_system()) {
1100                 for_each_online_cpu(cpu)
1101                         uv_heartbeat_enable(cpu);
1102         }
1103
1104         return 0;
1105 }
1106
1107 late_initcall(uv_init_heartbeat);
1108
1109 #endif /* !CONFIG_HOTPLUG_CPU */
1110
1111 /* Direct Legacy VGA I/O traffic to designated IOH */
1112 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1113 {
1114         int domain, bus, rc;
1115
1116         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1117                 return 0;
1118
1119         if ((command_bits & PCI_COMMAND_IO) == 0)
1120                 return 0;
1121
1122         domain = pci_domain_nr(pdev->bus);
1123         bus = pdev->bus->number;
1124
1125         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1126
1127         return rc;
1128 }
1129
1130 /*
1131  * Called on each CPU to initialize the per_cpu UV data area.
1132  * FIXME: hotplug not supported yet
1133  */
1134 void uv_cpu_init(void)
1135 {
1136         /* CPU 0 initialization will be done via uv_system_init. */
1137         if (smp_processor_id() == 0)
1138                 return;
1139
1140         uv_hub_info->nr_online_cpus++;
1141
1142         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1143                 set_x2apic_extra_bits(uv_hub_info->pnode);
1144 }
1145
1146 struct mn {
1147         unsigned char   m_val;
1148         unsigned char   n_val;
1149         unsigned char   m_shift;
1150         unsigned char   n_lshift;
1151 };
1152
1153 static void get_mn(struct mn *mnp)
1154 {
1155         union uvh_rh_gam_config_mmr_u m_n_config;
1156         union uv3h_gr0_gam_gr_config_u m_gr_config;
1157
1158         /* Make sure the whole structure is well initialized: */
1159         memset(mnp, 0, sizeof(*mnp));
1160
1161         m_n_config.v    = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1162         mnp->n_val      = m_n_config.s.n_skt;
1163
1164         if (is_uv4_hub()) {
1165                 mnp->m_val      = 0;
1166                 mnp->n_lshift   = 0;
1167         } else if (is_uv3_hub()) {
1168                 mnp->m_val      = m_n_config.s3.m_skt;
1169                 m_gr_config.v   = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1170                 mnp->n_lshift   = m_gr_config.s3.m_skt;
1171         } else if (is_uv2_hub()) {
1172                 mnp->m_val      = m_n_config.s2.m_skt;
1173                 mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1174         } else if (is_uv1_hub()) {
1175                 mnp->m_val      = m_n_config.s1.m_skt;
1176                 mnp->n_lshift   = mnp->m_val;
1177         }
1178         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1179 }
1180
1181 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1182 {
1183         union uvh_node_id_u node_id;
1184         struct mn mn;
1185
1186         get_mn(&mn);
1187         hi->gpa_mask = mn.m_val ?
1188                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1189                 (1UL << uv_cpuid.gpa_shift) - 1;
1190
1191         hi->m_val               = mn.m_val;
1192         hi->n_val               = mn.n_val;
1193         hi->m_shift             = mn.m_shift;
1194         hi->n_lshift            = mn.n_lshift ? mn.n_lshift : 0;
1195         hi->hub_revision        = uv_hub_info->hub_revision;
1196         hi->pnode_mask          = uv_cpuid.pnode_mask;
1197         hi->min_pnode           = _min_pnode;
1198         hi->min_socket          = _min_socket;
1199         hi->pnode_to_socket     = _pnode_to_socket;
1200         hi->socket_to_node      = _socket_to_node;
1201         hi->socket_to_pnode     = _socket_to_pnode;
1202         hi->gr_table_len        = _gr_table_len;
1203         hi->gr_table            = _gr_table;
1204
1205         node_id.v               = uv_read_local_mmr(UVH_NODE_ID);
1206         uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1207         hi->gnode_extra         = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1208         if (mn.m_val)
1209                 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1210
1211         if (uv_gp_table) {
1212                 hi->global_mmr_base     = uv_gp_table->mmr_base;
1213                 hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1214                 hi->global_gru_base     = uv_gp_table->gru_base;
1215                 hi->global_gru_shift    = uv_gp_table->gru_shift;
1216                 hi->gpa_shift           = uv_gp_table->gpa_shift;
1217                 hi->gpa_mask            = (1UL << hi->gpa_shift) - 1;
1218         } else {
1219                 hi->global_mmr_base     = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1220                 hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1221         }
1222
1223         get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1224
1225         hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1226
1227         /* Show system specific info: */
1228         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1229         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1230         pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1231         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1232 }
1233
1234 static void __init decode_gam_params(unsigned long ptr)
1235 {
1236         uv_gp_table = (struct uv_gam_parameters *)ptr;
1237
1238         pr_info("UV: GAM Params...\n");
1239         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1240                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1241                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1242                 uv_gp_table->gpa_shift);
1243 }
1244
1245 static void __init decode_gam_rng_tbl(unsigned long ptr)
1246 {
1247         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1248         unsigned long lgre = 0;
1249         int index = 0;
1250         int sock_min = 999999, pnode_min = 99999;
1251         int sock_max = -1, pnode_max = -1;
1252
1253         uv_gre_table = gre;
1254         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1255                 unsigned long size = ((unsigned long)(gre->limit - lgre)
1256                                         << UV_GAM_RANGE_SHFT);
1257                 int order = 0;
1258                 char suffix[] = " KMGTPE";
1259                 int flag = ' ';
1260
1261                 while (size > 9999 && order < sizeof(suffix)) {
1262                         size /= 1024;
1263                         order++;
1264                 }
1265
1266                 /* adjust max block size to current range start */
1267                 if (gre->type == 1 || gre->type == 2)
1268                         if (adj_blksize(lgre))
1269                                 flag = '*';
1270
1271                 if (!index) {
1272                         pr_info("UV: GAM Range Table...\n");
1273                         pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1274                 }
1275                 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1276                         index++,
1277                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1278                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1279                         flag, size, suffix[order],
1280                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1281
1282                 /* update to next range start */
1283                 lgre = gre->limit;
1284                 if (sock_min > gre->sockid)
1285                         sock_min = gre->sockid;
1286                 if (sock_max < gre->sockid)
1287                         sock_max = gre->sockid;
1288                 if (pnode_min > gre->pnode)
1289                         pnode_min = gre->pnode;
1290                 if (pnode_max < gre->pnode)
1291                         pnode_max = gre->pnode;
1292         }
1293         _min_socket     = sock_min;
1294         _max_socket     = sock_max;
1295         _min_pnode      = pnode_min;
1296         _max_pnode      = pnode_max;
1297         _gr_table_len   = index;
1298
1299         pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1300 }
1301
1302 static int __init decode_uv_systab(void)
1303 {
1304         struct uv_systab *st;
1305         int i;
1306
1307         /* If system is uv3 or lower, there is no extended UVsystab */
1308         if (is_uv_hubbed(0xfffffe) < uv(4) && is_uv_hubless(0xfffffe) < uv(4))
1309                 return 0;       /* No extended UVsystab required */
1310
1311         st = uv_systab;
1312         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1313                 int rev = st ? st->revision : 0;
1314
1315                 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1316                 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1317                 uv_system_type = UV_NONE;
1318
1319                 return -EINVAL;
1320         }
1321
1322         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1323                 unsigned long ptr = st->entry[i].offset;
1324
1325                 if (!ptr)
1326                         continue;
1327
1328                 ptr = ptr + (unsigned long)st;
1329
1330                 switch (st->entry[i].type) {
1331                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1332                         decode_gam_params(ptr);
1333                         break;
1334
1335                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1336                         decode_gam_rng_tbl(ptr);
1337                         break;
1338                 }
1339         }
1340         return 0;
1341 }
1342
1343 /*
1344  * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1345  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1346  * .. being replaced by GAM Range Table
1347  */
1348 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1349 {
1350         int i, uv_pb = 0;
1351
1352         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1353         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1354                 unsigned long np;
1355
1356                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1357                 if (np)
1358                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1359
1360                 uv_pb += hweight64(np);
1361         }
1362         if (uv_possible_blades != uv_pb)
1363                 uv_possible_blades = uv_pb;
1364 }
1365
1366 static void __init build_socket_tables(void)
1367 {
1368         struct uv_gam_range_entry *gre = uv_gre_table;
1369         int num, nump;
1370         int cpu, i, lnid;
1371         int minsock = _min_socket;
1372         int maxsock = _max_socket;
1373         int minpnode = _min_pnode;
1374         int maxpnode = _max_pnode;
1375         size_t bytes;
1376
1377         if (!gre) {
1378                 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1379                         pr_info("UV: No UVsystab socket table, ignoring\n");
1380                         return;
1381                 }
1382                 pr_crit("UV: Error: UVsystab address translations not available!\n");
1383                 BUG();
1384         }
1385
1386         /* Build socket id -> node id, pnode */
1387         num = maxsock - minsock + 1;
1388         bytes = num * sizeof(_socket_to_node[0]);
1389         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1390         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1391
1392         nump = maxpnode - minpnode + 1;
1393         bytes = nump * sizeof(_pnode_to_socket[0]);
1394         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1395         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1396
1397         for (i = 0; i < num; i++)
1398                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1399
1400         for (i = 0; i < nump; i++)
1401                 _pnode_to_socket[i] = SOCK_EMPTY;
1402
1403         /* Fill in pnode/node/addr conversion list values: */
1404         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1405         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1406                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1407                         continue;
1408                 i = gre->sockid - minsock;
1409                 /* Duplicate: */
1410                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1411                         continue;
1412                 _socket_to_pnode[i] = gre->pnode;
1413
1414                 i = gre->pnode - minpnode;
1415                 _pnode_to_socket[i] = gre->sockid;
1416
1417                 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1418                         gre->sockid, gre->type, gre->nasid,
1419                         _socket_to_pnode[gre->sockid - minsock],
1420                         _pnode_to_socket[gre->pnode - minpnode]);
1421         }
1422
1423         /* Set socket -> node values: */
1424         lnid = NUMA_NO_NODE;
1425         for_each_present_cpu(cpu) {
1426                 int nid = cpu_to_node(cpu);
1427                 int apicid, sockid;
1428
1429                 if (lnid == nid)
1430                         continue;
1431                 lnid = nid;
1432                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1433                 sockid = apicid >> uv_cpuid.socketid_shift;
1434                 _socket_to_node[sockid - minsock] = nid;
1435                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1436                         sockid, apicid, nid);
1437         }
1438
1439         /* Set up physical blade to pnode translation from GAM Range Table: */
1440         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1441         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1442         BUG_ON(!_node_to_pnode);
1443
1444         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1445                 unsigned short sockid;
1446
1447                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1448                         if (lnid == _socket_to_node[sockid - minsock]) {
1449                                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1450                                 break;
1451                         }
1452                 }
1453                 if (sockid > maxsock) {
1454                         pr_err("UV: socket for node %d not found!\n", lnid);
1455                         BUG();
1456                 }
1457         }
1458
1459         /*
1460          * If socket id == pnode or socket id == node for all nodes,
1461          *   system runs faster by removing corresponding conversion table.
1462          */
1463         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1464         if (minsock == 0) {
1465                 for (i = 0; i < num; i++)
1466                         if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1467                                 break;
1468                 if (i >= num) {
1469                         kfree(_socket_to_node);
1470                         _socket_to_node = NULL;
1471                         pr_info("UV: 1:1 socket_to_node table removed\n");
1472                 }
1473         }
1474         if (minsock == minpnode) {
1475                 for (i = 0; i < num; i++)
1476                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1477                                 _socket_to_pnode[i] != i + minpnode)
1478                                 break;
1479                 if (i >= num) {
1480                         kfree(_socket_to_pnode);
1481                         _socket_to_pnode = NULL;
1482                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1483                 }
1484         }
1485 }
1486
1487 /* Check which reboot to use */
1488 static void check_efi_reboot(void)
1489 {
1490         /* If EFI reboot not available, use ACPI reboot */
1491         if (!efi_enabled(EFI_BOOT))
1492                 reboot_type = BOOT_ACPI;
1493 }
1494
1495 /* Setup user proc fs files */
1496 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1497 {
1498         seq_printf(file, "0x%x\n", uv_hubbed_system);
1499         return 0;
1500 }
1501
1502 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1503 {
1504         seq_printf(file, "0x%x\n", uv_hubless_system);
1505         return 0;
1506 }
1507
1508 static int __maybe_unused proc_oemid_show(struct seq_file *file, void *data)
1509 {
1510         seq_printf(file, "%s/%s\n", oem_id, oem_table_id);
1511         return 0;
1512 }
1513
1514 static __init void uv_setup_proc_files(int hubless)
1515 {
1516         struct proc_dir_entry *pde;
1517
1518         pde = proc_mkdir(UV_PROC_NODE, NULL);
1519         proc_create_single("oemid", 0, pde, proc_oemid_show);
1520         if (hubless)
1521                 proc_create_single("hubless", 0, pde, proc_hubless_show);
1522         else
1523                 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1524 }
1525
1526 /* Initialize UV hubless systems */
1527 static __init int uv_system_init_hubless(void)
1528 {
1529         int rc;
1530
1531         /* Setup PCH NMI handler */
1532         uv_nmi_setup_hubless();
1533
1534         /* Init kernel/BIOS interface */
1535         rc = uv_bios_init();
1536         if (rc < 0)
1537                 return rc;
1538
1539         /* Process UVsystab */
1540         rc = decode_uv_systab();
1541         if (rc < 0)
1542                 return rc;
1543
1544         /* Create user access node */
1545         if (rc >= 0)
1546                 uv_setup_proc_files(1);
1547
1548         check_efi_reboot();
1549
1550         return rc;
1551 }
1552
1553 static void __init uv_system_init_hub(void)
1554 {
1555         struct uv_hub_info_s hub_info = {0};
1556         int bytes, cpu, nodeid;
1557         unsigned short min_pnode = 9999, max_pnode = 0;
1558         char *hub = is_uv4_hub() ? "UV400" :
1559                     is_uv3_hub() ? "UV300" :
1560                     is_uv2_hub() ? "UV2000/3000" :
1561                     is_uv1_hub() ? "UV100/1000" : NULL;
1562
1563         if (!hub) {
1564                 pr_err("UV: Unknown/unsupported UV hub\n");
1565                 return;
1566         }
1567         pr_info("UV: Found %s hub\n", hub);
1568
1569         map_low_mmrs();
1570
1571         /* Get uv_systab for decoding: */
1572         uv_bios_init();
1573
1574         /* If there's an UVsystab problem then abort UV init: */
1575         if (decode_uv_systab() < 0)
1576                 return;
1577
1578         build_socket_tables();
1579         build_uv_gr_table();
1580         set_block_size();
1581         uv_init_hub_info(&hub_info);
1582         uv_possible_blades = num_possible_nodes();
1583         if (!_node_to_pnode)
1584                 boot_init_possible_blades(&hub_info);
1585
1586         /* uv_num_possible_blades() is really the hub count: */
1587         pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1588
1589         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1590         hub_info.coherency_domain_number = sn_coherency_id;
1591         uv_rtc_init();
1592
1593         bytes = sizeof(void *) * uv_num_possible_blades();
1594         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1595         BUG_ON(!__uv_hub_info_list);
1596
1597         bytes = sizeof(struct uv_hub_info_s);
1598         for_each_node(nodeid) {
1599                 struct uv_hub_info_s *new_hub;
1600
1601                 if (__uv_hub_info_list[nodeid]) {
1602                         pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1603                         BUG();
1604                 }
1605
1606                 /* Allocate new per hub info list */
1607                 new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1608                 BUG_ON(!new_hub);
1609                 __uv_hub_info_list[nodeid] = new_hub;
1610                 new_hub = uv_hub_info_list(nodeid);
1611                 BUG_ON(!new_hub);
1612                 *new_hub = hub_info;
1613
1614                 /* Use information from GAM table if available: */
1615                 if (_node_to_pnode)
1616                         new_hub->pnode = _node_to_pnode[nodeid];
1617                 else /* Or fill in during CPU loop: */
1618                         new_hub->pnode = 0xffff;
1619
1620                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1621                 new_hub->memory_nid = NUMA_NO_NODE;
1622                 new_hub->nr_possible_cpus = 0;
1623                 new_hub->nr_online_cpus = 0;
1624         }
1625
1626         /* Initialize per CPU info: */
1627         for_each_possible_cpu(cpu) {
1628                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1629                 int numa_node_id;
1630                 unsigned short pnode;
1631
1632                 nodeid = cpu_to_node(cpu);
1633                 numa_node_id = numa_cpu_node(cpu);
1634                 pnode = uv_apicid_to_pnode(apicid);
1635
1636                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1637                 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1638                 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1639                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1640
1641                 /* Init memoryless node: */
1642                 if (nodeid != numa_node_id &&
1643                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1644                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1645                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1646                         uv_cpu_hub_info(cpu)->pnode = pnode;
1647
1648                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1649         }
1650
1651         for_each_node(nodeid) {
1652                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1653
1654                 /* Add pnode info for pre-GAM list nodes without CPUs: */
1655                 if (pnode == 0xffff) {
1656                         unsigned long paddr;
1657
1658                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1659                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1660                         uv_hub_info_list(nodeid)->pnode = pnode;
1661                 }
1662                 min_pnode = min(pnode, min_pnode);
1663                 max_pnode = max(pnode, max_pnode);
1664                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1665                         nodeid,
1666                         uv_hub_info_list(nodeid)->pnode,
1667                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1668         }
1669
1670         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1671         map_gru_high(max_pnode);
1672         map_mmr_high(max_pnode);
1673         map_mmioh_high(min_pnode, max_pnode);
1674
1675         uv_nmi_setup();
1676         uv_cpu_init();
1677         uv_scir_register_cpu_notifier();
1678         uv_setup_proc_files(0);
1679
1680         /* Register Legacy VGA I/O redirection handler: */
1681         pci_register_set_vga_state(uv_set_vga_state);
1682
1683         check_efi_reboot();
1684 }
1685
1686 /*
1687  * There is a different code path needed to initialize a UV system that does
1688  * not have a "UV HUB" (referred to as "hubless").
1689  */
1690 void __init uv_system_init(void)
1691 {
1692         if (likely(!is_uv_system() && !is_uv_hubless(1)))
1693                 return;
1694
1695         if (is_uv_system())
1696                 uv_system_init_hub();
1697         else
1698                 uv_system_init_hubless();
1699 }
1700
1701 apic_driver(apic_x2apic_uv_x);