1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <asm/processor.h>
13 #include <asm/cacheinfo.h>
15 #include <asm/spec-ctrl.h>
17 #include <asm/pci-direct.h>
18 #include <asm/delay.h>
19 #include <asm/debugreg.h>
22 # include <asm/mmconfig.h>
23 # include <asm/set_memory.h>
28 static const int amd_erratum_383[];
29 static const int amd_erratum_400[];
30 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
33 * nodes_per_socket: Stores the number of nodes per socket.
34 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
35 * Node Identifiers[10:8]
37 static u32 nodes_per_socket = 1;
39 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
44 WARN_ONCE((boot_cpu_data.x86 != 0xf),
45 "%s should only be used on K8!\n", __func__);
50 err = rdmsr_safe_regs(gprs);
52 *p = gprs[0] | ((u64)gprs[2] << 32);
57 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
61 WARN_ONCE((boot_cpu_data.x86 != 0xf),
62 "%s should only be used on K8!\n", __func__);
69 return wrmsr_safe_regs(gprs);
73 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
74 * misexecution of code under Linux. Owners of such processors should
75 * contact AMD for precise details and a CPU swap.
77 * See http://www.multimania.com/poulot/k6bug.html
78 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
79 * (Publication # 21266 Issue Date: August 1998)
81 * The following test is erm.. interesting. AMD neglected to up
82 * the chip setting when fixing the bug but they also tweaked some
83 * performance at the same time..
87 extern __visible void vide(void);
90 ".type vide, @function\n"
95 static void init_amd_k5(struct cpuinfo_x86 *c)
99 * General Systems BIOSen alias the cpu frequency registers
100 * of the Elan at 0x000df000. Unfortunately, one of the Linux
101 * drivers subsequently pokes it, and changes the CPU speed.
102 * Workaround : Remove the unneeded alias.
104 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
105 #define CBAR_ENB (0x80000000)
106 #define CBAR_KEY (0X000000CB)
107 if (c->x86_model == 9 || c->x86_model == 10) {
108 if (inl(CBAR) & CBAR_ENB)
109 outl(0 | CBAR_KEY, CBAR);
114 static void init_amd_k6(struct cpuinfo_x86 *c)
118 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
120 if (c->x86_model < 6) {
121 /* Based on AMD doc 20734R - June 2000 */
122 if (c->x86_model == 0) {
123 clear_cpu_cap(c, X86_FEATURE_APIC);
124 set_cpu_cap(c, X86_FEATURE_PGE);
129 if (c->x86_model == 6 && c->x86_stepping == 1) {
130 const int K6_BUG_LOOP = 1000000;
132 void (*f_vide)(void);
135 pr_info("AMD K6 stepping B detected - ");
138 * It looks like AMD fixed the 2.6.2 bug and improved indirect
139 * calls at the same time.
144 OPTIMIZER_HIDE_VAR(f_vide);
151 if (d > 20*K6_BUG_LOOP)
152 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
154 pr_cont("probably OK (after B9730xxxx).\n");
157 /* K6 with old style WHCR */
158 if (c->x86_model < 8 ||
159 (c->x86_model == 8 && c->x86_stepping < 8)) {
160 /* We can only write allocate on the low 508Mb */
164 rdmsr(MSR_K6_WHCR, l, h);
165 if ((l&0x0000FFFF) == 0) {
167 l = (1<<0)|((mbytes/4)<<1);
168 local_irq_save(flags);
170 wrmsr(MSR_K6_WHCR, l, h);
171 local_irq_restore(flags);
172 pr_info("Enabling old style K6 write allocation for %d Mb\n",
178 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
179 c->x86_model == 9 || c->x86_model == 13) {
180 /* The more serious chips .. */
185 rdmsr(MSR_K6_WHCR, l, h);
186 if ((l&0xFFFF0000) == 0) {
188 l = ((mbytes>>2)<<22)|(1<<16);
189 local_irq_save(flags);
191 wrmsr(MSR_K6_WHCR, l, h);
192 local_irq_restore(flags);
193 pr_info("Enabling new style K6 write allocation for %d Mb\n",
200 if (c->x86_model == 10) {
201 /* AMD Geode LX is model 10 */
202 /* placeholder for any needed mods */
208 static void init_amd_k7(struct cpuinfo_x86 *c)
214 * Bit 15 of Athlon specific MSR 15, needs to be 0
215 * to enable SSE on Palomino/Morgan/Barton CPU's.
216 * If the BIOS didn't enable it already, enable it here.
218 if (c->x86_model >= 6 && c->x86_model <= 10) {
219 if (!cpu_has(c, X86_FEATURE_XMM)) {
220 pr_info("Enabling disabled K7/SSE Support.\n");
221 msr_clear_bit(MSR_K7_HWCR, 15);
222 set_cpu_cap(c, X86_FEATURE_XMM);
227 * It's been determined by AMD that Athlons since model 8 stepping 1
228 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
229 * As per AMD technical note 27212 0.2
231 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
232 rdmsr(MSR_K7_CLK_CTL, l, h);
233 if ((l & 0xfff00000) != 0x20000000) {
234 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
235 l, ((l & 0x000fffff)|0x20000000));
236 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
240 /* calling is from identify_secondary_cpu() ? */
245 * Certain Athlons might work (for various values of 'work') in SMP
246 * but they are not certified as MP capable.
248 /* Athlon 660/661 is valid. */
249 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
250 (c->x86_stepping == 1)))
253 /* Duron 670 is valid */
254 if ((c->x86_model == 7) && (c->x86_stepping == 0))
258 * Athlon 662, Duron 671, and Athlon >model 7 have capability
259 * bit. It's worth noting that the A5 stepping (662) of some
260 * Athlon XP's have the MP bit set.
261 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
264 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
265 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
267 if (cpu_has(c, X86_FEATURE_MP))
270 /* If we get here, not a certified SMP capable AMD system. */
273 * Don't taint if we are running SMP kernel on a single non-MP
276 WARN_ONCE(1, "WARNING: This combination of AMD"
277 " processors is not suitable for SMP.\n");
278 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
284 * To workaround broken NUMA config. Read the comment in
285 * srat_detect_node().
287 static int nearby_node(int apicid)
291 for (i = apicid - 1; i >= 0; i--) {
292 node = __apicid_to_node[i];
293 if (node != NUMA_NO_NODE && node_online(node))
296 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
297 node = __apicid_to_node[i];
298 if (node != NUMA_NO_NODE && node_online(node))
301 return first_node(node_online_map); /* Shouldn't happen */
306 * Fix up cpu_core_id for pre-F17h systems to be in the
307 * [0 .. cores_per_node - 1] range. Not really needed but
308 * kept so as not to break existing setups.
310 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
317 cus_per_node = c->x86_max_cores / nodes_per_socket;
318 c->cpu_core_id %= cus_per_node;
322 static void amd_get_topology_early(struct cpuinfo_x86 *c)
324 if (cpu_has(c, X86_FEATURE_TOPOEXT))
325 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
329 * Fixup core topology information for
330 * (1) AMD multi-node processors
331 * Assumption: Number of cores in each internal node is the same.
332 * (2) AMD processors supporting compute units
334 static void amd_get_topology(struct cpuinfo_x86 *c)
337 int cpu = smp_processor_id();
339 /* get information required for multi-node processors */
340 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
342 u32 eax, ebx, ecx, edx;
344 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
346 node_id = ecx & 0xff;
349 c->cu_id = ebx & 0xff;
351 if (c->x86 >= 0x17) {
352 c->cpu_core_id = ebx & 0xff;
354 if (smp_num_siblings > 1)
355 c->x86_max_cores /= smp_num_siblings;
359 * In case leaf B is available, use it to derive
360 * topology information.
362 err = detect_extended_topology(c);
364 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
366 cacheinfo_amd_init_llc_id(c, cpu, node_id);
368 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
371 rdmsrl(MSR_FAM10H_NODE_ID, value);
374 per_cpu(cpu_llc_id, cpu) = node_id;
378 if (nodes_per_socket > 1) {
379 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
380 legacy_fixup_core_id(c);
385 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
386 * Assumes number of cores is a power of two.
388 static void amd_detect_cmp(struct cpuinfo_x86 *c)
391 int cpu = smp_processor_id();
393 bits = c->x86_coreid_bits;
394 /* Low order bits define the core id (index of core in socket) */
395 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
396 /* Convert the initial APIC ID into the socket ID */
397 c->phys_proc_id = c->initial_apicid >> bits;
398 /* use socket ID also for last level cache */
399 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
402 u16 amd_get_nb_id(int cpu)
404 return per_cpu(cpu_llc_id, cpu);
406 EXPORT_SYMBOL_GPL(amd_get_nb_id);
408 u32 amd_get_nodes_per_socket(void)
410 return nodes_per_socket;
412 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
414 static void srat_detect_node(struct cpuinfo_x86 *c)
417 int cpu = smp_processor_id();
419 unsigned apicid = c->apicid;
421 node = numa_cpu_node(cpu);
422 if (node == NUMA_NO_NODE)
423 node = per_cpu(cpu_llc_id, cpu);
426 * On multi-fabric platform (e.g. Numascale NumaChip) a
427 * platform-specific handler needs to be called to fixup some
430 if (x86_cpuinit.fixup_cpu_id)
431 x86_cpuinit.fixup_cpu_id(c, node);
433 if (!node_online(node)) {
435 * Two possibilities here:
437 * - The CPU is missing memory and no node was created. In
438 * that case try picking one from a nearby CPU.
440 * - The APIC IDs differ from the HyperTransport node IDs
441 * which the K8 northbridge parsing fills in. Assume
442 * they are all increased by a constant offset, but in
443 * the same order as the HT nodeids. If that doesn't
444 * result in a usable node fall back to the path for the
447 * This workaround operates directly on the mapping between
448 * APIC ID and NUMA node, assuming certain relationship
449 * between APIC ID, HT node ID and NUMA topology. As going
450 * through CPU mapping may alter the outcome, directly
451 * access __apicid_to_node[].
453 int ht_nodeid = c->initial_apicid;
455 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
456 node = __apicid_to_node[ht_nodeid];
457 /* Pick a nearby node */
458 if (!node_online(node))
459 node = nearby_node(apicid);
461 numa_set_node(cpu, node);
465 static void early_init_amd_mc(struct cpuinfo_x86 *c)
470 /* Multi core CPU? */
471 if (c->extended_cpuid_level < 0x80000008)
474 ecx = cpuid_ecx(0x80000008);
476 c->x86_max_cores = (ecx & 0xff) + 1;
478 /* CPU telling us the core id bits shift? */
479 bits = (ecx >> 12) & 0xF;
481 /* Otherwise recompute */
483 while ((1 << bits) < c->x86_max_cores)
487 c->x86_coreid_bits = bits;
491 static void bsp_init_amd(struct cpuinfo_x86 *c)
496 unsigned long long tseg;
499 * Split up direct mapping around the TSEG SMM area.
500 * Don't do it for gbpages because there seems very little
501 * benefit in doing so.
503 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
504 unsigned long pfn = tseg >> PAGE_SHIFT;
506 pr_debug("tseg: %010llx\n", tseg);
507 if (pfn_range_is_mapped(pfn, pfn + 1))
508 set_memory_4k((unsigned long)__va(tseg), 1);
513 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
516 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
519 rdmsrl(MSR_K7_HWCR, val);
520 if (!(val & BIT(24)))
521 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
525 if (c->x86 == 0x15) {
526 unsigned long upperbit;
529 cpuid = cpuid_edx(0x80000005);
530 assoc = cpuid >> 16 & 0xff;
531 upperbit = ((cpuid >> 24) << 10) / assoc;
533 va_align.mask = (upperbit - 1) & PAGE_MASK;
534 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
536 /* A random value per boot for bit slice [12:upper_bit) */
537 va_align.bits = get_random_int() & va_align.mask;
540 if (cpu_has(c, X86_FEATURE_MWAITX))
543 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
546 ecx = cpuid_ecx(0x8000001e);
547 nodes_per_socket = ((ecx >> 8) & 7) + 1;
548 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
551 rdmsrl(MSR_FAM10H_NODE_ID, value);
552 nodes_per_socket = ((value >> 3) & 7) + 1;
555 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
556 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
557 c->x86 >= 0x15 && c->x86 <= 0x17) {
561 case 0x15: bit = 54; break;
562 case 0x16: bit = 33; break;
563 case 0x17: bit = 10; break;
567 * Try to cache the base value so further operations can
568 * avoid RMW. If that faults, do not enable SSBD.
570 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
571 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
572 setup_force_cpu_cap(X86_FEATURE_SSBD);
573 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
578 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
583 * BIOS support is required for SME and SEV.
584 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
585 * the SME physical address space reduction value.
586 * If BIOS has not enabled SME then don't advertise the
587 * SME feature (set in scattered.c).
588 * For SEV: If BIOS has not enabled SEV then don't advertise the
589 * SEV feature (set in scattered.c).
591 * In all cases, since support for SME and SEV requires long mode,
592 * don't advertise the feature under CONFIG_X86_32.
594 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
595 /* Check if memory encryption is enabled */
596 rdmsrl(MSR_K8_SYSCFG, msr);
597 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
601 * Always adjust physical address bits. Even though this
602 * will be a value above 32-bits this is still done for
603 * CONFIG_X86_32 so that accurate values are reported.
605 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
607 if (IS_ENABLED(CONFIG_X86_32))
610 rdmsrl(MSR_K7_HWCR, msr);
611 if (!(msr & MSR_K7_HWCR_SMMLOCK))
617 clear_cpu_cap(c, X86_FEATURE_SME);
619 clear_cpu_cap(c, X86_FEATURE_SEV);
623 static void early_init_amd(struct cpuinfo_x86 *c)
628 early_init_amd_mc(c);
632 set_cpu_cap(c, X86_FEATURE_K7);
636 set_cpu_cap(c, X86_FEATURE_K8);
638 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
641 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
642 * with P/T states and does not stop in deep C-states
644 if (c->x86_power & (1 << 8)) {
645 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
646 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
649 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
650 if (c->x86_power & BIT(12))
651 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
654 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
656 /* Set MTRR capability flag if appropriate */
658 if (c->x86_model == 13 || c->x86_model == 9 ||
659 (c->x86_model == 8 && c->x86_stepping >= 8))
660 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
662 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
664 * ApicID can always be treated as an 8-bit value for AMD APIC versions
665 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
666 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
669 if (boot_cpu_has(X86_FEATURE_APIC)) {
671 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
672 else if (c->x86 >= 0xf) {
673 /* check CPU config space for extended APIC ID */
676 val = read_pci_config(0, 24, 0, 0x68);
677 if ((val >> 17 & 0x3) == 0x3)
678 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
684 * This is only needed to tell the kernel whether to use VMCALL
685 * and VMMCALL. VMMCALL is never executed except under virt, so
686 * we can set it unconditionally.
688 set_cpu_cap(c, X86_FEATURE_VMMCALL);
690 /* F16h erratum 793, CVE-2013-6885 */
691 if (c->x86 == 0x16 && c->x86_model <= 0xf)
692 msr_set_bit(MSR_AMD64_LS_CFG, 15);
695 * Check whether the machine is affected by erratum 400. This is
696 * used to select the proper idle routine and to enable the check
697 * whether the machine is affected in arch_post_acpi_init(), which
698 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
700 if (cpu_has_amd_erratum(c, amd_erratum_400))
701 set_cpu_bug(c, X86_BUG_AMD_E400);
703 early_detect_mem_encrypt(c);
705 /* Re-enable TopologyExtensions if switched off by BIOS */
706 if (c->x86 == 0x15 &&
707 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
719 amd_get_topology_early(c);
722 static void init_amd_k8(struct cpuinfo_x86 *c)
727 /* On C+ stepping K8 rep microcode works well for copy/memset */
728 level = cpuid_eax(1);
729 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
730 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
733 * Some BIOSes incorrectly force this feature, but only K8 revision D
734 * (model = 0x14) and later actually support it.
735 * (AMD Erratum #110, docId: 25759).
737 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
738 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
739 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
740 value &= ~BIT_64(32);
741 wrmsrl_amd_safe(0xc001100d, value);
745 if (!c->x86_model_id[0])
746 strcpy(c->x86_model_id, "Hammer");
750 * Disable TLB flush filter by setting HWCR.FFDIS on K8
751 * bit 6 of msr C001_0015
753 * Errata 63 for SH-B3 steppings
754 * Errata 122 for all steppings (F+ have it disabled by default)
756 msr_set_bit(MSR_K7_HWCR, 6);
758 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
761 static void init_amd_gh(struct cpuinfo_x86 *c)
763 #ifdef CONFIG_MMCONF_FAM10H
764 /* do this for boot cpu */
765 if (c == &boot_cpu_data)
766 check_enable_amd_mmconf_dmi();
768 fam10h_check_enable_mmcfg();
772 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
773 * is always needed when GART is enabled, even in a kernel which has no
774 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
775 * If it doesn't, we do it here as suggested by the BKDG.
777 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
779 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
782 * On family 10h BIOS may not have properly enabled WC+ support, causing
783 * it to be converted to CD memtype. This may result in performance
784 * degradation for certain nested-paging guests. Prevent this conversion
785 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
787 * NOTE: we want to use the _safe accessors so as not to #GP kvm
788 * guests on older kvm hosts.
790 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
792 if (cpu_has_amd_erratum(c, amd_erratum_383))
793 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
796 #define MSR_AMD64_DE_CFG 0xC0011029
798 static void init_amd_ln(struct cpuinfo_x86 *c)
801 * Apply erratum 665 fix unconditionally so machines without a BIOS
804 msr_set_bit(MSR_AMD64_DE_CFG, 31);
807 static bool rdrand_force;
809 static int __init rdrand_cmdline(char *str)
814 if (!strcmp(str, "force"))
821 early_param("rdrand", rdrand_cmdline);
823 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
826 * Saving of the MSR used to hide the RDRAND support during
827 * suspend/resume is done by arch/x86/power/cpu.c, which is
828 * dependent on CONFIG_PM_SLEEP.
830 if (!IS_ENABLED(CONFIG_PM_SLEEP))
834 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
835 * RDRAND support using the CPUID function directly.
837 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
840 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
843 * Verify that the CPUID change has occurred in case the kernel is
844 * running virtualized and the hypervisor doesn't support the MSR.
846 if (cpuid_ecx(1) & BIT(30)) {
847 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
851 clear_cpu_cap(c, X86_FEATURE_RDRAND);
852 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
855 static void init_amd_jg(struct cpuinfo_x86 *c)
858 * Some BIOS implementations do not restore proper RDRAND support
859 * across suspend and resume. Check on whether to hide the RDRAND
860 * instruction support via CPUID.
862 clear_rdrand_cpuid_bit(c);
865 static void init_amd_bd(struct cpuinfo_x86 *c)
870 * The way access filter has a performance penalty on some workloads.
871 * Disable it on the affected CPUs.
873 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
874 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
876 wrmsrl_safe(MSR_F15H_IC_CFG, value);
881 * Some BIOS implementations do not restore proper RDRAND support
882 * across suspend and resume. Check on whether to hide the RDRAND
883 * instruction support via CPUID.
885 clear_rdrand_cpuid_bit(c);
888 static void init_amd_zn(struct cpuinfo_x86 *c)
890 set_cpu_cap(c, X86_FEATURE_ZEN);
893 * Fix erratum 1076: CPB feature bit not being set in CPUID.
894 * Always set it, except when running under a hypervisor.
896 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
897 set_cpu_cap(c, X86_FEATURE_CPB);
900 static void init_amd(struct cpuinfo_x86 *c)
905 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
906 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
908 clear_cpu_cap(c, 0*32+31);
911 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
913 /* get apicid instead of initial apic id from cpuid */
914 c->apicid = hard_smp_processor_id();
916 /* K6s reports MCEs but don't actually have all the MSRs */
918 clear_cpu_cap(c, X86_FEATURE_MCE);
921 case 4: init_amd_k5(c); break;
922 case 5: init_amd_k6(c); break;
923 case 6: init_amd_k7(c); break;
924 case 0xf: init_amd_k8(c); break;
925 case 0x10: init_amd_gh(c); break;
926 case 0x12: init_amd_ln(c); break;
927 case 0x15: init_amd_bd(c); break;
928 case 0x16: init_amd_jg(c); break;
929 case 0x17: init_amd_zn(c); break;
933 * Enable workaround for FXSAVE leak on CPUs
934 * without a XSaveErPtr feature
936 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
937 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
939 cpu_detect_cache_sizes(c);
945 init_amd_cacheinfo(c);
947 if (cpu_has(c, X86_FEATURE_XMM2)) {
949 * Use LFENCE for execution serialization. On families which
950 * don't have that MSR, LFENCE is already serializing.
951 * msr_set_bit() uses the safe accessors, too, even if the MSR
954 msr_set_bit(MSR_F10H_DECFG,
955 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
957 /* A serializing LFENCE stops RDTSC speculation */
958 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
962 * Family 0x12 and above processors have APIC timer
963 * running in deep C states.
966 set_cpu_cap(c, X86_FEATURE_ARAT);
968 /* 3DNow or LM implies PREFETCHW */
969 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
970 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
971 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
973 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
974 if (!cpu_has(c, X86_FEATURE_XENPV))
975 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
979 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
981 /* AMD errata T13 (order #21922) */
984 if (c->x86_model == 3 && c->x86_stepping == 0)
986 /* Tbird rev A1/A2 */
987 if (c->x86_model == 4 &&
988 (c->x86_stepping == 0 || c->x86_stepping == 1))
995 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
997 u32 ebx, eax, ecx, edx;
1003 if (c->extended_cpuid_level < 0x80000006)
1006 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1008 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1009 tlb_lli_4k[ENTRIES] = ebx & mask;
1012 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1013 * characteristics from the CPUID function 0x80000005 instead.
1015 if (c->x86 == 0xf) {
1016 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1020 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1021 if (!((eax >> 16) & mask))
1022 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1024 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1026 /* a 4M entry uses two 2M entries */
1027 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1029 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1030 if (!(eax & mask)) {
1032 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1033 tlb_lli_2m[ENTRIES] = 1024;
1035 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1036 tlb_lli_2m[ENTRIES] = eax & 0xff;
1039 tlb_lli_2m[ENTRIES] = eax & mask;
1041 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1044 static const struct cpu_dev amd_cpu_dev = {
1046 .c_ident = { "AuthenticAMD" },
1047 #ifdef CONFIG_X86_32
1049 { .family = 4, .model_names =
1052 [7] = "486 DX/2-WB",
1054 [9] = "486 DX/4-WB",
1060 .legacy_cache_size = amd_size_cache,
1062 .c_early_init = early_init_amd,
1063 .c_detect_tlb = cpu_detect_tlb_amd,
1064 .c_bsp_init = bsp_init_amd,
1066 .c_x86_vendor = X86_VENDOR_AMD,
1069 cpu_dev_register(amd_cpu_dev);
1072 * AMD errata checking
1074 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1075 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1076 * have an OSVW id assigned, which it takes as first argument. Both take a
1077 * variable number of family-specific model-stepping ranges created by
1078 * AMD_MODEL_RANGE().
1082 * const int amd_erratum_319[] =
1083 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1084 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1085 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1088 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1089 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1090 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1091 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1092 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1093 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1094 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1096 static const int amd_erratum_400[] =
1097 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1098 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1100 static const int amd_erratum_383[] =
1101 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1104 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1106 int osvw_id = *erratum++;
1110 if (osvw_id >= 0 && osvw_id < 65536 &&
1111 cpu_has(cpu, X86_FEATURE_OSVW)) {
1114 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1115 if (osvw_id < osvw_len) {
1118 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1120 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1124 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1125 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1126 while ((range = *erratum++))
1127 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1128 (ms >= AMD_MODEL_RANGE_START(range)) &&
1129 (ms <= AMD_MODEL_RANGE_END(range)))
1135 void set_dr_addr_mask(unsigned long mask, int dr)
1137 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1142 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1147 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);