1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/random.h>
10 #include <asm/processor.h>
12 #include <asm/cacheinfo.h>
14 #include <asm/spec-ctrl.h>
16 #include <asm/pci-direct.h>
17 #include <asm/delay.h>
20 # include <asm/mmconfig.h>
21 # include <asm/set_memory.h>
26 static const int amd_erratum_383[];
27 static const int amd_erratum_400[];
28 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
31 * nodes_per_socket: Stores the number of nodes per socket.
32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
33 * Node Identifiers[10:8]
35 static u32 nodes_per_socket = 1;
37 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
42 WARN_ONCE((boot_cpu_data.x86 != 0xf),
43 "%s should only be used on K8!\n", __func__);
48 err = rdmsr_safe_regs(gprs);
50 *p = gprs[0] | ((u64)gprs[2] << 32);
55 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
59 WARN_ONCE((boot_cpu_data.x86 != 0xf),
60 "%s should only be used on K8!\n", __func__);
67 return wrmsr_safe_regs(gprs);
71 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
72 * misexecution of code under Linux. Owners of such processors should
73 * contact AMD for precise details and a CPU swap.
75 * See http://www.multimania.com/poulot/k6bug.html
76 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
77 * (Publication # 21266 Issue Date: August 1998)
79 * The following test is erm.. interesting. AMD neglected to up
80 * the chip setting when fixing the bug but they also tweaked some
81 * performance at the same time..
84 extern __visible void vide(void);
85 __asm__(".globl vide\n"
86 ".type vide, @function\n"
90 static void init_amd_k5(struct cpuinfo_x86 *c)
94 * General Systems BIOSen alias the cpu frequency registers
95 * of the Elan at 0x000df000. Unfortunately, one of the Linux
96 * drivers subsequently pokes it, and changes the CPU speed.
97 * Workaround : Remove the unneeded alias.
99 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
100 #define CBAR_ENB (0x80000000)
101 #define CBAR_KEY (0X000000CB)
102 if (c->x86_model == 9 || c->x86_model == 10) {
103 if (inl(CBAR) & CBAR_ENB)
104 outl(0 | CBAR_KEY, CBAR);
109 static void init_amd_k6(struct cpuinfo_x86 *c)
113 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
115 if (c->x86_model < 6) {
116 /* Based on AMD doc 20734R - June 2000 */
117 if (c->x86_model == 0) {
118 clear_cpu_cap(c, X86_FEATURE_APIC);
119 set_cpu_cap(c, X86_FEATURE_PGE);
124 if (c->x86_model == 6 && c->x86_stepping == 1) {
125 const int K6_BUG_LOOP = 1000000;
127 void (*f_vide)(void);
130 pr_info("AMD K6 stepping B detected - ");
133 * It looks like AMD fixed the 2.6.2 bug and improved indirect
134 * calls at the same time.
139 OPTIMIZER_HIDE_VAR(f_vide);
146 if (d > 20*K6_BUG_LOOP)
147 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
149 pr_cont("probably OK (after B9730xxxx).\n");
152 /* K6 with old style WHCR */
153 if (c->x86_model < 8 ||
154 (c->x86_model == 8 && c->x86_stepping < 8)) {
155 /* We can only write allocate on the low 508Mb */
159 rdmsr(MSR_K6_WHCR, l, h);
160 if ((l&0x0000FFFF) == 0) {
162 l = (1<<0)|((mbytes/4)<<1);
163 local_irq_save(flags);
165 wrmsr(MSR_K6_WHCR, l, h);
166 local_irq_restore(flags);
167 pr_info("Enabling old style K6 write allocation for %d Mb\n",
173 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
174 c->x86_model == 9 || c->x86_model == 13) {
175 /* The more serious chips .. */
180 rdmsr(MSR_K6_WHCR, l, h);
181 if ((l&0xFFFF0000) == 0) {
183 l = ((mbytes>>2)<<22)|(1<<16);
184 local_irq_save(flags);
186 wrmsr(MSR_K6_WHCR, l, h);
187 local_irq_restore(flags);
188 pr_info("Enabling new style K6 write allocation for %d Mb\n",
195 if (c->x86_model == 10) {
196 /* AMD Geode LX is model 10 */
197 /* placeholder for any needed mods */
203 static void init_amd_k7(struct cpuinfo_x86 *c)
209 * Bit 15 of Athlon specific MSR 15, needs to be 0
210 * to enable SSE on Palomino/Morgan/Barton CPU's.
211 * If the BIOS didn't enable it already, enable it here.
213 if (c->x86_model >= 6 && c->x86_model <= 10) {
214 if (!cpu_has(c, X86_FEATURE_XMM)) {
215 pr_info("Enabling disabled K7/SSE Support.\n");
216 msr_clear_bit(MSR_K7_HWCR, 15);
217 set_cpu_cap(c, X86_FEATURE_XMM);
222 * It's been determined by AMD that Athlons since model 8 stepping 1
223 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
224 * As per AMD technical note 27212 0.2
226 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
227 rdmsr(MSR_K7_CLK_CTL, l, h);
228 if ((l & 0xfff00000) != 0x20000000) {
229 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
230 l, ((l & 0x000fffff)|0x20000000));
231 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
235 set_cpu_cap(c, X86_FEATURE_K7);
237 /* calling is from identify_secondary_cpu() ? */
242 * Certain Athlons might work (for various values of 'work') in SMP
243 * but they are not certified as MP capable.
245 /* Athlon 660/661 is valid. */
246 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
247 (c->x86_stepping == 1)))
250 /* Duron 670 is valid */
251 if ((c->x86_model == 7) && (c->x86_stepping == 0))
255 * Athlon 662, Duron 671, and Athlon >model 7 have capability
256 * bit. It's worth noting that the A5 stepping (662) of some
257 * Athlon XP's have the MP bit set.
258 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
261 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
262 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
264 if (cpu_has(c, X86_FEATURE_MP))
267 /* If we get here, not a certified SMP capable AMD system. */
270 * Don't taint if we are running SMP kernel on a single non-MP
273 WARN_ONCE(1, "WARNING: This combination of AMD"
274 " processors is not suitable for SMP.\n");
275 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
281 * To workaround broken NUMA config. Read the comment in
282 * srat_detect_node().
284 static int nearby_node(int apicid)
288 for (i = apicid - 1; i >= 0; i--) {
289 node = __apicid_to_node[i];
290 if (node != NUMA_NO_NODE && node_online(node))
293 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
294 node = __apicid_to_node[i];
295 if (node != NUMA_NO_NODE && node_online(node))
298 return first_node(node_online_map); /* Shouldn't happen */
303 * Fix up cpu_core_id for pre-F17h systems to be in the
304 * [0 .. cores_per_node - 1] range. Not really needed but
305 * kept so as not to break existing setups.
307 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
314 cus_per_node = c->x86_max_cores / nodes_per_socket;
315 c->cpu_core_id %= cus_per_node;
319 * Fixup core topology information for
320 * (1) AMD multi-node processors
321 * Assumption: Number of cores in each internal node is the same.
322 * (2) AMD processors supporting compute units
324 static void amd_get_topology(struct cpuinfo_x86 *c)
327 int cpu = smp_processor_id();
329 /* get information required for multi-node processors */
330 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
332 u32 eax, ebx, ecx, edx;
334 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
336 node_id = ecx & 0xff;
337 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
340 c->cu_id = ebx & 0xff;
342 if (c->x86 >= 0x17) {
343 c->cpu_core_id = ebx & 0xff;
345 if (smp_num_siblings > 1)
346 c->x86_max_cores /= smp_num_siblings;
350 * In case leaf B is available, use it to derive
351 * topology information.
353 err = detect_extended_topology(c);
355 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
357 cacheinfo_amd_init_llc_id(c, cpu, node_id);
359 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
362 rdmsrl(MSR_FAM10H_NODE_ID, value);
365 per_cpu(cpu_llc_id, cpu) = node_id;
369 if (nodes_per_socket > 1) {
370 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
371 legacy_fixup_core_id(c);
376 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
377 * Assumes number of cores is a power of two.
379 static void amd_detect_cmp(struct cpuinfo_x86 *c)
382 int cpu = smp_processor_id();
384 bits = c->x86_coreid_bits;
385 /* Low order bits define the core id (index of core in socket) */
386 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
387 /* Convert the initial APIC ID into the socket ID */
388 c->phys_proc_id = c->initial_apicid >> bits;
389 /* use socket ID also for last level cache */
390 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
393 u16 amd_get_nb_id(int cpu)
395 return per_cpu(cpu_llc_id, cpu);
397 EXPORT_SYMBOL_GPL(amd_get_nb_id);
399 u32 amd_get_nodes_per_socket(void)
401 return nodes_per_socket;
403 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
405 static void srat_detect_node(struct cpuinfo_x86 *c)
408 int cpu = smp_processor_id();
410 unsigned apicid = c->apicid;
412 node = numa_cpu_node(cpu);
413 if (node == NUMA_NO_NODE)
414 node = per_cpu(cpu_llc_id, cpu);
417 * On multi-fabric platform (e.g. Numascale NumaChip) a
418 * platform-specific handler needs to be called to fixup some
421 if (x86_cpuinit.fixup_cpu_id)
422 x86_cpuinit.fixup_cpu_id(c, node);
424 if (!node_online(node)) {
426 * Two possibilities here:
428 * - The CPU is missing memory and no node was created. In
429 * that case try picking one from a nearby CPU.
431 * - The APIC IDs differ from the HyperTransport node IDs
432 * which the K8 northbridge parsing fills in. Assume
433 * they are all increased by a constant offset, but in
434 * the same order as the HT nodeids. If that doesn't
435 * result in a usable node fall back to the path for the
438 * This workaround operates directly on the mapping between
439 * APIC ID and NUMA node, assuming certain relationship
440 * between APIC ID, HT node ID and NUMA topology. As going
441 * through CPU mapping may alter the outcome, directly
442 * access __apicid_to_node[].
444 int ht_nodeid = c->initial_apicid;
446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
447 node = __apicid_to_node[ht_nodeid];
448 /* Pick a nearby node */
449 if (!node_online(node))
450 node = nearby_node(apicid);
452 numa_set_node(cpu, node);
456 static void early_init_amd_mc(struct cpuinfo_x86 *c)
461 /* Multi core CPU? */
462 if (c->extended_cpuid_level < 0x80000008)
465 ecx = cpuid_ecx(0x80000008);
467 c->x86_max_cores = (ecx & 0xff) + 1;
469 /* CPU telling us the core id bits shift? */
470 bits = (ecx >> 12) & 0xF;
472 /* Otherwise recompute */
474 while ((1 << bits) < c->x86_max_cores)
478 c->x86_coreid_bits = bits;
482 static void bsp_init_amd(struct cpuinfo_x86 *c)
487 unsigned long long tseg;
490 * Split up direct mapping around the TSEG SMM area.
491 * Don't do it for gbpages because there seems very little
492 * benefit in doing so.
494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
495 unsigned long pfn = tseg >> PAGE_SHIFT;
497 pr_debug("tseg: %010llx\n", tseg);
498 if (pfn_range_is_mapped(pfn, pfn + 1))
499 set_memory_4k((unsigned long)__va(tseg), 1);
504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
507 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
510 rdmsrl(MSR_K7_HWCR, val);
511 if (!(val & BIT(24)))
512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
516 if (c->x86 == 0x15) {
517 unsigned long upperbit;
520 cpuid = cpuid_edx(0x80000005);
521 assoc = cpuid >> 16 & 0xff;
522 upperbit = ((cpuid >> 24) << 10) / assoc;
524 va_align.mask = (upperbit - 1) & PAGE_MASK;
525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
527 /* A random value per boot for bit slice [12:upper_bit) */
528 va_align.bits = get_random_int() & va_align.mask;
531 if (cpu_has(c, X86_FEATURE_MWAITX))
534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
537 ecx = cpuid_ecx(0x8000001e);
538 nodes_per_socket = ((ecx >> 8) & 7) + 1;
539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
542 rdmsrl(MSR_FAM10H_NODE_ID, value);
543 nodes_per_socket = ((value >> 3) & 7) + 1;
546 if (c->x86 >= 0x15 && c->x86 <= 0x17) {
550 case 0x15: bit = 54; break;
551 case 0x16: bit = 33; break;
552 case 0x17: bit = 10; break;
556 * Try to cache the base value so further operations can
557 * avoid RMW. If that faults, do not enable SSBD.
559 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
560 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
561 setup_force_cpu_cap(X86_FEATURE_SSBD);
562 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
567 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
572 * BIOS support is required for SME and SEV.
573 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
574 * the SME physical address space reduction value.
575 * If BIOS has not enabled SME then don't advertise the
576 * SME feature (set in scattered.c).
577 * For SEV: If BIOS has not enabled SEV then don't advertise the
578 * SEV feature (set in scattered.c).
580 * In all cases, since support for SME and SEV requires long mode,
581 * don't advertise the feature under CONFIG_X86_32.
583 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
584 /* Check if memory encryption is enabled */
585 rdmsrl(MSR_K8_SYSCFG, msr);
586 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
590 * Always adjust physical address bits. Even though this
591 * will be a value above 32-bits this is still done for
592 * CONFIG_X86_32 so that accurate values are reported.
594 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
596 if (IS_ENABLED(CONFIG_X86_32))
599 rdmsrl(MSR_K7_HWCR, msr);
600 if (!(msr & MSR_K7_HWCR_SMMLOCK))
606 clear_cpu_cap(c, X86_FEATURE_SME);
608 clear_cpu_cap(c, X86_FEATURE_SEV);
612 static void early_init_amd(struct cpuinfo_x86 *c)
616 early_init_amd_mc(c);
618 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
621 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
622 * with P/T states and does not stop in deep C-states
624 if (c->x86_power & (1 << 8)) {
625 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
626 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
629 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
630 if (c->x86_power & BIT(12))
631 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
634 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
636 /* Set MTRR capability flag if appropriate */
638 if (c->x86_model == 13 || c->x86_model == 9 ||
639 (c->x86_model == 8 && c->x86_stepping >= 8))
640 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
642 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
644 * ApicID can always be treated as an 8-bit value for AMD APIC versions
645 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
646 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
649 if (boot_cpu_has(X86_FEATURE_APIC)) {
651 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
652 else if (c->x86 >= 0xf) {
653 /* check CPU config space for extended APIC ID */
656 val = read_pci_config(0, 24, 0, 0x68);
657 if ((val >> 17 & 0x3) == 0x3)
658 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
664 * This is only needed to tell the kernel whether to use VMCALL
665 * and VMMCALL. VMMCALL is never executed except under virt, so
666 * we can set it unconditionally.
668 set_cpu_cap(c, X86_FEATURE_VMMCALL);
670 /* F16h erratum 793, CVE-2013-6885 */
671 if (c->x86 == 0x16 && c->x86_model <= 0xf)
672 msr_set_bit(MSR_AMD64_LS_CFG, 15);
675 * Check whether the machine is affected by erratum 400. This is
676 * used to select the proper idle routine and to enable the check
677 * whether the machine is affected in arch_post_acpi_init(), which
678 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
680 if (cpu_has_amd_erratum(c, amd_erratum_400))
681 set_cpu_bug(c, X86_BUG_AMD_E400);
683 early_detect_mem_encrypt(c);
686 static void init_amd_k8(struct cpuinfo_x86 *c)
691 /* On C+ stepping K8 rep microcode works well for copy/memset */
692 level = cpuid_eax(1);
693 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
694 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
697 * Some BIOSes incorrectly force this feature, but only K8 revision D
698 * (model = 0x14) and later actually support it.
699 * (AMD Erratum #110, docId: 25759).
701 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
702 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
703 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
704 value &= ~BIT_64(32);
705 wrmsrl_amd_safe(0xc001100d, value);
709 if (!c->x86_model_id[0])
710 strcpy(c->x86_model_id, "Hammer");
714 * Disable TLB flush filter by setting HWCR.FFDIS on K8
715 * bit 6 of msr C001_0015
717 * Errata 63 for SH-B3 steppings
718 * Errata 122 for all steppings (F+ have it disabled by default)
720 msr_set_bit(MSR_K7_HWCR, 6);
722 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
725 static void init_amd_gh(struct cpuinfo_x86 *c)
727 #ifdef CONFIG_MMCONF_FAM10H
728 /* do this for boot cpu */
729 if (c == &boot_cpu_data)
730 check_enable_amd_mmconf_dmi();
732 fam10h_check_enable_mmcfg();
736 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
737 * is always needed when GART is enabled, even in a kernel which has no
738 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
739 * If it doesn't, we do it here as suggested by the BKDG.
741 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
743 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
746 * On family 10h BIOS may not have properly enabled WC+ support, causing
747 * it to be converted to CD memtype. This may result in performance
748 * degradation for certain nested-paging guests. Prevent this conversion
749 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
751 * NOTE: we want to use the _safe accessors so as not to #GP kvm
752 * guests on older kvm hosts.
754 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
756 if (cpu_has_amd_erratum(c, amd_erratum_383))
757 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
760 #define MSR_AMD64_DE_CFG 0xC0011029
762 static void init_amd_ln(struct cpuinfo_x86 *c)
765 * Apply erratum 665 fix unconditionally so machines without a BIOS
768 msr_set_bit(MSR_AMD64_DE_CFG, 31);
771 static void init_amd_bd(struct cpuinfo_x86 *c)
775 /* re-enable TopologyExtensions if switched off by BIOS */
776 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
777 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
779 if (msr_set_bit(0xc0011005, 54) > 0) {
780 rdmsrl(0xc0011005, value);
781 if (value & BIT_64(54)) {
782 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
783 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
789 * The way access filter has a performance penalty on some workloads.
790 * Disable it on the affected CPUs.
792 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
793 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
795 wrmsrl_safe(MSR_F15H_IC_CFG, value);
800 static void init_amd_zn(struct cpuinfo_x86 *c)
802 set_cpu_cap(c, X86_FEATURE_ZEN);
804 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
805 * all up to and including B1.
807 if (c->x86_model <= 1 && c->x86_stepping <= 1)
808 set_cpu_cap(c, X86_FEATURE_CPB);
811 static void init_amd(struct cpuinfo_x86 *c)
816 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
817 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
819 clear_cpu_cap(c, 0*32+31);
822 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
824 /* get apicid instead of initial apic id from cpuid */
825 c->apicid = hard_smp_processor_id();
827 /* K6s reports MCEs but don't actually have all the MSRs */
829 clear_cpu_cap(c, X86_FEATURE_MCE);
832 case 4: init_amd_k5(c); break;
833 case 5: init_amd_k6(c); break;
834 case 6: init_amd_k7(c); break;
835 case 0xf: init_amd_k8(c); break;
836 case 0x10: init_amd_gh(c); break;
837 case 0x12: init_amd_ln(c); break;
838 case 0x15: init_amd_bd(c); break;
839 case 0x17: init_amd_zn(c); break;
843 * Enable workaround for FXSAVE leak on CPUs
844 * without a XSaveErPtr feature
846 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
847 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
849 cpu_detect_cache_sizes(c);
851 /* Multi core CPU? */
852 if (c->extended_cpuid_level >= 0x80000008) {
862 init_amd_cacheinfo(c);
865 set_cpu_cap(c, X86_FEATURE_K8);
867 if (cpu_has(c, X86_FEATURE_XMM2)) {
868 unsigned long long val;
872 * A serializing LFENCE has less overhead than MFENCE, so
873 * use it for execution serialization. On families which
874 * don't have that MSR, LFENCE is already serializing.
875 * msr_set_bit() uses the safe accessors, too, even if the MSR
878 msr_set_bit(MSR_F10H_DECFG,
879 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
882 * Verify that the MSR write was successful (could be running
883 * under a hypervisor) and only then assume that LFENCE is
886 ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
887 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
888 /* A serializing LFENCE stops RDTSC speculation */
889 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
891 /* MFENCE stops RDTSC speculation */
892 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
897 * Family 0x12 and above processors have APIC timer
898 * running in deep C states.
901 set_cpu_cap(c, X86_FEATURE_ARAT);
903 /* 3DNow or LM implies PREFETCHW */
904 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
905 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
906 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
908 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
909 if (!cpu_has(c, X86_FEATURE_XENPV))
910 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
914 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
916 /* AMD errata T13 (order #21922) */
919 if (c->x86_model == 3 && c->x86_stepping == 0)
921 /* Tbird rev A1/A2 */
922 if (c->x86_model == 4 &&
923 (c->x86_stepping == 0 || c->x86_stepping == 1))
930 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
932 u32 ebx, eax, ecx, edx;
938 if (c->extended_cpuid_level < 0x80000006)
941 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
943 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
944 tlb_lli_4k[ENTRIES] = ebx & mask;
947 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
948 * characteristics from the CPUID function 0x80000005 instead.
951 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
955 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
956 if (!((eax >> 16) & mask))
957 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
959 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
961 /* a 4M entry uses two 2M entries */
962 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
964 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
967 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
968 tlb_lli_2m[ENTRIES] = 1024;
970 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
971 tlb_lli_2m[ENTRIES] = eax & 0xff;
974 tlb_lli_2m[ENTRIES] = eax & mask;
976 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
979 static const struct cpu_dev amd_cpu_dev = {
981 .c_ident = { "AuthenticAMD" },
984 { .family = 4, .model_names =
995 .legacy_cache_size = amd_size_cache,
997 .c_early_init = early_init_amd,
998 .c_detect_tlb = cpu_detect_tlb_amd,
999 .c_bsp_init = bsp_init_amd,
1001 .c_x86_vendor = X86_VENDOR_AMD,
1004 cpu_dev_register(amd_cpu_dev);
1007 * AMD errata checking
1009 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1010 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1011 * have an OSVW id assigned, which it takes as first argument. Both take a
1012 * variable number of family-specific model-stepping ranges created by
1013 * AMD_MODEL_RANGE().
1017 * const int amd_erratum_319[] =
1018 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1019 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1020 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1023 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1024 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1025 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1026 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1027 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1028 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1029 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1031 static const int amd_erratum_400[] =
1032 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1033 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1035 static const int amd_erratum_383[] =
1036 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1039 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1041 int osvw_id = *erratum++;
1045 if (osvw_id >= 0 && osvw_id < 65536 &&
1046 cpu_has(cpu, X86_FEATURE_OSVW)) {
1049 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1050 if (osvw_id < osvw_len) {
1053 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1055 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1059 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1060 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1061 while ((range = *erratum++))
1062 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1063 (ms >= AMD_MODEL_RANGE_START(range)) &&
1064 (ms <= AMD_MODEL_RANGE_END(range)))
1070 void set_dr_addr_mask(unsigned long mask, int dr)
1072 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1077 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1082 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);