1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/random.h>
10 #include <asm/processor.h>
14 #include <asm/pci-direct.h>
15 #include <asm/delay.h>
18 # include <asm/mmconfig.h>
19 # include <asm/set_memory.h>
24 static const int amd_erratum_383[];
25 static const int amd_erratum_400[];
26 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
29 * nodes_per_socket: Stores the number of nodes per socket.
30 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
31 * Node Identifiers[10:8]
33 static u32 nodes_per_socket = 1;
35 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
40 WARN_ONCE((boot_cpu_data.x86 != 0xf),
41 "%s should only be used on K8!\n", __func__);
46 err = rdmsr_safe_regs(gprs);
48 *p = gprs[0] | ((u64)gprs[2] << 32);
53 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
57 WARN_ONCE((boot_cpu_data.x86 != 0xf),
58 "%s should only be used on K8!\n", __func__);
65 return wrmsr_safe_regs(gprs);
69 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
70 * misexecution of code under Linux. Owners of such processors should
71 * contact AMD for precise details and a CPU swap.
73 * See http://www.multimania.com/poulot/k6bug.html
74 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
75 * (Publication # 21266 Issue Date: August 1998)
77 * The following test is erm.. interesting. AMD neglected to up
78 * the chip setting when fixing the bug but they also tweaked some
79 * performance at the same time..
82 extern __visible void vide(void);
83 __asm__(".globl vide\n"
84 ".type vide, @function\n"
88 static void init_amd_k5(struct cpuinfo_x86 *c)
92 * General Systems BIOSen alias the cpu frequency registers
93 * of the Elan at 0x000df000. Unfortunately, one of the Linux
94 * drivers subsequently pokes it, and changes the CPU speed.
95 * Workaround : Remove the unneeded alias.
97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
98 #define CBAR_ENB (0x80000000)
99 #define CBAR_KEY (0X000000CB)
100 if (c->x86_model == 9 || c->x86_model == 10) {
101 if (inl(CBAR) & CBAR_ENB)
102 outl(0 | CBAR_KEY, CBAR);
107 static void init_amd_k6(struct cpuinfo_x86 *c)
111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
113 if (c->x86_model < 6) {
114 /* Based on AMD doc 20734R - June 2000 */
115 if (c->x86_model == 0) {
116 clear_cpu_cap(c, X86_FEATURE_APIC);
117 set_cpu_cap(c, X86_FEATURE_PGE);
122 if (c->x86_model == 6 && c->x86_mask == 1) {
123 const int K6_BUG_LOOP = 1000000;
125 void (*f_vide)(void);
128 pr_info("AMD K6 stepping B detected - ");
131 * It looks like AMD fixed the 2.6.2 bug and improved indirect
132 * calls at the same time.
137 OPTIMIZER_HIDE_VAR(f_vide);
144 if (d > 20*K6_BUG_LOOP)
145 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
147 pr_cont("probably OK (after B9730xxxx).\n");
150 /* K6 with old style WHCR */
151 if (c->x86_model < 8 ||
152 (c->x86_model == 8 && c->x86_mask < 8)) {
153 /* We can only write allocate on the low 508Mb */
157 rdmsr(MSR_K6_WHCR, l, h);
158 if ((l&0x0000FFFF) == 0) {
160 l = (1<<0)|((mbytes/4)<<1);
161 local_irq_save(flags);
163 wrmsr(MSR_K6_WHCR, l, h);
164 local_irq_restore(flags);
165 pr_info("Enabling old style K6 write allocation for %d Mb\n",
171 if ((c->x86_model == 8 && c->x86_mask > 7) ||
172 c->x86_model == 9 || c->x86_model == 13) {
173 /* The more serious chips .. */
178 rdmsr(MSR_K6_WHCR, l, h);
179 if ((l&0xFFFF0000) == 0) {
181 l = ((mbytes>>2)<<22)|(1<<16);
182 local_irq_save(flags);
184 wrmsr(MSR_K6_WHCR, l, h);
185 local_irq_restore(flags);
186 pr_info("Enabling new style K6 write allocation for %d Mb\n",
193 if (c->x86_model == 10) {
194 /* AMD Geode LX is model 10 */
195 /* placeholder for any needed mods */
201 static void init_amd_k7(struct cpuinfo_x86 *c)
207 * Bit 15 of Athlon specific MSR 15, needs to be 0
208 * to enable SSE on Palomino/Morgan/Barton CPU's.
209 * If the BIOS didn't enable it already, enable it here.
211 if (c->x86_model >= 6 && c->x86_model <= 10) {
212 if (!cpu_has(c, X86_FEATURE_XMM)) {
213 pr_info("Enabling disabled K7/SSE Support.\n");
214 msr_clear_bit(MSR_K7_HWCR, 15);
215 set_cpu_cap(c, X86_FEATURE_XMM);
220 * It's been determined by AMD that Athlons since model 8 stepping 1
221 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
222 * As per AMD technical note 27212 0.2
224 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
225 rdmsr(MSR_K7_CLK_CTL, l, h);
226 if ((l & 0xfff00000) != 0x20000000) {
227 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
228 l, ((l & 0x000fffff)|0x20000000));
229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
233 set_cpu_cap(c, X86_FEATURE_K7);
235 /* calling is from identify_secondary_cpu() ? */
240 * Certain Athlons might work (for various values of 'work') in SMP
241 * but they are not certified as MP capable.
243 /* Athlon 660/661 is valid. */
244 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
248 /* Duron 670 is valid */
249 if ((c->x86_model == 7) && (c->x86_mask == 0))
253 * Athlon 662, Duron 671, and Athlon >model 7 have capability
254 * bit. It's worth noting that the A5 stepping (662) of some
255 * Athlon XP's have the MP bit set.
256 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
259 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
260 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
262 if (cpu_has(c, X86_FEATURE_MP))
265 /* If we get here, not a certified SMP capable AMD system. */
268 * Don't taint if we are running SMP kernel on a single non-MP
271 WARN_ONCE(1, "WARNING: This combination of AMD"
272 " processors is not suitable for SMP.\n");
273 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
279 * To workaround broken NUMA config. Read the comment in
280 * srat_detect_node().
282 static int nearby_node(int apicid)
286 for (i = apicid - 1; i >= 0; i--) {
287 node = __apicid_to_node[i];
288 if (node != NUMA_NO_NODE && node_online(node))
291 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
292 node = __apicid_to_node[i];
293 if (node != NUMA_NO_NODE && node_online(node))
296 return first_node(node_online_map); /* Shouldn't happen */
301 * Fixup core topology information for
302 * (1) AMD multi-node processors
303 * Assumption: Number of cores in each internal node is the same.
304 * (2) AMD processors supporting compute units
307 static void amd_get_topology(struct cpuinfo_x86 *c)
310 int cpu = smp_processor_id();
312 /* get information required for multi-node processors */
313 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
314 u32 eax, ebx, ecx, edx;
316 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
318 node_id = ecx & 0xff;
319 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
322 c->cu_id = ebx & 0xff;
324 if (c->x86 >= 0x17) {
325 c->cpu_core_id = ebx & 0xff;
327 if (smp_num_siblings > 1)
328 c->x86_max_cores /= smp_num_siblings;
332 * We may have multiple LLCs if L3 caches exist, so check if we
333 * have an L3 cache by looking at the L3 cache CPUID leaf.
335 if (cpuid_edx(0x80000006)) {
336 if (c->x86 == 0x17) {
338 * LLC is at the core complex level.
339 * Core complex id is ApicId[3].
341 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
343 /* LLC is at the node level. */
344 per_cpu(cpu_llc_id, cpu) = node_id;
347 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
350 rdmsrl(MSR_FAM10H_NODE_ID, value);
353 per_cpu(cpu_llc_id, cpu) = node_id;
357 /* fixup multi-node processor information */
358 if (nodes_per_socket > 1) {
361 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
362 cus_per_node = c->x86_max_cores / nodes_per_socket;
364 /* core id has to be in the [0 .. cores_per_node - 1] range */
365 c->cpu_core_id %= cus_per_node;
371 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
372 * Assumes number of cores is a power of two.
374 static void amd_detect_cmp(struct cpuinfo_x86 *c)
378 int cpu = smp_processor_id();
380 bits = c->x86_coreid_bits;
381 /* Low order bits define the core id (index of core in socket) */
382 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
383 /* Convert the initial APIC ID into the socket ID */
384 c->phys_proc_id = c->initial_apicid >> bits;
385 /* use socket ID also for last level cache */
386 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
391 u16 amd_get_nb_id(int cpu)
395 id = per_cpu(cpu_llc_id, cpu);
399 EXPORT_SYMBOL_GPL(amd_get_nb_id);
401 u32 amd_get_nodes_per_socket(void)
403 return nodes_per_socket;
405 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
407 static void srat_detect_node(struct cpuinfo_x86 *c)
410 int cpu = smp_processor_id();
412 unsigned apicid = c->apicid;
414 node = numa_cpu_node(cpu);
415 if (node == NUMA_NO_NODE)
416 node = per_cpu(cpu_llc_id, cpu);
419 * On multi-fabric platform (e.g. Numascale NumaChip) a
420 * platform-specific handler needs to be called to fixup some
423 if (x86_cpuinit.fixup_cpu_id)
424 x86_cpuinit.fixup_cpu_id(c, node);
426 if (!node_online(node)) {
428 * Two possibilities here:
430 * - The CPU is missing memory and no node was created. In
431 * that case try picking one from a nearby CPU.
433 * - The APIC IDs differ from the HyperTransport node IDs
434 * which the K8 northbridge parsing fills in. Assume
435 * they are all increased by a constant offset, but in
436 * the same order as the HT nodeids. If that doesn't
437 * result in a usable node fall back to the path for the
440 * This workaround operates directly on the mapping between
441 * APIC ID and NUMA node, assuming certain relationship
442 * between APIC ID, HT node ID and NUMA topology. As going
443 * through CPU mapping may alter the outcome, directly
444 * access __apicid_to_node[].
446 int ht_nodeid = c->initial_apicid;
448 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
449 node = __apicid_to_node[ht_nodeid];
450 /* Pick a nearby node */
451 if (!node_online(node))
452 node = nearby_node(apicid);
454 numa_set_node(cpu, node);
458 static void early_init_amd_mc(struct cpuinfo_x86 *c)
463 /* Multi core CPU? */
464 if (c->extended_cpuid_level < 0x80000008)
467 ecx = cpuid_ecx(0x80000008);
469 c->x86_max_cores = (ecx & 0xff) + 1;
471 /* CPU telling us the core id bits shift? */
472 bits = (ecx >> 12) & 0xF;
474 /* Otherwise recompute */
476 while ((1 << bits) < c->x86_max_cores)
480 c->x86_coreid_bits = bits;
484 static void bsp_init_amd(struct cpuinfo_x86 *c)
489 unsigned long long tseg;
492 * Split up direct mapping around the TSEG SMM area.
493 * Don't do it for gbpages because there seems very little
494 * benefit in doing so.
496 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
497 unsigned long pfn = tseg >> PAGE_SHIFT;
499 pr_debug("tseg: %010llx\n", tseg);
500 if (pfn_range_is_mapped(pfn, pfn + 1))
501 set_memory_4k((unsigned long)__va(tseg), 1);
506 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
509 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
512 rdmsrl(MSR_K7_HWCR, val);
513 if (!(val & BIT(24)))
514 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
518 if (c->x86 == 0x15) {
519 unsigned long upperbit;
522 cpuid = cpuid_edx(0x80000005);
523 assoc = cpuid >> 16 & 0xff;
524 upperbit = ((cpuid >> 24) << 10) / assoc;
526 va_align.mask = (upperbit - 1) & PAGE_MASK;
527 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
529 /* A random value per boot for bit slice [12:upper_bit) */
530 va_align.bits = get_random_int() & va_align.mask;
533 if (cpu_has(c, X86_FEATURE_MWAITX))
536 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
539 ecx = cpuid_ecx(0x8000001e);
540 nodes_per_socket = ((ecx >> 8) & 7) + 1;
541 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
544 rdmsrl(MSR_FAM10H_NODE_ID, value);
545 nodes_per_socket = ((value >> 3) & 7) + 1;
549 static void early_init_amd(struct cpuinfo_x86 *c)
551 early_init_amd_mc(c);
554 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
555 * with P/T states and does not stop in deep C-states
557 if (c->x86_power & (1 << 8)) {
558 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
559 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
562 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
563 if (c->x86_power & BIT(12))
564 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
567 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
569 /* Set MTRR capability flag if appropriate */
571 if (c->x86_model == 13 || c->x86_model == 9 ||
572 (c->x86_model == 8 && c->x86_mask >= 8))
573 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
575 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
577 * ApicID can always be treated as an 8-bit value for AMD APIC versions
578 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
579 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
582 if (boot_cpu_has(X86_FEATURE_APIC)) {
584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
585 else if (c->x86 >= 0xf) {
586 /* check CPU config space for extended APIC ID */
589 val = read_pci_config(0, 24, 0, 0x68);
590 if ((val >> 17 & 0x3) == 0x3)
591 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
597 * This is only needed to tell the kernel whether to use VMCALL
598 * and VMMCALL. VMMCALL is never executed except under virt, so
599 * we can set it unconditionally.
601 set_cpu_cap(c, X86_FEATURE_VMMCALL);
603 /* F16h erratum 793, CVE-2013-6885 */
604 if (c->x86 == 0x16 && c->x86_model <= 0xf)
605 msr_set_bit(MSR_AMD64_LS_CFG, 15);
608 * Check whether the machine is affected by erratum 400. This is
609 * used to select the proper idle routine and to enable the check
610 * whether the machine is affected in arch_post_acpi_init(), which
611 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
613 if (cpu_has_amd_erratum(c, amd_erratum_400))
614 set_cpu_bug(c, X86_BUG_AMD_E400);
617 static void init_amd_k8(struct cpuinfo_x86 *c)
622 /* On C+ stepping K8 rep microcode works well for copy/memset */
623 level = cpuid_eax(1);
624 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
625 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
628 * Some BIOSes incorrectly force this feature, but only K8 revision D
629 * (model = 0x14) and later actually support it.
630 * (AMD Erratum #110, docId: 25759).
632 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
633 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
634 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
635 value &= ~BIT_64(32);
636 wrmsrl_amd_safe(0xc001100d, value);
640 if (!c->x86_model_id[0])
641 strcpy(c->x86_model_id, "Hammer");
645 * Disable TLB flush filter by setting HWCR.FFDIS on K8
646 * bit 6 of msr C001_0015
648 * Errata 63 for SH-B3 steppings
649 * Errata 122 for all steppings (F+ have it disabled by default)
651 msr_set_bit(MSR_K7_HWCR, 6);
653 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
656 static void init_amd_gh(struct cpuinfo_x86 *c)
659 /* do this for boot cpu */
660 if (c == &boot_cpu_data)
661 check_enable_amd_mmconf_dmi();
663 fam10h_check_enable_mmcfg();
667 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
668 * is always needed when GART is enabled, even in a kernel which has no
669 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
670 * If it doesn't, we do it here as suggested by the BKDG.
672 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
674 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
677 * On family 10h BIOS may not have properly enabled WC+ support, causing
678 * it to be converted to CD memtype. This may result in performance
679 * degradation for certain nested-paging guests. Prevent this conversion
680 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
682 * NOTE: we want to use the _safe accessors so as not to #GP kvm
683 * guests on older kvm hosts.
685 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
687 if (cpu_has_amd_erratum(c, amd_erratum_383))
688 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
691 #define MSR_AMD64_DE_CFG 0xC0011029
693 static void init_amd_ln(struct cpuinfo_x86 *c)
696 * Apply erratum 665 fix unconditionally so machines without a BIOS
699 msr_set_bit(MSR_AMD64_DE_CFG, 31);
702 static void init_amd_bd(struct cpuinfo_x86 *c)
706 /* re-enable TopologyExtensions if switched off by BIOS */
707 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
720 * The way access filter has a performance penalty on some workloads.
721 * Disable it on the affected CPUs.
723 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
724 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
726 wrmsrl_safe(MSR_F15H_IC_CFG, value);
731 static void init_amd(struct cpuinfo_x86 *c)
738 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
739 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
741 clear_cpu_cap(c, 0*32+31);
744 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
746 /* get apicid instead of initial apic id from cpuid */
747 c->apicid = hard_smp_processor_id();
749 /* K6s reports MCEs but don't actually have all the MSRs */
751 clear_cpu_cap(c, X86_FEATURE_MCE);
754 case 4: init_amd_k5(c); break;
755 case 5: init_amd_k6(c); break;
756 case 6: init_amd_k7(c); break;
757 case 0xf: init_amd_k8(c); break;
758 case 0x10: init_amd_gh(c); break;
759 case 0x12: init_amd_ln(c); break;
760 case 0x15: init_amd_bd(c); break;
763 /* Enable workaround for FXSAVE leak */
765 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
767 cpu_detect_cache_sizes(c);
769 /* Multi core CPU? */
770 if (c->extended_cpuid_level >= 0x80000008) {
779 init_amd_cacheinfo(c);
782 set_cpu_cap(c, X86_FEATURE_K8);
784 if (cpu_has(c, X86_FEATURE_XMM2)) {
785 /* MFENCE stops RDTSC speculation */
786 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
790 * Family 0x12 and above processors have APIC timer
791 * running in deep C states.
794 set_cpu_cap(c, X86_FEATURE_ARAT);
796 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
798 /* 3DNow or LM implies PREFETCHW */
799 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
800 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
801 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
803 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
804 if (!cpu_has(c, X86_FEATURE_XENPV))
805 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
809 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
811 /* AMD errata T13 (order #21922) */
814 if (c->x86_model == 3 && c->x86_mask == 0)
816 /* Tbird rev A1/A2 */
817 if (c->x86_model == 4 &&
818 (c->x86_mask == 0 || c->x86_mask == 1))
825 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
827 u32 ebx, eax, ecx, edx;
833 if (c->extended_cpuid_level < 0x80000006)
836 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
838 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
839 tlb_lli_4k[ENTRIES] = ebx & mask;
842 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
843 * characteristics from the CPUID function 0x80000005 instead.
846 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
850 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
851 if (!((eax >> 16) & mask))
852 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
854 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
856 /* a 4M entry uses two 2M entries */
857 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
859 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
862 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
863 tlb_lli_2m[ENTRIES] = 1024;
865 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
866 tlb_lli_2m[ENTRIES] = eax & 0xff;
869 tlb_lli_2m[ENTRIES] = eax & mask;
871 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
874 static const struct cpu_dev amd_cpu_dev = {
876 .c_ident = { "AuthenticAMD" },
879 { .family = 4, .model_names =
890 .legacy_cache_size = amd_size_cache,
892 .c_early_init = early_init_amd,
893 .c_detect_tlb = cpu_detect_tlb_amd,
894 .c_bsp_init = bsp_init_amd,
896 .c_x86_vendor = X86_VENDOR_AMD,
899 cpu_dev_register(amd_cpu_dev);
902 * AMD errata checking
904 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
905 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
906 * have an OSVW id assigned, which it takes as first argument. Both take a
907 * variable number of family-specific model-stepping ranges created by
912 * const int amd_erratum_319[] =
913 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
914 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
915 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
918 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
919 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
920 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
921 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
922 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
923 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
924 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
926 static const int amd_erratum_400[] =
927 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
928 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
930 static const int amd_erratum_383[] =
931 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
934 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
936 int osvw_id = *erratum++;
940 if (osvw_id >= 0 && osvw_id < 65536 &&
941 cpu_has(cpu, X86_FEATURE_OSVW)) {
944 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
945 if (osvw_id < osvw_len) {
948 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
950 return osvw_bits & (1ULL << (osvw_id & 0x3f));
954 /* OSVW unavailable or ID unknown, match family-model-stepping range */
955 ms = (cpu->x86_model << 4) | cpu->x86_mask;
956 while ((range = *erratum++))
957 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
958 (ms >= AMD_MODEL_RANGE_START(range)) &&
959 (ms <= AMD_MODEL_RANGE_END(range)))
965 void set_dr_addr_mask(unsigned long mask, int dr)
967 if (!boot_cpu_has(X86_FEATURE_BPEXT))
972 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
977 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);