arch/x86/kernel/cpu/centaur.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <linux/sched.h>
   4 #include <linux/sched/clock.h>
   5
   6 #include <asm/cpufeature.h>
   7 #include <asm/e820/api.h>
   8 #include <asm/mtrr.h>
   9 #include <asm/msr.h>
  10
  11 #include "cpu.h"
  12
  13 #define ACE_PRESENT     (1 << 6)
  14 #define ACE_ENABLED     (1 << 7)
  15 #define ACE_FCR         (1 << 28)       /* MSR_VIA_FCR */
  16
  17 #define RNG_PRESENT     (1 << 2)
  18 #define RNG_ENABLED     (1 << 3)
  19 #define RNG_ENABLE      (1 << 6)        /* MSR_VIA_RNG */
  20
  21 static void init_c3(struct cpuinfo_x86 *c)
  22 {
  23         u32  lo, hi;
  24
  25         /* Test for Centaur Extended Feature Flags presence */
  26         if (cpuid_eax(0xC0000000) >= 0xC0000001) {
  27                 u32 tmp = cpuid_edx(0xC0000001);
  28
  29                 /* enable ACE unit, if present and disabled */
  30                 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
  31                         rdmsr(MSR_VIA_FCR, lo, hi);
  32                         lo |= ACE_FCR;          /* enable ACE unit */
  33                         wrmsr(MSR_VIA_FCR, lo, hi);
  34                         pr_info("CPU: Enabled ACE h/w crypto\n");
  35                 }
  36
  37                 /* enable RNG unit, if present and disabled */
  38                 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
  39                         rdmsr(MSR_VIA_RNG, lo, hi);
  40                         lo |= RNG_ENABLE;       /* enable RNG unit */
  41                         wrmsr(MSR_VIA_RNG, lo, hi);
  42                         pr_info("CPU: Enabled h/w RNG\n");
  43                 }
  44
  45                 /* store Centaur Extended Feature Flags as
  46                  * word 5 of the CPU capability bit array
  47                  */
  48                 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
  49         }
  50 #ifdef CONFIG_X86_32
  51         /* Cyrix III family needs CX8 & PGE explicitly enabled. */
  52         if (c->x86_model >= 6 && c->x86_model <= 13) {
  53                 rdmsr(MSR_VIA_FCR, lo, hi);
  54                 lo |= (1<<1 | 1<<7);
  55                 wrmsr(MSR_VIA_FCR, lo, hi);
  56                 set_cpu_cap(c, X86_FEATURE_CX8);
  57         }
  58
  59         /* Before Nehemiah, the C3's had 3dNOW! */
  60         if (c->x86_model >= 6 && c->x86_model < 9)
  61                 set_cpu_cap(c, X86_FEATURE_3DNOW);
  62 #endif
  63         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
  64                 c->x86_cache_alignment = c->x86_clflush_size * 2;
  65                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  66         }
  67
  68         cpu_detect_cache_sizes(c);
  69 }
  70
  71 enum {
  72                 ECX8            = 1<<1,
  73                 EIERRINT        = 1<<2,
  74                 DPM             = 1<<3,
  75                 DMCE            = 1<<4,
  76                 DSTPCLK         = 1<<5,
  77                 ELINEAR         = 1<<6,
  78                 DSMC            = 1<<7,
  79                 DTLOCK          = 1<<8,
  80                 EDCTLB          = 1<<8,
  81                 EMMX            = 1<<9,
  82                 DPDC            = 1<<11,
  83                 EBRPRED         = 1<<12,
  84                 DIC             = 1<<13,
  85                 DDC             = 1<<14,
  86                 DNA             = 1<<15,
  87                 ERETSTK         = 1<<16,
  88                 E2MMX           = 1<<19,
  89                 EAMD3D          = 1<<20,
  90 };
  91
  92 static void early_init_centaur(struct cpuinfo_x86 *c)
  93 {
  94         switch (c->x86) {
  95 #ifdef CONFIG_X86_32
  96         case 5:
  97                 /* Emulate MTRRs using Centaur's MCR. */
  98                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
  99                 break;
 100 #endif
 101         case 6:
 102                 if (c->x86_model >= 0xf)
 103                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 104                 break;
 105         }
 106 #ifdef CONFIG_X86_64
 107         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 108 #endif
 109         if (c->x86_power & (1 << 8)) {
 110                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 111                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 112         }
 113 }
 114
 115 static void init_centaur(struct cpuinfo_x86 *c)
 116 {
 117 #ifdef CONFIG_X86_32
 118         char *name;
 119         u32  fcr_set = 0;
 120         u32  fcr_clr = 0;
 121         u32  lo, hi, newlo;
 122         u32  aa, bb, cc, dd;
 123
 124         /*
 125          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 126          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 127          */
 128         clear_cpu_cap(c, 0*32+31);
 129 #endif
 130         early_init_centaur(c);
 131         init_intel_cacheinfo(c);
 132         detect_num_cpu_cores(c);
 133 #ifdef CONFIG_X86_32
 134         detect_ht(c);
 135 #endif
 136
 137         if (c->cpuid_level > 9) {
 138                 unsigned int eax = cpuid_eax(10);
 139
 140                 /*
 141                  * Check for version and the number of counters
 142                  * Version(eax[7:0]) can't be 0;
 143                  * Counters(eax[15:8]) should be greater than 1;
 144                  */
 145                 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
 146                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 147         }
 148
 149         switch (c->x86) {
 150 #ifdef CONFIG_X86_32
 151         case 5:
 152                 switch (c->x86_model) {
 153                 case 4:
 154                         name = "C6";
 155                         fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
 156                         fcr_clr = DPDC;
 157                         pr_notice("Disabling bugged TSC.\n");
 158                         clear_cpu_cap(c, X86_FEATURE_TSC);
 159                         break;
 160                 case 8:
 161                         switch (c->x86_stepping) {
 162                         default:
 163                         name = "2";
 164                                 break;
 165                         case 7 ... 9:
 166                                 name = "2A";
 167                                 break;
 168                         case 10 ... 15:
 169                                 name = "2B";
 170                                 break;
 171                         }
 172                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 173                                   E2MMX|EAMD3D;
 174                         fcr_clr = DPDC;
 175                         break;
 176                 case 9:
 177                         name = "3";
 178                         fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
 179                                   E2MMX|EAMD3D;
 180                         fcr_clr = DPDC;
 181                         break;
 182                 default:
 183                         name = "??";
 184                 }
 185
 186                 rdmsr(MSR_IDT_FCR1, lo, hi);
 187                 newlo = (lo|fcr_set) & (~fcr_clr);
 188
 189                 if (newlo != lo) {
 190                         pr_info("Centaur FCR was 0x%X now 0x%X\n",
 191                                 lo, newlo);
 192                         wrmsr(MSR_IDT_FCR1, newlo, hi);
 193                 } else {
 194                         pr_info("Centaur FCR is 0x%X\n", lo);
 195                 }
 196                 /* Emulate MTRRs using Centaur's MCR. */
 197                 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
 198                 /* Report CX8 */
 199                 set_cpu_cap(c, X86_FEATURE_CX8);
 200                 /* Set 3DNow! on Winchip 2 and above. */
 201                 if (c->x86_model >= 8)
 202                         set_cpu_cap(c, X86_FEATURE_3DNOW);
 203                 /* See if we can find out some more. */
 204                 if (cpuid_eax(0x80000000) >= 0x80000005) {
 205                         /* Yes, we can. */
 206                         cpuid(0x80000005, &aa, &bb, &cc, &dd);
 207                         /* Add L1 data and code cache sizes. */
 208                         c->x86_cache_size = (cc>>24)+(dd>>24);
 209                 }
 210                 sprintf(c->x86_model_id, "WinChip %s", name);
 211                 break;
 212 #endif
 213         case 6:
 214                 init_c3(c);
 215                 break;
 216         }
 217 #ifdef CONFIG_X86_64
 218         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 219 #endif
 220
 221         init_ia32_feat_ctl(c);
 222 }
 223
 224 #ifdef CONFIG_X86_32
 225 static unsigned int
 226 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 227 {
 228         /* VIA C3 CPUs (670-68F) need further shifting. */
 229         if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
 230                 size >>= 8;
 231
 232         /*
 233          * There's also an erratum in Nehemiah stepping 1, which
 234          * returns '65KB' instead of '64KB'
 235          *  - Note, it seems this may only be in engineering samples.
 236          */
 237         if ((c->x86 == 6) && (c->x86_model == 9) &&
 238                                 (c->x86_stepping == 1) && (size == 65))
 239                 size -= 1;
 240         return size;
 241 }
 242 #endif
 243
 244 static const struct cpu_dev centaur_cpu_dev = {
 245         .c_vendor       = "Centaur",
 246         .c_ident        = { "CentaurHauls" },
 247         .c_early_init   = early_init_centaur,
 248         .c_init         = init_centaur,
 249 #ifdef CONFIG_X86_32
 250         .legacy_cache_size = centaur_size_cache,
 251 #endif
 252         .c_x86_vendor   = X86_VENDOR_CENTAUR,
 253 };
 254
 255 cpu_dev_register(centaur_cpu_dev);