1 #include <linux/bitops.h>
2 #include <linux/kernel.h>
4 #include <asm/cpufeature.h>
11 #define ACE_PRESENT (1 << 6)
12 #define ACE_ENABLED (1 << 7)
13 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
15 #define RNG_PRESENT (1 << 2)
16 #define RNG_ENABLED (1 << 3)
17 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
19 static void init_c3(struct cpuinfo_x86 *c)
23 /* Test for Centaur Extended Feature Flags presence */
24 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
25 u32 tmp = cpuid_edx(0xC0000001);
27 /* enable ACE unit, if present and disabled */
28 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
29 rdmsr(MSR_VIA_FCR, lo, hi);
30 lo |= ACE_FCR; /* enable ACE unit */
31 wrmsr(MSR_VIA_FCR, lo, hi);
32 pr_info("CPU: Enabled ACE h/w crypto\n");
35 /* enable RNG unit, if present and disabled */
36 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
37 rdmsr(MSR_VIA_RNG, lo, hi);
38 lo |= RNG_ENABLE; /* enable RNG unit */
39 wrmsr(MSR_VIA_RNG, lo, hi);
40 pr_info("CPU: Enabled h/w RNG\n");
43 /* store Centaur Extended Feature Flags as
44 * word 5 of the CPU capability bit array
46 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
49 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
50 if (c->x86_model >= 6 && c->x86_model <= 13) {
51 rdmsr(MSR_VIA_FCR, lo, hi);
53 wrmsr(MSR_VIA_FCR, lo, hi);
54 set_cpu_cap(c, X86_FEATURE_CX8);
57 /* Before Nehemiah, the C3's had 3dNOW! */
58 if (c->x86_model >= 6 && c->x86_model < 9)
59 set_cpu_cap(c, X86_FEATURE_3DNOW);
61 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
62 c->x86_cache_alignment = c->x86_clflush_size * 2;
63 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
66 cpu_detect_cache_sizes(c);
90 static void early_init_centaur(struct cpuinfo_x86 *c)
95 /* Emulate MTRRs using Centaur's MCR. */
96 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
100 if (c->x86_model >= 0xf)
101 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
105 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
109 static void init_centaur(struct cpuinfo_x86 *c)
119 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
120 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
122 clear_cpu_cap(c, 0*32+31);
124 early_init_centaur(c);
128 switch (c->x86_model) {
131 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
133 pr_notice("Disabling bugged TSC.\n");
134 clear_cpu_cap(c, X86_FEATURE_TSC);
137 switch (c->x86_mask) {
148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
162 rdmsr(MSR_IDT_FCR1, lo, hi);
163 newlo = (lo|fcr_set) & (~fcr_clr);
166 pr_info("Centaur FCR was 0x%X now 0x%X\n",
168 wrmsr(MSR_IDT_FCR1, newlo, hi);
170 pr_info("Centaur FCR is 0x%X\n", lo);
172 /* Emulate MTRRs using Centaur's MCR. */
173 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
175 set_cpu_cap(c, X86_FEATURE_CX8);
176 /* Set 3DNow! on Winchip 2 and above. */
177 if (c->x86_model >= 8)
178 set_cpu_cap(c, X86_FEATURE_3DNOW);
179 /* See if we can find out some more. */
180 if (cpuid_eax(0x80000000) >= 0x80000005) {
182 cpuid(0x80000005, &aa, &bb, &cc, &dd);
183 /* Add L1 data and code cache sizes. */
184 c->x86_cache_size = (cc>>24)+(dd>>24);
186 sprintf(c->x86_model_id, "WinChip %s", name);
194 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
200 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
202 /* VIA C3 CPUs (670-68F) need further shifting. */
203 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
207 * There's also an erratum in Nehemiah stepping 1, which
208 * returns '65KB' instead of '64KB'
209 * - Note, it seems this may only be in engineering samples.
211 if ((c->x86 == 6) && (c->x86_model == 9) &&
212 (c->x86_mask == 1) && (size == 65))
218 static const struct cpu_dev centaur_cpu_dev = {
219 .c_vendor = "Centaur",
220 .c_ident = { "CentaurHauls" },
221 .c_early_init = early_init_centaur,
222 .c_init = init_centaur,
224 .legacy_cache_size = centaur_size_cache,
226 .c_x86_vendor = X86_VENDOR_CENTAUR,
229 cpu_dev_register(centaur_cpu_dev);