2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
46 #include <asm/intel-family.h>
47 #include <asm/processor.h>
48 #include <asm/traps.h>
49 #include <asm/tlbflush.h>
53 #include "mce-internal.h"
55 static DEFINE_MUTEX(mce_chrdev_read_mutex);
57 #define mce_log_get_idx_check(p) \
59 RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
60 !lockdep_is_held(&mce_chrdev_read_mutex), \
61 "suspicious mce_log_get_idx_check() usage"); \
62 smp_load_acquire(&(p)); \
65 #define CREATE_TRACE_POINTS
66 #include <trace/events/mce.h>
68 #define SPINUNIT 100 /* 100ns */
70 DEFINE_PER_CPU(unsigned, mce_exception_count);
72 struct mce_bank *mce_banks __read_mostly;
73 struct mce_vendor_flags mce_flags __read_mostly;
75 struct mca_config mca_cfg __read_mostly = {
79 * 0: always panic on uncorrected errors, log corrected errors
80 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
81 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
82 * 3: never panic or SIGBUS, log all errors (for testing only)
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * MCA banks polled by the period polling timer for corrected events.
100 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
102 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
103 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
107 * MCA banks controlled through firmware first for corrected errors.
108 * This is a global list of banks for which we won't enable CMCI and we
109 * won't poll. Firmware controls these banks and is responsible for
110 * reporting corrected errors through GHES. Uncorrected/recoverable
111 * errors are still notified through a machine check.
113 mce_banks_t mce_banks_ce_disabled;
115 static struct work_struct mce_work;
116 static struct irq_work mce_irq_work;
118 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
121 * CPU/chipset specific EDAC code can register a notifier call here to print
122 * MCE errors in a human-readable form.
124 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
126 /* Do initial initialization of a struct mce */
127 void mce_setup(struct mce *m)
129 memset(m, 0, sizeof(struct mce));
130 m->cpu = m->extcpu = smp_processor_id();
132 /* We hope get_seconds stays lockless */
133 m->time = get_seconds();
134 m->cpuvendor = boot_cpu_data.x86_vendor;
135 m->cpuid = cpuid_eax(1);
136 m->socketid = cpu_data(m->extcpu).phys_proc_id;
137 m->apicid = cpu_data(m->extcpu).initial_apicid;
138 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
140 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
141 rdmsrl(MSR_PPIN, m->ppin);
144 DEFINE_PER_CPU(struct mce, injectm);
145 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
148 * Lockless MCE logging infrastructure.
149 * This avoids deadlocks on printk locks without having to break locks. Also
150 * separate MCEs from kernel messages to avoid bogus bug reports.
153 static struct mce_log mcelog = {
154 .signature = MCE_LOG_SIGNATURE,
156 .recordlen = sizeof(struct mce),
159 void mce_log(struct mce *mce)
161 unsigned next, entry;
163 /* Emit the trace record: */
164 trace_mce_record(mce);
166 if (!mce_gen_pool_add(mce))
167 irq_work_queue(&mce_irq_work);
171 entry = mce_log_get_idx_check(mcelog.next);
175 * When the buffer fills up discard new entries.
176 * Assume that the earlier errors are the more
179 if (entry >= MCE_LOG_LEN) {
180 set_bit(MCE_OVERFLOW,
181 (unsigned long *)&mcelog.flags);
184 /* Old left over entry. Skip: */
185 if (mcelog.entry[entry].finished) {
193 if (cmpxchg(&mcelog.next, entry, next) == entry)
196 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
198 mcelog.entry[entry].finished = 1;
201 set_bit(0, &mce_need_notify);
204 void mce_inject_log(struct mce *m)
206 mutex_lock(&mce_chrdev_read_mutex);
208 mutex_unlock(&mce_chrdev_read_mutex);
210 EXPORT_SYMBOL_GPL(mce_inject_log);
212 static struct notifier_block mce_srao_nb;
214 static atomic_t num_notifiers;
216 void mce_register_decode_chain(struct notifier_block *nb)
218 atomic_inc(&num_notifiers);
220 /* Ensure SRAO notifier has the highest priority in the decode chain. */
221 if (nb != &mce_srao_nb && nb->priority == INT_MAX)
224 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
226 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
228 void mce_unregister_decode_chain(struct notifier_block *nb)
230 atomic_dec(&num_notifiers);
232 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
234 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
236 static inline u32 ctl_reg(int bank)
238 return MSR_IA32_MCx_CTL(bank);
241 static inline u32 status_reg(int bank)
243 return MSR_IA32_MCx_STATUS(bank);
246 static inline u32 addr_reg(int bank)
248 return MSR_IA32_MCx_ADDR(bank);
251 static inline u32 misc_reg(int bank)
253 return MSR_IA32_MCx_MISC(bank);
256 static inline u32 smca_ctl_reg(int bank)
258 return MSR_AMD64_SMCA_MCx_CTL(bank);
261 static inline u32 smca_status_reg(int bank)
263 return MSR_AMD64_SMCA_MCx_STATUS(bank);
266 static inline u32 smca_addr_reg(int bank)
268 return MSR_AMD64_SMCA_MCx_ADDR(bank);
271 static inline u32 smca_misc_reg(int bank)
273 return MSR_AMD64_SMCA_MCx_MISC(bank);
276 struct mca_msr_regs msr_ops = {
278 .status = status_reg,
283 static void __print_mce(struct mce *m)
285 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
287 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
288 m->mcgstatus, m->bank, m->status);
291 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
292 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
295 if (m->cs == __KERNEL_CS)
296 print_symbol("{%s}", m->ip);
300 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
302 pr_cont("ADDR %llx ", m->addr);
304 pr_cont("MISC %llx ", m->misc);
306 if (mce_flags.smca) {
308 pr_cont("SYND %llx ", m->synd);
310 pr_cont("IPID %llx ", m->ipid);
315 * Note this output is parsed by external tools and old fields
316 * should not be changed.
318 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
319 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
320 cpu_data(m->extcpu).microcode);
323 static void print_mce(struct mce *m)
330 * Print out human-readable details about the MCE error,
331 * (if the CPU has an implementation for that)
333 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
334 if (ret == NOTIFY_STOP)
337 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
340 #define PANIC_TIMEOUT 5 /* 5 seconds */
342 static atomic_t mce_panicked;
344 static int fake_panic;
345 static atomic_t mce_fake_panicked;
347 /* Panic in progress. Enable interrupts and wait for final IPI */
348 static void wait_for_panic(void)
350 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
354 while (timeout-- > 0)
356 if (panic_timeout == 0)
357 panic_timeout = mca_cfg.panic_timeout;
358 panic("Panicing machine check CPU died");
361 static void mce_panic(const char *msg, struct mce *final, char *exp)
364 struct llist_node *pending;
365 struct mce_evt_llist *l;
369 * Make sure only one CPU runs in machine check panic
371 if (atomic_inc_return(&mce_panicked) > 1)
378 /* Don't log too much for fake panic */
379 if (atomic_inc_return(&mce_fake_panicked) > 1)
382 pending = mce_gen_pool_prepare_records();
383 /* First print corrected ones that are still unlogged */
384 llist_for_each_entry(l, pending, llnode) {
385 struct mce *m = &l->mce;
386 if (!(m->status & MCI_STATUS_UC)) {
389 apei_err = apei_write_mce(m);
392 /* Now print uncorrected but with the final one last */
393 llist_for_each_entry(l, pending, llnode) {
394 struct mce *m = &l->mce;
395 if (!(m->status & MCI_STATUS_UC))
397 if (!final || mce_cmp(m, final)) {
400 apei_err = apei_write_mce(m);
406 apei_err = apei_write_mce(final);
409 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
411 pr_emerg(HW_ERR "Machine check: %s\n", exp);
413 if (panic_timeout == 0)
414 panic_timeout = mca_cfg.panic_timeout;
417 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
420 /* Support code for software error injection */
422 static int msr_to_offset(u32 msr)
424 unsigned bank = __this_cpu_read(injectm.bank);
426 if (msr == mca_cfg.rip_msr)
427 return offsetof(struct mce, ip);
428 if (msr == msr_ops.status(bank))
429 return offsetof(struct mce, status);
430 if (msr == msr_ops.addr(bank))
431 return offsetof(struct mce, addr);
432 if (msr == msr_ops.misc(bank))
433 return offsetof(struct mce, misc);
434 if (msr == MSR_IA32_MCG_STATUS)
435 return offsetof(struct mce, mcgstatus);
439 /* MSR access wrappers used for error injection */
440 static u64 mce_rdmsrl(u32 msr)
444 if (__this_cpu_read(injectm.finished)) {
445 int offset = msr_to_offset(msr);
449 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
452 if (rdmsrl_safe(msr, &v)) {
453 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
455 * Return zero in case the access faulted. This should
456 * not happen normally but can happen if the CPU does
457 * something weird, or if the code is buggy.
465 static void mce_wrmsrl(u32 msr, u64 v)
467 if (__this_cpu_read(injectm.finished)) {
468 int offset = msr_to_offset(msr);
471 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
478 * Collect all global (w.r.t. this processor) status about this machine
479 * check into our "mce" struct so that we can use it later to assess
480 * the severity of the problem as we read per-bank specific details.
482 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
486 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
489 * Get the address of the instruction at the time of
490 * the machine check error.
492 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
497 * When in VM86 mode make the cs look like ring 3
498 * always. This is a lie, but it's better than passing
499 * the additional vm86 bit around everywhere.
501 if (v8086_mode(regs))
504 /* Use accurate RIP reporting if available. */
506 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
510 int mce_available(struct cpuinfo_x86 *c)
512 if (mca_cfg.disabled)
514 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
517 static void mce_schedule_work(void)
519 if (!mce_gen_pool_empty())
520 schedule_work(&mce_work);
523 static void mce_irq_work_cb(struct irq_work *entry)
529 static void mce_report_event(struct pt_regs *regs)
531 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
534 * Triggering the work queue here is just an insurance
535 * policy in case the syscall exit notify handler
536 * doesn't run soon enough or ends up running on the
537 * wrong CPU (can happen when audit sleeps)
543 irq_work_queue(&mce_irq_work);
547 * Check if the address reported by the CPU is in a format we can parse.
548 * It would be possible to add code for most other cases, but all would
549 * be somewhat complicated (e.g. segment offset would require an instruction
550 * parser). So only support physical addresses up to page granuality for now.
552 static int mce_usable_address(struct mce *m)
554 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
557 /* Checks after this one are Intel-specific: */
558 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
561 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
563 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
568 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
571 struct mce *mce = (struct mce *)data;
577 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
578 pfn = mce->addr >> PAGE_SHIFT;
579 memory_failure(pfn, MCE_VECTOR, 0);
584 static struct notifier_block mce_srao_nb = {
585 .notifier_call = srao_decode_notifier,
589 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
592 struct mce *m = (struct mce *)data;
598 * Run the default notifier if we have only the SRAO
599 * notifier and us registered.
601 if (atomic_read(&num_notifiers) > 2)
609 static struct notifier_block mce_default_nb = {
610 .notifier_call = mce_default_notifier,
611 /* lowest prio, we want it to run last. */
616 * Read ADDR and MISC registers.
618 static void mce_read_aux(struct mce *m, int i)
620 if (m->status & MCI_STATUS_MISCV)
621 m->misc = mce_rdmsrl(msr_ops.misc(i));
623 if (m->status & MCI_STATUS_ADDRV) {
624 m->addr = mce_rdmsrl(msr_ops.addr(i));
627 * Mask the reported address by the reported granularity.
629 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
630 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
636 * Extract [55:<lsb>] where lsb is the least significant
637 * *valid* bit of the address bits.
639 if (mce_flags.smca) {
640 u8 lsb = (m->addr >> 56) & 0x3f;
642 m->addr &= GENMASK_ULL(55, lsb);
646 if (mce_flags.smca) {
647 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
649 if (m->status & MCI_STATUS_SYNDV)
650 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
654 static bool memory_error(struct mce *m)
656 struct cpuinfo_x86 *c = &boot_cpu_data;
658 if (c->x86_vendor == X86_VENDOR_AMD) {
659 /* ErrCodeExt[20:16] */
660 u8 xec = (m->status >> 16) & 0x1f;
662 return (xec == 0x0 || xec == 0x8);
663 } else if (c->x86_vendor == X86_VENDOR_INTEL) {
665 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
667 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
668 * indicating a memory error. Bit 8 is used for indicating a
669 * cache hierarchy error. The combination of bit 2 and bit 3
670 * is used for indicating a `generic' cache hierarchy error
671 * But we can't just blindly check the above bits, because if
672 * bit 11 is set, then it is a bus/interconnect error - and
673 * either way the above bits just gives more detail on what
674 * bus/interconnect error happened. Note that bit 12 can be
675 * ignored, as it's the "filter" bit.
677 return (m->status & 0xef80) == BIT(7) ||
678 (m->status & 0xef00) == BIT(8) ||
679 (m->status & 0xeffc) == 0xc;
685 DEFINE_PER_CPU(unsigned, mce_poll_count);
688 * Poll for corrected events or events that happened before reset.
689 * Those are just logged through /dev/mcelog.
691 * This is executed in standard interrupt context.
693 * Note: spec recommends to panic for fatal unsignalled
694 * errors here. However this would be quite problematic --
695 * we would need to reimplement the Monarch handling and
696 * it would mess up the exclusion between exception handler
697 * and poll hander -- * so we skip this for now.
698 * These cases should not happen anyways, or only when the CPU
699 * is already totally * confused. In this case it's likely it will
700 * not fully execute the machine check handler either.
702 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
704 bool error_seen = false;
709 this_cpu_inc(mce_poll_count);
711 mce_gather_info(&m, NULL);
714 * m.tsc was set in mce_setup(). Clear it if not requested.
716 * FIXME: Propagate @flags to mce_gather_info/mce_setup() to avoid
719 if (!(flags & MCP_TIMESTAMP))
722 for (i = 0; i < mca_cfg.banks; i++) {
723 if (!mce_banks[i].ctl || !test_bit(i, *b))
731 m.status = mce_rdmsrl(msr_ops.status(i));
732 if (!(m.status & MCI_STATUS_VAL))
736 * Uncorrected or signalled events are handled by the exception
737 * handler when it is enabled, so don't process those here.
739 * TBD do the same check for MCI_STATUS_EN here?
741 if (!(flags & MCP_UC) &&
742 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
749 severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
751 if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m))
752 if (m.status & MCI_STATUS_ADDRV)
753 m.severity = severity;
756 * Don't get the IP here because it's unlikely to
757 * have anything to do with the actual error location.
759 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
761 else if (mce_usable_address(&m)) {
763 * Although we skipped logging this, we still want
764 * to take action. Add to the pool so the registered
765 * notifiers will see it.
767 if (!mce_gen_pool_add(&m))
772 * Clear state for this bank.
774 mce_wrmsrl(msr_ops.status(i), 0);
778 * Don't clear MCG_STATUS here because it's only defined for
786 EXPORT_SYMBOL_GPL(machine_check_poll);
789 * Do a quick check if any of the events requires a panic.
790 * This decides if we keep the events around or clear them.
792 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
793 struct pt_regs *regs)
798 for (i = 0; i < mca_cfg.banks; i++) {
799 m->status = mce_rdmsrl(msr_ops.status(i));
800 if (m->status & MCI_STATUS_VAL) {
801 __set_bit(i, validp);
802 if (quirk_no_way_out)
803 quirk_no_way_out(i, m, regs);
806 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
815 * Variable to establish order between CPUs while scanning.
816 * Each CPU spins initially until executing is equal its number.
818 static atomic_t mce_executing;
821 * Defines order of CPUs on entry. First CPU becomes Monarch.
823 static atomic_t mce_callin;
826 * Check if a timeout waiting for other CPUs happened.
828 static int mce_timed_out(u64 *t, const char *msg)
831 * The others already did panic for some reason.
832 * Bail out like in a timeout.
833 * rmb() to tell the compiler that system_state
834 * might have been modified by someone else.
837 if (atomic_read(&mce_panicked))
839 if (!mca_cfg.monarch_timeout)
841 if ((s64)*t < SPINUNIT) {
842 if (mca_cfg.tolerant <= 1)
843 mce_panic(msg, NULL, NULL);
849 touch_nmi_watchdog();
854 * The Monarch's reign. The Monarch is the CPU who entered
855 * the machine check handler first. It waits for the others to
856 * raise the exception too and then grades them. When any
857 * error is fatal panic. Only then let the others continue.
859 * The other CPUs entering the MCE handler will be controlled by the
860 * Monarch. They are called Subjects.
862 * This way we prevent any potential data corruption in a unrecoverable case
863 * and also makes sure always all CPU's errors are examined.
865 * Also this detects the case of a machine check event coming from outer
866 * space (not detected by any CPUs) In this case some external agent wants
867 * us to shut down, so panic too.
869 * The other CPUs might still decide to panic if the handler happens
870 * in a unrecoverable place, but in this case the system is in a semi-stable
871 * state and won't corrupt anything by itself. It's ok to let the others
872 * continue for a bit first.
874 * All the spin loops have timeouts; when a timeout happens a CPU
875 * typically elects itself to be Monarch.
877 static void mce_reign(void)
880 struct mce *m = NULL;
881 int global_worst = 0;
886 * This CPU is the Monarch and the other CPUs have run
887 * through their handlers.
888 * Grade the severity of the errors of all the CPUs.
890 for_each_possible_cpu(cpu) {
891 int severity = mce_severity(&per_cpu(mces_seen, cpu),
894 if (severity > global_worst) {
896 global_worst = severity;
897 m = &per_cpu(mces_seen, cpu);
902 * Cannot recover? Panic here then.
903 * This dumps all the mces in the log buffer and stops the
906 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
907 mce_panic("Fatal machine check", m, msg);
910 * For UC somewhere we let the CPU who detects it handle it.
911 * Also must let continue the others, otherwise the handling
912 * CPU could deadlock on a lock.
916 * No machine check event found. Must be some external
917 * source or one CPU is hung. Panic.
919 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
920 mce_panic("Fatal machine check from unknown source", NULL, NULL);
923 * Now clear all the mces_seen so that they don't reappear on
926 for_each_possible_cpu(cpu)
927 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
930 static atomic_t global_nwo;
933 * Start of Monarch synchronization. This waits until all CPUs have
934 * entered the exception handler and then determines if any of them
935 * saw a fatal event that requires panic. Then it executes them
936 * in the entry order.
937 * TBD double check parallel CPU hotunplug
939 static int mce_start(int *no_way_out)
942 int cpus = num_online_cpus();
943 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
948 atomic_add(*no_way_out, &global_nwo);
950 * Rely on the implied barrier below, such that global_nwo
951 * is updated before mce_callin.
953 order = atomic_inc_return(&mce_callin);
958 while (atomic_read(&mce_callin) != cpus) {
959 if (mce_timed_out(&timeout,
960 "Timeout: Not all CPUs entered broadcast exception handler")) {
961 atomic_set(&global_nwo, 0);
968 * mce_callin should be read before global_nwo
974 * Monarch: Starts executing now, the others wait.
976 atomic_set(&mce_executing, 1);
979 * Subject: Now start the scanning loop one by one in
980 * the original callin order.
981 * This way when there are any shared banks it will be
982 * only seen by one CPU before cleared, avoiding duplicates.
984 while (atomic_read(&mce_executing) < order) {
985 if (mce_timed_out(&timeout,
986 "Timeout: Subject CPUs unable to finish machine check processing")) {
987 atomic_set(&global_nwo, 0);
995 * Cache the global no_way_out state.
997 *no_way_out = atomic_read(&global_nwo);
1003 * Synchronize between CPUs after main scanning loop.
1004 * This invokes the bulk of the Monarch processing.
1006 static int mce_end(int order)
1009 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1017 * Allow others to run.
1019 atomic_inc(&mce_executing);
1022 /* CHECKME: Can this race with a parallel hotplug? */
1023 int cpus = num_online_cpus();
1026 * Monarch: Wait for everyone to go through their scanning
1029 while (atomic_read(&mce_executing) <= cpus) {
1030 if (mce_timed_out(&timeout,
1031 "Timeout: Monarch CPU unable to finish machine check processing"))
1041 * Subject: Wait for Monarch to finish.
1043 while (atomic_read(&mce_executing) != 0) {
1044 if (mce_timed_out(&timeout,
1045 "Timeout: Monarch CPU did not finish machine check processing"))
1051 * Don't reset anything. That's done by the Monarch.
1057 * Reset all global state.
1060 atomic_set(&global_nwo, 0);
1061 atomic_set(&mce_callin, 0);
1065 * Let others run again.
1067 atomic_set(&mce_executing, 0);
1071 static void mce_clear_state(unsigned long *toclear)
1075 for (i = 0; i < mca_cfg.banks; i++) {
1076 if (test_bit(i, toclear))
1077 mce_wrmsrl(msr_ops.status(i), 0);
1081 static int do_memory_failure(struct mce *m)
1083 int flags = MF_ACTION_REQUIRED;
1086 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1087 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1088 flags |= MF_MUST_KILL;
1089 ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags);
1091 pr_err("Memory error not recovered");
1096 * The actual machine check handler. This only handles real
1097 * exceptions when something got corrupted coming in through int 18.
1099 * This is executed in NMI context not subject to normal locking rules. This
1100 * implies that most kernel services cannot be safely used. Don't even
1101 * think about putting a printk in there!
1103 * On Intel systems this is entered on all CPUs in parallel through
1104 * MCE broadcast. However some CPUs might be broken beyond repair,
1105 * so be always careful when synchronizing with others.
1107 void do_machine_check(struct pt_regs *regs, long error_code)
1109 struct mca_config *cfg = &mca_cfg;
1110 struct mce m, *final;
1116 * Establish sequential order between the CPUs entering the machine
1121 * If no_way_out gets set, there is no safe way to recover from this
1122 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1126 * If kill_it gets set, there might be a way to recover from this
1130 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1131 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1132 char *msg = "Unknown";
1135 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1140 /* If this CPU is offline, just bail out. */
1141 if (cpu_is_offline(smp_processor_id())) {
1144 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1145 if (mcgstatus & MCG_STATUS_RIPV) {
1146 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1153 this_cpu_inc(mce_exception_count);
1158 mce_gather_info(&m, regs);
1160 final = this_cpu_ptr(&mces_seen);
1163 memset(valid_banks, 0, sizeof(valid_banks));
1164 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1169 * When no restart IP might need to kill or panic.
1170 * Assume the worst for now, but if we find the
1171 * severity is MCE_AR_SEVERITY we have other options.
1173 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1177 * Check if this MCE is signaled to only this logical processor,
1180 if (m.cpuvendor == X86_VENDOR_INTEL)
1181 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1184 * Go through all banks in exclusion of the other CPUs. This way we
1185 * don't report duplicated events on shared banks because the first one
1186 * to see it will clear it. If this is a Local MCE, then no need to
1187 * perform rendezvous.
1190 order = mce_start(&no_way_out);
1192 for (i = 0; i < cfg->banks; i++) {
1193 __clear_bit(i, toclear);
1194 if (!test_bit(i, valid_banks))
1196 if (!mce_banks[i].ctl)
1203 m.status = mce_rdmsrl(msr_ops.status(i));
1204 if ((m.status & MCI_STATUS_VAL) == 0)
1208 * Non uncorrected or non signaled errors are handled by
1209 * machine_check_poll. Leave them alone, unless this panics.
1211 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1216 * Set taint even when machine check was not enabled.
1218 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1220 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1223 * When machine check was for corrected/deferred handler don't
1224 * touch, unless we're panicing.
1226 if ((severity == MCE_KEEP_SEVERITY ||
1227 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1229 __set_bit(i, toclear);
1230 if (severity == MCE_NO_SEVERITY) {
1232 * Machine check event was not enabled. Clear, but
1238 mce_read_aux(&m, i);
1240 /* assuming valid severity level != 0 */
1241 m.severity = severity;
1245 if (severity > worst) {
1251 /* mce_clear_state will clear *final, save locally for use later */
1255 mce_clear_state(toclear);
1258 * Do most of the synchronization with other CPUs.
1259 * When there's any problem use only local no_way_out state.
1262 if (mce_end(order) < 0)
1263 no_way_out = worst >= MCE_PANIC_SEVERITY;
1266 * Local MCE skipped calling mce_reign()
1267 * If we found a fatal error, we need to panic here.
1269 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
1270 mce_panic("Machine check from unknown source",
1275 * If tolerant is at an insane level we drop requests to kill
1276 * processes and continue even when there is no way out.
1278 if (cfg->tolerant == 3)
1280 else if (no_way_out)
1281 mce_panic("Fatal machine check on current CPU", &m, msg);
1284 mce_report_event(regs);
1285 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1289 if (worst != MCE_AR_SEVERITY && !kill_it)
1292 /* Fault was in user mode and we need to take some action */
1293 if ((m.cs & 3) == 3) {
1294 ist_begin_non_atomic(regs);
1297 if (kill_it || do_memory_failure(&m))
1298 force_sig(SIGBUS, current);
1299 local_irq_disable();
1300 ist_end_non_atomic();
1302 if (!fixup_exception(regs, X86_TRAP_MC))
1303 mce_panic("Failed kernel mode recovery", &m, NULL);
1309 EXPORT_SYMBOL_GPL(do_machine_check);
1311 #ifndef CONFIG_MEMORY_FAILURE
1312 int memory_failure(unsigned long pfn, int vector, int flags)
1314 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1315 BUG_ON(flags & MF_ACTION_REQUIRED);
1316 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1317 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1325 * Action optional processing happens here (picking up
1326 * from the list of faulting pages that do_machine_check()
1327 * placed into the genpool).
1329 static void mce_process_work(struct work_struct *dummy)
1331 mce_gen_pool_process();
1335 * Periodic polling timer for "silent" machine check errors. If the
1336 * poller finds an MCE, poll 2x faster. When the poller finds no more
1337 * errors, poll 2x slower (up to check_interval seconds).
1339 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1341 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1342 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1344 static unsigned long mce_adjust_timer_default(unsigned long interval)
1349 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1351 static void __restart_timer(struct timer_list *t, unsigned long interval)
1353 unsigned long when = jiffies + interval;
1354 unsigned long flags;
1356 local_irq_save(flags);
1358 if (timer_pending(t)) {
1359 if (time_before(when, t->expires))
1362 t->expires = round_jiffies(when);
1363 add_timer_on(t, smp_processor_id());
1366 local_irq_restore(flags);
1369 static void mce_timer_fn(unsigned long data)
1371 struct timer_list *t = this_cpu_ptr(&mce_timer);
1372 int cpu = smp_processor_id();
1375 WARN_ON(cpu != data);
1377 iv = __this_cpu_read(mce_next_interval);
1379 if (mce_available(this_cpu_ptr(&cpu_info))) {
1380 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1382 if (mce_intel_cmci_poll()) {
1383 iv = mce_adjust_timer(iv);
1389 * Alert userspace if needed. If we logged an MCE, reduce the polling
1390 * interval, otherwise increase the polling interval.
1392 if (mce_notify_irq())
1393 iv = max(iv / 2, (unsigned long) HZ/100);
1395 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1398 __this_cpu_write(mce_next_interval, iv);
1399 __restart_timer(t, iv);
1403 * Ensure that the timer is firing in @interval from now.
1405 void mce_timer_kick(unsigned long interval)
1407 struct timer_list *t = this_cpu_ptr(&mce_timer);
1408 unsigned long iv = __this_cpu_read(mce_next_interval);
1410 __restart_timer(t, interval);
1413 __this_cpu_write(mce_next_interval, interval);
1416 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1417 static void mce_timer_delete_all(void)
1421 for_each_online_cpu(cpu)
1422 del_timer_sync(&per_cpu(mce_timer, cpu));
1425 static void mce_do_trigger(struct work_struct *work)
1427 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1430 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1433 * Notify the user(s) about new machine check events.
1434 * Can be called from interrupt context, but not from machine check/NMI
1437 int mce_notify_irq(void)
1439 /* Not more than two messages every minute */
1440 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1442 if (test_and_clear_bit(0, &mce_need_notify)) {
1443 /* wake processes polling /dev/mcelog */
1444 wake_up_interruptible(&mce_chrdev_wait);
1447 schedule_work(&mce_trigger_work);
1449 if (__ratelimit(&ratelimit))
1450 pr_info(HW_ERR "Machine check events logged\n");
1456 EXPORT_SYMBOL_GPL(mce_notify_irq);
1458 static int __mcheck_cpu_mce_banks_init(void)
1461 u8 num_banks = mca_cfg.banks;
1463 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1467 for (i = 0; i < num_banks; i++) {
1468 struct mce_bank *b = &mce_banks[i];
1477 * Initialize Machine Checks for a CPU.
1479 static int __mcheck_cpu_cap_init(void)
1484 rdmsrl(MSR_IA32_MCG_CAP, cap);
1486 b = cap & MCG_BANKCNT_MASK;
1488 pr_info("CPU supports %d MCE banks\n", b);
1490 if (b > MAX_NR_BANKS) {
1491 pr_warn("Using only %u machine check banks out of %u\n",
1496 /* Don't support asymmetric configurations today */
1497 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1501 int err = __mcheck_cpu_mce_banks_init();
1507 /* Use accurate RIP reporting if available. */
1508 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1509 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1511 if (cap & MCG_SER_P)
1517 static void __mcheck_cpu_init_generic(void)
1519 enum mcp_flags m_fl = 0;
1520 mce_banks_t all_banks;
1523 if (!mca_cfg.bootlog)
1527 * Log the machine checks left over from the previous reset.
1529 bitmap_fill(all_banks, MAX_NR_BANKS);
1530 machine_check_poll(MCP_UC | m_fl, &all_banks);
1532 cr4_set_bits(X86_CR4_MCE);
1534 rdmsrl(MSR_IA32_MCG_CAP, cap);
1535 if (cap & MCG_CTL_P)
1536 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1539 static void __mcheck_cpu_init_clear_banks(void)
1543 for (i = 0; i < mca_cfg.banks; i++) {
1544 struct mce_bank *b = &mce_banks[i];
1548 wrmsrl(msr_ops.ctl(i), b->ctl);
1549 wrmsrl(msr_ops.status(i), 0);
1554 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1555 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1556 * Vol 3B Table 15-20). But this confuses both the code that determines
1557 * whether the machine check occurred in kernel or user mode, and also
1558 * the severity assessment code. Pretend that EIPV was set, and take the
1559 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1561 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1565 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1567 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1568 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1569 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1571 (MCI_STATUS_UC|MCI_STATUS_EN|
1572 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1573 MCI_STATUS_AR|MCACOD_INSTR))
1576 m->mcgstatus |= MCG_STATUS_EIPV;
1581 /* Add per CPU specific workarounds here */
1582 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1584 struct mca_config *cfg = &mca_cfg;
1586 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1587 pr_info("unknown CPU type - not enabling MCE support\n");
1591 /* This should be disabled by the BIOS, but isn't always */
1592 if (c->x86_vendor == X86_VENDOR_AMD) {
1593 if (c->x86 == 15 && cfg->banks > 4) {
1595 * disable GART TBL walk error reporting, which
1596 * trips off incorrectly with the IOMMU & 3ware
1599 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1601 if (c->x86 < 17 && cfg->bootlog < 0) {
1603 * Lots of broken BIOS around that don't clear them
1604 * by default and leave crap in there. Don't log:
1609 * Various K7s with broken bank 0 around. Always disable
1612 if (c->x86 == 6 && cfg->banks > 0)
1613 mce_banks[0].ctl = 0;
1616 * overflow_recov is supported for F15h Models 00h-0fh
1617 * even though we don't have a CPUID bit for it.
1619 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1620 mce_flags.overflow_recov = 1;
1623 * Turn off MC4_MISC thresholding banks on those models since
1624 * they're not supported there.
1626 if (c->x86 == 0x15 &&
1627 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1632 0x00000413, /* MC4_MISC0 */
1633 0xc0000408, /* MC4_MISC1 */
1636 rdmsrl(MSR_K7_HWCR, hwcr);
1638 /* McStatusWrEn has to be set */
1639 need_toggle = !(hwcr & BIT(18));
1642 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1644 /* Clear CntP bit safely */
1645 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1646 msr_clear_bit(msrs[i], 62);
1648 /* restore old settings */
1650 wrmsrl(MSR_K7_HWCR, hwcr);
1654 if (c->x86_vendor == X86_VENDOR_INTEL) {
1656 * SDM documents that on family 6 bank 0 should not be written
1657 * because it aliases to another special BIOS controlled
1659 * But it's not aliased anymore on model 0x1a+
1660 * Don't ignore bank 0 completely because there could be a
1661 * valid event later, merely don't write CTL0.
1664 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1665 mce_banks[0].init = 0;
1668 * All newer Intel systems support MCE broadcasting. Enable
1669 * synchronization with a one second timeout.
1671 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1672 cfg->monarch_timeout < 0)
1673 cfg->monarch_timeout = USEC_PER_SEC;
1676 * There are also broken BIOSes on some Pentium M and
1679 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1682 if (c->x86 == 6 && c->x86_model == 45)
1683 quirk_no_way_out = quirk_sandybridge_ifu;
1685 if (cfg->monarch_timeout < 0)
1686 cfg->monarch_timeout = 0;
1687 if (cfg->bootlog != 0)
1688 cfg->panic_timeout = 30;
1693 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1698 switch (c->x86_vendor) {
1699 case X86_VENDOR_INTEL:
1700 intel_p5_mcheck_init(c);
1703 case X86_VENDOR_CENTAUR:
1704 winchip_mcheck_init(c);
1714 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1716 switch (c->x86_vendor) {
1717 case X86_VENDOR_INTEL:
1718 mce_intel_feature_init(c);
1719 mce_adjust_timer = cmci_intel_adjust_timer;
1722 case X86_VENDOR_AMD: {
1723 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1724 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1725 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1728 * Install proper ops for Scalable MCA enabled processors
1730 if (mce_flags.smca) {
1731 msr_ops.ctl = smca_ctl_reg;
1732 msr_ops.status = smca_status_reg;
1733 msr_ops.addr = smca_addr_reg;
1734 msr_ops.misc = smca_misc_reg;
1736 mce_amd_feature_init(c);
1746 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1748 switch (c->x86_vendor) {
1749 case X86_VENDOR_INTEL:
1750 mce_intel_feature_clear(c);
1757 static void mce_start_timer(unsigned int cpu, struct timer_list *t)
1759 unsigned long iv = check_interval * HZ;
1761 if (mca_cfg.ignore_ce || !iv)
1764 per_cpu(mce_next_interval, cpu) = iv;
1766 t->expires = round_jiffies(jiffies + iv);
1767 add_timer_on(t, cpu);
1770 static void __mcheck_cpu_setup_timer(void)
1772 struct timer_list *t = this_cpu_ptr(&mce_timer);
1773 unsigned int cpu = smp_processor_id();
1775 setup_pinned_timer(t, mce_timer_fn, cpu);
1778 static void __mcheck_cpu_init_timer(void)
1780 struct timer_list *t = this_cpu_ptr(&mce_timer);
1781 unsigned int cpu = smp_processor_id();
1783 setup_pinned_timer(t, mce_timer_fn, cpu);
1784 mce_start_timer(cpu, t);
1787 /* Handle unconfigured int18 (should never happen) */
1788 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1790 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1791 smp_processor_id());
1794 /* Call the installed machine check handler for this CPU setup. */
1795 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1796 unexpected_machine_check;
1799 * Called for each booted CPU to set up machine checks.
1800 * Must be called with preempt off:
1802 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1804 if (mca_cfg.disabled)
1807 if (__mcheck_cpu_ancient_init(c))
1810 if (!mce_available(c))
1813 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1814 mca_cfg.disabled = true;
1818 if (mce_gen_pool_init()) {
1819 mca_cfg.disabled = true;
1820 pr_emerg("Couldn't allocate MCE records pool!\n");
1824 machine_check_vector = do_machine_check;
1826 __mcheck_cpu_init_generic();
1827 __mcheck_cpu_init_vendor(c);
1828 __mcheck_cpu_init_clear_banks();
1829 __mcheck_cpu_setup_timer();
1833 * Called for each booted CPU to clear some machine checks opt-ins
1835 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1837 if (mca_cfg.disabled)
1840 if (!mce_available(c))
1844 * Possibly to clear general settings generic to x86
1845 * __mcheck_cpu_clear_generic(c);
1847 __mcheck_cpu_clear_vendor(c);
1852 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1855 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1856 static int mce_chrdev_open_count; /* #times opened */
1857 static int mce_chrdev_open_exclu; /* already open exclusive? */
1859 static int mce_chrdev_open(struct inode *inode, struct file *file)
1861 spin_lock(&mce_chrdev_state_lock);
1863 if (mce_chrdev_open_exclu ||
1864 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1865 spin_unlock(&mce_chrdev_state_lock);
1870 if (file->f_flags & O_EXCL)
1871 mce_chrdev_open_exclu = 1;
1872 mce_chrdev_open_count++;
1874 spin_unlock(&mce_chrdev_state_lock);
1876 return nonseekable_open(inode, file);
1879 static int mce_chrdev_release(struct inode *inode, struct file *file)
1881 spin_lock(&mce_chrdev_state_lock);
1883 mce_chrdev_open_count--;
1884 mce_chrdev_open_exclu = 0;
1886 spin_unlock(&mce_chrdev_state_lock);
1891 static void collect_tscs(void *data)
1893 unsigned long *cpu_tsc = (unsigned long *)data;
1895 cpu_tsc[smp_processor_id()] = rdtsc();
1898 static int mce_apei_read_done;
1900 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1901 static int __mce_read_apei(char __user **ubuf, size_t usize)
1907 if (usize < sizeof(struct mce))
1910 rc = apei_read_mce(&m, &record_id);
1911 /* Error or no more MCE record */
1913 mce_apei_read_done = 1;
1915 * When ERST is disabled, mce_chrdev_read() should return
1916 * "no record" instead of "no device."
1923 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1926 * In fact, we should have cleared the record after that has
1927 * been flushed to the disk or sent to network in
1928 * /sbin/mcelog, but we have no interface to support that now,
1929 * so just clear it to avoid duplication.
1931 rc = apei_clear_mce(record_id);
1933 mce_apei_read_done = 1;
1936 *ubuf += sizeof(struct mce);
1941 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1942 size_t usize, loff_t *off)
1944 char __user *buf = ubuf;
1945 unsigned long *cpu_tsc;
1946 unsigned prev, next;
1949 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1953 mutex_lock(&mce_chrdev_read_mutex);
1955 if (!mce_apei_read_done) {
1956 err = __mce_read_apei(&buf, usize);
1957 if (err || buf != ubuf)
1961 next = mce_log_get_idx_check(mcelog.next);
1963 /* Only supports full reads right now */
1965 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1971 for (i = prev; i < next; i++) {
1972 unsigned long start = jiffies;
1973 struct mce *m = &mcelog.entry[i];
1975 while (!m->finished) {
1976 if (time_after_eq(jiffies, start + 2)) {
1977 memset(m, 0, sizeof(*m));
1983 err |= copy_to_user(buf, m, sizeof(*m));
1989 memset(mcelog.entry + prev, 0,
1990 (next - prev) * sizeof(struct mce));
1992 next = cmpxchg(&mcelog.next, prev, 0);
1993 } while (next != prev);
1995 synchronize_sched();
1998 * Collect entries that were still getting written before the
2001 on_each_cpu(collect_tscs, cpu_tsc, 1);
2003 for (i = next; i < MCE_LOG_LEN; i++) {
2004 struct mce *m = &mcelog.entry[i];
2006 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
2007 err |= copy_to_user(buf, m, sizeof(*m));
2010 memset(m, 0, sizeof(*m));
2018 mutex_unlock(&mce_chrdev_read_mutex);
2021 return err ? err : buf - ubuf;
2024 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
2026 poll_wait(file, &mce_chrdev_wait, wait);
2027 if (READ_ONCE(mcelog.next))
2028 return POLLIN | POLLRDNORM;
2029 if (!mce_apei_read_done && apei_check_mce())
2030 return POLLIN | POLLRDNORM;
2034 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
2037 int __user *p = (int __user *)arg;
2039 if (!capable(CAP_SYS_ADMIN))
2043 case MCE_GET_RECORD_LEN:
2044 return put_user(sizeof(struct mce), p);
2045 case MCE_GET_LOG_LEN:
2046 return put_user(MCE_LOG_LEN, p);
2047 case MCE_GETCLEAR_FLAGS: {
2051 flags = mcelog.flags;
2052 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
2054 return put_user(flags, p);
2061 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
2062 size_t usize, loff_t *off);
2064 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
2065 const char __user *ubuf,
2066 size_t usize, loff_t *off))
2070 EXPORT_SYMBOL_GPL(register_mce_write_callback);
2072 static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
2073 size_t usize, loff_t *off)
2076 return mce_write(filp, ubuf, usize, off);
2081 static const struct file_operations mce_chrdev_ops = {
2082 .open = mce_chrdev_open,
2083 .release = mce_chrdev_release,
2084 .read = mce_chrdev_read,
2085 .write = mce_chrdev_write,
2086 .poll = mce_chrdev_poll,
2087 .unlocked_ioctl = mce_chrdev_ioctl,
2088 .llseek = no_llseek,
2091 static struct miscdevice mce_chrdev_device = {
2097 static void __mce_disable_bank(void *arg)
2099 int bank = *((int *)arg);
2100 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2101 cmci_disable_bank(bank);
2104 void mce_disable_bank(int bank)
2106 if (bank >= mca_cfg.banks) {
2108 "Ignoring request to disable invalid MCA bank %d.\n",
2112 set_bit(bank, mce_banks_ce_disabled);
2113 on_each_cpu(__mce_disable_bank, &bank, 1);
2117 * mce=off Disables machine check
2118 * mce=no_cmci Disables CMCI
2119 * mce=no_lmce Disables LMCE
2120 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2121 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2122 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2123 * monarchtimeout is how long to wait for other CPUs on machine
2124 * check, or 0 to not wait
2125 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
2126 * mce=nobootlog Don't log MCEs from before booting.
2127 * mce=bios_cmci_threshold Don't program the CMCI threshold
2128 * mce=recovery force enable memcpy_mcsafe()
2130 static int __init mcheck_enable(char *str)
2132 struct mca_config *cfg = &mca_cfg;
2140 if (!strcmp(str, "off"))
2141 cfg->disabled = true;
2142 else if (!strcmp(str, "no_cmci"))
2143 cfg->cmci_disabled = true;
2144 else if (!strcmp(str, "no_lmce"))
2145 cfg->lmce_disabled = true;
2146 else if (!strcmp(str, "dont_log_ce"))
2147 cfg->dont_log_ce = true;
2148 else if (!strcmp(str, "ignore_ce"))
2149 cfg->ignore_ce = true;
2150 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2151 cfg->bootlog = (str[0] == 'b');
2152 else if (!strcmp(str, "bios_cmci_threshold"))
2153 cfg->bios_cmci_threshold = true;
2154 else if (!strcmp(str, "recovery"))
2155 cfg->recovery = true;
2156 else if (isdigit(str[0])) {
2157 if (get_option(&str, &cfg->tolerant) == 2)
2158 get_option(&str, &(cfg->monarch_timeout));
2160 pr_info("mce argument %s ignored. Please use /sys\n", str);
2165 __setup("mce", mcheck_enable);
2167 int __init mcheck_init(void)
2169 mcheck_intel_therm_init();
2170 mce_register_decode_chain(&mce_srao_nb);
2171 mce_register_decode_chain(&mce_default_nb);
2172 mcheck_vendor_init_severity();
2174 INIT_WORK(&mce_work, mce_process_work);
2175 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2181 * mce_syscore: PM support
2185 * Disable machine checks on suspend and shutdown. We can't really handle
2188 static void mce_disable_error_reporting(void)
2192 for (i = 0; i < mca_cfg.banks; i++) {
2193 struct mce_bank *b = &mce_banks[i];
2196 wrmsrl(msr_ops.ctl(i), 0);
2201 static void vendor_disable_error_reporting(void)
2204 * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
2205 * Disabling them for just a single offlined CPU is bad, since it will
2206 * inhibit reporting for all shared resources on the socket like the
2207 * last level cache (LLC), the integrated memory controller (iMC), etc.
2209 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2212 mce_disable_error_reporting();
2215 static int mce_syscore_suspend(void)
2217 vendor_disable_error_reporting();
2221 static void mce_syscore_shutdown(void)
2223 vendor_disable_error_reporting();
2227 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2228 * Only one CPU is active at this time, the others get re-added later using
2231 static void mce_syscore_resume(void)
2233 __mcheck_cpu_init_generic();
2234 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2235 __mcheck_cpu_init_clear_banks();
2238 static struct syscore_ops mce_syscore_ops = {
2239 .suspend = mce_syscore_suspend,
2240 .shutdown = mce_syscore_shutdown,
2241 .resume = mce_syscore_resume,
2245 * mce_device: Sysfs support
2248 static void mce_cpu_restart(void *data)
2250 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2252 __mcheck_cpu_init_generic();
2253 __mcheck_cpu_init_clear_banks();
2254 __mcheck_cpu_init_timer();
2257 /* Reinit MCEs after user configuration changes */
2258 static void mce_restart(void)
2260 mce_timer_delete_all();
2261 on_each_cpu(mce_cpu_restart, NULL, 1);
2264 /* Toggle features for corrected errors */
2265 static void mce_disable_cmci(void *data)
2267 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2272 static void mce_enable_ce(void *all)
2274 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2279 __mcheck_cpu_init_timer();
2282 static struct bus_type mce_subsys = {
2283 .name = "machinecheck",
2284 .dev_name = "machinecheck",
2287 DEFINE_PER_CPU(struct device *, mce_device);
2289 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2291 return container_of(attr, struct mce_bank, attr);
2294 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2297 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2300 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2301 const char *buf, size_t size)
2305 if (kstrtou64(buf, 0, &new) < 0)
2308 attr_to_bank(attr)->ctl = new;
2315 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2317 strcpy(buf, mce_helper);
2319 return strlen(mce_helper) + 1;
2322 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2323 const char *buf, size_t siz)
2327 strncpy(mce_helper, buf, sizeof(mce_helper));
2328 mce_helper[sizeof(mce_helper)-1] = 0;
2329 p = strchr(mce_helper, '\n');
2334 return strlen(mce_helper) + !!p;
2337 static ssize_t set_ignore_ce(struct device *s,
2338 struct device_attribute *attr,
2339 const char *buf, size_t size)
2343 if (kstrtou64(buf, 0, &new) < 0)
2346 if (mca_cfg.ignore_ce ^ !!new) {
2348 /* disable ce features */
2349 mce_timer_delete_all();
2350 on_each_cpu(mce_disable_cmci, NULL, 1);
2351 mca_cfg.ignore_ce = true;
2353 /* enable ce features */
2354 mca_cfg.ignore_ce = false;
2355 on_each_cpu(mce_enable_ce, (void *)1, 1);
2361 static ssize_t set_cmci_disabled(struct device *s,
2362 struct device_attribute *attr,
2363 const char *buf, size_t size)
2367 if (kstrtou64(buf, 0, &new) < 0)
2370 if (mca_cfg.cmci_disabled ^ !!new) {
2373 on_each_cpu(mce_disable_cmci, NULL, 1);
2374 mca_cfg.cmci_disabled = true;
2377 mca_cfg.cmci_disabled = false;
2378 on_each_cpu(mce_enable_ce, NULL, 1);
2384 static ssize_t store_int_with_restart(struct device *s,
2385 struct device_attribute *attr,
2386 const char *buf, size_t size)
2388 ssize_t ret = device_store_int(s, attr, buf, size);
2393 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2394 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2395 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2396 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2398 static struct dev_ext_attribute dev_attr_check_interval = {
2399 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2403 static struct dev_ext_attribute dev_attr_ignore_ce = {
2404 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2408 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2409 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2410 &mca_cfg.cmci_disabled
2413 static struct device_attribute *mce_device_attrs[] = {
2414 &dev_attr_tolerant.attr,
2415 &dev_attr_check_interval.attr,
2417 &dev_attr_monarch_timeout.attr,
2418 &dev_attr_dont_log_ce.attr,
2419 &dev_attr_ignore_ce.attr,
2420 &dev_attr_cmci_disabled.attr,
2424 static cpumask_var_t mce_device_initialized;
2426 static void mce_device_release(struct device *dev)
2431 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2432 static int mce_device_create(unsigned int cpu)
2438 if (!mce_available(&boot_cpu_data))
2441 dev = per_cpu(mce_device, cpu);
2445 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2449 dev->bus = &mce_subsys;
2450 dev->release = &mce_device_release;
2452 err = device_register(dev);
2458 for (i = 0; mce_device_attrs[i]; i++) {
2459 err = device_create_file(dev, mce_device_attrs[i]);
2463 for (j = 0; j < mca_cfg.banks; j++) {
2464 err = device_create_file(dev, &mce_banks[j].attr);
2468 cpumask_set_cpu(cpu, mce_device_initialized);
2469 per_cpu(mce_device, cpu) = dev;
2474 device_remove_file(dev, &mce_banks[j].attr);
2477 device_remove_file(dev, mce_device_attrs[i]);
2479 device_unregister(dev);
2484 static void mce_device_remove(unsigned int cpu)
2486 struct device *dev = per_cpu(mce_device, cpu);
2489 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2492 for (i = 0; mce_device_attrs[i]; i++)
2493 device_remove_file(dev, mce_device_attrs[i]);
2495 for (i = 0; i < mca_cfg.banks; i++)
2496 device_remove_file(dev, &mce_banks[i].attr);
2498 device_unregister(dev);
2499 cpumask_clear_cpu(cpu, mce_device_initialized);
2500 per_cpu(mce_device, cpu) = NULL;
2503 /* Make sure there are no machine checks on offlined CPUs. */
2504 static void mce_disable_cpu(void)
2506 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2509 if (!cpuhp_tasks_frozen)
2512 vendor_disable_error_reporting();
2515 static void mce_reenable_cpu(void)
2519 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2522 if (!cpuhp_tasks_frozen)
2524 for (i = 0; i < mca_cfg.banks; i++) {
2525 struct mce_bank *b = &mce_banks[i];
2528 wrmsrl(msr_ops.ctl(i), b->ctl);
2532 static int mce_cpu_dead(unsigned int cpu)
2534 mce_intel_hcpu_update(cpu);
2536 /* intentionally ignoring frozen here */
2537 if (!cpuhp_tasks_frozen)
2542 static int mce_cpu_online(unsigned int cpu)
2544 struct timer_list *t = &per_cpu(mce_timer, cpu);
2547 mce_device_create(cpu);
2549 ret = mce_threshold_create_device(cpu);
2551 mce_device_remove(cpu);
2555 mce_start_timer(cpu, t);
2559 static int mce_cpu_pre_down(unsigned int cpu)
2561 struct timer_list *t = &per_cpu(mce_timer, cpu);
2565 mce_threshold_remove_device(cpu);
2566 mce_device_remove(cpu);
2570 static __init void mce_init_banks(void)
2574 for (i = 0; i < mca_cfg.banks; i++) {
2575 struct mce_bank *b = &mce_banks[i];
2576 struct device_attribute *a = &b->attr;
2578 sysfs_attr_init(&a->attr);
2579 a->attr.name = b->attrname;
2580 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2582 a->attr.mode = 0644;
2583 a->show = show_bank;
2584 a->store = set_bank;
2588 static __init int mcheck_init_device(void)
2590 enum cpuhp_state hp_online;
2593 if (!mce_available(&boot_cpu_data)) {
2598 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2605 err = subsys_system_register(&mce_subsys, NULL);
2609 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2614 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2615 mce_cpu_online, mce_cpu_pre_down);
2617 goto err_out_online;
2620 register_syscore_ops(&mce_syscore_ops);
2622 /* register character device /dev/mcelog */
2623 err = misc_register(&mce_chrdev_device);
2630 unregister_syscore_ops(&mce_syscore_ops);
2631 cpuhp_remove_state(hp_online);
2634 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2637 free_cpumask_var(mce_device_initialized);
2640 pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err);
2644 device_initcall_sync(mcheck_init_device);
2647 * Old style boot options parsing. Only for compatibility.
2649 static int __init mcheck_disable(char *str)
2651 mca_cfg.disabled = true;
2654 __setup("nomce", mcheck_disable);
2656 #ifdef CONFIG_DEBUG_FS
2657 struct dentry *mce_get_debugfs_dir(void)
2659 static struct dentry *dmce;
2662 dmce = debugfs_create_dir("mce", NULL);
2667 static void mce_reset(void)
2670 atomic_set(&mce_fake_panicked, 0);
2671 atomic_set(&mce_executing, 0);
2672 atomic_set(&mce_callin, 0);
2673 atomic_set(&global_nwo, 0);
2676 static int fake_panic_get(void *data, u64 *val)
2682 static int fake_panic_set(void *data, u64 val)
2689 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2690 fake_panic_set, "%llu\n");
2692 static int __init mcheck_debugfs_init(void)
2694 struct dentry *dmce, *ffake_panic;
2696 dmce = mce_get_debugfs_dir();
2699 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2707 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2710 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2711 EXPORT_SYMBOL_GPL(mcsafe_key);
2713 static int __init mcheck_late_init(void)
2715 if (mca_cfg.recovery)
2716 static_branch_inc(&mcsafe_key);
2718 mcheck_debugfs_init();
2721 * Flush out everything that has been logged during early boot, now that
2722 * everything has been initialized (workqueues, decoders, ...).
2724 mce_schedule_work();
2728 late_initcall(mcheck_late_init);