arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *  Maintained by: Borislav Petkov <bp@alien8.de>
   9  *
  10  *  All MC4_MISCi registers are shared between cores on a node.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/notifier.h>
  14 #include <linux/kobject.h>
  15 #include <linux/percpu.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/cpu.h>
  22 #include <linux/smp.h>
  23 #include <linux/string.h>
  24
  25 #include <asm/amd_nb.h>
  26 #include <asm/apic.h>
  27 #include <asm/mce.h>
  28 #include <asm/msr.h>
  29 #include <asm/trace/irq_vectors.h>
  30
  31 #include "mce-internal.h"
  32
  33 #define NR_BLOCKS         5
  34 #define THRESHOLD_MAX     0xFFF
  35 #define INT_TYPE_APIC     0x00020000
  36 #define MASK_VALID_HI     0x80000000
  37 #define MASK_CNTP_HI      0x40000000
  38 #define MASK_LOCKED_HI    0x20000000
  39 #define MASK_LVTOFF_HI    0x00F00000
  40 #define MASK_COUNT_EN_HI  0x00080000
  41 #define MASK_INT_TYPE_HI  0x00060000
  42 #define MASK_OVERFLOW_HI  0x00010000
  43 #define MASK_ERR_COUNT_HI 0x00000FFF
  44 #define MASK_BLKPTR_LO    0xFF000000
  45 #define MCG_XBLK_ADDR     0xC0000400
  46
  47 /* Deferred error settings */
  48 #define MSR_CU_DEF_ERR          0xC0000410
  49 #define MASK_DEF_LVTOFF         0x000000F0
  50 #define MASK_DEF_INT_TYPE       0x00000006
  51 #define DEF_LVT_OFF             0x2
  52 #define DEF_INT_TYPE_APIC       0x2
  53
  54 /* Scalable MCA: */
  55
  56 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  57 #define SMCA_THR_LVT_OFF        0xF000
  58
  59 static bool thresholding_en;
  60
  61 static const char * const th_names[] = {
  62         "load_store",
  63         "insn_fetch",
  64         "combined_unit",
  65         "decode_unit",
  66         "northbridge",
  67         "execution_unit",
  68 };
  69
  70 static const char * const smca_umc_block_names[] = {
  71         "dram_ecc",
  72         "misc_umc"
  73 };
  74
  75 struct smca_bank_name {
  76         const char *name;       /* Short name for sysfs */
  77         const char *long_name;  /* Long name for pretty-printing */
  78 };
  79
  80 static struct smca_bank_name smca_names[] = {
  81         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
  82         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
  83         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
  84         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
  85         [SMCA_RESERVED] = { "reserved",         "Reserved" },
  86         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
  87         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
  88         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
  89         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
  90         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
  91         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
  92         [SMCA_PB]       = { "param_block",      "Parameter Block" },
  93         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
  94         [SMCA_SMU]      = { "smu",              "System Management Unit" },
  95 };
  96
  97 const char *smca_get_name(enum smca_bank_types t)
  98 {
  99         if (t >= N_SMCA_BANK_TYPES)
 100                 return NULL;
 101
 102         return smca_names[t].name;
 103 }
 104
 105 const char *smca_get_long_name(enum smca_bank_types t)
 106 {
 107         if (t >= N_SMCA_BANK_TYPES)
 108                 return NULL;
 109
 110         return smca_names[t].long_name;
 111 }
 112 EXPORT_SYMBOL_GPL(smca_get_long_name);
 113
 114 static enum smca_bank_types smca_get_bank_type(unsigned int bank)
 115 {
 116         struct smca_bank *b;
 117
 118         if (bank >= MAX_NR_BANKS)
 119                 return N_SMCA_BANK_TYPES;
 120
 121         b = &smca_banks[bank];
 122         if (!b->hwid)
 123                 return N_SMCA_BANK_TYPES;
 124
 125         return b->hwid->bank_type;
 126 }
 127
 128 static struct smca_hwid smca_hwid_mcatypes[] = {
 129         /* { bank_type, hwid_mcatype, xec_bitmap } */
 130
 131         /* Reserved type */
 132         { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
 133
 134         /* ZN Core (HWID=0xB0) MCA types */
 135         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
 136         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
 137         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
 138         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
 139         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 140         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
 141         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
 142         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 143
 144         /* Data Fabric MCA types */
 145         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
 146         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
 147
 148         /* Unified Memory Controller MCA type */
 149         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
 150
 151         /* Parameter Block MCA type */
 152         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
 153
 154         /* Platform Security Processor MCA type */
 155         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
 156
 157         /* System Management Unit MCA type */
 158         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
 159 };
 160
 161 struct smca_bank smca_banks[MAX_NR_BANKS];
 162 EXPORT_SYMBOL_GPL(smca_banks);
 163
 164 /*
 165  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 166  * So to define a unique name for each bank, we use a temp c-string to append
 167  * the MCA_IPID[InstanceId] to type's name in get_name().
 168  *
 169  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 170  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 171  */
 172 #define MAX_MCATYPE_NAME_LEN    30
 173 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 174
 175 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 176 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
 177
 178 static void amd_threshold_interrupt(void);
 179 static void amd_deferred_error_interrupt(void);
 180
 181 static void default_deferred_error_interrupt(void)
 182 {
 183         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 184 }
 185 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 186
 187 static void smca_configure(unsigned int bank, unsigned int cpu)
 188 {
 189         unsigned int i, hwid_mcatype;
 190         struct smca_hwid *s_hwid;
 191         u32 high, low;
 192         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 193
 194         /* Set appropriate bits in MCA_CONFIG */
 195         if (!rdmsr_safe(smca_config, &low, &high)) {
 196                 /*
 197                  * OS is required to set the MCAX bit to acknowledge that it is
 198                  * now using the new MSR ranges and new registers under each
 199                  * bank. It also means that the OS will configure deferred
 200                  * errors in the new MCx_CONFIG register. If the bit is not set,
 201                  * uncorrectable errors will cause a system panic.
 202                  *
 203                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 204                  */
 205                 high |= BIT(0);
 206
 207                 /*
 208                  * SMCA sets the Deferred Error Interrupt type per bank.
 209                  *
 210                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 211                  * if the DeferredIntType bit field is available.
 212                  *
 213                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 214                  * high portion of the MSR). OS should set this to 0x1 to enable
 215                  * APIC based interrupt. First, check that no interrupt has been
 216                  * set.
 217                  */
 218                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
 219                         high |= BIT(5);
 220
 221                 wrmsr(smca_config, low, high);
 222         }
 223
 224         /* Return early if this bank was already initialized. */
 225         if (smca_banks[bank].hwid)
 226                 return;
 227
 228         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
 229                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 230                 return;
 231         }
 232
 233         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 234                                     (high & MCI_IPID_MCATYPE) >> 16);
 235
 236         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 237                 s_hwid = &smca_hwid_mcatypes[i];
 238                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 239                         smca_banks[bank].hwid = s_hwid;
 240                         smca_banks[bank].id = low;
 241                         smca_banks[bank].sysfs_id = s_hwid->count++;
 242                         break;
 243                 }
 244         }
 245 }
 246
 247 struct thresh_restart {
 248         struct threshold_block  *b;
 249         int                     reset;
 250         int                     set_lvt_off;
 251         int                     lvt_off;
 252         u16                     old_limit;
 253 };
 254
 255 static inline bool is_shared_bank(int bank)
 256 {
 257         /*
 258          * Scalable MCA provides for only one core to have access to the MSRs of
 259          * a shared bank.
 260          */
 261         if (mce_flags.smca)
 262                 return false;
 263
 264         /* Bank 4 is for northbridge reporting and is thus shared */
 265         return (bank == 4);
 266 }
 267
 268 static const char *bank4_names(const struct threshold_block *b)
 269 {
 270         switch (b->address) {
 271         /* MSR4_MISC0 */
 272         case 0x00000413:
 273                 return "dram";
 274
 275         case 0xc0000408:
 276                 return "ht_links";
 277
 278         case 0xc0000409:
 279                 return "l3_cache";
 280
 281         default:
 282                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 283                 return "";
 284         }
 285 };
 286
 287
 288 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 289 {
 290         /*
 291          * bank 4 supports APIC LVT interrupts implicitly since forever.
 292          */
 293         if (bank == 4)
 294                 return true;
 295
 296         /*
 297          * IntP: interrupt present; if this bit is set, the thresholding
 298          * bank can generate APIC LVT interrupts
 299          */
 300         return msr_high_bits & BIT(28);
 301 }
 302
 303 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 304 {
 305         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 306
 307         if (apic < 0) {
 308                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 309                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 310                        b->bank, b->block, b->address, hi, lo);
 311                 return 0;
 312         }
 313
 314         if (apic != msr) {
 315                 /*
 316                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 317                  * the BIOS provides the value. The original field where LVT offset
 318                  * was set is reserved. Return early here:
 319                  */
 320                 if (mce_flags.smca)
 321                         return 0;
 322
 323                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 324                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 325                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 326                 return 0;
 327         }
 328
 329         return 1;
 330 };
 331
 332 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 333 static void threshold_restart_bank(void *_tr)
 334 {
 335         struct thresh_restart *tr = _tr;
 336         u32 hi, lo;
 337
 338         rdmsr(tr->b->address, lo, hi);
 339
 340         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 341                 tr->reset = 1;  /* limit cannot be lower than err count */
 342
 343         if (tr->reset) {                /* reset err count and overflow bit */
 344                 hi =
 345                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 346                     (THRESHOLD_MAX - tr->b->threshold_limit);
 347         } else if (tr->old_limit) {     /* change limit w/o reset */
 348                 int new_count = (hi & THRESHOLD_MAX) +
 349                     (tr->old_limit - tr->b->threshold_limit);
 350
 351                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 352                     (new_count & THRESHOLD_MAX);
 353         }
 354
 355         /* clear IntType */
 356         hi &= ~MASK_INT_TYPE_HI;
 357
 358         if (!tr->b->interrupt_capable)
 359                 goto done;
 360
 361         if (tr->set_lvt_off) {
 362                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 363                         /* set new lvt offset */
 364                         hi &= ~MASK_LVTOFF_HI;
 365                         hi |= tr->lvt_off << 20;
 366                 }
 367         }
 368
 369         if (tr->b->interrupt_enable)
 370                 hi |= INT_TYPE_APIC;
 371
 372  done:
 373
 374         hi |= MASK_COUNT_EN_HI;
 375         wrmsr(tr->b->address, lo, hi);
 376 }
 377
 378 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 379 {
 380         struct thresh_restart tr = {
 381                 .b                      = b,
 382                 .set_lvt_off            = 1,
 383                 .lvt_off                = offset,
 384         };
 385
 386         b->threshold_limit              = THRESHOLD_MAX;
 387         threshold_restart_bank(&tr);
 388 };
 389
 390 static int setup_APIC_mce_threshold(int reserved, int new)
 391 {
 392         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 393                                               APIC_EILVT_MSG_FIX, 0))
 394                 return new;
 395
 396         return reserved;
 397 }
 398
 399 static int setup_APIC_deferred_error(int reserved, int new)
 400 {
 401         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 402                                               APIC_EILVT_MSG_FIX, 0))
 403                 return new;
 404
 405         return reserved;
 406 }
 407
 408 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 409 {
 410         u32 low = 0, high = 0;
 411         int def_offset = -1, def_new;
 412
 413         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 414                 return;
 415
 416         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 417         if (!(low & MASK_DEF_LVTOFF)) {
 418                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 419                 def_new = DEF_LVT_OFF;
 420                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 421         }
 422
 423         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 424         if ((def_offset == def_new) &&
 425             (deferred_error_int_vector != amd_deferred_error_interrupt))
 426                 deferred_error_int_vector = amd_deferred_error_interrupt;
 427
 428         if (!mce_flags.smca)
 429                 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 430
 431         wrmsr(MSR_CU_DEF_ERR, low, high);
 432 }
 433
 434 static u32 smca_get_block_address(unsigned int cpu, unsigned int bank,
 435                                   unsigned int block)
 436 {
 437         u32 low, high;
 438         u32 addr = 0;
 439
 440         if (smca_get_bank_type(bank) == SMCA_RESERVED)
 441                 return addr;
 442
 443         if (!block)
 444                 return MSR_AMD64_SMCA_MCx_MISC(bank);
 445
 446         /*
 447          * For SMCA enabled processors, BLKPTR field of the first MISC register
 448          * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
 449          */
 450         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 451                 return addr;
 452
 453         if (!(low & MCI_CONFIG_MCAX))
 454                 return addr;
 455
 456         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
 457             (low & MASK_BLKPTR_LO))
 458                 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 459
 460         return addr;
 461 }
 462
 463 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
 464                              unsigned int bank, unsigned int block)
 465 {
 466         u32 addr = 0, offset = 0;
 467
 468         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
 469                 return addr;
 470
 471         /* Get address from already initialized block. */
 472         if (per_cpu(threshold_banks, cpu)) {
 473                 struct threshold_bank *bankp = per_cpu(threshold_banks, cpu)[bank];
 474
 475                 if (bankp && bankp->blocks) {
 476                         struct threshold_block *blockp = &bankp->blocks[block];
 477
 478                         if (blockp)
 479                                 return blockp->address;
 480                 }
 481         }
 482
 483         if (mce_flags.smca)
 484                 return smca_get_block_address(cpu, bank, block);
 485
 486         /* Fall back to method we used for older processors: */
 487         switch (block) {
 488         case 0:
 489                 addr = msr_ops.misc(bank);
 490                 break;
 491         case 1:
 492                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 493                 if (offset)
 494                         addr = MCG_XBLK_ADDR + offset;
 495                 break;
 496         default:
 497                 addr = ++current_addr;
 498         }
 499         return addr;
 500 }
 501
 502 static int
 503 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 504                         int offset, u32 misc_high)
 505 {
 506         unsigned int cpu = smp_processor_id();
 507         u32 smca_low, smca_high;
 508         struct threshold_block b;
 509         int new;
 510
 511         if (!block)
 512                 per_cpu(bank_map, cpu) |= (1 << bank);
 513
 514         memset(&b, 0, sizeof(b));
 515         b.cpu                   = cpu;
 516         b.bank                  = bank;
 517         b.block                 = block;
 518         b.address               = addr;
 519         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 520
 521         if (!b.interrupt_capable)
 522                 goto done;
 523
 524         b.interrupt_enable = 1;
 525
 526         if (!mce_flags.smca) {
 527                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 528                 goto set_offset;
 529         }
 530
 531         /* Gather LVT offset for thresholding: */
 532         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 533                 goto out;
 534
 535         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 536
 537 set_offset:
 538         offset = setup_APIC_mce_threshold(offset, new);
 539
 540         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
 541                 mce_threshold_vector = amd_threshold_interrupt;
 542
 543 done:
 544         mce_threshold_block_init(&b, offset);
 545
 546 out:
 547         return offset;
 548 }
 549
 550 /* cpu init entry point, called from mce.c with preempt off */
 551 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 552 {
 553         u32 low = 0, high = 0, address = 0;
 554         unsigned int bank, block, cpu = smp_processor_id();
 555         int offset = -1;
 556
 557         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 558                 if (mce_flags.smca)
 559                         smca_configure(bank, cpu);
 560
 561                 for (block = 0; block < NR_BLOCKS; ++block) {
 562                         address = get_block_address(cpu, address, low, high, bank, block);
 563                         if (!address)
 564                                 break;
 565
 566                         if (rdmsr_safe(address, &low, &high))
 567                                 break;
 568
 569                         if (!(high & MASK_VALID_HI))
 570                                 continue;
 571
 572                         if (!(high & MASK_CNTP_HI)  ||
 573                              (high & MASK_LOCKED_HI))
 574                                 continue;
 575
 576                         offset = prepare_threshold_block(bank, block, address, offset, high);
 577                 }
 578         }
 579
 580         if (mce_flags.succor)
 581                 deferred_error_interrupt_enable(c);
 582 }
 583
 584 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 585 {
 586         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
 587         /* We start from the normalized address */
 588         u64 ret_addr = norm_addr;
 589
 590         u32 tmp;
 591
 592         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
 593         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 594         u8 intlv_addr_sel, intlv_addr_bit;
 595         u8 num_intlv_bits, hashed_bit;
 596         u8 lgcy_mmio_hole_en, base = 0;
 597         u8 cs_mask, cs_id = 0;
 598         bool hash_enabled = false;
 599
 600         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
 601         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 602                 goto out_err;
 603
 604         /* Remove HiAddrOffset from normalized address, if enabled: */
 605         if (tmp & BIT(0)) {
 606                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 607
 608                 if (norm_addr >= hi_addr_offset) {
 609                         ret_addr -= hi_addr_offset;
 610                         base = 1;
 611                 }
 612         }
 613
 614         /* Read D18F0x110 (DramBaseAddress). */
 615         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
 616                 goto out_err;
 617
 618         /* Check if address range is valid. */
 619         if (!(tmp & BIT(0))) {
 620                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
 621                         __func__, tmp);
 622                 goto out_err;
 623         }
 624
 625         lgcy_mmio_hole_en = tmp & BIT(1);
 626         intlv_num_chan    = (tmp >> 4) & 0xF;
 627         intlv_addr_sel    = (tmp >> 8) & 0x7;
 628         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
 629
 630         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
 631         if (intlv_addr_sel > 3) {
 632                 pr_err("%s: Invalid interleave address select %d.\n",
 633                         __func__, intlv_addr_sel);
 634                 goto out_err;
 635         }
 636
 637         /* Read D18F0x114 (DramLimitAddress). */
 638         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 639                 goto out_err;
 640
 641         intlv_num_sockets = (tmp >> 8) & 0x1;
 642         intlv_num_dies    = (tmp >> 10) & 0x3;
 643         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 644
 645         intlv_addr_bit = intlv_addr_sel + 8;
 646
 647         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
 648         switch (intlv_num_chan) {
 649         case 0: intlv_num_chan = 0; break;
 650         case 1: intlv_num_chan = 1; break;
 651         case 3: intlv_num_chan = 2; break;
 652         case 5: intlv_num_chan = 3; break;
 653         case 7: intlv_num_chan = 4; break;
 654
 655         case 8: intlv_num_chan = 1;
 656                 hash_enabled = true;
 657                 break;
 658         default:
 659                 pr_err("%s: Invalid number of interleaved channels %d.\n",
 660                         __func__, intlv_num_chan);
 661                 goto out_err;
 662         }
 663
 664         num_intlv_bits = intlv_num_chan;
 665
 666         if (intlv_num_dies > 2) {
 667                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
 668                         __func__, intlv_num_dies);
 669                 goto out_err;
 670         }
 671
 672         num_intlv_bits += intlv_num_dies;
 673
 674         /* Add a bit if sockets are interleaved. */
 675         num_intlv_bits += intlv_num_sockets;
 676
 677         /* Assert num_intlv_bits <= 4 */
 678         if (num_intlv_bits > 4) {
 679                 pr_err("%s: Invalid interleave bits %d.\n",
 680                         __func__, num_intlv_bits);
 681                 goto out_err;
 682         }
 683
 684         if (num_intlv_bits > 0) {
 685                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
 686                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
 687
 688                 /*
 689                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
 690                  * This is the fabric id for this coherent slave. Use
 691                  * umc/channel# as instance id of the coherent slave
 692                  * for FICAA.
 693                  */
 694                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 695                         goto out_err;
 696
 697                 cs_fabric_id = (tmp >> 8) & 0xFF;
 698                 die_id_bit   = 0;
 699
 700                 /* If interleaved over more than 1 channel: */
 701                 if (intlv_num_chan) {
 702                         die_id_bit = intlv_num_chan;
 703                         cs_mask    = (1 << die_id_bit) - 1;
 704                         cs_id      = cs_fabric_id & cs_mask;
 705                 }
 706
 707                 sock_id_bit = die_id_bit;
 708
 709                 /* Read D18F1x208 (SystemFabricIdMask). */
 710                 if (intlv_num_dies || intlv_num_sockets)
 711                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
 712                                 goto out_err;
 713
 714                 /* If interleaved over more than 1 die. */
 715                 if (intlv_num_dies) {
 716                         sock_id_bit  = die_id_bit + intlv_num_dies;
 717                         die_id_shift = (tmp >> 24) & 0xF;
 718                         die_id_mask  = (tmp >> 8) & 0xFF;
 719
 720                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 721                 }
 722
 723                 /* If interleaved over more than 1 socket. */
 724                 if (intlv_num_sockets) {
 725                         socket_id_shift = (tmp >> 28) & 0xF;
 726                         socket_id_mask  = (tmp >> 16) & 0xFF;
 727
 728                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 729                 }
 730
 731                 /*
 732                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
 733                  * where III is the ID for this CS, and XXXXXXYYYYY are the
 734                  * address bits from the post-interleaved address.
 735                  * "num_intlv_bits" has been calculated to tell us how many "I"
 736                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
 737                  * there are (where "I" starts).
 738                  */
 739                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
 740                 temp_addr_i = (cs_id << intlv_addr_bit);
 741                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
 742                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
 743         }
 744
 745         /* Add dram base address */
 746         ret_addr += dram_base_addr;
 747
 748         /* If legacy MMIO hole enabled */
 749         if (lgcy_mmio_hole_en) {
 750                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
 751                         goto out_err;
 752
 753                 dram_hole_base = tmp & GENMASK(31, 24);
 754                 if (ret_addr >= dram_hole_base)
 755                         ret_addr += (BIT_ULL(32) - dram_hole_base);
 756         }
 757
 758         if (hash_enabled) {
 759                 /* Save some parentheses and grab ls-bit at the end. */
 760                 hashed_bit =    (ret_addr >> 12) ^
 761                                 (ret_addr >> 18) ^
 762                                 (ret_addr >> 21) ^
 763                                 (ret_addr >> 30) ^
 764                                 cs_id;
 765
 766                 hashed_bit &= BIT(0);
 767
 768                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
 769                         ret_addr ^= BIT(intlv_addr_bit);
 770         }
 771
 772         /* Is calculated system address is above DRAM limit address? */
 773         if (ret_addr > dram_limit_addr)
 774                 goto out_err;
 775
 776         *sys_addr = ret_addr;
 777         return 0;
 778
 779 out_err:
 780         return -EINVAL;
 781 }
 782 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 783
 784 bool amd_mce_is_memory_error(struct mce *m)
 785 {
 786         /* ErrCodeExt[20:16] */
 787         u8 xec = (m->status >> 16) & 0x1f;
 788
 789         if (mce_flags.smca)
 790                 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
 791
 792         return m->bank == 4 && xec == 0x8;
 793 }
 794
 795 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 796 {
 797         struct mce m;
 798
 799         mce_setup(&m);
 800
 801         m.status = status;
 802         m.misc   = misc;
 803         m.bank   = bank;
 804         m.tsc    = rdtsc();
 805
 806         if (m.status & MCI_STATUS_ADDRV) {
 807                 m.addr = addr;
 808
 809                 /*
 810                  * Extract [55:<lsb>] where lsb is the least significant
 811                  * *valid* bit of the address bits.
 812                  */
 813                 if (mce_flags.smca) {
 814                         u8 lsb = (m.addr >> 56) & 0x3f;
 815
 816                         m.addr &= GENMASK_ULL(55, lsb);
 817                 }
 818         }
 819
 820         if (mce_flags.smca) {
 821                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
 822
 823                 if (m.status & MCI_STATUS_SYNDV)
 824                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
 825         }
 826
 827         mce_log(&m);
 828 }
 829
 830 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void)
 831 {
 832         entering_irq();
 833         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 834         inc_irq_stat(irq_deferred_error_count);
 835         deferred_error_int_vector();
 836         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 837         exiting_ack_irq();
 838 }
 839
 840 /*
 841  * Returns true if the logged error is deferred. False, otherwise.
 842  */
 843 static inline bool
 844 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 845 {
 846         u64 status, addr = 0;
 847
 848         rdmsrl(msr_stat, status);
 849         if (!(status & MCI_STATUS_VAL))
 850                 return false;
 851
 852         if (status & MCI_STATUS_ADDRV)
 853                 rdmsrl(msr_addr, addr);
 854
 855         __log_error(bank, status, addr, misc);
 856
 857         wrmsrl(msr_stat, 0);
 858
 859         return status & MCI_STATUS_DEFERRED;
 860 }
 861
 862 /*
 863  * We have three scenarios for checking for Deferred errors:
 864  *
 865  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 866  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 867  *    clear MCA_DESTAT.
 868  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 869  *    log it.
 870  */
 871 static void log_error_deferred(unsigned int bank)
 872 {
 873         bool defrd;
 874
 875         defrd = _log_error_bank(bank, msr_ops.status(bank),
 876                                         msr_ops.addr(bank), 0);
 877
 878         if (!mce_flags.smca)
 879                 return;
 880
 881         /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
 882         if (defrd) {
 883                 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
 884                 return;
 885         }
 886
 887         /*
 888          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
 889          * for a valid error.
 890          */
 891         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
 892                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
 893 }
 894
 895 /* APIC interrupt handler for deferred errors */
 896 static void amd_deferred_error_interrupt(void)
 897 {
 898         unsigned int bank;
 899
 900         for (bank = 0; bank < mca_cfg.banks; ++bank)
 901                 log_error_deferred(bank);
 902 }
 903
 904 static void log_error_thresholding(unsigned int bank, u64 misc)
 905 {
 906         _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
 907 }
 908
 909 static void log_and_reset_block(struct threshold_block *block)
 910 {
 911         struct thresh_restart tr;
 912         u32 low = 0, high = 0;
 913
 914         if (!block)
 915                 return;
 916
 917         if (rdmsr_safe(block->address, &low, &high))
 918                 return;
 919
 920         if (!(high & MASK_OVERFLOW_HI))
 921                 return;
 922
 923         /* Log the MCE which caused the threshold event. */
 924         log_error_thresholding(block->bank, ((u64)high << 32) | low);
 925
 926         /* Reset threshold block after logging error. */
 927         memset(&tr, 0, sizeof(tr));
 928         tr.b = block;
 929         threshold_restart_bank(&tr);
 930 }
 931
 932 /*
 933  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
 934  * goes off when error_count reaches threshold_limit.
 935  */
 936 static void amd_threshold_interrupt(void)
 937 {
 938         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
 939         unsigned int bank, cpu = smp_processor_id();
 940
 941         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 942                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 943                         continue;
 944
 945                 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
 946                 if (!first_block)
 947                         continue;
 948
 949                 /*
 950                  * The first block is also the head of the list. Check it first
 951                  * before iterating over the rest.
 952                  */
 953                 log_and_reset_block(first_block);
 954                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
 955                         log_and_reset_block(block);
 956         }
 957 }
 958
 959 /*
 960  * Sysfs Interface
 961  */
 962
 963 struct threshold_attr {
 964         struct attribute attr;
 965         ssize_t (*show) (struct threshold_block *, char *);
 966         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 967 };
 968
 969 #define SHOW_FIELDS(name)                                               \
 970 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 971 {                                                                       \
 972         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 973 }
 974 SHOW_FIELDS(interrupt_enable)
 975 SHOW_FIELDS(threshold_limit)
 976
 977 static ssize_t
 978 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 979 {
 980         struct thresh_restart tr;
 981         unsigned long new;
 982
 983         if (!b->interrupt_capable)
 984                 return -EINVAL;
 985
 986         if (kstrtoul(buf, 0, &new) < 0)
 987                 return -EINVAL;
 988
 989         b->interrupt_enable = !!new;
 990
 991         memset(&tr, 0, sizeof(tr));
 992         tr.b            = b;
 993
 994         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 995
 996         return size;
 997 }
 998
 999 static ssize_t
1000 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
1001 {
1002         struct thresh_restart tr;
1003         unsigned long new;
1004
1005         if (kstrtoul(buf, 0, &new) < 0)
1006                 return -EINVAL;
1007
1008         if (new > THRESHOLD_MAX)
1009                 new = THRESHOLD_MAX;
1010         if (new < 1)
1011                 new = 1;
1012
1013         memset(&tr, 0, sizeof(tr));
1014         tr.old_limit = b->threshold_limit;
1015         b->threshold_limit = new;
1016         tr.b = b;
1017
1018         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1019
1020         return size;
1021 }
1022
1023 static ssize_t show_error_count(struct threshold_block *b, char *buf)
1024 {
1025         u32 lo, hi;
1026
1027         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1028
1029         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1030                                      (THRESHOLD_MAX - b->threshold_limit)));
1031 }
1032
1033 static struct threshold_attr error_count = {
1034         .attr = {.name = __stringify(error_count), .mode = 0444 },
1035         .show = show_error_count,
1036 };
1037
1038 #define RW_ATTR(val)                                                    \
1039 static struct threshold_attr val = {                                    \
1040         .attr   = {.name = __stringify(val), .mode = 0644 },            \
1041         .show   = show_## val,                                          \
1042         .store  = store_## val,                                         \
1043 };
1044
1045 RW_ATTR(interrupt_enable);
1046 RW_ATTR(threshold_limit);
1047
1048 static struct attribute *default_attrs[] = {
1049         &threshold_limit.attr,
1050         &error_count.attr,
1051         NULL,   /* possibly interrupt_enable if supported, see below */
1052         NULL,
1053 };
1054
1055 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1056 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1057
1058 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1059 {
1060         struct threshold_block *b = to_block(kobj);
1061         struct threshold_attr *a = to_attr(attr);
1062         ssize_t ret;
1063
1064         ret = a->show ? a->show(b, buf) : -EIO;
1065
1066         return ret;
1067 }
1068
1069 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1070                      const char *buf, size_t count)
1071 {
1072         struct threshold_block *b = to_block(kobj);
1073         struct threshold_attr *a = to_attr(attr);
1074         ssize_t ret;
1075
1076         ret = a->store ? a->store(b, buf, count) : -EIO;
1077
1078         return ret;
1079 }
1080
1081 static const struct sysfs_ops threshold_ops = {
1082         .show                   = show,
1083         .store                  = store,
1084 };
1085
1086 static struct kobj_type threshold_ktype = {
1087         .sysfs_ops              = &threshold_ops,
1088         .default_attrs          = default_attrs,
1089 };
1090
1091 static const char *get_name(unsigned int bank, struct threshold_block *b)
1092 {
1093         enum smca_bank_types bank_type;
1094
1095         if (!mce_flags.smca) {
1096                 if (b && bank == 4)
1097                         return bank4_names(b);
1098
1099                 return th_names[bank];
1100         }
1101
1102         bank_type = smca_get_bank_type(bank);
1103         if (bank_type >= N_SMCA_BANK_TYPES)
1104                 return NULL;
1105
1106         if (b && bank_type == SMCA_UMC) {
1107                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1108                         return smca_umc_block_names[b->block];
1109                 return NULL;
1110         }
1111
1112         if (smca_banks[bank].hwid->count == 1)
1113                 return smca_get_name(bank_type);
1114
1115         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1116                  "%s_%x", smca_get_name(bank_type),
1117                           smca_banks[bank].sysfs_id);
1118         return buf_mcatype;
1119 }
1120
1121 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1122                                      unsigned int block, u32 address)
1123 {
1124         struct threshold_block *b = NULL;
1125         u32 low, high;
1126         int err;
1127
1128         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1129                 return 0;
1130
1131         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1132                 return 0;
1133
1134         if (!(high & MASK_VALID_HI)) {
1135                 if (block)
1136                         goto recurse;
1137                 else
1138                         return 0;
1139         }
1140
1141         if (!(high & MASK_CNTP_HI)  ||
1142              (high & MASK_LOCKED_HI))
1143                 goto recurse;
1144
1145         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1146         if (!b)
1147                 return -ENOMEM;
1148
1149         b->block                = block;
1150         b->bank                 = bank;
1151         b->cpu                  = cpu;
1152         b->address              = address;
1153         b->interrupt_enable     = 0;
1154         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1155         b->threshold_limit      = THRESHOLD_MAX;
1156
1157         if (b->interrupt_capable) {
1158                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1159                 b->interrupt_enable = 1;
1160         } else {
1161                 threshold_ktype.default_attrs[2] = NULL;
1162         }
1163
1164         INIT_LIST_HEAD(&b->miscj);
1165
1166         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1167                 list_add(&b->miscj,
1168                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1169         } else {
1170                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1171         }
1172
1173         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1174                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1175                                    get_name(bank, b));
1176         if (err)
1177                 goto out_free;
1178 recurse:
1179         address = get_block_address(cpu, address, low, high, bank, ++block);
1180         if (!address)
1181                 return 0;
1182
1183         err = allocate_threshold_blocks(cpu, bank, block, address);
1184         if (err)
1185                 goto out_free;
1186
1187         if (b)
1188                 kobject_uevent(&b->kobj, KOBJ_ADD);
1189
1190         return err;
1191
1192 out_free:
1193         if (b) {
1194                 kobject_put(&b->kobj);
1195                 list_del(&b->miscj);
1196                 kfree(b);
1197         }
1198         return err;
1199 }
1200
1201 static int __threshold_add_blocks(struct threshold_bank *b)
1202 {
1203         struct list_head *head = &b->blocks->miscj;
1204         struct threshold_block *pos = NULL;
1205         struct threshold_block *tmp = NULL;
1206         int err = 0;
1207
1208         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1209         if (err)
1210                 return err;
1211
1212         list_for_each_entry_safe(pos, tmp, head, miscj) {
1213
1214                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1215                 if (err) {
1216                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1217                                 kobject_del(&pos->kobj);
1218
1219                         return err;
1220                 }
1221         }
1222         return err;
1223 }
1224
1225 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1226 {
1227         struct device *dev = per_cpu(mce_device, cpu);
1228         struct amd_northbridge *nb = NULL;
1229         struct threshold_bank *b = NULL;
1230         const char *name = get_name(bank, NULL);
1231         int err = 0;
1232
1233         if (!dev)
1234                 return -ENODEV;
1235
1236         if (is_shared_bank(bank)) {
1237                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1238
1239                 /* threshold descriptor already initialized on this node? */
1240                 if (nb && nb->bank4) {
1241                         /* yes, use it */
1242                         b = nb->bank4;
1243                         err = kobject_add(b->kobj, &dev->kobj, name);
1244                         if (err)
1245                                 goto out;
1246
1247                         per_cpu(threshold_banks, cpu)[bank] = b;
1248                         refcount_inc(&b->cpus);
1249
1250                         err = __threshold_add_blocks(b);
1251
1252                         goto out;
1253                 }
1254         }
1255
1256         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1257         if (!b) {
1258                 err = -ENOMEM;
1259                 goto out;
1260         }
1261
1262         b->kobj = kobject_create_and_add(name, &dev->kobj);
1263         if (!b->kobj) {
1264                 err = -EINVAL;
1265                 goto out_free;
1266         }
1267
1268         per_cpu(threshold_banks, cpu)[bank] = b;
1269
1270         if (is_shared_bank(bank)) {
1271                 refcount_set(&b->cpus, 1);
1272
1273                 /* nb is already initialized, see above */
1274                 if (nb) {
1275                         WARN_ON(nb->bank4);
1276                         nb->bank4 = b;
1277                 }
1278         }
1279
1280         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1281         if (!err)
1282                 goto out;
1283
1284  out_free:
1285         kfree(b);
1286
1287  out:
1288         return err;
1289 }
1290
1291 static void deallocate_threshold_block(unsigned int cpu,
1292                                                  unsigned int bank)
1293 {
1294         struct threshold_block *pos = NULL;
1295         struct threshold_block *tmp = NULL;
1296         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1297
1298         if (!head)
1299                 return;
1300
1301         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1302                 kobject_put(&pos->kobj);
1303                 list_del(&pos->miscj);
1304                 kfree(pos);
1305         }
1306
1307         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1308         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1309 }
1310
1311 static void __threshold_remove_blocks(struct threshold_bank *b)
1312 {
1313         struct threshold_block *pos = NULL;
1314         struct threshold_block *tmp = NULL;
1315
1316         kobject_del(b->kobj);
1317
1318         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1319                 kobject_del(&pos->kobj);
1320 }
1321
1322 static void threshold_remove_bank(unsigned int cpu, int bank)
1323 {
1324         struct amd_northbridge *nb;
1325         struct threshold_bank *b;
1326
1327         b = per_cpu(threshold_banks, cpu)[bank];
1328         if (!b)
1329                 return;
1330
1331         if (!b->blocks)
1332                 goto free_out;
1333
1334         if (is_shared_bank(bank)) {
1335                 if (!refcount_dec_and_test(&b->cpus)) {
1336                         __threshold_remove_blocks(b);
1337                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1338                         return;
1339                 } else {
1340                         /*
1341                          * the last CPU on this node using the shared bank is
1342                          * going away, remove that bank now.
1343                          */
1344                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1345                         nb->bank4 = NULL;
1346                 }
1347         }
1348
1349         deallocate_threshold_block(cpu, bank);
1350
1351 free_out:
1352         kobject_del(b->kobj);
1353         kobject_put(b->kobj);
1354         kfree(b);
1355         per_cpu(threshold_banks, cpu)[bank] = NULL;
1356 }
1357
1358 int mce_threshold_remove_device(unsigned int cpu)
1359 {
1360         unsigned int bank;
1361
1362         if (!thresholding_en)
1363                 return 0;
1364
1365         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1366                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1367                         continue;
1368                 threshold_remove_bank(cpu, bank);
1369         }
1370         kfree(per_cpu(threshold_banks, cpu));
1371         per_cpu(threshold_banks, cpu) = NULL;
1372         return 0;
1373 }
1374
1375 /* create dir/files for all valid threshold banks */
1376 int mce_threshold_create_device(unsigned int cpu)
1377 {
1378         unsigned int bank;
1379         struct threshold_bank **bp;
1380         int err = 0;
1381
1382         if (!thresholding_en)
1383                 return 0;
1384
1385         bp = per_cpu(threshold_banks, cpu);
1386         if (bp)
1387                 return 0;
1388
1389         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1390                      GFP_KERNEL);
1391         if (!bp)
1392                 return -ENOMEM;
1393
1394         per_cpu(threshold_banks, cpu) = bp;
1395
1396         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1397                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1398                         continue;
1399                 err = threshold_create_bank(cpu, bank);
1400                 if (err)
1401                         goto err;
1402         }
1403         return err;
1404 err:
1405         mce_threshold_remove_device(cpu);
1406         return err;
1407 }
1408
1409 static __init int threshold_init_device(void)
1410 {
1411         unsigned lcpu = 0;
1412
1413         if (mce_threshold_vector == amd_threshold_interrupt)
1414                 thresholding_en = true;
1415
1416         /* to hit CPUs online before the notifier is up */
1417         for_each_online_cpu(lcpu) {
1418                 int err = mce_threshold_create_device(lcpu);
1419
1420                 if (err)
1421                         return err;
1422         }
1423
1424         return 0;
1425 }
1426 /*
1427  * there are 3 funcs which need to be _initcalled in a logic sequence:
1428  * 1. xen_late_init_mcelog
1429  * 2. mcheck_init_device
1430  * 3. threshold_init_device
1431  *
1432  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1433  * native mce_chrdev_device registration if running under xen platform;
1434  *
1435  * mcheck_init_device should be inited before threshold_init_device to
1436  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1437  *
1438  * so we use following _initcalls
1439  * 1. device_initcall(xen_late_init_mcelog);
1440  * 2. device_initcall_sync(mcheck_init_device);
1441  * 3. late_initcall(threshold_init_device);
1442  *
1443  * when running under xen, the initcall order is 1,2,3;
1444  * on baremetal, we skip 1 and we do only 2 and 3.
1445  */
1446 late_initcall(threshold_init_device);