arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35 #include <asm/desc.h>
  36 #include <asm/ldt.h>
  37
  38 #include "perf_event.h"
  39
  40 struct x86_pmu x86_pmu __read_mostly;
  41
  42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  43         .enabled = 1,
  44 };
  45
  46 u64 __read_mostly hw_cache_event_ids
  47                                 [PERF_COUNT_HW_CACHE_MAX]
  48                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  49                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  50 u64 __read_mostly hw_cache_extra_regs
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54
  55 /*
  56  * Propagate event elapsed time into the generic event.
  57  * Can only be executed on the CPU where the event is active.
  58  * Returns the delta events processed.
  59  */
  60 u64 x86_perf_event_update(struct perf_event *event)
  61 {
  62         struct hw_perf_event *hwc = &event->hw;
  63         int shift = 64 - x86_pmu.cntval_bits;
  64         u64 prev_raw_count, new_raw_count;
  65         int idx = hwc->idx;
  66         s64 delta;
  67
  68         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  69                 return 0;
  70
  71         /*
  72          * Careful: an NMI might modify the previous event value.
  73          *
  74          * Our tactic to handle this is to first atomically read and
  75          * exchange a new raw count - then add that new-prev delta
  76          * count to the generic event atomically:
  77          */
  78 again:
  79         prev_raw_count = local64_read(&hwc->prev_count);
  80         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  81
  82         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  83                                         new_raw_count) != prev_raw_count)
  84                 goto again;
  85
  86         /*
  87          * Now we have the new raw value and have updated the prev
  88          * timestamp already. We can now calculate the elapsed delta
  89          * (event-)time and add that to the generic event.
  90          *
  91          * Careful, not all hw sign-extends above the physical width
  92          * of the count.
  93          */
  94         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  95         delta >>= shift;
  96
  97         local64_add(delta, &event->count);
  98         local64_sub(delta, &hwc->period_left);
  99
 100         return new_raw_count;
 101 }
 102
 103 /*
 104  * Find and validate any extra registers to set up.
 105  */
 106 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 107 {
 108         struct hw_perf_event_extra *reg;
 109         struct extra_reg *er;
 110
 111         reg = &event->hw.extra_reg;
 112
 113         if (!x86_pmu.extra_regs)
 114                 return 0;
 115
 116         for (er = x86_pmu.extra_regs; er->msr; er++) {
 117                 if (er->event != (config & er->config_mask))
 118                         continue;
 119                 if (event->attr.config1 & ~er->valid_mask)
 120                         return -EINVAL;
 121
 122                 reg->idx = er->idx;
 123                 reg->config = event->attr.config1;
 124                 reg->reg = er->msr;
 125                 break;
 126         }
 127         return 0;
 128 }
 129
 130 static atomic_t active_events;
 131 static DEFINE_MUTEX(pmc_reserve_mutex);
 132
 133 #ifdef CONFIG_X86_LOCAL_APIC
 134
 135 static bool reserve_pmc_hardware(void)
 136 {
 137         int i;
 138
 139         for (i = 0; i < x86_pmu.num_counters; i++) {
 140                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 141                         goto perfctr_fail;
 142         }
 143
 144         for (i = 0; i < x86_pmu.num_counters; i++) {
 145                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 146                         goto eventsel_fail;
 147         }
 148
 149         return true;
 150
 151 eventsel_fail:
 152         for (i--; i >= 0; i--)
 153                 release_evntsel_nmi(x86_pmu_config_addr(i));
 154
 155         i = x86_pmu.num_counters;
 156
 157 perfctr_fail:
 158         for (i--; i >= 0; i--)
 159                 release_perfctr_nmi(x86_pmu_event_addr(i));
 160
 161         return false;
 162 }
 163
 164 static void release_pmc_hardware(void)
 165 {
 166         int i;
 167
 168         for (i = 0; i < x86_pmu.num_counters; i++) {
 169                 release_perfctr_nmi(x86_pmu_event_addr(i));
 170                 release_evntsel_nmi(x86_pmu_config_addr(i));
 171         }
 172 }
 173
 174 #else
 175
 176 static bool reserve_pmc_hardware(void) { return true; }
 177 static void release_pmc_hardware(void) {}
 178
 179 #endif
 180
 181 static bool check_hw_exists(void)
 182 {
 183         u64 val, val_fail, val_new= ~0;
 184         int i, reg, reg_fail, ret = 0;
 185         int bios_fail = 0;
 186
 187         /*
 188          * Check to see if the BIOS enabled any of the counters, if so
 189          * complain and bail.
 190          */
 191         for (i = 0; i < x86_pmu.num_counters; i++) {
 192                 reg = x86_pmu_config_addr(i);
 193                 ret = rdmsrl_safe(reg, &val);
 194                 if (ret)
 195                         goto msr_fail;
 196                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 197                         bios_fail = 1;
 198                         val_fail = val;
 199                         reg_fail = reg;
 200                 }
 201         }
 202
 203         if (x86_pmu.num_counters_fixed) {
 204                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 205                 ret = rdmsrl_safe(reg, &val);
 206                 if (ret)
 207                         goto msr_fail;
 208                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 209                         if (val & (0x03 << i*4)) {
 210                                 bios_fail = 1;
 211                                 val_fail = val;
 212                                 reg_fail = reg;
 213                         }
 214                 }
 215         }
 216
 217         /*
 218          * Read the current value, change it and read it back to see if it
 219          * matches, this is needed to detect certain hardware emulators
 220          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 221          */
 222         reg = x86_pmu_event_addr(0);
 223         if (rdmsrl_safe(reg, &val))
 224                 goto msr_fail;
 225         val ^= 0xffffUL;
 226         ret = wrmsrl_safe(reg, val);
 227         ret |= rdmsrl_safe(reg, &val_new);
 228         if (ret || val != val_new)
 229                 goto msr_fail;
 230
 231         /*
 232          * We still allow the PMU driver to operate:
 233          */
 234         if (bios_fail) {
 235                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 236                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 237         }
 238
 239         return true;
 240
 241 msr_fail:
 242         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 243         printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
 244
 245         return false;
 246 }
 247
 248 static void hw_perf_event_destroy(struct perf_event *event)
 249 {
 250         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 251                 release_pmc_hardware();
 252                 release_ds_buffers();
 253                 mutex_unlock(&pmc_reserve_mutex);
 254         }
 255 }
 256
 257 static inline int x86_pmu_initialized(void)
 258 {
 259         return x86_pmu.handle_irq != NULL;
 260 }
 261
 262 static inline int
 263 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 264 {
 265         struct perf_event_attr *attr = &event->attr;
 266         unsigned int cache_type, cache_op, cache_result;
 267         u64 config, val;
 268
 269         config = attr->config;
 270
 271         cache_type = (config >>  0) & 0xff;
 272         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 273                 return -EINVAL;
 274
 275         cache_op = (config >>  8) & 0xff;
 276         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 277                 return -EINVAL;
 278
 279         cache_result = (config >> 16) & 0xff;
 280         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 281                 return -EINVAL;
 282
 283         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 284
 285         if (val == 0)
 286                 return -ENOENT;
 287
 288         if (val == -1)
 289                 return -EINVAL;
 290
 291         hwc->config |= val;
 292         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 293         return x86_pmu_extra_regs(val, event);
 294 }
 295
 296 int x86_setup_perfctr(struct perf_event *event)
 297 {
 298         struct perf_event_attr *attr = &event->attr;
 299         struct hw_perf_event *hwc = &event->hw;
 300         u64 config;
 301
 302         if (!is_sampling_event(event)) {
 303                 hwc->sample_period = x86_pmu.max_period;
 304                 hwc->last_period = hwc->sample_period;
 305                 local64_set(&hwc->period_left, hwc->sample_period);
 306         } else {
 307                 /*
 308                  * If we have a PMU initialized but no APIC
 309                  * interrupts, we cannot sample hardware
 310                  * events (user-space has to fall back and
 311                  * sample via a hrtimer based software event):
 312                  */
 313                 if (!x86_pmu.apic)
 314                         return -EOPNOTSUPP;
 315         }
 316
 317         if (attr->type == PERF_TYPE_RAW)
 318                 return x86_pmu_extra_regs(event->attr.config, event);
 319
 320         if (attr->type == PERF_TYPE_HW_CACHE)
 321                 return set_ext_hw_attr(hwc, event);
 322
 323         if (attr->config >= x86_pmu.max_events)
 324                 return -EINVAL;
 325
 326         /*
 327          * The generic map:
 328          */
 329         config = x86_pmu.event_map(attr->config);
 330
 331         if (config == 0)
 332                 return -ENOENT;
 333
 334         if (config == -1LL)
 335                 return -EINVAL;
 336
 337         /*
 338          * Branch tracing:
 339          */
 340         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 341             !attr->freq && hwc->sample_period == 1) {
 342                 /* BTS is not supported by this architecture. */
 343                 if (!x86_pmu.bts_active)
 344                         return -EOPNOTSUPP;
 345
 346                 /* BTS is currently only allowed for user-mode. */
 347                 if (!attr->exclude_kernel)
 348                         return -EOPNOTSUPP;
 349         }
 350
 351         hwc->config |= config;
 352
 353         return 0;
 354 }
 355
 356 /*
 357  * check that branch_sample_type is compatible with
 358  * settings needed for precise_ip > 1 which implies
 359  * using the LBR to capture ALL taken branches at the
 360  * priv levels of the measurement
 361  */
 362 static inline int precise_br_compat(struct perf_event *event)
 363 {
 364         u64 m = event->attr.branch_sample_type;
 365         u64 b = 0;
 366
 367         /* must capture all branches */
 368         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 369                 return 0;
 370
 371         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 372
 373         if (!event->attr.exclude_user)
 374                 b |= PERF_SAMPLE_BRANCH_USER;
 375
 376         if (!event->attr.exclude_kernel)
 377                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 378
 379         /*
 380          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 381          */
 382
 383         return m == b;
 384 }
 385
 386 int x86_pmu_hw_config(struct perf_event *event)
 387 {
 388         if (event->attr.precise_ip) {
 389                 int precise = 0;
 390
 391                 /* Support for constant skid */
 392                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 393                         precise++;
 394
 395                         /* Support for IP fixup */
 396                         if (x86_pmu.lbr_nr)
 397                                 precise++;
 398                 }
 399
 400                 if (event->attr.precise_ip > precise)
 401                         return -EOPNOTSUPP;
 402                 /*
 403                  * check that PEBS LBR correction does not conflict with
 404                  * whatever the user is asking with attr->branch_sample_type
 405                  */
 406                 if (event->attr.precise_ip > 1 &&
 407                     x86_pmu.intel_cap.pebs_format < 2) {
 408                         u64 *br_type = &event->attr.branch_sample_type;
 409
 410                         if (has_branch_stack(event)) {
 411                                 if (!precise_br_compat(event))
 412                                         return -EOPNOTSUPP;
 413
 414                                 /* branch_sample_type is compatible */
 415
 416                         } else {
 417                                 /*
 418                                  * user did not specify  branch_sample_type
 419                                  *
 420                                  * For PEBS fixups, we capture all
 421                                  * the branches at the priv level of the
 422                                  * event.
 423                                  */
 424                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 425
 426                                 if (!event->attr.exclude_user)
 427                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 428
 429                                 if (!event->attr.exclude_kernel)
 430                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 431                         }
 432                 }
 433         }
 434
 435         /*
 436          * Generate PMC IRQs:
 437          * (keep 'enabled' bit clear for now)
 438          */
 439         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 440
 441         /*
 442          * Count user and OS events unless requested not to
 443          */
 444         if (!event->attr.exclude_user)
 445                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 446         if (!event->attr.exclude_kernel)
 447                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 448
 449         if (event->attr.type == PERF_TYPE_RAW)
 450                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 451
 452         return x86_setup_perfctr(event);
 453 }
 454
 455 /*
 456  * Setup the hardware configuration for a given attr_type
 457  */
 458 static int __x86_pmu_event_init(struct perf_event *event)
 459 {
 460         int err;
 461
 462         if (!x86_pmu_initialized())
 463                 return -ENODEV;
 464
 465         err = 0;
 466         if (!atomic_inc_not_zero(&active_events)) {
 467                 mutex_lock(&pmc_reserve_mutex);
 468                 if (atomic_read(&active_events) == 0) {
 469                         if (!reserve_pmc_hardware())
 470                                 err = -EBUSY;
 471                         else
 472                                 reserve_ds_buffers();
 473                 }
 474                 if (!err)
 475                         atomic_inc(&active_events);
 476                 mutex_unlock(&pmc_reserve_mutex);
 477         }
 478         if (err)
 479                 return err;
 480
 481         event->destroy = hw_perf_event_destroy;
 482
 483         event->hw.idx = -1;
 484         event->hw.last_cpu = -1;
 485         event->hw.last_tag = ~0ULL;
 486
 487         /* mark unused */
 488         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 489         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 490
 491         return x86_pmu.hw_config(event);
 492 }
 493
 494 void x86_pmu_disable_all(void)
 495 {
 496         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 497         int idx;
 498
 499         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 500                 u64 val;
 501
 502                 if (!test_bit(idx, cpuc->active_mask))
 503                         continue;
 504                 rdmsrl(x86_pmu_config_addr(idx), val);
 505                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 506                         continue;
 507                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 508                 wrmsrl(x86_pmu_config_addr(idx), val);
 509         }
 510 }
 511
 512 static void x86_pmu_disable(struct pmu *pmu)
 513 {
 514         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 515
 516         if (!x86_pmu_initialized())
 517                 return;
 518
 519         if (!cpuc->enabled)
 520                 return;
 521
 522         cpuc->n_added = 0;
 523         cpuc->enabled = 0;
 524         barrier();
 525
 526         x86_pmu.disable_all();
 527 }
 528
 529 void x86_pmu_enable_all(int added)
 530 {
 531         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 532         int idx;
 533
 534         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 535                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 536
 537                 if (!test_bit(idx, cpuc->active_mask))
 538                         continue;
 539
 540                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 541         }
 542 }
 543
 544 static struct pmu pmu;
 545
 546 static inline int is_x86_event(struct perf_event *event)
 547 {
 548         return event->pmu == &pmu;
 549 }
 550
 551 /*
 552  * Event scheduler state:
 553  *
 554  * Assign events iterating over all events and counters, beginning
 555  * with events with least weights first. Keep the current iterator
 556  * state in struct sched_state.
 557  */
 558 struct sched_state {
 559         int     weight;
 560         int     event;          /* event index */
 561         int     counter;        /* counter index */
 562         int     unassigned;     /* number of events to be assigned left */
 563         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 564 };
 565
 566 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 567 #define SCHED_STATES_MAX        2
 568
 569 struct perf_sched {
 570         int                     max_weight;
 571         int                     max_events;
 572         struct perf_event       **events;
 573         struct sched_state      state;
 574         int                     saved_states;
 575         struct sched_state      saved[SCHED_STATES_MAX];
 576 };
 577
 578 /*
 579  * Initialize interator that runs through all events and counters.
 580  */
 581 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
 582                             int num, int wmin, int wmax)
 583 {
 584         int idx;
 585
 586         memset(sched, 0, sizeof(*sched));
 587         sched->max_events       = num;
 588         sched->max_weight       = wmax;
 589         sched->events           = events;
 590
 591         for (idx = 0; idx < num; idx++) {
 592                 if (events[idx]->hw.constraint->weight == wmin)
 593                         break;
 594         }
 595
 596         sched->state.event      = idx;          /* start with min weight */
 597         sched->state.weight     = wmin;
 598         sched->state.unassigned = num;
 599 }
 600
 601 static void perf_sched_save_state(struct perf_sched *sched)
 602 {
 603         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 604                 return;
 605
 606         sched->saved[sched->saved_states] = sched->state;
 607         sched->saved_states++;
 608 }
 609
 610 static bool perf_sched_restore_state(struct perf_sched *sched)
 611 {
 612         if (!sched->saved_states)
 613                 return false;
 614
 615         sched->saved_states--;
 616         sched->state = sched->saved[sched->saved_states];
 617
 618         /* continue with next counter: */
 619         clear_bit(sched->state.counter++, sched->state.used);
 620
 621         return true;
 622 }
 623
 624 /*
 625  * Select a counter for the current event to schedule. Return true on
 626  * success.
 627  */
 628 static bool __perf_sched_find_counter(struct perf_sched *sched)
 629 {
 630         struct event_constraint *c;
 631         int idx;
 632
 633         if (!sched->state.unassigned)
 634                 return false;
 635
 636         if (sched->state.event >= sched->max_events)
 637                 return false;
 638
 639         c = sched->events[sched->state.event]->hw.constraint;
 640         /* Prefer fixed purpose counters */
 641         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 642                 idx = INTEL_PMC_IDX_FIXED;
 643                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 644                         if (!__test_and_set_bit(idx, sched->state.used))
 645                                 goto done;
 646                 }
 647         }
 648         /* Grab the first unused counter starting with idx */
 649         idx = sched->state.counter;
 650         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 651                 if (!__test_and_set_bit(idx, sched->state.used))
 652                         goto done;
 653         }
 654
 655         return false;
 656
 657 done:
 658         sched->state.counter = idx;
 659
 660         if (c->overlap)
 661                 perf_sched_save_state(sched);
 662
 663         return true;
 664 }
 665
 666 static bool perf_sched_find_counter(struct perf_sched *sched)
 667 {
 668         while (!__perf_sched_find_counter(sched)) {
 669                 if (!perf_sched_restore_state(sched))
 670                         return false;
 671         }
 672
 673         return true;
 674 }
 675
 676 /*
 677  * Go through all unassigned events and find the next one to schedule.
 678  * Take events with the least weight first. Return true on success.
 679  */
 680 static bool perf_sched_next_event(struct perf_sched *sched)
 681 {
 682         struct event_constraint *c;
 683
 684         if (!sched->state.unassigned || !--sched->state.unassigned)
 685                 return false;
 686
 687         do {
 688                 /* next event */
 689                 sched->state.event++;
 690                 if (sched->state.event >= sched->max_events) {
 691                         /* next weight */
 692                         sched->state.event = 0;
 693                         sched->state.weight++;
 694                         if (sched->state.weight > sched->max_weight)
 695                                 return false;
 696                 }
 697                 c = sched->events[sched->state.event]->hw.constraint;
 698         } while (c->weight != sched->state.weight);
 699
 700         sched->state.counter = 0;       /* start with first counter */
 701
 702         return true;
 703 }
 704
 705 /*
 706  * Assign a counter for each event.
 707  */
 708 int perf_assign_events(struct perf_event **events, int n,
 709                         int wmin, int wmax, int *assign)
 710 {
 711         struct perf_sched sched;
 712
 713         perf_sched_init(&sched, events, n, wmin, wmax);
 714
 715         do {
 716                 if (!perf_sched_find_counter(&sched))
 717                         break;  /* failed */
 718                 if (assign)
 719                         assign[sched.state.event] = sched.state.counter;
 720         } while (perf_sched_next_event(&sched));
 721
 722         return sched.state.unassigned;
 723 }
 724
 725 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 726 {
 727         struct event_constraint *c;
 728         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 729         struct perf_event *e;
 730         int i, wmin, wmax, num = 0;
 731         struct hw_perf_event *hwc;
 732
 733         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 734
 735         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 736                 hwc = &cpuc->event_list[i]->hw;
 737                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 738                 hwc->constraint = c;
 739
 740                 wmin = min(wmin, c->weight);
 741                 wmax = max(wmax, c->weight);
 742         }
 743
 744         /*
 745          * fastpath, try to reuse previous register
 746          */
 747         for (i = 0; i < n; i++) {
 748                 hwc = &cpuc->event_list[i]->hw;
 749                 c = hwc->constraint;
 750
 751                 /* never assigned */
 752                 if (hwc->idx == -1)
 753                         break;
 754
 755                 /* constraint still honored */
 756                 if (!test_bit(hwc->idx, c->idxmsk))
 757                         break;
 758
 759                 /* not already used */
 760                 if (test_bit(hwc->idx, used_mask))
 761                         break;
 762
 763                 __set_bit(hwc->idx, used_mask);
 764                 if (assign)
 765                         assign[i] = hwc->idx;
 766         }
 767
 768         /* slow path */
 769         if (i != n)
 770                 num = perf_assign_events(cpuc->event_list, n, wmin,
 771                                          wmax, assign);
 772
 773         /*
 774          * Mark the event as committed, so we do not put_constraint()
 775          * in case new events are added and fail scheduling.
 776          */
 777         if (!num && assign) {
 778                 for (i = 0; i < n; i++) {
 779                         e = cpuc->event_list[i];
 780                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 781                 }
 782         }
 783         /*
 784          * scheduling failed or is just a simulation,
 785          * free resources if necessary
 786          */
 787         if (!assign || num) {
 788                 for (i = 0; i < n; i++) {
 789                         e = cpuc->event_list[i];
 790                         /*
 791                          * do not put_constraint() on comitted events,
 792                          * because they are good to go
 793                          */
 794                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 795                                 continue;
 796
 797                         if (x86_pmu.put_event_constraints)
 798                                 x86_pmu.put_event_constraints(cpuc, e);
 799                 }
 800         }
 801         return num ? -EINVAL : 0;
 802 }
 803
 804 /*
 805  * dogrp: true if must collect siblings events (group)
 806  * returns total number of events and error code
 807  */
 808 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 809 {
 810         struct perf_event *event;
 811         int n, max_count;
 812
 813         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 814
 815         /* current number of events already accepted */
 816         n = cpuc->n_events;
 817
 818         if (is_x86_event(leader)) {
 819                 if (n >= max_count)
 820                         return -EINVAL;
 821                 cpuc->event_list[n] = leader;
 822                 n++;
 823         }
 824         if (!dogrp)
 825                 return n;
 826
 827         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 828                 if (!is_x86_event(event) ||
 829                     event->state <= PERF_EVENT_STATE_OFF)
 830                         continue;
 831
 832                 if (n >= max_count)
 833                         return -EINVAL;
 834
 835                 cpuc->event_list[n] = event;
 836                 n++;
 837         }
 838         return n;
 839 }
 840
 841 static inline void x86_assign_hw_event(struct perf_event *event,
 842                                 struct cpu_hw_events *cpuc, int i)
 843 {
 844         struct hw_perf_event *hwc = &event->hw;
 845
 846         hwc->idx = cpuc->assign[i];
 847         hwc->last_cpu = smp_processor_id();
 848         hwc->last_tag = ++cpuc->tags[i];
 849
 850         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 851                 hwc->config_base = 0;
 852                 hwc->event_base = 0;
 853         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 854                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 855                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 856                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 857         } else {
 858                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 859                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 860                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 861         }
 862 }
 863
 864 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 865                                         struct cpu_hw_events *cpuc,
 866                                         int i)
 867 {
 868         return hwc->idx == cpuc->assign[i] &&
 869                 hwc->last_cpu == smp_processor_id() &&
 870                 hwc->last_tag == cpuc->tags[i];
 871 }
 872
 873 static void x86_pmu_start(struct perf_event *event, int flags);
 874
 875 static void x86_pmu_enable(struct pmu *pmu)
 876 {
 877         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 878         struct perf_event *event;
 879         struct hw_perf_event *hwc;
 880         int i, added = cpuc->n_added;
 881
 882         if (!x86_pmu_initialized())
 883                 return;
 884
 885         if (cpuc->enabled)
 886                 return;
 887
 888         if (cpuc->n_added) {
 889                 int n_running = cpuc->n_events - cpuc->n_added;
 890                 /*
 891                  * apply assignment obtained either from
 892                  * hw_perf_group_sched_in() or x86_pmu_enable()
 893                  *
 894                  * step1: save events moving to new counters
 895                  */
 896                 for (i = 0; i < n_running; i++) {
 897                         event = cpuc->event_list[i];
 898                         hwc = &event->hw;
 899
 900                         /*
 901                          * we can avoid reprogramming counter if:
 902                          * - assigned same counter as last time
 903                          * - running on same CPU as last time
 904                          * - no other event has used the counter since
 905                          */
 906                         if (hwc->idx == -1 ||
 907                             match_prev_assignment(hwc, cpuc, i))
 908                                 continue;
 909
 910                         /*
 911                          * Ensure we don't accidentally enable a stopped
 912                          * counter simply because we rescheduled.
 913                          */
 914                         if (hwc->state & PERF_HES_STOPPED)
 915                                 hwc->state |= PERF_HES_ARCH;
 916
 917                         x86_pmu_stop(event, PERF_EF_UPDATE);
 918                 }
 919
 920                 /*
 921                  * step2: reprogram moved events into new counters
 922                  */
 923                 for (i = 0; i < cpuc->n_events; i++) {
 924                         event = cpuc->event_list[i];
 925                         hwc = &event->hw;
 926
 927                         if (!match_prev_assignment(hwc, cpuc, i))
 928                                 x86_assign_hw_event(event, cpuc, i);
 929                         else if (i < n_running)
 930                                 continue;
 931
 932                         if (hwc->state & PERF_HES_ARCH)
 933                                 continue;
 934
 935                         x86_pmu_start(event, PERF_EF_RELOAD);
 936                 }
 937                 cpuc->n_added = 0;
 938                 perf_events_lapic_init();
 939         }
 940
 941         cpuc->enabled = 1;
 942         barrier();
 943
 944         x86_pmu.enable_all(added);
 945 }
 946
 947 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 948
 949 /*
 950  * Set the next IRQ period, based on the hwc->period_left value.
 951  * To be called with the event disabled in hw:
 952  */
 953 int x86_perf_event_set_period(struct perf_event *event)
 954 {
 955         struct hw_perf_event *hwc = &event->hw;
 956         s64 left = local64_read(&hwc->period_left);
 957         s64 period = hwc->sample_period;
 958         int ret = 0, idx = hwc->idx;
 959
 960         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 961                 return 0;
 962
 963         /*
 964          * If we are way outside a reasonable range then just skip forward:
 965          */
 966         if (unlikely(left <= -period)) {
 967                 left = period;
 968                 local64_set(&hwc->period_left, left);
 969                 hwc->last_period = period;
 970                 ret = 1;
 971         }
 972
 973         if (unlikely(left <= 0)) {
 974                 left += period;
 975                 local64_set(&hwc->period_left, left);
 976                 hwc->last_period = period;
 977                 ret = 1;
 978         }
 979         /*
 980          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 981          */
 982         if (unlikely(left < 2))
 983                 left = 2;
 984
 985         if (left > x86_pmu.max_period)
 986                 left = x86_pmu.max_period;
 987
 988         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 989
 990         /*
 991          * The hw event starts counting from this event offset,
 992          * mark it to be able to extra future deltas:
 993          */
 994         local64_set(&hwc->prev_count, (u64)-left);
 995
 996         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 997
 998         /*
 999          * Due to erratum on certan cpu we need
1000          * a second write to be sure the register
1001          * is updated properly
1002          */
1003         if (x86_pmu.perfctr_second_write) {
1004                 wrmsrl(hwc->event_base,
1005                         (u64)(-left) & x86_pmu.cntval_mask);
1006         }
1007
1008         perf_event_update_userpage(event);
1009
1010         return ret;
1011 }
1012
1013 void x86_pmu_enable_event(struct perf_event *event)
1014 {
1015         if (__this_cpu_read(cpu_hw_events.enabled))
1016                 __x86_pmu_enable_event(&event->hw,
1017                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1018 }
1019
1020 /*
1021  * Add a single event to the PMU.
1022  *
1023  * The event is added to the group of enabled events
1024  * but only if it can be scehduled with existing events.
1025  */
1026 static int x86_pmu_add(struct perf_event *event, int flags)
1027 {
1028         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1029         struct hw_perf_event *hwc;
1030         int assign[X86_PMC_IDX_MAX];
1031         int n, n0, ret;
1032
1033         hwc = &event->hw;
1034
1035         perf_pmu_disable(event->pmu);
1036         n0 = cpuc->n_events;
1037         ret = n = collect_events(cpuc, event, false);
1038         if (ret < 0)
1039                 goto out;
1040
1041         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1042         if (!(flags & PERF_EF_START))
1043                 hwc->state |= PERF_HES_ARCH;
1044
1045         /*
1046          * If group events scheduling transaction was started,
1047          * skip the schedulability test here, it will be performed
1048          * at commit time (->commit_txn) as a whole.
1049          */
1050         if (cpuc->group_flag & PERF_EVENT_TXN)
1051                 goto done_collect;
1052
1053         ret = x86_pmu.schedule_events(cpuc, n, assign);
1054         if (ret)
1055                 goto out;
1056         /*
1057          * copy new assignment, now we know it is possible
1058          * will be used by hw_perf_enable()
1059          */
1060         memcpy(cpuc->assign, assign, n*sizeof(int));
1061
1062 done_collect:
1063         /*
1064          * Commit the collect_events() state. See x86_pmu_del() and
1065          * x86_pmu_*_txn().
1066          */
1067         cpuc->n_events = n;
1068         cpuc->n_added += n - n0;
1069         cpuc->n_txn += n - n0;
1070
1071         ret = 0;
1072 out:
1073         perf_pmu_enable(event->pmu);
1074         return ret;
1075 }
1076
1077 static void x86_pmu_start(struct perf_event *event, int flags)
1078 {
1079         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1080         int idx = event->hw.idx;
1081
1082         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1083                 return;
1084
1085         if (WARN_ON_ONCE(idx == -1))
1086                 return;
1087
1088         if (flags & PERF_EF_RELOAD) {
1089                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1090                 x86_perf_event_set_period(event);
1091         }
1092
1093         event->hw.state = 0;
1094
1095         cpuc->events[idx] = event;
1096         __set_bit(idx, cpuc->active_mask);
1097         __set_bit(idx, cpuc->running);
1098         x86_pmu.enable(event);
1099         perf_event_update_userpage(event);
1100 }
1101
1102 void perf_event_print_debug(void)
1103 {
1104         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1105         u64 pebs;
1106         struct cpu_hw_events *cpuc;
1107         unsigned long flags;
1108         int cpu, idx;
1109
1110         if (!x86_pmu.num_counters)
1111                 return;
1112
1113         local_irq_save(flags);
1114
1115         cpu = smp_processor_id();
1116         cpuc = &per_cpu(cpu_hw_events, cpu);
1117
1118         if (x86_pmu.version >= 2) {
1119                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1120                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1121                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1122                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1123                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1124
1125                 pr_info("\n");
1126                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1127                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1128                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1129                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1130                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1131         }
1132         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1133
1134         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1135                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1136                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1137
1138                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1139
1140                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1141                         cpu, idx, pmc_ctrl);
1142                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1143                         cpu, idx, pmc_count);
1144                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1145                         cpu, idx, prev_left);
1146         }
1147         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1148                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1149
1150                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1151                         cpu, idx, pmc_count);
1152         }
1153         local_irq_restore(flags);
1154 }
1155
1156 void x86_pmu_stop(struct perf_event *event, int flags)
1157 {
1158         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1159         struct hw_perf_event *hwc = &event->hw;
1160
1161         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1162                 x86_pmu.disable(event);
1163                 cpuc->events[hwc->idx] = NULL;
1164                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1165                 hwc->state |= PERF_HES_STOPPED;
1166         }
1167
1168         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1169                 /*
1170                  * Drain the remaining delta count out of a event
1171                  * that we are disabling:
1172                  */
1173                 x86_perf_event_update(event);
1174                 hwc->state |= PERF_HES_UPTODATE;
1175         }
1176 }
1177
1178 static void x86_pmu_del(struct perf_event *event, int flags)
1179 {
1180         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1181         int i;
1182
1183         /*
1184          * event is descheduled
1185          */
1186         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1187
1188         /*
1189          * If we're called during a txn, we don't need to do anything.
1190          * The events never got scheduled and ->cancel_txn will truncate
1191          * the event_list.
1192          *
1193          * XXX assumes any ->del() called during a TXN will only be on
1194          * an event added during that same TXN.
1195          */
1196         if (cpuc->group_flag & PERF_EVENT_TXN)
1197                 return;
1198
1199         /*
1200          * Not a TXN, therefore cleanup properly.
1201          */
1202         x86_pmu_stop(event, PERF_EF_UPDATE);
1203
1204         for (i = 0; i < cpuc->n_events; i++) {
1205                 if (event == cpuc->event_list[i])
1206                         break;
1207         }
1208
1209         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1210                 return;
1211
1212         /* If we have a newly added event; make sure to decrease n_added. */
1213         if (i >= cpuc->n_events - cpuc->n_added)
1214                 --cpuc->n_added;
1215
1216         if (x86_pmu.put_event_constraints)
1217                 x86_pmu.put_event_constraints(cpuc, event);
1218
1219         /* Delete the array entry. */
1220         while (++i < cpuc->n_events)
1221                 cpuc->event_list[i-1] = cpuc->event_list[i];
1222         --cpuc->n_events;
1223
1224         perf_event_update_userpage(event);
1225 }
1226
1227 int x86_pmu_handle_irq(struct pt_regs *regs)
1228 {
1229         struct perf_sample_data data;
1230         struct cpu_hw_events *cpuc;
1231         struct perf_event *event;
1232         int idx, handled = 0;
1233         u64 val;
1234
1235         cpuc = &__get_cpu_var(cpu_hw_events);
1236
1237         /*
1238          * Some chipsets need to unmask the LVTPC in a particular spot
1239          * inside the nmi handler.  As a result, the unmasking was pushed
1240          * into all the nmi handlers.
1241          *
1242          * This generic handler doesn't seem to have any issues where the
1243          * unmasking occurs so it was left at the top.
1244          */
1245         apic_write(APIC_LVTPC, APIC_DM_NMI);
1246
1247         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1248                 if (!test_bit(idx, cpuc->active_mask)) {
1249                         /*
1250                          * Though we deactivated the counter some cpus
1251                          * might still deliver spurious interrupts still
1252                          * in flight. Catch them:
1253                          */
1254                         if (__test_and_clear_bit(idx, cpuc->running))
1255                                 handled++;
1256                         continue;
1257                 }
1258
1259                 event = cpuc->events[idx];
1260
1261                 val = x86_perf_event_update(event);
1262                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1263                         continue;
1264
1265                 /*
1266                  * event overflow
1267                  */
1268                 handled++;
1269                 perf_sample_data_init(&data, 0, event->hw.last_period);
1270
1271                 if (!x86_perf_event_set_period(event))
1272                         continue;
1273
1274                 if (perf_event_overflow(event, &data, regs))
1275                         x86_pmu_stop(event, 0);
1276         }
1277
1278         if (handled)
1279                 inc_irq_stat(apic_perf_irqs);
1280
1281         return handled;
1282 }
1283
1284 void perf_events_lapic_init(void)
1285 {
1286         if (!x86_pmu.apic || !x86_pmu_initialized())
1287                 return;
1288
1289         /*
1290          * Always use NMI for PMU
1291          */
1292         apic_write(APIC_LVTPC, APIC_DM_NMI);
1293 }
1294
1295 static int
1296 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1297 {
1298         u64 start_clock;
1299         u64 finish_clock;
1300         int ret;
1301
1302         if (!atomic_read(&active_events))
1303                 return NMI_DONE;
1304
1305         start_clock = sched_clock();
1306         ret = x86_pmu.handle_irq(regs);
1307         finish_clock = sched_clock();
1308
1309         perf_sample_event_took(finish_clock - start_clock);
1310
1311         return ret;
1312 }
1313 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1314
1315 struct event_constraint emptyconstraint;
1316 struct event_constraint unconstrained;
1317
1318 static int
1319 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1320 {
1321         unsigned int cpu = (long)hcpu;
1322         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1323         int ret = NOTIFY_OK;
1324
1325         switch (action & ~CPU_TASKS_FROZEN) {
1326         case CPU_UP_PREPARE:
1327                 cpuc->kfree_on_online = NULL;
1328                 if (x86_pmu.cpu_prepare)
1329                         ret = x86_pmu.cpu_prepare(cpu);
1330                 break;
1331
1332         case CPU_STARTING:
1333                 if (x86_pmu.attr_rdpmc)
1334                         set_in_cr4(X86_CR4_PCE);
1335                 if (x86_pmu.cpu_starting)
1336                         x86_pmu.cpu_starting(cpu);
1337                 break;
1338
1339         case CPU_ONLINE:
1340                 kfree(cpuc->kfree_on_online);
1341                 break;
1342
1343         case CPU_DYING:
1344                 if (x86_pmu.cpu_dying)
1345                         x86_pmu.cpu_dying(cpu);
1346                 break;
1347
1348         case CPU_UP_CANCELED:
1349         case CPU_DEAD:
1350                 if (x86_pmu.cpu_dead)
1351                         x86_pmu.cpu_dead(cpu);
1352                 break;
1353
1354         default:
1355                 break;
1356         }
1357
1358         return ret;
1359 }
1360
1361 static void __init pmu_check_apic(void)
1362 {
1363         if (cpu_has_apic)
1364                 return;
1365
1366         x86_pmu.apic = 0;
1367         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1368         pr_info("no hardware sampling interrupt available.\n");
1369 }
1370
1371 static struct attribute_group x86_pmu_format_group = {
1372         .name = "format",
1373         .attrs = NULL,
1374 };
1375
1376 /*
1377  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1378  * out of events_attr attributes.
1379  */
1380 static void __init filter_events(struct attribute **attrs)
1381 {
1382         struct device_attribute *d;
1383         struct perf_pmu_events_attr *pmu_attr;
1384         int i, j;
1385
1386         for (i = 0; attrs[i]; i++) {
1387                 d = (struct device_attribute *)attrs[i];
1388                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1389                 /* str trumps id */
1390                 if (pmu_attr->event_str)
1391                         continue;
1392                 if (x86_pmu.event_map(i))
1393                         continue;
1394
1395                 for (j = i; attrs[j]; j++)
1396                         attrs[j] = attrs[j + 1];
1397
1398                 /* Check the shifted attr. */
1399                 i--;
1400         }
1401 }
1402
1403 /* Merge two pointer arrays */
1404 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1405 {
1406         struct attribute **new;
1407         int j, i;
1408
1409         for (j = 0; a[j]; j++)
1410                 ;
1411         for (i = 0; b[i]; i++)
1412                 j++;
1413         j++;
1414
1415         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1416         if (!new)
1417                 return NULL;
1418
1419         j = 0;
1420         for (i = 0; a[i]; i++)
1421                 new[j++] = a[i];
1422         for (i = 0; b[i]; i++)
1423                 new[j++] = b[i];
1424         new[j] = NULL;
1425
1426         return new;
1427 }
1428
1429 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1430                           char *page)
1431 {
1432         struct perf_pmu_events_attr *pmu_attr = \
1433                 container_of(attr, struct perf_pmu_events_attr, attr);
1434         u64 config = x86_pmu.event_map(pmu_attr->id);
1435
1436         /* string trumps id */
1437         if (pmu_attr->event_str)
1438                 return sprintf(page, "%s", pmu_attr->event_str);
1439
1440         return x86_pmu.events_sysfs_show(page, config);
1441 }
1442
1443 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1444 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1445 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1446 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1447 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1448 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1449 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1450 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1451 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1452 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1453
1454 static struct attribute *empty_attrs;
1455
1456 static struct attribute *events_attr[] = {
1457         EVENT_PTR(CPU_CYCLES),
1458         EVENT_PTR(INSTRUCTIONS),
1459         EVENT_PTR(CACHE_REFERENCES),
1460         EVENT_PTR(CACHE_MISSES),
1461         EVENT_PTR(BRANCH_INSTRUCTIONS),
1462         EVENT_PTR(BRANCH_MISSES),
1463         EVENT_PTR(BUS_CYCLES),
1464         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1465         EVENT_PTR(STALLED_CYCLES_BACKEND),
1466         EVENT_PTR(REF_CPU_CYCLES),
1467         NULL,
1468 };
1469
1470 static struct attribute_group x86_pmu_events_group = {
1471         .name = "events",
1472         .attrs = events_attr,
1473 };
1474
1475 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1476 {
1477         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1478         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1479         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1480         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1481         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1482         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1483         ssize_t ret;
1484
1485         /*
1486         * We have whole page size to spend and just little data
1487         * to write, so we can safely use sprintf.
1488         */
1489         ret = sprintf(page, "event=0x%02llx", event);
1490
1491         if (umask)
1492                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1493
1494         if (edge)
1495                 ret += sprintf(page + ret, ",edge");
1496
1497         if (pc)
1498                 ret += sprintf(page + ret, ",pc");
1499
1500         if (any)
1501                 ret += sprintf(page + ret, ",any");
1502
1503         if (inv)
1504                 ret += sprintf(page + ret, ",inv");
1505
1506         if (cmask)
1507                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1508
1509         ret += sprintf(page + ret, "\n");
1510
1511         return ret;
1512 }
1513
1514 static int __init init_hw_perf_events(void)
1515 {
1516         struct x86_pmu_quirk *quirk;
1517         int err;
1518
1519         pr_info("Performance Events: ");
1520
1521         switch (boot_cpu_data.x86_vendor) {
1522         case X86_VENDOR_INTEL:
1523                 err = intel_pmu_init();
1524                 break;
1525         case X86_VENDOR_AMD:
1526                 err = amd_pmu_init();
1527                 break;
1528         default:
1529                 err = -ENOTSUPP;
1530         }
1531         if (err != 0) {
1532                 pr_cont("no PMU driver, software events only.\n");
1533                 return 0;
1534         }
1535
1536         pmu_check_apic();
1537
1538         /* sanity check that the hardware exists or is emulated */
1539         if (!check_hw_exists())
1540                 return 0;
1541
1542         pr_cont("%s PMU driver.\n", x86_pmu.name);
1543
1544         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1545
1546         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1547                 quirk->func();
1548
1549         if (!x86_pmu.intel_ctrl)
1550                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1551
1552         perf_events_lapic_init();
1553         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1554
1555         unconstrained = (struct event_constraint)
1556                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1557                                    0, x86_pmu.num_counters, 0, 0);
1558
1559         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1560
1561         if (x86_pmu.event_attrs)
1562                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1563
1564         if (!x86_pmu.events_sysfs_show)
1565                 x86_pmu_events_group.attrs = &empty_attrs;
1566         else
1567                 filter_events(x86_pmu_events_group.attrs);
1568
1569         if (x86_pmu.cpu_events) {
1570                 struct attribute **tmp;
1571
1572                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1573                 if (!WARN_ON(!tmp))
1574                         x86_pmu_events_group.attrs = tmp;
1575         }
1576
1577         pr_info("... version:                %d\n",     x86_pmu.version);
1578         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1579         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1580         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1581         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1582         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1583         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1584
1585         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1586         perf_cpu_notifier(x86_pmu_notifier);
1587
1588         return 0;
1589 }
1590 early_initcall(init_hw_perf_events);
1591
1592 static inline void x86_pmu_read(struct perf_event *event)
1593 {
1594         x86_perf_event_update(event);
1595 }
1596
1597 /*
1598  * Start group events scheduling transaction
1599  * Set the flag to make pmu::enable() not perform the
1600  * schedulability test, it will be performed at commit time
1601  */
1602 static void x86_pmu_start_txn(struct pmu *pmu)
1603 {
1604         perf_pmu_disable(pmu);
1605         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1606         __this_cpu_write(cpu_hw_events.n_txn, 0);
1607 }
1608
1609 /*
1610  * Stop group events scheduling transaction
1611  * Clear the flag and pmu::enable() will perform the
1612  * schedulability test.
1613  */
1614 static void x86_pmu_cancel_txn(struct pmu *pmu)
1615 {
1616         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1617         /*
1618          * Truncate collected array by the number of events added in this
1619          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1620          */
1621         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1622         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1623         perf_pmu_enable(pmu);
1624 }
1625
1626 /*
1627  * Commit group events scheduling transaction
1628  * Perform the group schedulability test as a whole
1629  * Return 0 if success
1630  *
1631  * Does not cancel the transaction on failure; expects the caller to do this.
1632  */
1633 static int x86_pmu_commit_txn(struct pmu *pmu)
1634 {
1635         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1636         int assign[X86_PMC_IDX_MAX];
1637         int n, ret;
1638
1639         n = cpuc->n_events;
1640
1641         if (!x86_pmu_initialized())
1642                 return -EAGAIN;
1643
1644         ret = x86_pmu.schedule_events(cpuc, n, assign);
1645         if (ret)
1646                 return ret;
1647
1648         /*
1649          * copy new assignment, now we know it is possible
1650          * will be used by hw_perf_enable()
1651          */
1652         memcpy(cpuc->assign, assign, n*sizeof(int));
1653
1654         cpuc->group_flag &= ~PERF_EVENT_TXN;
1655         perf_pmu_enable(pmu);
1656         return 0;
1657 }
1658 /*
1659  * a fake_cpuc is used to validate event groups. Due to
1660  * the extra reg logic, we need to also allocate a fake
1661  * per_core and per_cpu structure. Otherwise, group events
1662  * using extra reg may conflict without the kernel being
1663  * able to catch this when the last event gets added to
1664  * the group.
1665  */
1666 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1667 {
1668         kfree(cpuc->shared_regs);
1669         kfree(cpuc);
1670 }
1671
1672 static struct cpu_hw_events *allocate_fake_cpuc(void)
1673 {
1674         struct cpu_hw_events *cpuc;
1675         int cpu = raw_smp_processor_id();
1676
1677         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1678         if (!cpuc)
1679                 return ERR_PTR(-ENOMEM);
1680
1681         /* only needed, if we have extra_regs */
1682         if (x86_pmu.extra_regs) {
1683                 cpuc->shared_regs = allocate_shared_regs(cpu);
1684                 if (!cpuc->shared_regs)
1685                         goto error;
1686         }
1687         cpuc->is_fake = 1;
1688         return cpuc;
1689 error:
1690         free_fake_cpuc(cpuc);
1691         return ERR_PTR(-ENOMEM);
1692 }
1693
1694 /*
1695  * validate that we can schedule this event
1696  */
1697 static int validate_event(struct perf_event *event)
1698 {
1699         struct cpu_hw_events *fake_cpuc;
1700         struct event_constraint *c;
1701         int ret = 0;
1702
1703         fake_cpuc = allocate_fake_cpuc();
1704         if (IS_ERR(fake_cpuc))
1705                 return PTR_ERR(fake_cpuc);
1706
1707         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1708
1709         if (!c || !c->weight)
1710                 ret = -EINVAL;
1711
1712         if (x86_pmu.put_event_constraints)
1713                 x86_pmu.put_event_constraints(fake_cpuc, event);
1714
1715         free_fake_cpuc(fake_cpuc);
1716
1717         return ret;
1718 }
1719
1720 /*
1721  * validate a single event group
1722  *
1723  * validation include:
1724  *      - check events are compatible which each other
1725  *      - events do not compete for the same counter
1726  *      - number of events <= number of counters
1727  *
1728  * validation ensures the group can be loaded onto the
1729  * PMU if it was the only group available.
1730  */
1731 static int validate_group(struct perf_event *event)
1732 {
1733         struct perf_event *leader = event->group_leader;
1734         struct cpu_hw_events *fake_cpuc;
1735         int ret = -EINVAL, n;
1736
1737         fake_cpuc = allocate_fake_cpuc();
1738         if (IS_ERR(fake_cpuc))
1739                 return PTR_ERR(fake_cpuc);
1740         /*
1741          * the event is not yet connected with its
1742          * siblings therefore we must first collect
1743          * existing siblings, then add the new event
1744          * before we can simulate the scheduling
1745          */
1746         n = collect_events(fake_cpuc, leader, true);
1747         if (n < 0)
1748                 goto out;
1749
1750         fake_cpuc->n_events = n;
1751         n = collect_events(fake_cpuc, event, false);
1752         if (n < 0)
1753                 goto out;
1754
1755         fake_cpuc->n_events = n;
1756
1757         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1758
1759 out:
1760         free_fake_cpuc(fake_cpuc);
1761         return ret;
1762 }
1763
1764 static int x86_pmu_event_init(struct perf_event *event)
1765 {
1766         struct pmu *tmp;
1767         int err;
1768
1769         switch (event->attr.type) {
1770         case PERF_TYPE_RAW:
1771         case PERF_TYPE_HARDWARE:
1772         case PERF_TYPE_HW_CACHE:
1773                 break;
1774
1775         default:
1776                 return -ENOENT;
1777         }
1778
1779         err = __x86_pmu_event_init(event);
1780         if (!err) {
1781                 /*
1782                  * we temporarily connect event to its pmu
1783                  * such that validate_group() can classify
1784                  * it as an x86 event using is_x86_event()
1785                  */
1786                 tmp = event->pmu;
1787                 event->pmu = &pmu;
1788
1789                 if (event->group_leader != event)
1790                         err = validate_group(event);
1791                 else
1792                         err = validate_event(event);
1793
1794                 event->pmu = tmp;
1795         }
1796         if (err) {
1797                 if (event->destroy)
1798                         event->destroy(event);
1799         }
1800
1801         return err;
1802 }
1803
1804 static int x86_pmu_event_idx(struct perf_event *event)
1805 {
1806         int idx = event->hw.idx;
1807
1808         if (!x86_pmu.attr_rdpmc)
1809                 return 0;
1810
1811         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1812                 idx -= INTEL_PMC_IDX_FIXED;
1813                 idx |= 1 << 30;
1814         }
1815
1816         return idx + 1;
1817 }
1818
1819 static ssize_t get_attr_rdpmc(struct device *cdev,
1820                               struct device_attribute *attr,
1821                               char *buf)
1822 {
1823         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1824 }
1825
1826 static void change_rdpmc(void *info)
1827 {
1828         bool enable = !!(unsigned long)info;
1829
1830         if (enable)
1831                 set_in_cr4(X86_CR4_PCE);
1832         else
1833                 clear_in_cr4(X86_CR4_PCE);
1834 }
1835
1836 static ssize_t set_attr_rdpmc(struct device *cdev,
1837                               struct device_attribute *attr,
1838                               const char *buf, size_t count)
1839 {
1840         unsigned long val;
1841         ssize_t ret;
1842
1843         ret = kstrtoul(buf, 0, &val);
1844         if (ret)
1845                 return ret;
1846
1847         if (x86_pmu.attr_rdpmc_broken)
1848                 return -ENOTSUPP;
1849
1850         if (!!val != !!x86_pmu.attr_rdpmc) {
1851                 x86_pmu.attr_rdpmc = !!val;
1852                 on_each_cpu(change_rdpmc, (void *)val, 1);
1853         }
1854
1855         return count;
1856 }
1857
1858 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1859
1860 static struct attribute *x86_pmu_attrs[] = {
1861         &dev_attr_rdpmc.attr,
1862         NULL,
1863 };
1864
1865 static struct attribute_group x86_pmu_attr_group = {
1866         .attrs = x86_pmu_attrs,
1867 };
1868
1869 static const struct attribute_group *x86_pmu_attr_groups[] = {
1870         &x86_pmu_attr_group,
1871         &x86_pmu_format_group,
1872         &x86_pmu_events_group,
1873         NULL,
1874 };
1875
1876 static void x86_pmu_flush_branch_stack(void)
1877 {
1878         if (x86_pmu.flush_branch_stack)
1879                 x86_pmu.flush_branch_stack();
1880 }
1881
1882 void perf_check_microcode(void)
1883 {
1884         if (x86_pmu.check_microcode)
1885                 x86_pmu.check_microcode();
1886 }
1887 EXPORT_SYMBOL_GPL(perf_check_microcode);
1888
1889 static struct pmu pmu = {
1890         .pmu_enable             = x86_pmu_enable,
1891         .pmu_disable            = x86_pmu_disable,
1892
1893         .attr_groups            = x86_pmu_attr_groups,
1894
1895         .event_init             = x86_pmu_event_init,
1896
1897         .add                    = x86_pmu_add,
1898         .del                    = x86_pmu_del,
1899         .start                  = x86_pmu_start,
1900         .stop                   = x86_pmu_stop,
1901         .read                   = x86_pmu_read,
1902
1903         .start_txn              = x86_pmu_start_txn,
1904         .cancel_txn             = x86_pmu_cancel_txn,
1905         .commit_txn             = x86_pmu_commit_txn,
1906
1907         .event_idx              = x86_pmu_event_idx,
1908         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1909 };
1910
1911 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1912 {
1913         struct cyc2ns_data *data;
1914
1915         userpg->cap_user_time = 0;
1916         userpg->cap_user_time_zero = 0;
1917         userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1918         userpg->pmc_width = x86_pmu.cntval_bits;
1919
1920         if (!sched_clock_stable())
1921                 return;
1922
1923         data = cyc2ns_read_begin();
1924
1925         userpg->cap_user_time = 1;
1926         userpg->time_mult = data->cyc2ns_mul;
1927         userpg->time_shift = data->cyc2ns_shift;
1928         userpg->time_offset = data->cyc2ns_offset - now;
1929
1930         userpg->cap_user_time_zero = 1;
1931         userpg->time_zero = data->cyc2ns_offset;
1932
1933         cyc2ns_read_end(data);
1934 }
1935
1936 /*
1937  * callchain support
1938  */
1939
1940 static int backtrace_stack(void *data, char *name)
1941 {
1942         return 0;
1943 }
1944
1945 static void backtrace_address(void *data, unsigned long addr, int reliable)
1946 {
1947         struct perf_callchain_entry *entry = data;
1948
1949         perf_callchain_store(entry, addr);
1950 }
1951
1952 static const struct stacktrace_ops backtrace_ops = {
1953         .stack                  = backtrace_stack,
1954         .address                = backtrace_address,
1955         .walk_stack             = print_context_stack_bp,
1956 };
1957
1958 void
1959 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1960 {
1961         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1962                 /* TODO: We don't support guest os callchain now */
1963                 return;
1964         }
1965
1966         perf_callchain_store(entry, regs->ip);
1967
1968         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1969 }
1970
1971 static inline int
1972 valid_user_frame(const void __user *fp, unsigned long size)
1973 {
1974         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1975 }
1976
1977 static unsigned long get_segment_base(unsigned int segment)
1978 {
1979         struct desc_struct *desc;
1980         int idx = segment >> 3;
1981
1982         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1983                 if (idx > LDT_ENTRIES)
1984                         return 0;
1985
1986                 if (idx > current->active_mm->context.size)
1987                         return 0;
1988
1989                 desc = current->active_mm->context.ldt;
1990         } else {
1991                 if (idx > GDT_ENTRIES)
1992                         return 0;
1993
1994                 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1995         }
1996
1997         return get_desc_base(desc + idx);
1998 }
1999
2000 #ifdef CONFIG_COMPAT
2001
2002 #include <asm/compat.h>
2003
2004 static inline int
2005 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2006 {
2007         /* 32-bit process in 64-bit kernel. */
2008         unsigned long ss_base, cs_base;
2009         struct stack_frame_ia32 frame;
2010         const void __user *fp;
2011
2012         if (!test_thread_flag(TIF_IA32))
2013                 return 0;
2014
2015         cs_base = get_segment_base(regs->cs);
2016         ss_base = get_segment_base(regs->ss);
2017
2018         fp = compat_ptr(ss_base + regs->bp);
2019         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2020                 unsigned long bytes;
2021                 frame.next_frame     = 0;
2022                 frame.return_address = 0;
2023
2024                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2025                 if (bytes != 0)
2026                         break;
2027
2028                 if (!valid_user_frame(fp, sizeof(frame)))
2029                         break;
2030
2031                 perf_callchain_store(entry, cs_base + frame.return_address);
2032                 fp = compat_ptr(ss_base + frame.next_frame);
2033         }
2034         return 1;
2035 }
2036 #else
2037 static inline int
2038 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2039 {
2040     return 0;
2041 }
2042 #endif
2043
2044 void
2045 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2046 {
2047         struct stack_frame frame;
2048         const void __user *fp;
2049
2050         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2051                 /* TODO: We don't support guest os callchain now */
2052                 return;
2053         }
2054
2055         /*
2056          * We don't know what to do with VM86 stacks.. ignore them for now.
2057          */
2058         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2059                 return;
2060
2061         fp = (void __user *)regs->bp;
2062
2063         perf_callchain_store(entry, regs->ip);
2064
2065         if (!current->mm)
2066                 return;
2067
2068         if (perf_callchain_user32(regs, entry))
2069                 return;
2070
2071         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2072                 unsigned long bytes;
2073                 frame.next_frame             = NULL;
2074                 frame.return_address = 0;
2075
2076                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2077                 if (bytes != 0)
2078                         break;
2079
2080                 if (!valid_user_frame(fp, sizeof(frame)))
2081                         break;
2082
2083                 perf_callchain_store(entry, frame.return_address);
2084                 fp = frame.next_frame;
2085         }
2086 }
2087
2088 /*
2089  * Deal with code segment offsets for the various execution modes:
2090  *
2091  *   VM86 - the good olde 16 bit days, where the linear address is
2092  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2093  *
2094  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2095  *          to figure out what the 32bit base address is.
2096  *
2097  *    X32 - has TIF_X32 set, but is running in x86_64
2098  *
2099  * X86_64 - CS,DS,SS,ES are all zero based.
2100  */
2101 static unsigned long code_segment_base(struct pt_regs *regs)
2102 {
2103         /*
2104          * If we are in VM86 mode, add the segment offset to convert to a
2105          * linear address.
2106          */
2107         if (regs->flags & X86_VM_MASK)
2108                 return 0x10 * regs->cs;
2109
2110         /*
2111          * For IA32 we look at the GDT/LDT segment base to convert the
2112          * effective IP to a linear address.
2113          */
2114 #ifdef CONFIG_X86_32
2115         if (user_mode(regs) && regs->cs != __USER_CS)
2116                 return get_segment_base(regs->cs);
2117 #else
2118         if (test_thread_flag(TIF_IA32)) {
2119                 if (user_mode(regs) && regs->cs != __USER32_CS)
2120                         return get_segment_base(regs->cs);
2121         }
2122 #endif
2123         return 0;
2124 }
2125
2126 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2127 {
2128         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2129                 return perf_guest_cbs->get_guest_ip();
2130
2131         return regs->ip + code_segment_base(regs);
2132 }
2133
2134 unsigned long perf_misc_flags(struct pt_regs *regs)
2135 {
2136         int misc = 0;
2137
2138         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2139                 if (perf_guest_cbs->is_user_mode())
2140                         misc |= PERF_RECORD_MISC_GUEST_USER;
2141                 else
2142                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2143         } else {
2144                 if (user_mode(regs))
2145                         misc |= PERF_RECORD_MISC_USER;
2146                 else
2147                         misc |= PERF_RECORD_MISC_KERNEL;
2148         }
2149
2150         if (regs->flags & PERF_EFLAGS_EXACT)
2151                 misc |= PERF_RECORD_MISC_EXACT_IP;
2152
2153         return misc;
2154 }
2155
2156 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2157 {
2158         cap->version            = x86_pmu.version;
2159         cap->num_counters_gp    = x86_pmu.num_counters;
2160         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2161         cap->bit_width_gp       = x86_pmu.cntval_bits;
2162         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2163         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2164         cap->events_mask_len    = x86_pmu.events_mask_len;
2165 }
2166 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);