2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/timer.h>
38 #include "perf_event.h"
40 struct x86_pmu x86_pmu __read_mostly;
42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
46 u64 __read_mostly hw_cache_event_ids
47 [PERF_COUNT_HW_CACHE_MAX]
48 [PERF_COUNT_HW_CACHE_OP_MAX]
49 [PERF_COUNT_HW_CACHE_RESULT_MAX];
50 u64 __read_mostly hw_cache_extra_regs
51 [PERF_COUNT_HW_CACHE_MAX]
52 [PERF_COUNT_HW_CACHE_OP_MAX]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX];
56 * Propagate event elapsed time into the generic event.
57 * Can only be executed on the CPU where the event is active.
58 * Returns the delta events processed.
60 u64 x86_perf_event_update(struct perf_event *event)
62 struct hw_perf_event *hwc = &event->hw;
63 int shift = 64 - x86_pmu.cntval_bits;
64 u64 prev_raw_count, new_raw_count;
68 if (idx == INTEL_PMC_IDX_FIXED_BTS)
72 * Careful: an NMI might modify the previous event value.
74 * Our tactic to handle this is to first atomically read and
75 * exchange a new raw count - then add that new-prev delta
76 * count to the generic event atomically:
79 prev_raw_count = local64_read(&hwc->prev_count);
80 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
82 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
83 new_raw_count) != prev_raw_count)
87 * Now we have the new raw value and have updated the prev
88 * timestamp already. We can now calculate the elapsed delta
89 * (event-)time and add that to the generic event.
91 * Careful, not all hw sign-extends above the physical width
94 delta = (new_raw_count << shift) - (prev_raw_count << shift);
97 local64_add(delta, &event->count);
98 local64_sub(delta, &hwc->period_left);
100 return new_raw_count;
104 * Find and validate any extra registers to set up.
106 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
108 struct hw_perf_event_extra *reg;
109 struct extra_reg *er;
111 reg = &event->hw.extra_reg;
113 if (!x86_pmu.extra_regs)
116 for (er = x86_pmu.extra_regs; er->msr; er++) {
117 if (er->event != (config & er->config_mask))
119 if (event->attr.config1 & ~er->valid_mask)
123 reg->config = event->attr.config1;
130 static atomic_t active_events;
131 static DEFINE_MUTEX(pmc_reserve_mutex);
133 #ifdef CONFIG_X86_LOCAL_APIC
135 static bool reserve_pmc_hardware(void)
139 for (i = 0; i < x86_pmu.num_counters; i++) {
140 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
144 for (i = 0; i < x86_pmu.num_counters; i++) {
145 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
152 for (i--; i >= 0; i--)
153 release_evntsel_nmi(x86_pmu_config_addr(i));
155 i = x86_pmu.num_counters;
158 for (i--; i >= 0; i--)
159 release_perfctr_nmi(x86_pmu_event_addr(i));
164 static void release_pmc_hardware(void)
168 for (i = 0; i < x86_pmu.num_counters; i++) {
169 release_perfctr_nmi(x86_pmu_event_addr(i));
170 release_evntsel_nmi(x86_pmu_config_addr(i));
176 static bool reserve_pmc_hardware(void) { return true; }
177 static void release_pmc_hardware(void) {}
181 static bool check_hw_exists(void)
183 u64 val, val_fail, val_new= ~0;
184 int i, reg, reg_fail, ret = 0;
188 * Check to see if the BIOS enabled any of the counters, if so
191 for (i = 0; i < x86_pmu.num_counters; i++) {
192 reg = x86_pmu_config_addr(i);
193 ret = rdmsrl_safe(reg, &val);
196 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
203 if (x86_pmu.num_counters_fixed) {
204 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
205 ret = rdmsrl_safe(reg, &val);
208 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
209 if (val & (0x03 << i*4)) {
218 * Read the current value, change it and read it back to see if it
219 * matches, this is needed to detect certain hardware emulators
220 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
222 reg = x86_pmu_event_addr(0);
223 if (rdmsrl_safe(reg, &val))
226 ret = wrmsrl_safe(reg, val);
227 ret |= rdmsrl_safe(reg, &val_new);
228 if (ret || val != val_new)
232 * We still allow the PMU driver to operate:
235 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
236 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
242 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
243 printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
248 static void hw_perf_event_destroy(struct perf_event *event)
250 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
251 release_pmc_hardware();
252 release_ds_buffers();
253 mutex_unlock(&pmc_reserve_mutex);
257 static inline int x86_pmu_initialized(void)
259 return x86_pmu.handle_irq != NULL;
263 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
265 struct perf_event_attr *attr = &event->attr;
266 unsigned int cache_type, cache_op, cache_result;
269 config = attr->config;
271 cache_type = (config >> 0) & 0xff;
272 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
275 cache_op = (config >> 8) & 0xff;
276 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
279 cache_result = (config >> 16) & 0xff;
280 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
283 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
292 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
293 return x86_pmu_extra_regs(val, event);
296 int x86_setup_perfctr(struct perf_event *event)
298 struct perf_event_attr *attr = &event->attr;
299 struct hw_perf_event *hwc = &event->hw;
302 if (!is_sampling_event(event)) {
303 hwc->sample_period = x86_pmu.max_period;
304 hwc->last_period = hwc->sample_period;
305 local64_set(&hwc->period_left, hwc->sample_period);
308 * If we have a PMU initialized but no APIC
309 * interrupts, we cannot sample hardware
310 * events (user-space has to fall back and
311 * sample via a hrtimer based software event):
317 if (attr->type == PERF_TYPE_RAW)
318 return x86_pmu_extra_regs(event->attr.config, event);
320 if (attr->type == PERF_TYPE_HW_CACHE)
321 return set_ext_hw_attr(hwc, event);
323 if (attr->config >= x86_pmu.max_events)
329 config = x86_pmu.event_map(attr->config);
340 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
341 !attr->freq && hwc->sample_period == 1) {
342 /* BTS is not supported by this architecture. */
343 if (!x86_pmu.bts_active)
346 /* BTS is currently only allowed for user-mode. */
347 if (!attr->exclude_kernel)
351 hwc->config |= config;
357 * check that branch_sample_type is compatible with
358 * settings needed for precise_ip > 1 which implies
359 * using the LBR to capture ALL taken branches at the
360 * priv levels of the measurement
362 static inline int precise_br_compat(struct perf_event *event)
364 u64 m = event->attr.branch_sample_type;
367 /* must capture all branches */
368 if (!(m & PERF_SAMPLE_BRANCH_ANY))
371 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
373 if (!event->attr.exclude_user)
374 b |= PERF_SAMPLE_BRANCH_USER;
376 if (!event->attr.exclude_kernel)
377 b |= PERF_SAMPLE_BRANCH_KERNEL;
380 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
386 int x86_pmu_hw_config(struct perf_event *event)
388 if (event->attr.precise_ip) {
391 /* Support for constant skid */
392 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
395 /* Support for IP fixup */
400 if (event->attr.precise_ip > precise)
403 * check that PEBS LBR correction does not conflict with
404 * whatever the user is asking with attr->branch_sample_type
406 if (event->attr.precise_ip > 1 &&
407 x86_pmu.intel_cap.pebs_format < 2) {
408 u64 *br_type = &event->attr.branch_sample_type;
410 if (has_branch_stack(event)) {
411 if (!precise_br_compat(event))
414 /* branch_sample_type is compatible */
418 * user did not specify branch_sample_type
420 * For PEBS fixups, we capture all
421 * the branches at the priv level of the
424 *br_type = PERF_SAMPLE_BRANCH_ANY;
426 if (!event->attr.exclude_user)
427 *br_type |= PERF_SAMPLE_BRANCH_USER;
429 if (!event->attr.exclude_kernel)
430 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
437 * (keep 'enabled' bit clear for now)
439 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
442 * Count user and OS events unless requested not to
444 if (!event->attr.exclude_user)
445 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
446 if (!event->attr.exclude_kernel)
447 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
449 if (event->attr.type == PERF_TYPE_RAW)
450 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
452 return x86_setup_perfctr(event);
456 * Setup the hardware configuration for a given attr_type
458 static int __x86_pmu_event_init(struct perf_event *event)
462 if (!x86_pmu_initialized())
466 if (!atomic_inc_not_zero(&active_events)) {
467 mutex_lock(&pmc_reserve_mutex);
468 if (atomic_read(&active_events) == 0) {
469 if (!reserve_pmc_hardware())
472 reserve_ds_buffers();
475 atomic_inc(&active_events);
476 mutex_unlock(&pmc_reserve_mutex);
481 event->destroy = hw_perf_event_destroy;
484 event->hw.last_cpu = -1;
485 event->hw.last_tag = ~0ULL;
488 event->hw.extra_reg.idx = EXTRA_REG_NONE;
489 event->hw.branch_reg.idx = EXTRA_REG_NONE;
491 return x86_pmu.hw_config(event);
494 void x86_pmu_disable_all(void)
496 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
499 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
502 if (!test_bit(idx, cpuc->active_mask))
504 rdmsrl(x86_pmu_config_addr(idx), val);
505 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
507 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
508 wrmsrl(x86_pmu_config_addr(idx), val);
512 static void x86_pmu_disable(struct pmu *pmu)
514 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
516 if (!x86_pmu_initialized())
526 x86_pmu.disable_all();
529 void x86_pmu_enable_all(int added)
531 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
534 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
535 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
537 if (!test_bit(idx, cpuc->active_mask))
540 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
544 static struct pmu pmu;
546 static inline int is_x86_event(struct perf_event *event)
548 return event->pmu == &pmu;
552 * Event scheduler state:
554 * Assign events iterating over all events and counters, beginning
555 * with events with least weights first. Keep the current iterator
556 * state in struct sched_state.
560 int event; /* event index */
561 int counter; /* counter index */
562 int unassigned; /* number of events to be assigned left */
563 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
566 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
567 #define SCHED_STATES_MAX 2
572 struct perf_event **events;
573 struct sched_state state;
575 struct sched_state saved[SCHED_STATES_MAX];
579 * Initialize interator that runs through all events and counters.
581 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
582 int num, int wmin, int wmax)
586 memset(sched, 0, sizeof(*sched));
587 sched->max_events = num;
588 sched->max_weight = wmax;
589 sched->events = events;
591 for (idx = 0; idx < num; idx++) {
592 if (events[idx]->hw.constraint->weight == wmin)
596 sched->state.event = idx; /* start with min weight */
597 sched->state.weight = wmin;
598 sched->state.unassigned = num;
601 static void perf_sched_save_state(struct perf_sched *sched)
603 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
606 sched->saved[sched->saved_states] = sched->state;
607 sched->saved_states++;
610 static bool perf_sched_restore_state(struct perf_sched *sched)
612 if (!sched->saved_states)
615 sched->saved_states--;
616 sched->state = sched->saved[sched->saved_states];
618 /* continue with next counter: */
619 clear_bit(sched->state.counter++, sched->state.used);
625 * Select a counter for the current event to schedule. Return true on
628 static bool __perf_sched_find_counter(struct perf_sched *sched)
630 struct event_constraint *c;
633 if (!sched->state.unassigned)
636 if (sched->state.event >= sched->max_events)
639 c = sched->events[sched->state.event]->hw.constraint;
640 /* Prefer fixed purpose counters */
641 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
642 idx = INTEL_PMC_IDX_FIXED;
643 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
644 if (!__test_and_set_bit(idx, sched->state.used))
648 /* Grab the first unused counter starting with idx */
649 idx = sched->state.counter;
650 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
651 if (!__test_and_set_bit(idx, sched->state.used))
658 sched->state.counter = idx;
661 perf_sched_save_state(sched);
666 static bool perf_sched_find_counter(struct perf_sched *sched)
668 while (!__perf_sched_find_counter(sched)) {
669 if (!perf_sched_restore_state(sched))
677 * Go through all unassigned events and find the next one to schedule.
678 * Take events with the least weight first. Return true on success.
680 static bool perf_sched_next_event(struct perf_sched *sched)
682 struct event_constraint *c;
684 if (!sched->state.unassigned || !--sched->state.unassigned)
689 sched->state.event++;
690 if (sched->state.event >= sched->max_events) {
692 sched->state.event = 0;
693 sched->state.weight++;
694 if (sched->state.weight > sched->max_weight)
697 c = sched->events[sched->state.event]->hw.constraint;
698 } while (c->weight != sched->state.weight);
700 sched->state.counter = 0; /* start with first counter */
706 * Assign a counter for each event.
708 int perf_assign_events(struct perf_event **events, int n,
709 int wmin, int wmax, int *assign)
711 struct perf_sched sched;
713 perf_sched_init(&sched, events, n, wmin, wmax);
716 if (!perf_sched_find_counter(&sched))
719 assign[sched.state.event] = sched.state.counter;
720 } while (perf_sched_next_event(&sched));
722 return sched.state.unassigned;
725 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
727 struct event_constraint *c;
728 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
729 struct perf_event *e;
730 int i, wmin, wmax, num = 0;
731 struct hw_perf_event *hwc;
733 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
735 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
736 hwc = &cpuc->event_list[i]->hw;
737 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
740 wmin = min(wmin, c->weight);
741 wmax = max(wmax, c->weight);
745 * fastpath, try to reuse previous register
747 for (i = 0; i < n; i++) {
748 hwc = &cpuc->event_list[i]->hw;
755 /* constraint still honored */
756 if (!test_bit(hwc->idx, c->idxmsk))
759 /* not already used */
760 if (test_bit(hwc->idx, used_mask))
763 __set_bit(hwc->idx, used_mask);
765 assign[i] = hwc->idx;
770 num = perf_assign_events(cpuc->event_list, n, wmin,
774 * Mark the event as committed, so we do not put_constraint()
775 * in case new events are added and fail scheduling.
777 if (!num && assign) {
778 for (i = 0; i < n; i++) {
779 e = cpuc->event_list[i];
780 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
784 * scheduling failed or is just a simulation,
785 * free resources if necessary
787 if (!assign || num) {
788 for (i = 0; i < n; i++) {
789 e = cpuc->event_list[i];
791 * do not put_constraint() on comitted events,
792 * because they are good to go
794 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
797 if (x86_pmu.put_event_constraints)
798 x86_pmu.put_event_constraints(cpuc, e);
801 return num ? -EINVAL : 0;
805 * dogrp: true if must collect siblings events (group)
806 * returns total number of events and error code
808 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
810 struct perf_event *event;
813 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
815 /* current number of events already accepted */
818 if (is_x86_event(leader)) {
821 cpuc->event_list[n] = leader;
827 list_for_each_entry(event, &leader->sibling_list, group_entry) {
828 if (!is_x86_event(event) ||
829 event->state <= PERF_EVENT_STATE_OFF)
835 cpuc->event_list[n] = event;
841 static inline void x86_assign_hw_event(struct perf_event *event,
842 struct cpu_hw_events *cpuc, int i)
844 struct hw_perf_event *hwc = &event->hw;
846 hwc->idx = cpuc->assign[i];
847 hwc->last_cpu = smp_processor_id();
848 hwc->last_tag = ++cpuc->tags[i];
850 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
851 hwc->config_base = 0;
853 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
854 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
855 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
856 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
858 hwc->config_base = x86_pmu_config_addr(hwc->idx);
859 hwc->event_base = x86_pmu_event_addr(hwc->idx);
860 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
864 static inline int match_prev_assignment(struct hw_perf_event *hwc,
865 struct cpu_hw_events *cpuc,
868 return hwc->idx == cpuc->assign[i] &&
869 hwc->last_cpu == smp_processor_id() &&
870 hwc->last_tag == cpuc->tags[i];
873 static void x86_pmu_start(struct perf_event *event, int flags);
875 static void x86_pmu_enable(struct pmu *pmu)
877 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
878 struct perf_event *event;
879 struct hw_perf_event *hwc;
880 int i, added = cpuc->n_added;
882 if (!x86_pmu_initialized())
889 int n_running = cpuc->n_events - cpuc->n_added;
891 * apply assignment obtained either from
892 * hw_perf_group_sched_in() or x86_pmu_enable()
894 * step1: save events moving to new counters
895 * step2: reprogram moved events into new counters
897 for (i = 0; i < n_running; i++) {
898 event = cpuc->event_list[i];
902 * we can avoid reprogramming counter if:
903 * - assigned same counter as last time
904 * - running on same CPU as last time
905 * - no other event has used the counter since
907 if (hwc->idx == -1 ||
908 match_prev_assignment(hwc, cpuc, i))
912 * Ensure we don't accidentally enable a stopped
913 * counter simply because we rescheduled.
915 if (hwc->state & PERF_HES_STOPPED)
916 hwc->state |= PERF_HES_ARCH;
918 x86_pmu_stop(event, PERF_EF_UPDATE);
921 for (i = 0; i < cpuc->n_events; i++) {
922 event = cpuc->event_list[i];
925 if (!match_prev_assignment(hwc, cpuc, i))
926 x86_assign_hw_event(event, cpuc, i);
927 else if (i < n_running)
930 if (hwc->state & PERF_HES_ARCH)
933 x86_pmu_start(event, PERF_EF_RELOAD);
936 perf_events_lapic_init();
942 x86_pmu.enable_all(added);
945 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
948 * Set the next IRQ period, based on the hwc->period_left value.
949 * To be called with the event disabled in hw:
951 int x86_perf_event_set_period(struct perf_event *event)
953 struct hw_perf_event *hwc = &event->hw;
954 s64 left = local64_read(&hwc->period_left);
955 s64 period = hwc->sample_period;
956 int ret = 0, idx = hwc->idx;
958 if (idx == INTEL_PMC_IDX_FIXED_BTS)
962 * If we are way outside a reasonable range then just skip forward:
964 if (unlikely(left <= -period)) {
966 local64_set(&hwc->period_left, left);
967 hwc->last_period = period;
971 if (unlikely(left <= 0)) {
973 local64_set(&hwc->period_left, left);
974 hwc->last_period = period;
978 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
980 if (unlikely(left < 2))
983 if (left > x86_pmu.max_period)
984 left = x86_pmu.max_period;
986 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
989 * The hw event starts counting from this event offset,
990 * mark it to be able to extra future deltas:
992 local64_set(&hwc->prev_count, (u64)-left);
994 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
997 * Due to erratum on certan cpu we need
998 * a second write to be sure the register
999 * is updated properly
1001 if (x86_pmu.perfctr_second_write) {
1002 wrmsrl(hwc->event_base,
1003 (u64)(-left) & x86_pmu.cntval_mask);
1006 perf_event_update_userpage(event);
1011 void x86_pmu_enable_event(struct perf_event *event)
1013 if (__this_cpu_read(cpu_hw_events.enabled))
1014 __x86_pmu_enable_event(&event->hw,
1015 ARCH_PERFMON_EVENTSEL_ENABLE);
1019 * Add a single event to the PMU.
1021 * The event is added to the group of enabled events
1022 * but only if it can be scehduled with existing events.
1024 static int x86_pmu_add(struct perf_event *event, int flags)
1026 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1027 struct hw_perf_event *hwc;
1028 int assign[X86_PMC_IDX_MAX];
1033 perf_pmu_disable(event->pmu);
1034 n0 = cpuc->n_events;
1035 ret = n = collect_events(cpuc, event, false);
1039 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1040 if (!(flags & PERF_EF_START))
1041 hwc->state |= PERF_HES_ARCH;
1044 * If group events scheduling transaction was started,
1045 * skip the schedulability test here, it will be performed
1046 * at commit time (->commit_txn) as a whole
1048 if (cpuc->group_flag & PERF_EVENT_TXN)
1051 ret = x86_pmu.schedule_events(cpuc, n, assign);
1055 * copy new assignment, now we know it is possible
1056 * will be used by hw_perf_enable()
1058 memcpy(cpuc->assign, assign, n*sizeof(int));
1062 cpuc->n_added += n - n0;
1063 cpuc->n_txn += n - n0;
1067 perf_pmu_enable(event->pmu);
1071 static void x86_pmu_start(struct perf_event *event, int flags)
1073 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1074 int idx = event->hw.idx;
1076 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1079 if (WARN_ON_ONCE(idx == -1))
1082 if (flags & PERF_EF_RELOAD) {
1083 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1084 x86_perf_event_set_period(event);
1087 event->hw.state = 0;
1089 cpuc->events[idx] = event;
1090 __set_bit(idx, cpuc->active_mask);
1091 __set_bit(idx, cpuc->running);
1092 x86_pmu.enable(event);
1093 perf_event_update_userpage(event);
1096 void perf_event_print_debug(void)
1098 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1100 struct cpu_hw_events *cpuc;
1101 unsigned long flags;
1104 if (!x86_pmu.num_counters)
1107 local_irq_save(flags);
1109 cpu = smp_processor_id();
1110 cpuc = &per_cpu(cpu_hw_events, cpu);
1112 if (x86_pmu.version >= 2) {
1113 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1114 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1115 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1116 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1117 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1120 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1121 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1122 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1123 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1124 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1126 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1128 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1129 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1130 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1132 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1134 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1135 cpu, idx, pmc_ctrl);
1136 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1137 cpu, idx, pmc_count);
1138 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1139 cpu, idx, prev_left);
1141 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1142 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1144 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1145 cpu, idx, pmc_count);
1147 local_irq_restore(flags);
1150 void x86_pmu_stop(struct perf_event *event, int flags)
1152 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1153 struct hw_perf_event *hwc = &event->hw;
1155 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1156 x86_pmu.disable(event);
1157 cpuc->events[hwc->idx] = NULL;
1158 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1159 hwc->state |= PERF_HES_STOPPED;
1162 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1164 * Drain the remaining delta count out of a event
1165 * that we are disabling:
1167 x86_perf_event_update(event);
1168 hwc->state |= PERF_HES_UPTODATE;
1172 static void x86_pmu_del(struct perf_event *event, int flags)
1174 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1178 * event is descheduled
1180 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1183 * If we're called during a txn, we don't need to do anything.
1184 * The events never got scheduled and ->cancel_txn will truncate
1187 if (cpuc->group_flag & PERF_EVENT_TXN)
1190 x86_pmu_stop(event, PERF_EF_UPDATE);
1192 for (i = 0; i < cpuc->n_events; i++) {
1193 if (event == cpuc->event_list[i]) {
1195 if (i >= cpuc->n_events - cpuc->n_added)
1198 if (x86_pmu.put_event_constraints)
1199 x86_pmu.put_event_constraints(cpuc, event);
1201 while (++i < cpuc->n_events)
1202 cpuc->event_list[i-1] = cpuc->event_list[i];
1208 perf_event_update_userpage(event);
1211 int x86_pmu_handle_irq(struct pt_regs *regs)
1213 struct perf_sample_data data;
1214 struct cpu_hw_events *cpuc;
1215 struct perf_event *event;
1216 int idx, handled = 0;
1219 cpuc = &__get_cpu_var(cpu_hw_events);
1222 * Some chipsets need to unmask the LVTPC in a particular spot
1223 * inside the nmi handler. As a result, the unmasking was pushed
1224 * into all the nmi handlers.
1226 * This generic handler doesn't seem to have any issues where the
1227 * unmasking occurs so it was left at the top.
1229 apic_write(APIC_LVTPC, APIC_DM_NMI);
1231 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1232 if (!test_bit(idx, cpuc->active_mask)) {
1234 * Though we deactivated the counter some cpus
1235 * might still deliver spurious interrupts still
1236 * in flight. Catch them:
1238 if (__test_and_clear_bit(idx, cpuc->running))
1243 event = cpuc->events[idx];
1245 val = x86_perf_event_update(event);
1246 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1253 perf_sample_data_init(&data, 0, event->hw.last_period);
1255 if (!x86_perf_event_set_period(event))
1258 if (perf_event_overflow(event, &data, regs))
1259 x86_pmu_stop(event, 0);
1263 inc_irq_stat(apic_perf_irqs);
1268 void perf_events_lapic_init(void)
1270 if (!x86_pmu.apic || !x86_pmu_initialized())
1274 * Always use NMI for PMU
1276 apic_write(APIC_LVTPC, APIC_DM_NMI);
1279 static int __kprobes
1280 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1286 if (!atomic_read(&active_events))
1289 start_clock = sched_clock();
1290 ret = x86_pmu.handle_irq(regs);
1291 finish_clock = sched_clock();
1293 perf_sample_event_took(finish_clock - start_clock);
1298 struct event_constraint emptyconstraint;
1299 struct event_constraint unconstrained;
1302 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1304 unsigned int cpu = (long)hcpu;
1305 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1306 int ret = NOTIFY_OK;
1308 switch (action & ~CPU_TASKS_FROZEN) {
1309 case CPU_UP_PREPARE:
1310 cpuc->kfree_on_online = NULL;
1311 if (x86_pmu.cpu_prepare)
1312 ret = x86_pmu.cpu_prepare(cpu);
1316 if (x86_pmu.attr_rdpmc)
1317 set_in_cr4(X86_CR4_PCE);
1318 if (x86_pmu.cpu_starting)
1319 x86_pmu.cpu_starting(cpu);
1323 kfree(cpuc->kfree_on_online);
1327 if (x86_pmu.cpu_dying)
1328 x86_pmu.cpu_dying(cpu);
1331 case CPU_UP_CANCELED:
1333 if (x86_pmu.cpu_dead)
1334 x86_pmu.cpu_dead(cpu);
1344 static void __init pmu_check_apic(void)
1350 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1351 pr_info("no hardware sampling interrupt available.\n");
1354 static struct attribute_group x86_pmu_format_group = {
1360 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1361 * out of events_attr attributes.
1363 static void __init filter_events(struct attribute **attrs)
1365 struct device_attribute *d;
1366 struct perf_pmu_events_attr *pmu_attr;
1369 for (i = 0; attrs[i]; i++) {
1370 d = (struct device_attribute *)attrs[i];
1371 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1373 if (pmu_attr->event_str)
1375 if (x86_pmu.event_map(i))
1378 for (j = i; attrs[j]; j++)
1379 attrs[j] = attrs[j + 1];
1381 /* Check the shifted attr. */
1386 /* Merge two pointer arrays */
1387 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1389 struct attribute **new;
1392 for (j = 0; a[j]; j++)
1394 for (i = 0; b[i]; i++)
1398 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1403 for (i = 0; a[i]; i++)
1405 for (i = 0; b[i]; i++)
1412 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1415 struct perf_pmu_events_attr *pmu_attr = \
1416 container_of(attr, struct perf_pmu_events_attr, attr);
1417 u64 config = x86_pmu.event_map(pmu_attr->id);
1419 /* string trumps id */
1420 if (pmu_attr->event_str)
1421 return sprintf(page, "%s", pmu_attr->event_str);
1423 return x86_pmu.events_sysfs_show(page, config);
1426 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1427 EVENT_ATTR(instructions, INSTRUCTIONS );
1428 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1429 EVENT_ATTR(cache-misses, CACHE_MISSES );
1430 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1431 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1432 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1433 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1434 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1435 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1437 static struct attribute *empty_attrs;
1439 static struct attribute *events_attr[] = {
1440 EVENT_PTR(CPU_CYCLES),
1441 EVENT_PTR(INSTRUCTIONS),
1442 EVENT_PTR(CACHE_REFERENCES),
1443 EVENT_PTR(CACHE_MISSES),
1444 EVENT_PTR(BRANCH_INSTRUCTIONS),
1445 EVENT_PTR(BRANCH_MISSES),
1446 EVENT_PTR(BUS_CYCLES),
1447 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1448 EVENT_PTR(STALLED_CYCLES_BACKEND),
1449 EVENT_PTR(REF_CPU_CYCLES),
1453 static struct attribute_group x86_pmu_events_group = {
1455 .attrs = events_attr,
1458 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1460 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1461 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1462 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1463 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1464 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1465 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1469 * We have whole page size to spend and just little data
1470 * to write, so we can safely use sprintf.
1472 ret = sprintf(page, "event=0x%02llx", event);
1475 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1478 ret += sprintf(page + ret, ",edge");
1481 ret += sprintf(page + ret, ",pc");
1484 ret += sprintf(page + ret, ",any");
1487 ret += sprintf(page + ret, ",inv");
1490 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1492 ret += sprintf(page + ret, "\n");
1497 static int __init init_hw_perf_events(void)
1499 struct x86_pmu_quirk *quirk;
1502 pr_info("Performance Events: ");
1504 switch (boot_cpu_data.x86_vendor) {
1505 case X86_VENDOR_INTEL:
1506 err = intel_pmu_init();
1508 case X86_VENDOR_AMD:
1509 err = amd_pmu_init();
1515 pr_cont("no PMU driver, software events only.\n");
1521 /* sanity check that the hardware exists or is emulated */
1522 if (!check_hw_exists())
1525 pr_cont("%s PMU driver.\n", x86_pmu.name);
1527 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1529 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1532 if (!x86_pmu.intel_ctrl)
1533 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1535 perf_events_lapic_init();
1536 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1538 unconstrained = (struct event_constraint)
1539 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1540 0, x86_pmu.num_counters, 0, 0);
1542 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1544 if (x86_pmu.event_attrs)
1545 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1547 if (!x86_pmu.events_sysfs_show)
1548 x86_pmu_events_group.attrs = &empty_attrs;
1550 filter_events(x86_pmu_events_group.attrs);
1552 if (x86_pmu.cpu_events) {
1553 struct attribute **tmp;
1555 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1557 x86_pmu_events_group.attrs = tmp;
1560 pr_info("... version: %d\n", x86_pmu.version);
1561 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1562 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1563 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1564 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1565 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1566 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1568 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1569 perf_cpu_notifier(x86_pmu_notifier);
1573 early_initcall(init_hw_perf_events);
1575 static inline void x86_pmu_read(struct perf_event *event)
1577 x86_perf_event_update(event);
1581 * Start group events scheduling transaction
1582 * Set the flag to make pmu::enable() not perform the
1583 * schedulability test, it will be performed at commit time
1585 static void x86_pmu_start_txn(struct pmu *pmu)
1587 perf_pmu_disable(pmu);
1588 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1589 __this_cpu_write(cpu_hw_events.n_txn, 0);
1593 * Stop group events scheduling transaction
1594 * Clear the flag and pmu::enable() will perform the
1595 * schedulability test.
1597 static void x86_pmu_cancel_txn(struct pmu *pmu)
1599 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1601 * Truncate the collected events.
1603 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1604 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1605 perf_pmu_enable(pmu);
1609 * Commit group events scheduling transaction
1610 * Perform the group schedulability test as a whole
1611 * Return 0 if success
1613 static int x86_pmu_commit_txn(struct pmu *pmu)
1615 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1616 int assign[X86_PMC_IDX_MAX];
1621 if (!x86_pmu_initialized())
1624 ret = x86_pmu.schedule_events(cpuc, n, assign);
1629 * copy new assignment, now we know it is possible
1630 * will be used by hw_perf_enable()
1632 memcpy(cpuc->assign, assign, n*sizeof(int));
1634 cpuc->group_flag &= ~PERF_EVENT_TXN;
1635 perf_pmu_enable(pmu);
1639 * a fake_cpuc is used to validate event groups. Due to
1640 * the extra reg logic, we need to also allocate a fake
1641 * per_core and per_cpu structure. Otherwise, group events
1642 * using extra reg may conflict without the kernel being
1643 * able to catch this when the last event gets added to
1646 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1648 kfree(cpuc->shared_regs);
1652 static struct cpu_hw_events *allocate_fake_cpuc(void)
1654 struct cpu_hw_events *cpuc;
1655 int cpu = raw_smp_processor_id();
1657 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1659 return ERR_PTR(-ENOMEM);
1661 /* only needed, if we have extra_regs */
1662 if (x86_pmu.extra_regs) {
1663 cpuc->shared_regs = allocate_shared_regs(cpu);
1664 if (!cpuc->shared_regs)
1670 free_fake_cpuc(cpuc);
1671 return ERR_PTR(-ENOMEM);
1675 * validate that we can schedule this event
1677 static int validate_event(struct perf_event *event)
1679 struct cpu_hw_events *fake_cpuc;
1680 struct event_constraint *c;
1683 fake_cpuc = allocate_fake_cpuc();
1684 if (IS_ERR(fake_cpuc))
1685 return PTR_ERR(fake_cpuc);
1687 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1689 if (!c || !c->weight)
1692 if (x86_pmu.put_event_constraints)
1693 x86_pmu.put_event_constraints(fake_cpuc, event);
1695 free_fake_cpuc(fake_cpuc);
1701 * validate a single event group
1703 * validation include:
1704 * - check events are compatible which each other
1705 * - events do not compete for the same counter
1706 * - number of events <= number of counters
1708 * validation ensures the group can be loaded onto the
1709 * PMU if it was the only group available.
1711 static int validate_group(struct perf_event *event)
1713 struct perf_event *leader = event->group_leader;
1714 struct cpu_hw_events *fake_cpuc;
1715 int ret = -EINVAL, n;
1717 fake_cpuc = allocate_fake_cpuc();
1718 if (IS_ERR(fake_cpuc))
1719 return PTR_ERR(fake_cpuc);
1721 * the event is not yet connected with its
1722 * siblings therefore we must first collect
1723 * existing siblings, then add the new event
1724 * before we can simulate the scheduling
1726 n = collect_events(fake_cpuc, leader, true);
1730 fake_cpuc->n_events = n;
1731 n = collect_events(fake_cpuc, event, false);
1735 fake_cpuc->n_events = n;
1737 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1740 free_fake_cpuc(fake_cpuc);
1744 static int x86_pmu_event_init(struct perf_event *event)
1749 switch (event->attr.type) {
1751 case PERF_TYPE_HARDWARE:
1752 case PERF_TYPE_HW_CACHE:
1759 err = __x86_pmu_event_init(event);
1762 * we temporarily connect event to its pmu
1763 * such that validate_group() can classify
1764 * it as an x86 event using is_x86_event()
1769 if (event->group_leader != event)
1770 err = validate_group(event);
1772 err = validate_event(event);
1778 event->destroy(event);
1784 static int x86_pmu_event_idx(struct perf_event *event)
1786 int idx = event->hw.idx;
1788 if (!x86_pmu.attr_rdpmc)
1791 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1792 idx -= INTEL_PMC_IDX_FIXED;
1799 static ssize_t get_attr_rdpmc(struct device *cdev,
1800 struct device_attribute *attr,
1803 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1806 static void change_rdpmc(void *info)
1808 bool enable = !!(unsigned long)info;
1811 set_in_cr4(X86_CR4_PCE);
1813 clear_in_cr4(X86_CR4_PCE);
1816 static ssize_t set_attr_rdpmc(struct device *cdev,
1817 struct device_attribute *attr,
1818 const char *buf, size_t count)
1823 ret = kstrtoul(buf, 0, &val);
1827 if (x86_pmu.attr_rdpmc_broken)
1830 if (!!val != !!x86_pmu.attr_rdpmc) {
1831 x86_pmu.attr_rdpmc = !!val;
1832 on_each_cpu(change_rdpmc, (void *)val, 1);
1838 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1840 static struct attribute *x86_pmu_attrs[] = {
1841 &dev_attr_rdpmc.attr,
1845 static struct attribute_group x86_pmu_attr_group = {
1846 .attrs = x86_pmu_attrs,
1849 static const struct attribute_group *x86_pmu_attr_groups[] = {
1850 &x86_pmu_attr_group,
1851 &x86_pmu_format_group,
1852 &x86_pmu_events_group,
1856 static void x86_pmu_flush_branch_stack(void)
1858 if (x86_pmu.flush_branch_stack)
1859 x86_pmu.flush_branch_stack();
1862 void perf_check_microcode(void)
1864 if (x86_pmu.check_microcode)
1865 x86_pmu.check_microcode();
1867 EXPORT_SYMBOL_GPL(perf_check_microcode);
1869 static struct pmu pmu = {
1870 .pmu_enable = x86_pmu_enable,
1871 .pmu_disable = x86_pmu_disable,
1873 .attr_groups = x86_pmu_attr_groups,
1875 .event_init = x86_pmu_event_init,
1879 .start = x86_pmu_start,
1880 .stop = x86_pmu_stop,
1881 .read = x86_pmu_read,
1883 .start_txn = x86_pmu_start_txn,
1884 .cancel_txn = x86_pmu_cancel_txn,
1885 .commit_txn = x86_pmu_commit_txn,
1887 .event_idx = x86_pmu_event_idx,
1888 .flush_branch_stack = x86_pmu_flush_branch_stack,
1891 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1893 struct cyc2ns_data *data;
1895 userpg->cap_user_time = 0;
1896 userpg->cap_user_time_zero = 0;
1897 userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1898 userpg->pmc_width = x86_pmu.cntval_bits;
1900 if (!sched_clock_stable())
1903 data = cyc2ns_read_begin();
1905 userpg->cap_user_time = 1;
1906 userpg->time_mult = data->cyc2ns_mul;
1907 userpg->time_shift = data->cyc2ns_shift;
1908 userpg->time_offset = data->cyc2ns_offset - now;
1910 userpg->cap_user_time_zero = 1;
1911 userpg->time_zero = data->cyc2ns_offset;
1913 cyc2ns_read_end(data);
1920 static int backtrace_stack(void *data, char *name)
1925 static void backtrace_address(void *data, unsigned long addr, int reliable)
1927 struct perf_callchain_entry *entry = data;
1929 perf_callchain_store(entry, addr);
1932 static const struct stacktrace_ops backtrace_ops = {
1933 .stack = backtrace_stack,
1934 .address = backtrace_address,
1935 .walk_stack = print_context_stack_bp,
1939 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1941 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1942 /* TODO: We don't support guest os callchain now */
1946 perf_callchain_store(entry, regs->ip);
1948 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1952 valid_user_frame(const void __user *fp, unsigned long size)
1954 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1957 static unsigned long get_segment_base(unsigned int segment)
1959 struct desc_struct *desc;
1960 int idx = segment >> 3;
1962 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1963 if (idx > LDT_ENTRIES)
1966 if (idx > current->active_mm->context.size)
1969 desc = current->active_mm->context.ldt;
1971 if (idx > GDT_ENTRIES)
1974 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1977 return get_desc_base(desc + idx);
1980 #ifdef CONFIG_COMPAT
1982 #include <asm/compat.h>
1985 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1987 /* 32-bit process in 64-bit kernel. */
1988 unsigned long ss_base, cs_base;
1989 struct stack_frame_ia32 frame;
1990 const void __user *fp;
1992 if (!test_thread_flag(TIF_IA32))
1995 cs_base = get_segment_base(regs->cs);
1996 ss_base = get_segment_base(regs->ss);
1998 fp = compat_ptr(ss_base + regs->bp);
1999 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2000 unsigned long bytes;
2001 frame.next_frame = 0;
2002 frame.return_address = 0;
2004 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2008 if (!valid_user_frame(fp, sizeof(frame)))
2011 perf_callchain_store(entry, cs_base + frame.return_address);
2012 fp = compat_ptr(ss_base + frame.next_frame);
2018 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2025 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2027 struct stack_frame frame;
2028 const void __user *fp;
2030 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2031 /* TODO: We don't support guest os callchain now */
2036 * We don't know what to do with VM86 stacks.. ignore them for now.
2038 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2041 fp = (void __user *)regs->bp;
2043 perf_callchain_store(entry, regs->ip);
2048 if (perf_callchain_user32(regs, entry))
2051 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2052 unsigned long bytes;
2053 frame.next_frame = NULL;
2054 frame.return_address = 0;
2056 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2060 if (!valid_user_frame(fp, sizeof(frame)))
2063 perf_callchain_store(entry, frame.return_address);
2064 fp = frame.next_frame;
2069 * Deal with code segment offsets for the various execution modes:
2071 * VM86 - the good olde 16 bit days, where the linear address is
2072 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2074 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2075 * to figure out what the 32bit base address is.
2077 * X32 - has TIF_X32 set, but is running in x86_64
2079 * X86_64 - CS,DS,SS,ES are all zero based.
2081 static unsigned long code_segment_base(struct pt_regs *regs)
2084 * If we are in VM86 mode, add the segment offset to convert to a
2087 if (regs->flags & X86_VM_MASK)
2088 return 0x10 * regs->cs;
2091 * For IA32 we look at the GDT/LDT segment base to convert the
2092 * effective IP to a linear address.
2094 #ifdef CONFIG_X86_32
2095 if (user_mode(regs) && regs->cs != __USER_CS)
2096 return get_segment_base(regs->cs);
2098 if (test_thread_flag(TIF_IA32)) {
2099 if (user_mode(regs) && regs->cs != __USER32_CS)
2100 return get_segment_base(regs->cs);
2106 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2108 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2109 return perf_guest_cbs->get_guest_ip();
2111 return regs->ip + code_segment_base(regs);
2114 unsigned long perf_misc_flags(struct pt_regs *regs)
2118 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2119 if (perf_guest_cbs->is_user_mode())
2120 misc |= PERF_RECORD_MISC_GUEST_USER;
2122 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2124 if (user_mode(regs))
2125 misc |= PERF_RECORD_MISC_USER;
2127 misc |= PERF_RECORD_MISC_KERNEL;
2130 if (regs->flags & PERF_EFLAGS_EXACT)
2131 misc |= PERF_RECORD_MISC_EXACT_IP;
2136 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2138 cap->version = x86_pmu.version;
2139 cap->num_counters_gp = x86_pmu.num_counters;
2140 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2141 cap->bit_width_gp = x86_pmu.cntval_bits;
2142 cap->bit_width_fixed = x86_pmu.cntval_bits;
2143 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2144 cap->events_mask_len = x86_pmu.events_mask_len;
2146 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);