2 * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
3 * Copyright (C) 2013 Google, Inc., Stephane Eranian
5 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
6 * section 14.7.1 (September 2013)
8 * RAPL provides more controls than just reporting energy consumption
9 * however here we only expose the 3 energy consumption free running
10 * counters (pp0, pkg, dram).
12 * Each of those counters increments in a power unit defined by the
13 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules
16 * Counter to rapl events mappings:
18 * pp0 counter: consumption of all physical cores (power plane 0)
19 * event: rapl_energy_cores
22 * pkg counter: consumption of the whole processor package
23 * event: rapl_energy_pkg
26 * dram counter: consumption of the dram domain (servers only)
27 * event: rapl_energy_dram
30 * dram counter: consumption of the builtin-gpu domain (client only)
31 * event: rapl_energy_gpu
34 * We manage those counters as free running (read-only). They may be
35 * use simultaneously by other tools, such as turbostat.
37 * The events only support system-wide mode counting. There is no
38 * sampling support because it does not make sense and is not
39 * supported by the RAPL hardware.
41 * Because we want to avoid floating-point operations in the kernel,
42 * the events are all reported in fixed point arithmetic (32.32).
43 * Tools must adjust the counts to convert them to Watts using
44 * the duration of the measurement. Tools may use a function such as
45 * ldexp(raw_count, -32);
47 #include <linux/module.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <asm/cpu_device_id.h>
51 #include "perf_event.h"
54 * RAPL energy status counters
56 #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */
57 #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */
58 #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */
59 #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
60 #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
61 #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
62 #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */
63 #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
65 #define NR_RAPL_DOMAINS 0x4
66 static const char *rapl_domain_names[NR_RAPL_DOMAINS] __initconst = {
73 /* Clients have PP0, PKG */
74 #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
75 1<<RAPL_IDX_PKG_NRG_STAT|\
76 1<<RAPL_IDX_PP1_NRG_STAT)
78 /* Servers have PP0, PKG, RAM */
79 #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
80 1<<RAPL_IDX_PKG_NRG_STAT|\
81 1<<RAPL_IDX_RAM_NRG_STAT)
83 /* Servers have PP0, PKG, RAM, PP1 */
84 #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\
85 1<<RAPL_IDX_PKG_NRG_STAT|\
86 1<<RAPL_IDX_RAM_NRG_STAT|\
87 1<<RAPL_IDX_PP1_NRG_STAT)
89 /* Knights Landing has PKG, RAM */
90 #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\
91 1<<RAPL_IDX_RAM_NRG_STAT)
94 * event code: LSB 8 bits, passed in attr->config
95 * any other bit is reserved
97 #define RAPL_EVENT_MASK 0xFFULL
99 #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \
100 static ssize_t __rapl_##_var##_show(struct kobject *kobj, \
101 struct kobj_attribute *attr, \
104 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
105 return sprintf(page, _format "\n"); \
107 static struct kobj_attribute format_attr_##_var = \
108 __ATTR(_name, 0444, __rapl_##_var##_show, NULL)
110 #define RAPL_EVENT_DESC(_name, _config) \
112 .attr = __ATTR(_name, 0444, rapl_event_show, NULL), \
116 #define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */
118 #define RAPL_EVENT_ATTR_STR(_name, v, str) \
119 static struct perf_pmu_events_attr event_attr_##v = { \
120 .attr = __ATTR(_name, 0444, rapl_sysfs_show, NULL), \
127 int n_active; /* number of active events */
128 struct list_head active_list;
129 struct pmu *pmu; /* pointer to rapl_pmu_class */
130 ktime_t timer_interval; /* in ktime_t unit */
131 struct hrtimer hrtimer;
134 static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; /* 1/2^hw_unit Joule */
135 static struct pmu rapl_pmu_class;
136 static cpumask_t rapl_cpu_mask;
137 static int rapl_cntr_mask;
139 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu);
140 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu_to_free);
142 static struct x86_pmu_quirk *rapl_quirks;
143 static inline u64 rapl_read_counter(struct perf_event *event)
146 rdmsrl(event->hw.event_base, raw);
150 #define rapl_add_quirk(func_) \
152 static struct x86_pmu_quirk __quirk __initdata = { \
155 __quirk.next = rapl_quirks; \
156 rapl_quirks = &__quirk; \
159 static inline u64 rapl_scale(u64 v, int cfg)
161 if (cfg > NR_RAPL_DOMAINS) {
162 pr_warn("invalid domain %d, failed to scale data\n", cfg);
166 * scale delta to smallest unit (1/2^32)
167 * users must then scale back: count * 1/(1e9*2^32) to get Joules
168 * or use ldexp(count, -32).
169 * Watts = Joules/Time delta
171 return v << (32 - rapl_hw_unit[cfg - 1]);
174 static u64 rapl_event_update(struct perf_event *event)
176 struct hw_perf_event *hwc = &event->hw;
177 u64 prev_raw_count, new_raw_count;
179 int shift = RAPL_CNTR_WIDTH;
182 prev_raw_count = local64_read(&hwc->prev_count);
183 rdmsrl(event->hw.event_base, new_raw_count);
185 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
186 new_raw_count) != prev_raw_count) {
192 * Now we have the new raw value and have updated the prev
193 * timestamp already. We can now calculate the elapsed delta
194 * (event-)time and add that to the generic event.
196 * Careful, not all hw sign-extends above the physical width
199 delta = (new_raw_count << shift) - (prev_raw_count << shift);
202 sdelta = rapl_scale(delta, event->hw.config);
204 local64_add(sdelta, &event->count);
206 return new_raw_count;
209 static void rapl_start_hrtimer(struct rapl_pmu *pmu)
211 hrtimer_start(&pmu->hrtimer, pmu->timer_interval,
212 HRTIMER_MODE_REL_PINNED);
215 static void rapl_stop_hrtimer(struct rapl_pmu *pmu)
217 hrtimer_cancel(&pmu->hrtimer);
220 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
222 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
223 struct perf_event *event;
227 return HRTIMER_NORESTART;
229 spin_lock_irqsave(&pmu->lock, flags);
231 list_for_each_entry(event, &pmu->active_list, active_entry) {
232 rapl_event_update(event);
235 spin_unlock_irqrestore(&pmu->lock, flags);
237 hrtimer_forward_now(hrtimer, pmu->timer_interval);
239 return HRTIMER_RESTART;
242 static void rapl_hrtimer_init(struct rapl_pmu *pmu)
244 struct hrtimer *hr = &pmu->hrtimer;
246 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
247 hr->function = rapl_hrtimer_handle;
250 static void __rapl_pmu_event_start(struct rapl_pmu *pmu,
251 struct perf_event *event)
253 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
258 list_add_tail(&event->active_entry, &pmu->active_list);
260 local64_set(&event->hw.prev_count, rapl_read_counter(event));
263 if (pmu->n_active == 1)
264 rapl_start_hrtimer(pmu);
267 static void rapl_pmu_event_start(struct perf_event *event, int mode)
269 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
272 spin_lock_irqsave(&pmu->lock, flags);
273 __rapl_pmu_event_start(pmu, event);
274 spin_unlock_irqrestore(&pmu->lock, flags);
277 static void rapl_pmu_event_stop(struct perf_event *event, int mode)
279 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
280 struct hw_perf_event *hwc = &event->hw;
283 spin_lock_irqsave(&pmu->lock, flags);
285 /* mark event as deactivated and stopped */
286 if (!(hwc->state & PERF_HES_STOPPED)) {
287 WARN_ON_ONCE(pmu->n_active <= 0);
289 if (pmu->n_active == 0)
290 rapl_stop_hrtimer(pmu);
292 list_del(&event->active_entry);
294 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
295 hwc->state |= PERF_HES_STOPPED;
298 /* check if update of sw counter is necessary */
299 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
301 * Drain the remaining delta count out of a event
302 * that we are disabling:
304 rapl_event_update(event);
305 hwc->state |= PERF_HES_UPTODATE;
308 spin_unlock_irqrestore(&pmu->lock, flags);
311 static int rapl_pmu_event_add(struct perf_event *event, int mode)
313 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
314 struct hw_perf_event *hwc = &event->hw;
317 spin_lock_irqsave(&pmu->lock, flags);
319 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
321 if (mode & PERF_EF_START)
322 __rapl_pmu_event_start(pmu, event);
324 spin_unlock_irqrestore(&pmu->lock, flags);
329 static void rapl_pmu_event_del(struct perf_event *event, int flags)
331 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
334 static int rapl_pmu_event_init(struct perf_event *event)
336 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
337 int bit, msr, ret = 0;
339 /* only look at RAPL events */
340 if (event->attr.type != rapl_pmu_class.type)
343 /* check only supported bits are set */
344 if (event->attr.config & ~RAPL_EVENT_MASK)
348 * check event is known (determines counter)
352 bit = RAPL_IDX_PP0_NRG_STAT;
353 msr = MSR_PP0_ENERGY_STATUS;
356 bit = RAPL_IDX_PKG_NRG_STAT;
357 msr = MSR_PKG_ENERGY_STATUS;
360 bit = RAPL_IDX_RAM_NRG_STAT;
361 msr = MSR_DRAM_ENERGY_STATUS;
364 bit = RAPL_IDX_PP1_NRG_STAT;
365 msr = MSR_PP1_ENERGY_STATUS;
370 /* check event supported */
371 if (!(rapl_cntr_mask & (1 << bit)))
374 /* unsupported modes and filters */
375 if (event->attr.exclude_user ||
376 event->attr.exclude_kernel ||
377 event->attr.exclude_hv ||
378 event->attr.exclude_idle ||
379 event->attr.exclude_host ||
380 event->attr.exclude_guest ||
381 event->attr.sample_period) /* no sampling */
384 /* must be done before validate_group */
385 event->hw.event_base = msr;
386 event->hw.config = cfg;
392 static void rapl_pmu_event_read(struct perf_event *event)
394 rapl_event_update(event);
397 static ssize_t rapl_get_attr_cpumask(struct device *dev,
398 struct device_attribute *attr, char *buf)
400 return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask);
403 static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL);
405 static struct attribute *rapl_pmu_attrs[] = {
406 &dev_attr_cpumask.attr,
410 static struct attribute_group rapl_pmu_attr_group = {
411 .attrs = rapl_pmu_attrs,
414 static ssize_t rapl_sysfs_show(struct device *dev,
415 struct device_attribute *attr,
418 struct perf_pmu_events_attr *pmu_attr = \
419 container_of(attr, struct perf_pmu_events_attr, attr);
421 if (pmu_attr->event_str)
422 return sprintf(page, "%s", pmu_attr->event_str);
427 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
428 RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
429 RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
430 RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
432 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
433 RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
434 RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
435 RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
438 * we compute in 0.23 nJ increments regardless of MSR
440 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
441 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
442 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
443 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
445 static struct attribute *rapl_events_srv_attr[] = {
446 EVENT_PTR(rapl_cores),
450 EVENT_PTR(rapl_cores_unit),
451 EVENT_PTR(rapl_pkg_unit),
452 EVENT_PTR(rapl_ram_unit),
454 EVENT_PTR(rapl_cores_scale),
455 EVENT_PTR(rapl_pkg_scale),
456 EVENT_PTR(rapl_ram_scale),
460 static struct attribute *rapl_events_cln_attr[] = {
461 EVENT_PTR(rapl_cores),
465 EVENT_PTR(rapl_cores_unit),
466 EVENT_PTR(rapl_pkg_unit),
467 EVENT_PTR(rapl_gpu_unit),
469 EVENT_PTR(rapl_cores_scale),
470 EVENT_PTR(rapl_pkg_scale),
471 EVENT_PTR(rapl_gpu_scale),
475 static struct attribute *rapl_events_hsw_attr[] = {
476 EVENT_PTR(rapl_cores),
481 EVENT_PTR(rapl_cores_unit),
482 EVENT_PTR(rapl_pkg_unit),
483 EVENT_PTR(rapl_gpu_unit),
484 EVENT_PTR(rapl_ram_unit),
486 EVENT_PTR(rapl_cores_scale),
487 EVENT_PTR(rapl_pkg_scale),
488 EVENT_PTR(rapl_gpu_scale),
489 EVENT_PTR(rapl_ram_scale),
493 static struct attribute *rapl_events_knl_attr[] = {
497 EVENT_PTR(rapl_pkg_unit),
498 EVENT_PTR(rapl_ram_unit),
500 EVENT_PTR(rapl_pkg_scale),
501 EVENT_PTR(rapl_ram_scale),
505 static struct attribute_group rapl_pmu_events_group = {
507 .attrs = NULL, /* patched at runtime */
510 DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7");
511 static struct attribute *rapl_formats_attr[] = {
512 &format_attr_event.attr,
516 static struct attribute_group rapl_pmu_format_group = {
518 .attrs = rapl_formats_attr,
521 const struct attribute_group *rapl_attr_groups[] = {
522 &rapl_pmu_attr_group,
523 &rapl_pmu_format_group,
524 &rapl_pmu_events_group,
528 static struct pmu rapl_pmu_class = {
529 .attr_groups = rapl_attr_groups,
530 .task_ctx_nr = perf_invalid_context, /* system-wide only */
531 .event_init = rapl_pmu_event_init,
532 .add = rapl_pmu_event_add, /* must have */
533 .del = rapl_pmu_event_del, /* must have */
534 .start = rapl_pmu_event_start,
535 .stop = rapl_pmu_event_stop,
536 .read = rapl_pmu_event_read,
539 static void rapl_cpu_exit(int cpu)
541 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
542 int i, phys_id = topology_physical_package_id(cpu);
545 /* find a new cpu on same package */
546 for_each_online_cpu(i) {
549 if (phys_id == topology_physical_package_id(i)) {
555 * clear cpu from cpumask
556 * if was set in cpumask and still some cpu on package,
557 * then move to new cpu
559 if (cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask) && target >= 0)
560 cpumask_set_cpu(target, &rapl_cpu_mask);
562 WARN_ON(cpumask_empty(&rapl_cpu_mask));
564 * migrate events and context to new cpu
567 perf_pmu_migrate_context(pmu->pmu, cpu, target);
569 /* cancel overflow polling timer for CPU */
570 rapl_stop_hrtimer(pmu);
573 static void rapl_cpu_init(int cpu)
575 int i, phys_id = topology_physical_package_id(cpu);
577 /* check if phys_is is already covered */
578 for_each_cpu(i, &rapl_cpu_mask) {
579 if (phys_id == topology_physical_package_id(i))
582 /* was not found, so add it */
583 cpumask_set_cpu(cpu, &rapl_cpu_mask);
586 static __init void rapl_hsw_server_quirk(void)
589 * DRAM domain on HSW server has fixed energy unit which can be
590 * different than the unit from power unit MSR.
591 * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
592 * of 2. Datasheet, September 2014, Reference Number: 330784-001 "
594 rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16;
597 static int rapl_cpu_prepare(int cpu)
599 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
600 int phys_id = topology_physical_package_id(cpu);
609 pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
612 spin_lock_init(&pmu->lock);
614 INIT_LIST_HEAD(&pmu->active_list);
616 pmu->pmu = &rapl_pmu_class;
619 * use reference of 200W for scaling the timeout
620 * to avoid missing counter overflows.
621 * 200W = 200 Joules/sec
622 * divide interval by 2 to avoid lockstep (2 * 100)
623 * if hw unit is 32, then we use 2 ms 1/200/2
625 if (rapl_hw_unit[0] < 32)
626 ms = (1000 / (2 * 100)) * (1ULL << (32 - rapl_hw_unit[0] - 1));
630 pmu->timer_interval = ms_to_ktime(ms);
632 rapl_hrtimer_init(pmu);
634 /* set RAPL pmu for this cpu for now */
635 per_cpu(rapl_pmu, cpu) = pmu;
636 per_cpu(rapl_pmu_to_free, cpu) = NULL;
641 static void rapl_cpu_kfree(int cpu)
643 struct rapl_pmu *pmu = per_cpu(rapl_pmu_to_free, cpu);
647 per_cpu(rapl_pmu_to_free, cpu) = NULL;
650 static int rapl_cpu_dying(int cpu)
652 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
657 per_cpu(rapl_pmu, cpu) = NULL;
659 per_cpu(rapl_pmu_to_free, cpu) = pmu;
664 static int rapl_cpu_notifier(struct notifier_block *self,
665 unsigned long action, void *hcpu)
667 unsigned int cpu = (long)hcpu;
669 switch (action & ~CPU_TASKS_FROZEN) {
671 rapl_cpu_prepare(cpu);
676 case CPU_UP_CANCELED:
684 case CPU_DOWN_PREPARE:
694 static int rapl_check_hw_unit(void)
696 u64 msr_rapl_power_unit_bits;
699 /* protect rdmsrl() to handle virtualization */
700 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
702 for (i = 0; i < NR_RAPL_DOMAINS; i++)
703 rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
708 static const struct x86_cpu_id rapl_cpu_match[] = {
709 [0] = { .vendor = X86_VENDOR_INTEL, .family = 6 },
713 static int __init rapl_pmu_init(void)
715 struct rapl_pmu *pmu;
717 struct x86_pmu_quirk *quirk;
721 * check for Intel processor family 6
723 if (!x86_match_cpu(rapl_cpu_match))
726 /* check supported CPU */
727 switch (boot_cpu_data.x86_model) {
728 case 42: /* Sandy Bridge */
729 case 58: /* Ivy Bridge */
730 rapl_cntr_mask = RAPL_IDX_CLN;
731 rapl_pmu_events_group.attrs = rapl_events_cln_attr;
733 case 63: /* Haswell-Server */
734 rapl_add_quirk(rapl_hsw_server_quirk);
735 rapl_cntr_mask = RAPL_IDX_SRV;
736 rapl_pmu_events_group.attrs = rapl_events_srv_attr;
738 case 60: /* Haswell */
739 case 69: /* Haswell-Celeron */
740 case 61: /* Broadwell */
741 rapl_cntr_mask = RAPL_IDX_HSW;
742 rapl_pmu_events_group.attrs = rapl_events_hsw_attr;
744 case 45: /* Sandy Bridge-EP */
745 case 62: /* IvyTown */
746 rapl_cntr_mask = RAPL_IDX_SRV;
747 rapl_pmu_events_group.attrs = rapl_events_srv_attr;
749 case 87: /* Knights Landing */
750 rapl_add_quirk(rapl_hsw_server_quirk);
751 rapl_cntr_mask = RAPL_IDX_KNL;
752 rapl_pmu_events_group.attrs = rapl_events_knl_attr;
758 ret = rapl_check_hw_unit();
762 /* run cpu model quirks */
763 for (quirk = rapl_quirks; quirk; quirk = quirk->next)
765 cpu_notifier_register_begin();
767 for_each_online_cpu(cpu) {
768 ret = rapl_cpu_prepare(cpu);
774 __perf_cpu_notifier(rapl_cpu_notifier);
776 ret = perf_pmu_register(&rapl_pmu_class, "power", -1);
778 pr_info("RAPL PMU detected, registration failed (%d), RAPL PMU disabled\n", ret);
779 cpu_notifier_register_done();
783 pmu = __this_cpu_read(rapl_pmu);
785 pr_info("RAPL PMU detected,"
786 " API unit is 2^-32 Joules,"
788 " %llu ms ovfl timer\n",
789 hweight32(rapl_cntr_mask),
790 ktime_to_ms(pmu->timer_interval));
791 for (i = 0; i < NR_RAPL_DOMAINS; i++) {
792 if (rapl_cntr_mask & (1 << i)) {
793 pr_info("hw unit of domain %s 2^-%d Joules\n",
794 rapl_domain_names[i], rapl_hw_unit[i]);
798 cpu_notifier_register_done();
802 device_initcall(rapl_pmu_init);