1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/syscore_ops.h>
3 #include <linux/suspend.h>
8 #define UMWAIT_C02_ENABLE 0
10 #define UMWAIT_CTRL_VAL(max_time, c02_disable) \
11 (((max_time) & MSR_IA32_UMWAIT_CONTROL_TIME_MASK) | \
12 ((c02_disable) & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE))
15 * Cache IA32_UMWAIT_CONTROL MSR. This is a systemwide control. By default,
16 * umwait max time is 100000 in TSC-quanta and C0.2 is enabled
18 static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE);
20 u32 get_umwait_control_msr(void)
22 return umwait_control_cached;
24 EXPORT_SYMBOL_GPL(get_umwait_control_msr);
27 * Cache the original IA32_UMWAIT_CONTROL MSR value which is configured by
28 * hardware or BIOS before kernel boot.
30 static u32 orig_umwait_control_cached __ro_after_init;
33 * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in
34 * the sysfs write functions.
36 static DEFINE_MUTEX(umwait_lock);
38 static void umwait_update_control_msr(void * unused)
40 lockdep_assert_irqs_disabled();
41 wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0);
45 * The CPU hotplug callback sets the control MSR to the global control
48 * Disable interrupts so the read of umwait_control_cached and the WRMSR
49 * are protected against a concurrent sysfs write. Otherwise the sysfs
50 * write could update the cached value after it had been read on this CPU
51 * and issue the IPI before the old value had been written. The IPI would
52 * interrupt, write the new value and after return from IPI the previous
53 * value would be written by this CPU.
55 * With interrupts disabled the upcoming CPU either sees the new control
56 * value or the IPI is updating this CPU to the new control value after
57 * interrupts have been reenabled.
59 static int umwait_cpu_online(unsigned int cpu)
62 umwait_update_control_msr(NULL);
68 * The CPU hotplug callback sets the control MSR to the original control
71 static int umwait_cpu_offline(unsigned int cpu)
74 * This code is protected by the CPU hotplug already and
75 * orig_umwait_control_cached is never changed after it caches
76 * the original control MSR value in umwait_init(). So there
77 * is no race condition here.
79 wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0);
85 * On resume, restore IA32_UMWAIT_CONTROL MSR on the boot processor which
86 * is the only active CPU at this time. The MSR is set up on the APs via the
87 * CPU hotplug callback.
89 * This function is invoked on resume from suspend and hibernation. On
90 * resume from suspend the restore should be not required, but we neither
91 * trust the firmware nor does it matter if the same value is written
94 static void umwait_syscore_resume(void)
96 umwait_update_control_msr(NULL);
99 static struct syscore_ops umwait_syscore_ops = {
100 .resume = umwait_syscore_resume,
103 /* sysfs interface */
106 * When bit 0 in IA32_UMWAIT_CONTROL MSR is 1, C0.2 is disabled.
107 * Otherwise, C0.2 is enabled.
109 static inline bool umwait_ctrl_c02_enabled(u32 ctrl)
111 return !(ctrl & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE);
114 static inline u32 umwait_ctrl_max_time(u32 ctrl)
116 return ctrl & MSR_IA32_UMWAIT_CONTROL_TIME_MASK;
119 static inline void umwait_update_control(u32 maxtime, bool c02_enable)
121 u32 ctrl = maxtime & MSR_IA32_UMWAIT_CONTROL_TIME_MASK;
124 ctrl |= MSR_IA32_UMWAIT_CONTROL_C02_DISABLE;
126 WRITE_ONCE(umwait_control_cached, ctrl);
127 /* Propagate to all CPUs */
128 on_each_cpu(umwait_update_control_msr, NULL, 1);
132 enable_c02_show(struct device *dev, struct device_attribute *attr, char *buf)
134 u32 ctrl = READ_ONCE(umwait_control_cached);
136 return sprintf(buf, "%d\n", umwait_ctrl_c02_enabled(ctrl));
139 static ssize_t enable_c02_store(struct device *dev,
140 struct device_attribute *attr,
141 const char *buf, size_t count)
147 ret = kstrtobool(buf, &c02_enable);
151 mutex_lock(&umwait_lock);
153 ctrl = READ_ONCE(umwait_control_cached);
154 if (c02_enable != umwait_ctrl_c02_enabled(ctrl))
155 umwait_update_control(ctrl, c02_enable);
157 mutex_unlock(&umwait_lock);
161 static DEVICE_ATTR_RW(enable_c02);
164 max_time_show(struct device *kobj, struct device_attribute *attr, char *buf)
166 u32 ctrl = READ_ONCE(umwait_control_cached);
168 return sprintf(buf, "%u\n", umwait_ctrl_max_time(ctrl));
171 static ssize_t max_time_store(struct device *kobj,
172 struct device_attribute *attr,
173 const char *buf, size_t count)
178 ret = kstrtou32(buf, 0, &max_time);
182 /* bits[1:0] must be zero */
183 if (max_time & ~MSR_IA32_UMWAIT_CONTROL_TIME_MASK)
186 mutex_lock(&umwait_lock);
188 ctrl = READ_ONCE(umwait_control_cached);
189 if (max_time != umwait_ctrl_max_time(ctrl))
190 umwait_update_control(max_time, umwait_ctrl_c02_enabled(ctrl));
192 mutex_unlock(&umwait_lock);
196 static DEVICE_ATTR_RW(max_time);
198 static struct attribute *umwait_attrs[] = {
199 &dev_attr_enable_c02.attr,
200 &dev_attr_max_time.attr,
204 static struct attribute_group umwait_attr_group = {
205 .attrs = umwait_attrs,
206 .name = "umwait_control",
209 static int __init umwait_init(void)
214 if (!boot_cpu_has(X86_FEATURE_WAITPKG))
218 * Cache the original control MSR value before the control MSR is
219 * changed. This is the only place where orig_umwait_control_cached
222 rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);
224 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online",
225 umwait_cpu_online, umwait_cpu_offline);
228 * On failure, the control MSR on all CPUs has the
229 * original control value.
234 register_syscore_ops(&umwait_syscore_ops);
237 * Add umwait control interface. Ignore failure, so at least the
238 * default values are set up in case the machine manages to boot.
240 dev = cpu_subsys.dev_root;
241 return sysfs_create_group(&dev->kobj, &umwait_attr_group);
243 device_initcall(umwait_init);