1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <drm/i915_drm.h>
16 #include <asm/pci-direct.h>
18 #include <asm/io_apic.h>
21 #include <asm/iommu.h>
23 #include <asm/irq_remapping.h>
25 static void __init fix_hypertransport_config(int num, int slot, int func)
29 * we found a hypertransport bus
30 * make sure that we are broadcasting
31 * interrupts to all cpus on the ht bus
32 * if we're using extended apic ids
34 htcfg = read_pci_config(num, slot, func, 0x68);
35 if (htcfg & (1 << 18)) {
36 printk(KERN_INFO "Detected use of extended apic ids "
37 "on hypertransport bus\n");
38 if ((htcfg & (1 << 17)) == 0) {
39 printk(KERN_INFO "Enabling hypertransport extended "
40 "apic interrupt broadcast\n");
41 printk(KERN_INFO "Note this is a bios bug, "
42 "please contact your hw vendor\n");
44 write_pci_config(num, slot, func, 0x68, htcfg);
51 static void __init via_bugs(int num, int slot, int func)
53 #ifdef CONFIG_GART_IOMMU
54 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
55 !gart_iommu_aperture_allowed) {
57 "Looks like a VIA chipset. Disabling IOMMU."
58 " Override with iommu=allowed\n");
59 gart_iommu_aperture_disabled = 1;
65 #ifdef CONFIG_X86_IO_APIC
67 static int __init nvidia_hpet_check(struct acpi_table_header *header)
71 #endif /* CONFIG_X86_IO_APIC */
72 #endif /* CONFIG_ACPI */
74 static void __init nvidia_bugs(int num, int slot, int func)
77 #ifdef CONFIG_X86_IO_APIC
79 * Only applies to Nvidia root ports (bus 0) and not to
80 * Nvidia graphics cards with PCI ports on secondary buses.
86 * All timer overrides on Nvidia are
87 * wrong unless HPET is enabled.
88 * Unfortunately that's not true on many Asus boards.
89 * We don't know yet how to detect this automatically, but
90 * at least allow a command line override.
92 if (acpi_use_timer_override)
95 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
96 acpi_skip_timer_override = 1;
97 printk(KERN_INFO "Nvidia board "
98 "detected. Ignoring ACPI "
100 printk(KERN_INFO "If you got timer trouble "
101 "try acpi_use_timer_override\n");
105 /* RED-PEN skip them on mptables too? */
109 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
110 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
115 b = read_pci_config_byte(num, slot, func, 0xac);
117 write_pci_config_byte(num, slot, func, 0xac, b);
119 d = read_pci_config(num, slot, func, 0x70);
121 write_pci_config(num, slot, func, 0x70, d);
123 d = read_pci_config(num, slot, func, 0x8);
128 static void __init ati_bugs(int num, int slot, int func)
133 if (acpi_use_timer_override)
136 d = ati_ixp4x0_rev(num, slot, func);
138 acpi_skip_timer_override = 1;
140 /* check for IRQ0 interrupt swap */
141 outb(0x72, 0xcd6); b = inb(0xcd7);
143 acpi_skip_timer_override = 1;
146 if (acpi_skip_timer_override) {
147 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
148 printk(KERN_INFO "Ignoring ACPI timer override.\n");
149 printk(KERN_INFO "If you got timer trouble "
150 "try acpi_use_timer_override\n");
154 static u32 __init ati_sbx00_rev(int num, int slot, int func)
158 d = read_pci_config(num, slot, func, 0x8);
164 static void __init ati_bugs_contd(int num, int slot, int func)
168 rev = ati_sbx00_rev(num, slot, func);
170 acpi_fix_pin2_polarity = 1;
173 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
174 * SB700: revisions 0x39, 0x3a, ...
175 * SB800: revisions 0x40, 0x41, ...
180 if (acpi_use_timer_override)
183 /* check for IRQ0 interrupt swap */
184 d = read_pci_config(num, slot, func, 0x64);
186 acpi_skip_timer_override = 1;
188 if (acpi_skip_timer_override) {
189 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
190 printk(KERN_INFO "Ignoring ACPI timer override.\n");
191 printk(KERN_INFO "If you got timer trouble "
192 "try acpi_use_timer_override\n");
196 static void __init ati_bugs(int num, int slot, int func)
200 static void __init ati_bugs_contd(int num, int slot, int func)
205 static void __init intel_remapping_check(int num, int slot, int func)
210 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
211 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
214 * Revision <= 13 of all triggering devices id in this quirk
215 * have a problem draining interrupts when irq remapping is
216 * enabled, and should be flagged as broken. Additionally
217 * revision 0x22 of device id 0x3405 has this problem.
219 if (revision <= 0x13)
220 set_irq_remapping_broken();
221 else if (device == 0x3405 && revision == 0x22)
222 set_irq_remapping_broken();
226 * Systems with Intel graphics controllers set aside memory exclusively
227 * for gfx driver use. This memory is not marked in the E820 as reserved
228 * or as RAM, and so is subject to overlap from E820 manipulation later
229 * in the boot process. On some systems, MMIO space is allocated on top,
230 * despite the efforts of the "RAM buffer" approach, which simply rounds
231 * memory boundaries up to 64M to try to catch space that may decode
232 * as RAM and so is not suitable for MMIO.
234 * And yes, so far on current devices the base addr is always under 4G.
236 static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
241 * For the PCI IDs in this quirk, the stolen base is always
242 * in 0x5c, aka the BDSM register (yes that's really what
245 base = read_pci_config(num, slot, func, 0x5c);
246 base &= ~((1<<20) - 1);
251 #define KB(x) ((x) * 1024UL)
252 #define MB(x) (KB (KB (x)))
253 #define GB(x) (MB (KB (x)))
255 static size_t __init i830_tseg_size(void)
257 u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
259 if (!(tmp & TSEG_ENABLE))
262 if (tmp & I830_TSEG_SIZE_1M)
268 static size_t __init i845_tseg_size(void)
270 u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
272 if (!(tmp & TSEG_ENABLE))
275 switch (tmp & I845_TSEG_SIZE_MASK) {
276 case I845_TSEG_SIZE_512K:
278 case I845_TSEG_SIZE_1M:
286 static size_t __init i85x_tseg_size(void)
288 u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
290 if (!(tmp & TSEG_ENABLE))
296 static size_t __init i830_mem_size(void)
298 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
301 static size_t __init i85x_mem_size(void)
303 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
307 * On 830/845/85x the stolen memory base isn't available in any
308 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
310 static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
312 return i830_mem_size() - i830_tseg_size() - stolen_size;
315 static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
317 return i830_mem_size() - i845_tseg_size() - stolen_size;
320 static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
322 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
325 static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
328 * FIXME is the graphics stolen memory region
329 * always at TOUD? Ie. is it always the last
330 * one to be allocated by the BIOS?
332 return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
335 static size_t __init i830_stolen_size(int num, int slot, int func)
340 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
342 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
343 case I830_GMCH_GMS_STOLEN_512:
344 stolen_size = KB(512);
346 case I830_GMCH_GMS_STOLEN_1024:
349 case I830_GMCH_GMS_STOLEN_8192:
352 case I830_GMCH_GMS_LOCAL:
353 /* local memory isn't part of the normal address space */
363 static size_t __init gen3_stolen_size(int num, int slot, int func)
368 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
370 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
371 case I855_GMCH_GMS_STOLEN_1M:
374 case I855_GMCH_GMS_STOLEN_4M:
377 case I855_GMCH_GMS_STOLEN_8M:
380 case I855_GMCH_GMS_STOLEN_16M:
381 stolen_size = MB(16);
383 case I855_GMCH_GMS_STOLEN_32M:
384 stolen_size = MB(32);
386 case I915_GMCH_GMS_STOLEN_48M:
387 stolen_size = MB(48);
389 case I915_GMCH_GMS_STOLEN_64M:
390 stolen_size = MB(64);
392 case G33_GMCH_GMS_STOLEN_128M:
393 stolen_size = MB(128);
395 case G33_GMCH_GMS_STOLEN_256M:
396 stolen_size = MB(256);
398 case INTEL_GMCH_GMS_STOLEN_96M:
399 stolen_size = MB(96);
401 case INTEL_GMCH_GMS_STOLEN_160M:
402 stolen_size = MB(160);
404 case INTEL_GMCH_GMS_STOLEN_224M:
405 stolen_size = MB(224);
407 case INTEL_GMCH_GMS_STOLEN_352M:
408 stolen_size = MB(352);
418 static size_t __init gen6_stolen_size(int num, int slot, int func)
422 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
423 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
424 gmch_ctrl &= SNB_GMCH_GMS_MASK;
426 return gmch_ctrl << 25; /* 32 MB units */
429 static size_t __init gen8_stolen_size(int num, int slot, int func)
433 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
434 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
435 gmch_ctrl &= BDW_GMCH_GMS_MASK;
436 return gmch_ctrl << 25; /* 32 MB units */
439 static size_t __init chv_stolen_size(int num, int slot, int func)
443 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
444 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
445 gmch_ctrl &= SNB_GMCH_GMS_MASK;
448 * 0x0 to 0x10: 32MB increments starting at 0MB
449 * 0x11 to 0x16: 4MB increments starting at 8MB
450 * 0x17 to 0x1d: 4MB increments start at 36MB
452 if (gmch_ctrl < 0x11)
453 return gmch_ctrl << 25;
454 else if (gmch_ctrl < 0x17)
455 return (gmch_ctrl - 0x11 + 2) << 22;
457 return (gmch_ctrl - 0x17 + 9) << 22;
460 struct intel_stolen_funcs {
461 size_t (*size)(int num, int slot, int func);
462 u32 (*base)(int num, int slot, int func, size_t size);
465 static size_t __init gen9_stolen_size(int num, int slot, int func)
469 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
470 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
471 gmch_ctrl &= BDW_GMCH_GMS_MASK;
473 if (gmch_ctrl < 0xf0)
474 return gmch_ctrl << 25; /* 32 MB units */
476 /* 4MB increments starting at 0xf0 for 4MB */
477 return (gmch_ctrl - 0xf0 + 1) << 22;
480 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
482 static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
483 .base = i830_stolen_base,
484 .size = i830_stolen_size,
487 static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
488 .base = i845_stolen_base,
489 .size = i830_stolen_size,
492 static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
493 .base = i85x_stolen_base,
494 .size = gen3_stolen_size,
497 static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
498 .base = i865_stolen_base,
499 .size = gen3_stolen_size,
502 static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
503 .base = intel_stolen_base,
504 .size = gen3_stolen_size,
507 static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
508 .base = intel_stolen_base,
509 .size = gen6_stolen_size,
512 static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
513 .base = intel_stolen_base,
514 .size = gen8_stolen_size,
517 static const struct intel_stolen_funcs gen9_stolen_funcs __initconst = {
518 .base = intel_stolen_base,
519 .size = gen9_stolen_size,
522 static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
523 .base = intel_stolen_base,
524 .size = chv_stolen_size,
527 static const struct pci_device_id intel_stolen_ids[] __initconst = {
528 INTEL_I830_IDS(&i830_stolen_funcs),
529 INTEL_I845G_IDS(&i845_stolen_funcs),
530 INTEL_I85X_IDS(&i85x_stolen_funcs),
531 INTEL_I865G_IDS(&i865_stolen_funcs),
532 INTEL_I915G_IDS(&gen3_stolen_funcs),
533 INTEL_I915GM_IDS(&gen3_stolen_funcs),
534 INTEL_I945G_IDS(&gen3_stolen_funcs),
535 INTEL_I945GM_IDS(&gen3_stolen_funcs),
536 INTEL_VLV_M_IDS(&gen6_stolen_funcs),
537 INTEL_VLV_D_IDS(&gen6_stolen_funcs),
538 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
539 INTEL_I965G_IDS(&gen3_stolen_funcs),
540 INTEL_G33_IDS(&gen3_stolen_funcs),
541 INTEL_I965GM_IDS(&gen3_stolen_funcs),
542 INTEL_GM45_IDS(&gen3_stolen_funcs),
543 INTEL_G45_IDS(&gen3_stolen_funcs),
544 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
545 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
546 INTEL_SNB_D_IDS(&gen6_stolen_funcs),
547 INTEL_SNB_M_IDS(&gen6_stolen_funcs),
548 INTEL_IVB_M_IDS(&gen6_stolen_funcs),
549 INTEL_IVB_D_IDS(&gen6_stolen_funcs),
550 INTEL_HSW_D_IDS(&gen6_stolen_funcs),
551 INTEL_HSW_M_IDS(&gen6_stolen_funcs),
552 INTEL_BDW_M_IDS(&gen8_stolen_funcs),
553 INTEL_BDW_D_IDS(&gen8_stolen_funcs),
554 INTEL_CHV_IDS(&chv_stolen_funcs),
555 INTEL_SKL_IDS(&gen9_stolen_funcs),
556 INTEL_BXT_IDS(&gen9_stolen_funcs),
557 INTEL_KBL_IDS(&gen9_stolen_funcs),
560 static void __init intel_graphics_stolen(int num, int slot, int func)
565 u16 device, subvendor, subdevice;
567 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
568 subvendor = read_pci_config_16(num, slot, func,
569 PCI_SUBSYSTEM_VENDOR_ID);
570 subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
572 for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
573 if (intel_stolen_ids[i].device == device) {
574 const struct intel_stolen_funcs *stolen_funcs =
575 (const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
576 size = stolen_funcs->size(num, slot, func);
577 start = stolen_funcs->base(num, slot, func, size);
579 printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
580 start, start + (u32)size - 1);
581 /* Mark this space as reserved */
582 e820_add_region(start, size, E820_RESERVED);
583 sanitize_e820_map(e820.map,
584 ARRAY_SIZE(e820.map),
592 static void __init force_disable_hpet(int num, int slot, int func)
594 #ifdef CONFIG_HPET_TIMER
595 boot_hpet_disable = true;
596 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
601 #define QFLAG_APPLY_ONCE 0x1
602 #define QFLAG_APPLIED 0x2
603 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
610 void (*f)(int num, int slot, int func);
614 * Only works for devices on the root bus. If you add any devices
615 * not on bus 0 readd another loop level in early_quirks(). But
616 * be careful because at least the Nvidia quirk here relies on
617 * only matching on bus 0.
619 static struct chipset early_qrk[] __initdata = {
620 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
621 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
622 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
623 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
624 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
625 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
626 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
627 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
628 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
629 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
630 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
631 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
632 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
633 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
634 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
635 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
636 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
637 QFLAG_APPLY_ONCE, intel_graphics_stolen },
639 * HPET on the current version of the Baytrail platform has accuracy
640 * problems: it will halt in deep idle state - so we disable it.
642 * More details can be found in section 18.10.1.3 of the datasheet:
644 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
646 { PCI_VENDOR_ID_INTEL, 0x0f00,
647 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
652 * check_dev_quirk - apply early quirks to a given PCI device
655 * @func: PCI function
657 * Check the vendor & device ID against the early quirks table.
659 * If the device is single function, let early_quirks() know so we don't
660 * poke at this device again.
662 static int __init check_dev_quirk(int num, int slot, int func)
670 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
673 return -1; /* no class, treat as single function */
675 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
677 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
679 for (i = 0; early_qrk[i].f != NULL; i++) {
680 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
681 (early_qrk[i].vendor == vendor)) &&
682 ((early_qrk[i].device == PCI_ANY_ID) ||
683 (early_qrk[i].device == device)) &&
684 (!((early_qrk[i].class ^ class) &
685 early_qrk[i].class_mask))) {
686 if ((early_qrk[i].flags &
687 QFLAG_DONE) != QFLAG_DONE)
688 early_qrk[i].f(num, slot, func);
689 early_qrk[i].flags |= QFLAG_APPLIED;
693 type = read_pci_config_byte(num, slot, func,
701 void __init early_quirks(void)
705 if (!early_pci_allowed())
708 /* Poor man's PCI discovery */
709 /* Only scan the root bus */
710 for (slot = 0; slot < 32; slot++)
711 for (func = 0; func < 8; func++) {
712 /* Only probe function 0 on single fn devices */
713 if (check_dev_quirk(0, slot, func))