arch/x86/kernel/pci-calgary_64.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Derived from arch/powerpc/kernel/iommu.c
   4  *
   5  * Copyright IBM Corporation, 2006-2007
   6  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   7  *
   8  * Author: Jon Mason <jdmason@kudzu.us>
   9  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
  10
  11  */
  12
  13 #define pr_fmt(fmt) "Calgary: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/slab.h>
  19 #include <linux/mm.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/string.h>
  22 #include <linux/crash_dump.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dma-direct.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/pci_ids.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/iommu-helper.h>
  31
  32 #include <asm/iommu.h>
  33 #include <asm/calgary.h>
  34 #include <asm/tce.h>
  35 #include <asm/pci-direct.h>
  36 #include <asm/dma.h>
  37 #include <asm/rio.h>
  38 #include <asm/bios_ebda.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/iommu_table.h>
  41
  42 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  43 int use_calgary __read_mostly = 1;
  44 #else
  45 int use_calgary __read_mostly = 0;
  46 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  47
  48 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  49 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  50
  51 /* register offsets inside the host bridge space */
  52 #define CALGARY_CONFIG_REG      0x0108
  53 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  54 #define PHB_PLSSR_OFFSET        0x0120
  55 #define PHB_CONFIG_RW_OFFSET    0x0160
  56 #define PHB_IOBASE_BAR_LOW      0x0170
  57 #define PHB_IOBASE_BAR_HIGH     0x0180
  58 #define PHB_MEM_1_LOW           0x0190
  59 #define PHB_MEM_1_HIGH          0x01A0
  60 #define PHB_IO_ADDR_SIZE        0x01B0
  61 #define PHB_MEM_1_SIZE          0x01C0
  62 #define PHB_MEM_ST_OFFSET       0x01D0
  63 #define PHB_AER_OFFSET          0x0200
  64 #define PHB_CONFIG_0_HIGH       0x0220
  65 #define PHB_CONFIG_0_LOW        0x0230
  66 #define PHB_CONFIG_0_END        0x0240
  67 #define PHB_MEM_2_LOW           0x02B0
  68 #define PHB_MEM_2_HIGH          0x02C0
  69 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  70 #define PHB_MEM_2_SIZE_LOW      0x02E0
  71 #define PHB_DOSHOLE_OFFSET      0x08E0
  72
  73 /* CalIOC2 specific */
  74 #define PHB_SAVIOR_L2           0x0DB0
  75 #define PHB_PAGE_MIG_CTRL       0x0DA8
  76 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  77 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  78
  79 /* PHB_CONFIG_RW */
  80 #define PHB_TCE_ENABLE          0x20000000
  81 #define PHB_SLOT_DISABLE        0x1C000000
  82 #define PHB_DAC_DISABLE         0x01000000
  83 #define PHB_MEM2_ENABLE         0x00400000
  84 #define PHB_MCSR_ENABLE         0x00100000
  85 /* TAR (Table Address Register) */
  86 #define TAR_SW_BITS             0x0000ffffffff800fUL
  87 #define TAR_VALID               0x0000000000000008UL
  88 /* CSR (Channel/DMA Status Register) */
  89 #define CSR_AGENT_MASK          0xffe0ffff
  90 /* CCR (Calgary Configuration Register) */
  91 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  92 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  93 #define PMR_SOFTSTOP            0x80000000
  94 #define PMR_SOFTSTOPFAULT       0x40000000
  95 #define PMR_HARDSTOP            0x20000000
  96
  97 /*
  98  * The maximum PHB bus number.
  99  * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 100  * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
 101  * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
 102  * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
 103  */
 104 #define MAX_PHB_BUS_NUM         256
 105
 106 #define PHBS_PER_CALGARY          4
 107
 108 /* register offsets in Calgary's internal register space */
 109 static const unsigned long tar_offsets[] = {
 110         0x0580 /* TAR0 */,
 111         0x0588 /* TAR1 */,
 112         0x0590 /* TAR2 */,
 113         0x0598 /* TAR3 */
 114 };
 115
 116 static const unsigned long split_queue_offsets[] = {
 117         0x4870 /* SPLIT QUEUE 0 */,
 118         0x5870 /* SPLIT QUEUE 1 */,
 119         0x6870 /* SPLIT QUEUE 2 */,
 120         0x7870 /* SPLIT QUEUE 3 */
 121 };
 122
 123 static const unsigned long phb_offsets[] = {
 124         0x8000 /* PHB0 */,
 125         0x9000 /* PHB1 */,
 126         0xA000 /* PHB2 */,
 127         0xB000 /* PHB3 */
 128 };
 129
 130 /* PHB debug registers */
 131
 132 static const unsigned long phb_debug_offsets[] = {
 133         0x4000  /* PHB 0 DEBUG */,
 134         0x5000  /* PHB 1 DEBUG */,
 135         0x6000  /* PHB 2 DEBUG */,
 136         0x7000  /* PHB 3 DEBUG */
 137 };
 138
 139 /*
 140  * STUFF register for each debug PHB,
 141  * byte 1 = start bus number, byte 2 = end bus number
 142  */
 143
 144 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 145
 146 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 147 static int translate_empty_slots __read_mostly = 0;
 148 static int calgary_detected __read_mostly = 0;
 149
 150 static struct rio_table_hdr     *rio_table_hdr __initdata;
 151 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 152 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 153
 154 struct calgary_bus_info {
 155         void *tce_space;
 156         unsigned char translation_disabled;
 157         signed char phbid;
 158         void __iomem *bbar;
 159 };
 160
 161 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 162 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 163 static void calgary_dump_error_regs(struct iommu_table *tbl);
 164 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 165 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 166 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 167 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 168 static void get_tce_space_from_tar(void);
 169
 170 static const struct cal_chipset_ops calgary_chip_ops = {
 171         .handle_quirks = calgary_handle_quirks,
 172         .tce_cache_blast = calgary_tce_cache_blast,
 173         .dump_error_regs = calgary_dump_error_regs
 174 };
 175
 176 static const struct cal_chipset_ops calioc2_chip_ops = {
 177         .handle_quirks = calioc2_handle_quirks,
 178         .tce_cache_blast = calioc2_tce_cache_blast,
 179         .dump_error_regs = calioc2_dump_error_regs
 180 };
 181
 182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 183
 184 static inline int translation_enabled(struct iommu_table *tbl)
 185 {
 186         /* only PHBs with translation enabled have an IOMMU table */
 187         return (tbl != NULL);
 188 }
 189
 190 static void iommu_range_reserve(struct iommu_table *tbl,
 191         unsigned long start_addr, unsigned int npages)
 192 {
 193         unsigned long index;
 194         unsigned long end;
 195         unsigned long flags;
 196
 197         index = start_addr >> PAGE_SHIFT;
 198
 199         /* bail out if we're asked to reserve a region we don't cover */
 200         if (index >= tbl->it_size)
 201                 return;
 202
 203         end = index + npages;
 204         if (end > tbl->it_size) /* don't go off the table */
 205                 end = tbl->it_size;
 206
 207         spin_lock_irqsave(&tbl->it_lock, flags);
 208
 209         bitmap_set(tbl->it_map, index, npages);
 210
 211         spin_unlock_irqrestore(&tbl->it_lock, flags);
 212 }
 213
 214 static unsigned long iommu_range_alloc(struct device *dev,
 215                                        struct iommu_table *tbl,
 216                                        unsigned int npages)
 217 {
 218         unsigned long flags;
 219         unsigned long offset;
 220         unsigned long boundary_size;
 221
 222         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 223                               PAGE_SIZE) >> PAGE_SHIFT;
 224
 225         BUG_ON(npages == 0);
 226
 227         spin_lock_irqsave(&tbl->it_lock, flags);
 228
 229         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 230                                   npages, 0, boundary_size, 0);
 231         if (offset == ~0UL) {
 232                 tbl->chip_ops->tce_cache_blast(tbl);
 233
 234                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 235                                           npages, 0, boundary_size, 0);
 236                 if (offset == ~0UL) {
 237                         pr_warn("IOMMU full\n");
 238                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 239                         if (panic_on_overflow)
 240                                 panic("Calgary: fix the allocator.\n");
 241                         else
 242                                 return DMA_MAPPING_ERROR;
 243                 }
 244         }
 245
 246         tbl->it_hint = offset + npages;
 247         BUG_ON(tbl->it_hint > tbl->it_size);
 248
 249         spin_unlock_irqrestore(&tbl->it_lock, flags);
 250
 251         return offset;
 252 }
 253
 254 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 255                               void *vaddr, unsigned int npages, int direction)
 256 {
 257         unsigned long entry;
 258         dma_addr_t ret;
 259
 260         entry = iommu_range_alloc(dev, tbl, npages);
 261         if (unlikely(entry == DMA_MAPPING_ERROR)) {
 262                 pr_warn("failed to allocate %u pages in iommu %p\n",
 263                         npages, tbl);
 264                 return DMA_MAPPING_ERROR;
 265         }
 266
 267         /* set the return dma address */
 268         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 269
 270         /* put the TCEs in the HW table */
 271         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 272                   direction);
 273         return ret;
 274 }
 275
 276 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 277         unsigned int npages)
 278 {
 279         unsigned long entry;
 280         unsigned long flags;
 281
 282         /* were we called with bad_dma_address? */
 283         if (unlikely(dma_addr == DMA_MAPPING_ERROR)) {
 284                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 285                        "address 0x%Lx\n", dma_addr);
 286                 return;
 287         }
 288
 289         entry = dma_addr >> PAGE_SHIFT;
 290
 291         BUG_ON(entry + npages > tbl->it_size);
 292
 293         tce_free(tbl, entry, npages);
 294
 295         spin_lock_irqsave(&tbl->it_lock, flags);
 296
 297         bitmap_clear(tbl->it_map, entry, npages);
 298
 299         spin_unlock_irqrestore(&tbl->it_lock, flags);
 300 }
 301
 302 static inline struct iommu_table *find_iommu_table(struct device *dev)
 303 {
 304         struct pci_dev *pdev;
 305         struct pci_bus *pbus;
 306         struct iommu_table *tbl;
 307
 308         pdev = to_pci_dev(dev);
 309
 310         /* search up the device tree for an iommu */
 311         pbus = pdev->bus;
 312         do {
 313                 tbl = pci_iommu(pbus);
 314                 if (tbl && tbl->it_busno == pbus->number)
 315                         break;
 316                 tbl = NULL;
 317                 pbus = pbus->parent;
 318         } while (pbus);
 319
 320         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 321
 322         return tbl;
 323 }
 324
 325 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 326                              int nelems,enum dma_data_direction dir,
 327                              unsigned long attrs)
 328 {
 329         struct iommu_table *tbl = find_iommu_table(dev);
 330         struct scatterlist *s;
 331         int i;
 332
 333         if (!translation_enabled(tbl))
 334                 return;
 335
 336         for_each_sg(sglist, s, nelems, i) {
 337                 unsigned int npages;
 338                 dma_addr_t dma = s->dma_address;
 339                 unsigned int dmalen = s->dma_length;
 340
 341                 if (dmalen == 0)
 342                         break;
 343
 344                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 345                 iommu_free(tbl, dma, npages);
 346         }
 347 }
 348
 349 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 350                           int nelems, enum dma_data_direction dir,
 351                           unsigned long attrs)
 352 {
 353         struct iommu_table *tbl = find_iommu_table(dev);
 354         struct scatterlist *s;
 355         unsigned long vaddr;
 356         unsigned int npages;
 357         unsigned long entry;
 358         int i;
 359
 360         for_each_sg(sg, s, nelems, i) {
 361                 BUG_ON(!sg_page(s));
 362
 363                 vaddr = (unsigned long) sg_virt(s);
 364                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 365
 366                 entry = iommu_range_alloc(dev, tbl, npages);
 367                 if (entry == DMA_MAPPING_ERROR) {
 368                         /* makes sure unmap knows to stop */
 369                         s->dma_length = 0;
 370                         goto error;
 371                 }
 372
 373                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 374
 375                 /* insert into HW table */
 376                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
 377
 378                 s->dma_length = s->length;
 379         }
 380
 381         return nelems;
 382 error:
 383         calgary_unmap_sg(dev, sg, nelems, dir, 0);
 384         for_each_sg(sg, s, nelems, i) {
 385                 sg->dma_address = DMA_MAPPING_ERROR;
 386                 sg->dma_length = 0;
 387         }
 388         return 0;
 389 }
 390
 391 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 392                                    unsigned long offset, size_t size,
 393                                    enum dma_data_direction dir,
 394                                    unsigned long attrs)
 395 {
 396         void *vaddr = page_address(page) + offset;
 397         unsigned long uaddr;
 398         unsigned int npages;
 399         struct iommu_table *tbl = find_iommu_table(dev);
 400
 401         uaddr = (unsigned long)vaddr;
 402         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 403
 404         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 405 }
 406
 407 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 408                                size_t size, enum dma_data_direction dir,
 409                                unsigned long attrs)
 410 {
 411         struct iommu_table *tbl = find_iommu_table(dev);
 412         unsigned int npages;
 413
 414         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 415         iommu_free(tbl, dma_addr, npages);
 416 }
 417
 418 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 419         dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
 420 {
 421         void *ret = NULL;
 422         dma_addr_t mapping;
 423         unsigned int npages, order;
 424         struct iommu_table *tbl = find_iommu_table(dev);
 425
 426         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 427         npages = size >> PAGE_SHIFT;
 428         order = get_order(size);
 429
 430         /* alloc enough pages (and possibly more) */
 431         ret = (void *)__get_free_pages(flag, order);
 432         if (!ret)
 433                 goto error;
 434         memset(ret, 0, size);
 435
 436         /* set up tces to cover the allocated range */
 437         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 438         if (mapping == DMA_MAPPING_ERROR)
 439                 goto free;
 440         *dma_handle = mapping;
 441         return ret;
 442 free:
 443         free_pages((unsigned long)ret, get_order(size));
 444         ret = NULL;
 445 error:
 446         return ret;
 447 }
 448
 449 static void calgary_free_coherent(struct device *dev, size_t size,
 450                                   void *vaddr, dma_addr_t dma_handle,
 451                                   unsigned long attrs)
 452 {
 453         unsigned int npages;
 454         struct iommu_table *tbl = find_iommu_table(dev);
 455
 456         size = PAGE_ALIGN(size);
 457         npages = size >> PAGE_SHIFT;
 458
 459         iommu_free(tbl, dma_handle, npages);
 460         free_pages((unsigned long)vaddr, get_order(size));
 461 }
 462
 463 static const struct dma_map_ops calgary_dma_ops = {
 464         .alloc = calgary_alloc_coherent,
 465         .free = calgary_free_coherent,
 466         .map_sg = calgary_map_sg,
 467         .unmap_sg = calgary_unmap_sg,
 468         .map_page = calgary_map_page,
 469         .unmap_page = calgary_unmap_page,
 470         .dma_supported = dma_direct_supported,
 471 };
 472
 473 static inline void __iomem * busno_to_bbar(unsigned char num)
 474 {
 475         return bus_info[num].bbar;
 476 }
 477
 478 static inline int busno_to_phbid(unsigned char num)
 479 {
 480         return bus_info[num].phbid;
 481 }
 482
 483 static inline unsigned long split_queue_offset(unsigned char num)
 484 {
 485         size_t idx = busno_to_phbid(num);
 486
 487         return split_queue_offsets[idx];
 488 }
 489
 490 static inline unsigned long tar_offset(unsigned char num)
 491 {
 492         size_t idx = busno_to_phbid(num);
 493
 494         return tar_offsets[idx];
 495 }
 496
 497 static inline unsigned long phb_offset(unsigned char num)
 498 {
 499         size_t idx = busno_to_phbid(num);
 500
 501         return phb_offsets[idx];
 502 }
 503
 504 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 505 {
 506         unsigned long target = ((unsigned long)bar) | offset;
 507         return (void __iomem*)target;
 508 }
 509
 510 static inline int is_calioc2(unsigned short device)
 511 {
 512         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 513 }
 514
 515 static inline int is_calgary(unsigned short device)
 516 {
 517         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 518 }
 519
 520 static inline int is_cal_pci_dev(unsigned short device)
 521 {
 522         return (is_calgary(device) || is_calioc2(device));
 523 }
 524
 525 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 526 {
 527         u64 val;
 528         u32 aer;
 529         int i = 0;
 530         void __iomem *bbar = tbl->bbar;
 531         void __iomem *target;
 532
 533         /* disable arbitration on the bus */
 534         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 535         aer = readl(target);
 536         writel(0, target);
 537
 538         /* read plssr to ensure it got there */
 539         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 540         val = readl(target);
 541
 542         /* poll split queues until all DMA activity is done */
 543         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 544         do {
 545                 val = readq(target);
 546                 i++;
 547         } while ((val & 0xff) != 0xff && i < 100);
 548         if (i == 100)
 549                 pr_warn("PCI bus not quiesced, continuing anyway\n");
 550
 551         /* invalidate TCE cache */
 552         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 553         writeq(tbl->tar_val, target);
 554
 555         /* enable arbitration */
 556         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 557         writel(aer, target);
 558         (void)readl(target); /* flush */
 559 }
 560
 561 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 562 {
 563         void __iomem *bbar = tbl->bbar;
 564         void __iomem *target;
 565         u64 val64;
 566         u32 val;
 567         int i = 0;
 568         int count = 1;
 569         unsigned char bus = tbl->it_busno;
 570
 571 begin:
 572         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 573                "sequence - count %d\n", bus, count);
 574
 575         /* 1. using the Page Migration Control reg set SoftStop */
 576         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 577         val = be32_to_cpu(readl(target));
 578         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 579         val |= PMR_SOFTSTOP;
 580         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 581         writel(cpu_to_be32(val), target);
 582
 583         /* 2. poll split queues until all DMA activity is done */
 584         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 585         target = calgary_reg(bbar, split_queue_offset(bus));
 586         do {
 587                 val64 = readq(target);
 588                 i++;
 589         } while ((val64 & 0xff) != 0xff && i < 100);
 590         if (i == 100)
 591                 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
 592
 593         /* 3. poll Page Migration DEBUG for SoftStopFault */
 594         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 595         val = be32_to_cpu(readl(target));
 596         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 597
 598         /* 4. if SoftStopFault - goto (1) */
 599         if (val & PMR_SOFTSTOPFAULT) {
 600                 if (++count < 100)
 601                         goto begin;
 602                 else {
 603                         pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
 604                         return; /* pray for the best */
 605                 }
 606         }
 607
 608         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 609         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 610         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 611         val = be32_to_cpu(readl(target));
 612         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 613         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 614         val = be32_to_cpu(readl(target));
 615         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 616
 617         /* 6. invalidate TCE cache */
 618         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 619         target = calgary_reg(bbar, tar_offset(bus));
 620         writeq(tbl->tar_val, target);
 621
 622         /* 7. Re-read PMCR */
 623         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 624         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 625         val = be32_to_cpu(readl(target));
 626         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 627
 628         /* 8. Remove HardStop */
 629         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 630         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 631         val = 0;
 632         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 633         writel(cpu_to_be32(val), target);
 634         val = be32_to_cpu(readl(target));
 635         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 636 }
 637
 638 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 639         u64 limit)
 640 {
 641         unsigned int numpages;
 642
 643         limit = limit | 0xfffff;
 644         limit++;
 645
 646         numpages = ((limit - start) >> PAGE_SHIFT);
 647         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 648 }
 649
 650 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 651 {
 652         void __iomem *target;
 653         u64 low, high, sizelow;
 654         u64 start, limit;
 655         struct iommu_table *tbl = pci_iommu(dev->bus);
 656         unsigned char busnum = dev->bus->number;
 657         void __iomem *bbar = tbl->bbar;
 658
 659         /* peripheral MEM_1 region */
 660         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 661         low = be32_to_cpu(readl(target));
 662         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 663         high = be32_to_cpu(readl(target));
 664         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 665         sizelow = be32_to_cpu(readl(target));
 666
 667         start = (high << 32) | low;
 668         limit = sizelow;
 669
 670         calgary_reserve_mem_region(dev, start, limit);
 671 }
 672
 673 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 674 {
 675         void __iomem *target;
 676         u32 val32;
 677         u64 low, high, sizelow, sizehigh;
 678         u64 start, limit;
 679         struct iommu_table *tbl = pci_iommu(dev->bus);
 680         unsigned char busnum = dev->bus->number;
 681         void __iomem *bbar = tbl->bbar;
 682
 683         /* is it enabled? */
 684         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 685         val32 = be32_to_cpu(readl(target));
 686         if (!(val32 & PHB_MEM2_ENABLE))
 687                 return;
 688
 689         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 690         low = be32_to_cpu(readl(target));
 691         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 692         high = be32_to_cpu(readl(target));
 693         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 694         sizelow = be32_to_cpu(readl(target));
 695         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 696         sizehigh = be32_to_cpu(readl(target));
 697
 698         start = (high << 32) | low;
 699         limit = (sizehigh << 32) | sizelow;
 700
 701         calgary_reserve_mem_region(dev, start, limit);
 702 }
 703
 704 /*
 705  * some regions of the IO address space do not get translated, so we
 706  * must not give devices IO addresses in those regions. The regions
 707  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 708  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 709  * later.
 710  */
 711 static void __init calgary_reserve_regions(struct pci_dev *dev)
 712 {
 713         unsigned int npages;
 714         u64 start;
 715         struct iommu_table *tbl = pci_iommu(dev->bus);
 716
 717         /* avoid the BIOS/VGA first 640KB-1MB region */
 718         /* for CalIOC2 - avoid the entire first MB */
 719         if (is_calgary(dev->device)) {
 720                 start = (640 * 1024);
 721                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 722         } else { /* calioc2 */
 723                 start = 0;
 724                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 725         }
 726         iommu_range_reserve(tbl, start, npages);
 727
 728         /* reserve the two PCI peripheral memory regions in IO space */
 729         calgary_reserve_peripheral_mem_1(dev);
 730         calgary_reserve_peripheral_mem_2(dev);
 731 }
 732
 733 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 734 {
 735         u64 val64;
 736         u64 table_phys;
 737         void __iomem *target;
 738         int ret;
 739         struct iommu_table *tbl;
 740
 741         /* build TCE tables for each PHB */
 742         ret = build_tce_table(dev, bbar);
 743         if (ret)
 744                 return ret;
 745
 746         tbl = pci_iommu(dev->bus);
 747         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 748
 749         if (is_kdump_kernel())
 750                 calgary_init_bitmap_from_tce_table(tbl);
 751         else
 752                 tce_free(tbl, 0, tbl->it_size);
 753
 754         if (is_calgary(dev->device))
 755                 tbl->chip_ops = &calgary_chip_ops;
 756         else if (is_calioc2(dev->device))
 757                 tbl->chip_ops = &calioc2_chip_ops;
 758         else
 759                 BUG();
 760
 761         calgary_reserve_regions(dev);
 762
 763         /* set TARs for each PHB */
 764         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 765         val64 = be64_to_cpu(readq(target));
 766
 767         /* zero out all TAR bits under sw control */
 768         val64 &= ~TAR_SW_BITS;
 769         table_phys = (u64)__pa(tbl->it_base);
 770
 771         val64 |= table_phys;
 772
 773         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 774         val64 |= (u64) specified_table_size;
 775
 776         tbl->tar_val = cpu_to_be64(val64);
 777
 778         writeq(tbl->tar_val, target);
 779         readq(target); /* flush */
 780
 781         return 0;
 782 }
 783
 784 static void __init calgary_free_bus(struct pci_dev *dev)
 785 {
 786         u64 val64;
 787         struct iommu_table *tbl = pci_iommu(dev->bus);
 788         void __iomem *target;
 789         unsigned int bitmapsz;
 790
 791         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 792         val64 = be64_to_cpu(readq(target));
 793         val64 &= ~TAR_SW_BITS;
 794         writeq(cpu_to_be64(val64), target);
 795         readq(target); /* flush */
 796
 797         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 798         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 799         tbl->it_map = NULL;
 800
 801         kfree(tbl);
 802
 803         set_pci_iommu(dev->bus, NULL);
 804
 805         /* Can't free bootmem allocated memory after system is up :-( */
 806         bus_info[dev->bus->number].tce_space = NULL;
 807 }
 808
 809 static void calgary_dump_error_regs(struct iommu_table *tbl)
 810 {
 811         void __iomem *bbar = tbl->bbar;
 812         void __iomem *target;
 813         u32 csr, plssr;
 814
 815         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 816         csr = be32_to_cpu(readl(target));
 817
 818         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 819         plssr = be32_to_cpu(readl(target));
 820
 821         /* If no error, the agent ID in the CSR is not valid */
 822         pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
 823                  tbl->it_busno, csr, plssr);
 824 }
 825
 826 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 827 {
 828         void __iomem *bbar = tbl->bbar;
 829         u32 csr, csmr, plssr, mck, rcstat;
 830         void __iomem *target;
 831         unsigned long phboff = phb_offset(tbl->it_busno);
 832         unsigned long erroff;
 833         u32 errregs[7];
 834         int i;
 835
 836         /* dump CSR */
 837         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 838         csr = be32_to_cpu(readl(target));
 839         /* dump PLSSR */
 840         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 841         plssr = be32_to_cpu(readl(target));
 842         /* dump CSMR */
 843         target = calgary_reg(bbar, phboff | 0x290);
 844         csmr = be32_to_cpu(readl(target));
 845         /* dump mck */
 846         target = calgary_reg(bbar, phboff | 0x800);
 847         mck = be32_to_cpu(readl(target));
 848
 849         pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
 850
 851         pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 852                  csr, plssr, csmr, mck);
 853
 854         /* dump rest of error regs */
 855         pr_emerg("");
 856         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 857                 /* err regs are at 0x810 - 0x870 */
 858                 erroff = (0x810 + (i * 0x10));
 859                 target = calgary_reg(bbar, phboff | erroff);
 860                 errregs[i] = be32_to_cpu(readl(target));
 861                 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
 862         }
 863         pr_cont("\n");
 864
 865         /* root complex status */
 866         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 867         rcstat = be32_to_cpu(readl(target));
 868         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 869                PHB_ROOT_COMPLEX_STATUS);
 870 }
 871
 872 static void calgary_watchdog(struct timer_list *t)
 873 {
 874         struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer);
 875         void __iomem *bbar = tbl->bbar;
 876         u32 val32;
 877         void __iomem *target;
 878
 879         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 880         val32 = be32_to_cpu(readl(target));
 881
 882         /* If no error, the agent ID in the CSR is not valid */
 883         if (val32 & CSR_AGENT_MASK) {
 884                 tbl->chip_ops->dump_error_regs(tbl);
 885
 886                 /* reset error */
 887                 writel(0, target);
 888
 889                 /* Disable bus that caused the error */
 890                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 891                                      PHB_CONFIG_RW_OFFSET);
 892                 val32 = be32_to_cpu(readl(target));
 893                 val32 |= PHB_SLOT_DISABLE;
 894                 writel(cpu_to_be32(val32), target);
 895                 readl(target); /* flush */
 896         } else {
 897                 /* Reset the timer */
 898                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 899         }
 900 }
 901
 902 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 903         unsigned char busnum, unsigned long timeout)
 904 {
 905         u64 val64;
 906         void __iomem *target;
 907         unsigned int phb_shift = ~0; /* silence gcc */
 908         u64 mask;
 909
 910         switch (busno_to_phbid(busnum)) {
 911         case 0: phb_shift = (63 - 19);
 912                 break;
 913         case 1: phb_shift = (63 - 23);
 914                 break;
 915         case 2: phb_shift = (63 - 27);
 916                 break;
 917         case 3: phb_shift = (63 - 35);
 918                 break;
 919         default:
 920                 BUG_ON(busno_to_phbid(busnum));
 921         }
 922
 923         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 924         val64 = be64_to_cpu(readq(target));
 925
 926         /* zero out this PHB's timer bits */
 927         mask = ~(0xFUL << phb_shift);
 928         val64 &= mask;
 929         val64 |= (timeout << phb_shift);
 930         writeq(cpu_to_be64(val64), target);
 931         readq(target); /* flush */
 932 }
 933
 934 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 935 {
 936         unsigned char busnum = dev->bus->number;
 937         void __iomem *bbar = tbl->bbar;
 938         void __iomem *target;
 939         u32 val;
 940
 941         /*
 942          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
 943          */
 944         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
 945         val = cpu_to_be32(readl(target));
 946         val |= 0x00800000;
 947         writel(cpu_to_be32(val), target);
 948 }
 949
 950 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 951 {
 952         unsigned char busnum = dev->bus->number;
 953
 954         /*
 955          * Give split completion a longer timeout on bus 1 for aic94xx
 956          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 957          */
 958         if (is_calgary(dev->device) && (busnum == 1))
 959                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
 960                                                      CCR_2SEC_TIMEOUT);
 961 }
 962
 963 static void __init calgary_enable_translation(struct pci_dev *dev)
 964 {
 965         u32 val32;
 966         unsigned char busnum;
 967         void __iomem *target;
 968         void __iomem *bbar;
 969         struct iommu_table *tbl;
 970
 971         busnum = dev->bus->number;
 972         tbl = pci_iommu(dev->bus);
 973         bbar = tbl->bbar;
 974
 975         /* enable TCE in PHB Config Register */
 976         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 977         val32 = be32_to_cpu(readl(target));
 978         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 979
 980         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
 981                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
 982                "Calgary" : "CalIOC2", busnum);
 983         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 984                "bus.\n");
 985
 986         writel(cpu_to_be32(val32), target);
 987         readl(target); /* flush */
 988
 989         timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0);
 990         mod_timer(&tbl->watchdog_timer, jiffies);
 991 }
 992
 993 static void __init calgary_disable_translation(struct pci_dev *dev)
 994 {
 995         u32 val32;
 996         unsigned char busnum;
 997         void __iomem *target;
 998         void __iomem *bbar;
 999         struct iommu_table *tbl;
1000
1001         busnum = dev->bus->number;
1002         tbl = pci_iommu(dev->bus);
1003         bbar = tbl->bbar;
1004
1005         /* disable TCE in PHB Config Register */
1006         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1007         val32 = be32_to_cpu(readl(target));
1008         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1009
1010         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1011         writel(cpu_to_be32(val32), target);
1012         readl(target); /* flush */
1013
1014         del_timer_sync(&tbl->watchdog_timer);
1015 }
1016
1017 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1018 {
1019         pci_dev_get(dev);
1020         set_pci_iommu(dev->bus, NULL);
1021
1022         /* is the device behind a bridge? */
1023         if (dev->bus->parent)
1024                 dev->bus->parent->self = dev;
1025         else
1026                 dev->bus->self = dev;
1027 }
1028
1029 static int __init calgary_init_one(struct pci_dev *dev)
1030 {
1031         void __iomem *bbar;
1032         struct iommu_table *tbl;
1033         int ret;
1034
1035         bbar = busno_to_bbar(dev->bus->number);
1036         ret = calgary_setup_tar(dev, bbar);
1037         if (ret)
1038                 goto done;
1039
1040         pci_dev_get(dev);
1041
1042         if (dev->bus->parent) {
1043                 if (dev->bus->parent->self)
1044                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1045                                "bus->parent->self!\n", dev);
1046                 dev->bus->parent->self = dev;
1047         } else
1048                 dev->bus->self = dev;
1049
1050         tbl = pci_iommu(dev->bus);
1051         tbl->chip_ops->handle_quirks(tbl, dev);
1052
1053         calgary_enable_translation(dev);
1054
1055         return 0;
1056
1057 done:
1058         return ret;
1059 }
1060
1061 static int __init calgary_locate_bbars(void)
1062 {
1063         int ret;
1064         int rioidx, phb, bus;
1065         void __iomem *bbar;
1066         void __iomem *target;
1067         unsigned long offset;
1068         u8 start_bus, end_bus;
1069         u32 val;
1070
1071         ret = -ENODATA;
1072         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1073                 struct rio_detail *rio = rio_devs[rioidx];
1074
1075                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1076                         continue;
1077
1078                 /* map entire 1MB of Calgary config space */
1079                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1080                 if (!bbar)
1081                         goto error;
1082
1083                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1084                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1085                         target = calgary_reg(bbar, offset);
1086
1087                         val = be32_to_cpu(readl(target));
1088
1089                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1090                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1091
1092                         if (end_bus) {
1093                                 for (bus = start_bus; bus <= end_bus; bus++) {
1094                                         bus_info[bus].bbar = bbar;
1095                                         bus_info[bus].phbid = phb;
1096                                 }
1097                         } else {
1098                                 bus_info[start_bus].bbar = bbar;
1099                                 bus_info[start_bus].phbid = phb;
1100                         }
1101                 }
1102         }
1103
1104         return 0;
1105
1106 error:
1107         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1108         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1109                 if (bus_info[bus].bbar)
1110                         iounmap(bus_info[bus].bbar);
1111
1112         return ret;
1113 }
1114
1115 static int __init calgary_init(void)
1116 {
1117         int ret;
1118         struct pci_dev *dev = NULL;
1119         struct calgary_bus_info *info;
1120
1121         ret = calgary_locate_bbars();
1122         if (ret)
1123                 return ret;
1124
1125         /* Purely for kdump kernel case */
1126         if (is_kdump_kernel())
1127                 get_tce_space_from_tar();
1128
1129         do {
1130                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1131                 if (!dev)
1132                         break;
1133                 if (!is_cal_pci_dev(dev->device))
1134                         continue;
1135
1136                 info = &bus_info[dev->bus->number];
1137                 if (info->translation_disabled) {
1138                         calgary_init_one_nontraslated(dev);
1139                         continue;
1140                 }
1141
1142                 if (!info->tce_space && !translate_empty_slots)
1143                         continue;
1144
1145                 ret = calgary_init_one(dev);
1146                 if (ret)
1147                         goto error;
1148         } while (1);
1149
1150         dev = NULL;
1151         for_each_pci_dev(dev) {
1152                 struct iommu_table *tbl;
1153
1154                 tbl = find_iommu_table(&dev->dev);
1155
1156                 if (translation_enabled(tbl))
1157                         dev->dev.dma_ops = &calgary_dma_ops;
1158         }
1159
1160         return ret;
1161
1162 error:
1163         do {
1164                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1165                 if (!dev)
1166                         break;
1167                 if (!is_cal_pci_dev(dev->device))
1168                         continue;
1169
1170                 info = &bus_info[dev->bus->number];
1171                 if (info->translation_disabled) {
1172                         pci_dev_put(dev);
1173                         continue;
1174                 }
1175                 if (!info->tce_space && !translate_empty_slots)
1176                         continue;
1177
1178                 calgary_disable_translation(dev);
1179                 calgary_free_bus(dev);
1180                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1181                 dev->dev.dma_ops = NULL;
1182         } while (1);
1183
1184         return ret;
1185 }
1186
1187 static inline int __init determine_tce_table_size(void)
1188 {
1189         int ret;
1190
1191         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1192                 return specified_table_size;
1193
1194         if (is_kdump_kernel() && saved_max_pfn) {
1195                 /*
1196                  * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1197                  * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1198                  * larger table size has twice as many entries, so shift the
1199                  * max ram address by 13 to divide by 8K and then look at the
1200                  * order of the result to choose between 0-7.
1201                  */
1202                 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1203                 if (ret > TCE_TABLE_SIZE_8M)
1204                         ret = TCE_TABLE_SIZE_8M;
1205         } else {
1206                 /*
1207                  * Use 8M by default (suggested by Muli) if it's not
1208                  * kdump kernel and saved_max_pfn isn't set.
1209                  */
1210                 ret = TCE_TABLE_SIZE_8M;
1211         }
1212
1213         return ret;
1214 }
1215
1216 static int __init build_detail_arrays(void)
1217 {
1218         unsigned long ptr;
1219         unsigned numnodes, i;
1220         int scal_detail_size, rio_detail_size;
1221
1222         numnodes = rio_table_hdr->num_scal_dev;
1223         if (numnodes > MAX_NUMNODES){
1224                 printk(KERN_WARNING
1225                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1226                         "but system has %d nodes.\n",
1227                         MAX_NUMNODES, numnodes);
1228                 return -ENODEV;
1229         }
1230
1231         switch (rio_table_hdr->version){
1232         case 2:
1233                 scal_detail_size = 11;
1234                 rio_detail_size = 13;
1235                 break;
1236         case 3:
1237                 scal_detail_size = 12;
1238                 rio_detail_size = 15;
1239                 break;
1240         default:
1241                 printk(KERN_WARNING
1242                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1243                        rio_table_hdr->version);
1244                 return -EPROTO;
1245         }
1246
1247         ptr = ((unsigned long)rio_table_hdr) + 3;
1248         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1249                 scal_devs[i] = (struct scal_detail *)ptr;
1250
1251         for (i = 0; i < rio_table_hdr->num_rio_dev;
1252                     i++, ptr += rio_detail_size)
1253                 rio_devs[i] = (struct rio_detail *)ptr;
1254
1255         return 0;
1256 }
1257
1258 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1259 {
1260         int dev;
1261         u32 val;
1262
1263         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1264                 /*
1265                  * FIXME: properly scan for devices across the
1266                  * PCI-to-PCI bridge on every CalIOC2 port.
1267                  */
1268                 return 1;
1269         }
1270
1271         for (dev = 1; dev < 8; dev++) {
1272                 val = read_pci_config(bus, dev, 0, 0);
1273                 if (val != 0xffffffff)
1274                         break;
1275         }
1276         return (val != 0xffffffff);
1277 }
1278
1279 /*
1280  * calgary_init_bitmap_from_tce_table():
1281  * Function for kdump case. In the second/kdump kernel initialize
1282  * the bitmap based on the tce table entries obtained from first kernel
1283  */
1284 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1285 {
1286         u64 *tp;
1287         unsigned int index;
1288         tp = ((u64 *)tbl->it_base);
1289         for (index = 0 ; index < tbl->it_size; index++) {
1290                 if (*tp != 0x0)
1291                         set_bit(index, tbl->it_map);
1292                 tp++;
1293         }
1294 }
1295
1296 /*
1297  * get_tce_space_from_tar():
1298  * Function for kdump case. Get the tce tables from first kernel
1299  * by reading the contents of the base address register of calgary iommu
1300  */
1301 static void __init get_tce_space_from_tar(void)
1302 {
1303         int bus;
1304         void __iomem *target;
1305         unsigned long tce_space;
1306
1307         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1308                 struct calgary_bus_info *info = &bus_info[bus];
1309                 unsigned short pci_device;
1310                 u32 val;
1311
1312                 val = read_pci_config(bus, 0, 0, 0);
1313                 pci_device = (val & 0xFFFF0000) >> 16;
1314
1315                 if (!is_cal_pci_dev(pci_device))
1316                         continue;
1317                 if (info->translation_disabled)
1318                         continue;
1319
1320                 if (calgary_bus_has_devices(bus, pci_device) ||
1321                                                 translate_empty_slots) {
1322                         target = calgary_reg(bus_info[bus].bbar,
1323                                                 tar_offset(bus));
1324                         tce_space = be64_to_cpu(readq(target));
1325                         tce_space = tce_space & TAR_SW_BITS;
1326
1327                         tce_space = tce_space & (~specified_table_size);
1328                         info->tce_space = (u64 *)__va(tce_space);
1329                 }
1330         }
1331         return;
1332 }
1333
1334 static int __init calgary_iommu_init(void)
1335 {
1336         int ret;
1337
1338         /* ok, we're trying to use Calgary - let's roll */
1339         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1340
1341         ret = calgary_init();
1342         if (ret) {
1343                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1344                        "falling back to no_iommu\n", ret);
1345                 return ret;
1346         }
1347
1348         return 0;
1349 }
1350
1351 int __init detect_calgary(void)
1352 {
1353         int bus;
1354         void *tbl;
1355         int calgary_found = 0;
1356         unsigned long ptr;
1357         unsigned int offset, prev_offset;
1358         int ret;
1359
1360         /*
1361          * if the user specified iommu=off or iommu=soft or we found
1362          * another HW IOMMU already, bail out.
1363          */
1364         if (no_iommu || iommu_detected)
1365                 return -ENODEV;
1366
1367         if (!use_calgary)
1368                 return -ENODEV;
1369
1370         if (!early_pci_allowed())
1371                 return -ENODEV;
1372
1373         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1374
1375         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1376
1377         rio_table_hdr = NULL;
1378         prev_offset = 0;
1379         offset = 0x180;
1380         /*
1381          * The next offset is stored in the 1st word.
1382          * Only parse up until the offset increases:
1383          */
1384         while (offset > prev_offset) {
1385                 /* The block id is stored in the 2nd word */
1386                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1387                         /* set the pointer past the offset & block id */
1388                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1389                         break;
1390                 }
1391                 prev_offset = offset;
1392                 offset = *((unsigned short *)(ptr + offset));
1393         }
1394         if (!rio_table_hdr) {
1395                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1396                        "in EBDA - bailing!\n");
1397                 return -ENODEV;
1398         }
1399
1400         ret = build_detail_arrays();
1401         if (ret) {
1402                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1403                 return -ENOMEM;
1404         }
1405
1406         specified_table_size = determine_tce_table_size();
1407
1408         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1409                 struct calgary_bus_info *info = &bus_info[bus];
1410                 unsigned short pci_device;
1411                 u32 val;
1412
1413                 val = read_pci_config(bus, 0, 0, 0);
1414                 pci_device = (val & 0xFFFF0000) >> 16;
1415
1416                 if (!is_cal_pci_dev(pci_device))
1417                         continue;
1418
1419                 if (info->translation_disabled)
1420                         continue;
1421
1422                 if (calgary_bus_has_devices(bus, pci_device) ||
1423                     translate_empty_slots) {
1424                         /*
1425                          * If it is kdump kernel, find and use tce tables
1426                          * from first kernel, else allocate tce tables here
1427                          */
1428                         if (!is_kdump_kernel()) {
1429                                 tbl = alloc_tce_table();
1430                                 if (!tbl)
1431                                         goto cleanup;
1432                                 info->tce_space = tbl;
1433                         }
1434                         calgary_found = 1;
1435                 }
1436         }
1437
1438         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1439                calgary_found ? "found" : "not found");
1440
1441         if (calgary_found) {
1442                 iommu_detected = 1;
1443                 calgary_detected = 1;
1444                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1445                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1446                        specified_table_size);
1447
1448                 x86_init.iommu.iommu_init = calgary_iommu_init;
1449         }
1450         return calgary_found;
1451
1452 cleanup:
1453         for (--bus; bus >= 0; --bus) {
1454                 struct calgary_bus_info *info = &bus_info[bus];
1455
1456                 if (info->tce_space)
1457                         free_tce_table(info->tce_space);
1458         }
1459         return -ENOMEM;
1460 }
1461
1462 static int __init calgary_parse_options(char *p)
1463 {
1464         unsigned int bridge;
1465         unsigned long val;
1466         size_t len;
1467         ssize_t ret;
1468
1469         while (*p) {
1470                 if (!strncmp(p, "64k", 3))
1471                         specified_table_size = TCE_TABLE_SIZE_64K;
1472                 else if (!strncmp(p, "128k", 4))
1473                         specified_table_size = TCE_TABLE_SIZE_128K;
1474                 else if (!strncmp(p, "256k", 4))
1475                         specified_table_size = TCE_TABLE_SIZE_256K;
1476                 else if (!strncmp(p, "512k", 4))
1477                         specified_table_size = TCE_TABLE_SIZE_512K;
1478                 else if (!strncmp(p, "1M", 2))
1479                         specified_table_size = TCE_TABLE_SIZE_1M;
1480                 else if (!strncmp(p, "2M", 2))
1481                         specified_table_size = TCE_TABLE_SIZE_2M;
1482                 else if (!strncmp(p, "4M", 2))
1483                         specified_table_size = TCE_TABLE_SIZE_4M;
1484                 else if (!strncmp(p, "8M", 2))
1485                         specified_table_size = TCE_TABLE_SIZE_8M;
1486
1487                 len = strlen("translate_empty_slots");
1488                 if (!strncmp(p, "translate_empty_slots", len))
1489                         translate_empty_slots = 1;
1490
1491                 len = strlen("disable");
1492                 if (!strncmp(p, "disable", len)) {
1493                         p += len;
1494                         if (*p == '=')
1495                                 ++p;
1496                         if (*p == '\0')
1497                                 break;
1498                         ret = kstrtoul(p, 0, &val);
1499                         if (ret)
1500                                 break;
1501
1502                         bridge = val;
1503                         if (bridge < MAX_PHB_BUS_NUM) {
1504                                 printk(KERN_INFO "Calgary: disabling "
1505                                        "translation for PHB %#x\n", bridge);
1506                                 bus_info[bridge].translation_disabled = 1;
1507                         }
1508                 }
1509
1510                 p = strpbrk(p, ",");
1511                 if (!p)
1512                         break;
1513
1514                 p++; /* skip ',' */
1515         }
1516         return 1;
1517 }
1518 __setup("calgary=", calgary_parse_options);
1519
1520 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1521 {
1522         struct iommu_table *tbl;
1523         unsigned int npages;
1524         int i;
1525
1526         tbl = pci_iommu(dev->bus);
1527
1528         for (i = 0; i < 4; i++) {
1529                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1530
1531                 /* Don't give out TCEs that map MEM resources */
1532                 if (!(r->flags & IORESOURCE_MEM))
1533                         continue;
1534
1535                 /* 0-based? we reserve the whole 1st MB anyway */
1536                 if (!r->start)
1537                         continue;
1538
1539                 /* cover the whole region */
1540                 npages = resource_size(r) >> PAGE_SHIFT;
1541                 npages++;
1542
1543                 iommu_range_reserve(tbl, r->start, npages);
1544         }
1545 }
1546
1547 static int __init calgary_fixup_tce_spaces(void)
1548 {
1549         struct pci_dev *dev = NULL;
1550         struct calgary_bus_info *info;
1551
1552         if (no_iommu || swiotlb || !calgary_detected)
1553                 return -ENODEV;
1554
1555         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1556
1557         do {
1558                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1559                 if (!dev)
1560                         break;
1561                 if (!is_cal_pci_dev(dev->device))
1562                         continue;
1563
1564                 info = &bus_info[dev->bus->number];
1565                 if (info->translation_disabled)
1566                         continue;
1567
1568                 if (!info->tce_space)
1569                         continue;
1570
1571                 calgary_fixup_one_tce_space(dev);
1572
1573         } while (1);
1574
1575         return 0;
1576 }
1577
1578 /*
1579  * We need to be call after pcibios_assign_resources (fs_initcall level)
1580  * and before device_initcall.
1581  */
1582 rootfs_initcall(calgary_fixup_tce_spaces);
1583
1584 IOMMU_INIT_POST(detect_calgary);