1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from arch/powerpc/kernel/iommu.c
5 * Copyright IBM Corporation, 2006-2007
6 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
8 * Author: Jon Mason <jdmason@kudzu.us>
9 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
13 #define pr_fmt(fmt) "Calgary: " fmt
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/string.h>
22 #include <linux/crash_dump.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dma-direct.h>
25 #include <linux/bitmap.h>
26 #include <linux/pci_ids.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/scatterlist.h>
30 #include <linux/iommu-helper.h>
32 #include <asm/iommu.h>
33 #include <asm/calgary.h>
35 #include <asm/pci-direct.h>
38 #include <asm/bios_ebda.h>
39 #include <asm/x86_init.h>
40 #include <asm/iommu_table.h>
42 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
43 int use_calgary __read_mostly = 1;
45 int use_calgary __read_mostly = 0;
46 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
48 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
49 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
51 /* register offsets inside the host bridge space */
52 #define CALGARY_CONFIG_REG 0x0108
53 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
54 #define PHB_PLSSR_OFFSET 0x0120
55 #define PHB_CONFIG_RW_OFFSET 0x0160
56 #define PHB_IOBASE_BAR_LOW 0x0170
57 #define PHB_IOBASE_BAR_HIGH 0x0180
58 #define PHB_MEM_1_LOW 0x0190
59 #define PHB_MEM_1_HIGH 0x01A0
60 #define PHB_IO_ADDR_SIZE 0x01B0
61 #define PHB_MEM_1_SIZE 0x01C0
62 #define PHB_MEM_ST_OFFSET 0x01D0
63 #define PHB_AER_OFFSET 0x0200
64 #define PHB_CONFIG_0_HIGH 0x0220
65 #define PHB_CONFIG_0_LOW 0x0230
66 #define PHB_CONFIG_0_END 0x0240
67 #define PHB_MEM_2_LOW 0x02B0
68 #define PHB_MEM_2_HIGH 0x02C0
69 #define PHB_MEM_2_SIZE_HIGH 0x02D0
70 #define PHB_MEM_2_SIZE_LOW 0x02E0
71 #define PHB_DOSHOLE_OFFSET 0x08E0
73 /* CalIOC2 specific */
74 #define PHB_SAVIOR_L2 0x0DB0
75 #define PHB_PAGE_MIG_CTRL 0x0DA8
76 #define PHB_PAGE_MIG_DEBUG 0x0DA0
77 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
80 #define PHB_TCE_ENABLE 0x20000000
81 #define PHB_SLOT_DISABLE 0x1C000000
82 #define PHB_DAC_DISABLE 0x01000000
83 #define PHB_MEM2_ENABLE 0x00400000
84 #define PHB_MCSR_ENABLE 0x00100000
85 /* TAR (Table Address Register) */
86 #define TAR_SW_BITS 0x0000ffffffff800fUL
87 #define TAR_VALID 0x0000000000000008UL
88 /* CSR (Channel/DMA Status Register) */
89 #define CSR_AGENT_MASK 0xffe0ffff
90 /* CCR (Calgary Configuration Register) */
91 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
92 /* PMCR/PMDR (Page Migration Control/Debug Registers */
93 #define PMR_SOFTSTOP 0x80000000
94 #define PMR_SOFTSTOPFAULT 0x40000000
95 #define PMR_HARDSTOP 0x20000000
98 * The maximum PHB bus number.
99 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
100 * x3950M2: 4 chassis, 48 PHBs per chassis = 192
101 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
102 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
104 #define MAX_PHB_BUS_NUM 256
106 #define PHBS_PER_CALGARY 4
108 /* register offsets in Calgary's internal register space */
109 static const unsigned long tar_offsets[] = {
116 static const unsigned long split_queue_offsets[] = {
117 0x4870 /* SPLIT QUEUE 0 */,
118 0x5870 /* SPLIT QUEUE 1 */,
119 0x6870 /* SPLIT QUEUE 2 */,
120 0x7870 /* SPLIT QUEUE 3 */
123 static const unsigned long phb_offsets[] = {
130 /* PHB debug registers */
132 static const unsigned long phb_debug_offsets[] = {
133 0x4000 /* PHB 0 DEBUG */,
134 0x5000 /* PHB 1 DEBUG */,
135 0x6000 /* PHB 2 DEBUG */,
136 0x7000 /* PHB 3 DEBUG */
140 * STUFF register for each debug PHB,
141 * byte 1 = start bus number, byte 2 = end bus number
144 #define PHB_DEBUG_STUFF_OFFSET 0x0020
146 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
147 static int translate_empty_slots __read_mostly = 0;
148 static int calgary_detected __read_mostly = 0;
150 static struct rio_table_hdr *rio_table_hdr __initdata;
151 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
152 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
154 struct calgary_bus_info {
156 unsigned char translation_disabled;
161 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
162 static void calgary_tce_cache_blast(struct iommu_table *tbl);
163 static void calgary_dump_error_regs(struct iommu_table *tbl);
164 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
165 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
166 static void calioc2_dump_error_regs(struct iommu_table *tbl);
167 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
168 static void get_tce_space_from_tar(void);
170 static const struct cal_chipset_ops calgary_chip_ops = {
171 .handle_quirks = calgary_handle_quirks,
172 .tce_cache_blast = calgary_tce_cache_blast,
173 .dump_error_regs = calgary_dump_error_regs
176 static const struct cal_chipset_ops calioc2_chip_ops = {
177 .handle_quirks = calioc2_handle_quirks,
178 .tce_cache_blast = calioc2_tce_cache_blast,
179 .dump_error_regs = calioc2_dump_error_regs
182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
184 static inline int translation_enabled(struct iommu_table *tbl)
186 /* only PHBs with translation enabled have an IOMMU table */
187 return (tbl != NULL);
190 static void iommu_range_reserve(struct iommu_table *tbl,
191 unsigned long start_addr, unsigned int npages)
197 index = start_addr >> PAGE_SHIFT;
199 /* bail out if we're asked to reserve a region we don't cover */
200 if (index >= tbl->it_size)
203 end = index + npages;
204 if (end > tbl->it_size) /* don't go off the table */
207 spin_lock_irqsave(&tbl->it_lock, flags);
209 bitmap_set(tbl->it_map, index, npages);
211 spin_unlock_irqrestore(&tbl->it_lock, flags);
214 static unsigned long iommu_range_alloc(struct device *dev,
215 struct iommu_table *tbl,
219 unsigned long offset;
220 unsigned long boundary_size;
222 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
223 PAGE_SIZE) >> PAGE_SHIFT;
227 spin_lock_irqsave(&tbl->it_lock, flags);
229 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
230 npages, 0, boundary_size, 0);
231 if (offset == ~0UL) {
232 tbl->chip_ops->tce_cache_blast(tbl);
234 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
235 npages, 0, boundary_size, 0);
236 if (offset == ~0UL) {
237 pr_warn("IOMMU full\n");
238 spin_unlock_irqrestore(&tbl->it_lock, flags);
239 if (panic_on_overflow)
240 panic("Calgary: fix the allocator.\n");
242 return DMA_MAPPING_ERROR;
246 tbl->it_hint = offset + npages;
247 BUG_ON(tbl->it_hint > tbl->it_size);
249 spin_unlock_irqrestore(&tbl->it_lock, flags);
254 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
255 void *vaddr, unsigned int npages, int direction)
260 entry = iommu_range_alloc(dev, tbl, npages);
261 if (unlikely(entry == DMA_MAPPING_ERROR)) {
262 pr_warn("failed to allocate %u pages in iommu %p\n",
264 return DMA_MAPPING_ERROR;
267 /* set the return dma address */
268 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
270 /* put the TCEs in the HW table */
271 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
276 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
282 /* were we called with bad_dma_address? */
283 if (unlikely(dma_addr == DMA_MAPPING_ERROR)) {
284 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
285 "address 0x%Lx\n", dma_addr);
289 entry = dma_addr >> PAGE_SHIFT;
291 BUG_ON(entry + npages > tbl->it_size);
293 tce_free(tbl, entry, npages);
295 spin_lock_irqsave(&tbl->it_lock, flags);
297 bitmap_clear(tbl->it_map, entry, npages);
299 spin_unlock_irqrestore(&tbl->it_lock, flags);
302 static inline struct iommu_table *find_iommu_table(struct device *dev)
304 struct pci_dev *pdev;
305 struct pci_bus *pbus;
306 struct iommu_table *tbl;
308 pdev = to_pci_dev(dev);
310 /* search up the device tree for an iommu */
313 tbl = pci_iommu(pbus);
314 if (tbl && tbl->it_busno == pbus->number)
320 BUG_ON(tbl && (tbl->it_busno != pbus->number));
325 static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
326 int nelems,enum dma_data_direction dir,
329 struct iommu_table *tbl = find_iommu_table(dev);
330 struct scatterlist *s;
333 if (!translation_enabled(tbl))
336 for_each_sg(sglist, s, nelems, i) {
338 dma_addr_t dma = s->dma_address;
339 unsigned int dmalen = s->dma_length;
344 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
345 iommu_free(tbl, dma, npages);
349 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
350 int nelems, enum dma_data_direction dir,
353 struct iommu_table *tbl = find_iommu_table(dev);
354 struct scatterlist *s;
360 for_each_sg(sg, s, nelems, i) {
363 vaddr = (unsigned long) sg_virt(s);
364 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
366 entry = iommu_range_alloc(dev, tbl, npages);
367 if (entry == DMA_MAPPING_ERROR) {
368 /* makes sure unmap knows to stop */
373 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
375 /* insert into HW table */
376 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
378 s->dma_length = s->length;
383 calgary_unmap_sg(dev, sg, nelems, dir, 0);
384 for_each_sg(sg, s, nelems, i) {
385 sg->dma_address = DMA_MAPPING_ERROR;
391 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
392 unsigned long offset, size_t size,
393 enum dma_data_direction dir,
396 void *vaddr = page_address(page) + offset;
399 struct iommu_table *tbl = find_iommu_table(dev);
401 uaddr = (unsigned long)vaddr;
402 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
404 return iommu_alloc(dev, tbl, vaddr, npages, dir);
407 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
408 size_t size, enum dma_data_direction dir,
411 struct iommu_table *tbl = find_iommu_table(dev);
414 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
415 iommu_free(tbl, dma_addr, npages);
418 static void* calgary_alloc_coherent(struct device *dev, size_t size,
419 dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
423 unsigned int npages, order;
424 struct iommu_table *tbl = find_iommu_table(dev);
426 size = PAGE_ALIGN(size); /* size rounded up to full pages */
427 npages = size >> PAGE_SHIFT;
428 order = get_order(size);
430 /* alloc enough pages (and possibly more) */
431 ret = (void *)__get_free_pages(flag, order);
434 memset(ret, 0, size);
436 /* set up tces to cover the allocated range */
437 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
438 if (mapping == DMA_MAPPING_ERROR)
440 *dma_handle = mapping;
443 free_pages((unsigned long)ret, get_order(size));
449 static void calgary_free_coherent(struct device *dev, size_t size,
450 void *vaddr, dma_addr_t dma_handle,
454 struct iommu_table *tbl = find_iommu_table(dev);
456 size = PAGE_ALIGN(size);
457 npages = size >> PAGE_SHIFT;
459 iommu_free(tbl, dma_handle, npages);
460 free_pages((unsigned long)vaddr, get_order(size));
463 static const struct dma_map_ops calgary_dma_ops = {
464 .alloc = calgary_alloc_coherent,
465 .free = calgary_free_coherent,
466 .map_sg = calgary_map_sg,
467 .unmap_sg = calgary_unmap_sg,
468 .map_page = calgary_map_page,
469 .unmap_page = calgary_unmap_page,
470 .dma_supported = dma_direct_supported,
473 static inline void __iomem * busno_to_bbar(unsigned char num)
475 return bus_info[num].bbar;
478 static inline int busno_to_phbid(unsigned char num)
480 return bus_info[num].phbid;
483 static inline unsigned long split_queue_offset(unsigned char num)
485 size_t idx = busno_to_phbid(num);
487 return split_queue_offsets[idx];
490 static inline unsigned long tar_offset(unsigned char num)
492 size_t idx = busno_to_phbid(num);
494 return tar_offsets[idx];
497 static inline unsigned long phb_offset(unsigned char num)
499 size_t idx = busno_to_phbid(num);
501 return phb_offsets[idx];
504 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
506 unsigned long target = ((unsigned long)bar) | offset;
507 return (void __iomem*)target;
510 static inline int is_calioc2(unsigned short device)
512 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
515 static inline int is_calgary(unsigned short device)
517 return (device == PCI_DEVICE_ID_IBM_CALGARY);
520 static inline int is_cal_pci_dev(unsigned short device)
522 return (is_calgary(device) || is_calioc2(device));
525 static void calgary_tce_cache_blast(struct iommu_table *tbl)
530 void __iomem *bbar = tbl->bbar;
531 void __iomem *target;
533 /* disable arbitration on the bus */
534 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
538 /* read plssr to ensure it got there */
539 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
542 /* poll split queues until all DMA activity is done */
543 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
547 } while ((val & 0xff) != 0xff && i < 100);
549 pr_warn("PCI bus not quiesced, continuing anyway\n");
551 /* invalidate TCE cache */
552 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
553 writeq(tbl->tar_val, target);
555 /* enable arbitration */
556 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
558 (void)readl(target); /* flush */
561 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
563 void __iomem *bbar = tbl->bbar;
564 void __iomem *target;
569 unsigned char bus = tbl->it_busno;
572 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
573 "sequence - count %d\n", bus, count);
575 /* 1. using the Page Migration Control reg set SoftStop */
576 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
577 val = be32_to_cpu(readl(target));
578 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
580 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
581 writel(cpu_to_be32(val), target);
583 /* 2. poll split queues until all DMA activity is done */
584 printk(KERN_DEBUG "2a. starting to poll split queues\n");
585 target = calgary_reg(bbar, split_queue_offset(bus));
587 val64 = readq(target);
589 } while ((val64 & 0xff) != 0xff && i < 100);
591 pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
593 /* 3. poll Page Migration DEBUG for SoftStopFault */
594 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
595 val = be32_to_cpu(readl(target));
596 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
598 /* 4. if SoftStopFault - goto (1) */
599 if (val & PMR_SOFTSTOPFAULT) {
603 pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
604 return; /* pray for the best */
608 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
609 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
610 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
611 val = be32_to_cpu(readl(target));
612 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
613 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
614 val = be32_to_cpu(readl(target));
615 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
617 /* 6. invalidate TCE cache */
618 printk(KERN_DEBUG "6. invalidating TCE cache\n");
619 target = calgary_reg(bbar, tar_offset(bus));
620 writeq(tbl->tar_val, target);
622 /* 7. Re-read PMCR */
623 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
624 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
625 val = be32_to_cpu(readl(target));
626 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
628 /* 8. Remove HardStop */
629 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
630 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
632 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
633 writel(cpu_to_be32(val), target);
634 val = be32_to_cpu(readl(target));
635 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
638 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
641 unsigned int numpages;
643 limit = limit | 0xfffff;
646 numpages = ((limit - start) >> PAGE_SHIFT);
647 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
650 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
652 void __iomem *target;
653 u64 low, high, sizelow;
655 struct iommu_table *tbl = pci_iommu(dev->bus);
656 unsigned char busnum = dev->bus->number;
657 void __iomem *bbar = tbl->bbar;
659 /* peripheral MEM_1 region */
660 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
661 low = be32_to_cpu(readl(target));
662 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
663 high = be32_to_cpu(readl(target));
664 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
665 sizelow = be32_to_cpu(readl(target));
667 start = (high << 32) | low;
670 calgary_reserve_mem_region(dev, start, limit);
673 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
675 void __iomem *target;
677 u64 low, high, sizelow, sizehigh;
679 struct iommu_table *tbl = pci_iommu(dev->bus);
680 unsigned char busnum = dev->bus->number;
681 void __iomem *bbar = tbl->bbar;
684 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
685 val32 = be32_to_cpu(readl(target));
686 if (!(val32 & PHB_MEM2_ENABLE))
689 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
690 low = be32_to_cpu(readl(target));
691 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
692 high = be32_to_cpu(readl(target));
693 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
694 sizelow = be32_to_cpu(readl(target));
695 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
696 sizehigh = be32_to_cpu(readl(target));
698 start = (high << 32) | low;
699 limit = (sizehigh << 32) | sizelow;
701 calgary_reserve_mem_region(dev, start, limit);
705 * some regions of the IO address space do not get translated, so we
706 * must not give devices IO addresses in those regions. The regions
707 * are the 640KB-1MB region and the two PCI peripheral memory holes.
708 * Reserve all of them in the IOMMU bitmap to avoid giving them out
711 static void __init calgary_reserve_regions(struct pci_dev *dev)
715 struct iommu_table *tbl = pci_iommu(dev->bus);
717 /* avoid the BIOS/VGA first 640KB-1MB region */
718 /* for CalIOC2 - avoid the entire first MB */
719 if (is_calgary(dev->device)) {
720 start = (640 * 1024);
721 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
722 } else { /* calioc2 */
724 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
726 iommu_range_reserve(tbl, start, npages);
728 /* reserve the two PCI peripheral memory regions in IO space */
729 calgary_reserve_peripheral_mem_1(dev);
730 calgary_reserve_peripheral_mem_2(dev);
733 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
737 void __iomem *target;
739 struct iommu_table *tbl;
741 /* build TCE tables for each PHB */
742 ret = build_tce_table(dev, bbar);
746 tbl = pci_iommu(dev->bus);
747 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
749 if (is_kdump_kernel())
750 calgary_init_bitmap_from_tce_table(tbl);
752 tce_free(tbl, 0, tbl->it_size);
754 if (is_calgary(dev->device))
755 tbl->chip_ops = &calgary_chip_ops;
756 else if (is_calioc2(dev->device))
757 tbl->chip_ops = &calioc2_chip_ops;
761 calgary_reserve_regions(dev);
763 /* set TARs for each PHB */
764 target = calgary_reg(bbar, tar_offset(dev->bus->number));
765 val64 = be64_to_cpu(readq(target));
767 /* zero out all TAR bits under sw control */
768 val64 &= ~TAR_SW_BITS;
769 table_phys = (u64)__pa(tbl->it_base);
773 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
774 val64 |= (u64) specified_table_size;
776 tbl->tar_val = cpu_to_be64(val64);
778 writeq(tbl->tar_val, target);
779 readq(target); /* flush */
784 static void __init calgary_free_bus(struct pci_dev *dev)
787 struct iommu_table *tbl = pci_iommu(dev->bus);
788 void __iomem *target;
789 unsigned int bitmapsz;
791 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
792 val64 = be64_to_cpu(readq(target));
793 val64 &= ~TAR_SW_BITS;
794 writeq(cpu_to_be64(val64), target);
795 readq(target); /* flush */
797 bitmapsz = tbl->it_size / BITS_PER_BYTE;
798 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
803 set_pci_iommu(dev->bus, NULL);
805 /* Can't free bootmem allocated memory after system is up :-( */
806 bus_info[dev->bus->number].tce_space = NULL;
809 static void calgary_dump_error_regs(struct iommu_table *tbl)
811 void __iomem *bbar = tbl->bbar;
812 void __iomem *target;
815 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
816 csr = be32_to_cpu(readl(target));
818 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
819 plssr = be32_to_cpu(readl(target));
821 /* If no error, the agent ID in the CSR is not valid */
822 pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
823 tbl->it_busno, csr, plssr);
826 static void calioc2_dump_error_regs(struct iommu_table *tbl)
828 void __iomem *bbar = tbl->bbar;
829 u32 csr, csmr, plssr, mck, rcstat;
830 void __iomem *target;
831 unsigned long phboff = phb_offset(tbl->it_busno);
832 unsigned long erroff;
837 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
838 csr = be32_to_cpu(readl(target));
840 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
841 plssr = be32_to_cpu(readl(target));
843 target = calgary_reg(bbar, phboff | 0x290);
844 csmr = be32_to_cpu(readl(target));
846 target = calgary_reg(bbar, phboff | 0x800);
847 mck = be32_to_cpu(readl(target));
849 pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
851 pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
852 csr, plssr, csmr, mck);
854 /* dump rest of error regs */
856 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
857 /* err regs are at 0x810 - 0x870 */
858 erroff = (0x810 + (i * 0x10));
859 target = calgary_reg(bbar, phboff | erroff);
860 errregs[i] = be32_to_cpu(readl(target));
861 pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
865 /* root complex status */
866 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
867 rcstat = be32_to_cpu(readl(target));
868 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
869 PHB_ROOT_COMPLEX_STATUS);
872 static void calgary_watchdog(struct timer_list *t)
874 struct iommu_table *tbl = from_timer(tbl, t, watchdog_timer);
875 void __iomem *bbar = tbl->bbar;
877 void __iomem *target;
879 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
880 val32 = be32_to_cpu(readl(target));
882 /* If no error, the agent ID in the CSR is not valid */
883 if (val32 & CSR_AGENT_MASK) {
884 tbl->chip_ops->dump_error_regs(tbl);
889 /* Disable bus that caused the error */
890 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
891 PHB_CONFIG_RW_OFFSET);
892 val32 = be32_to_cpu(readl(target));
893 val32 |= PHB_SLOT_DISABLE;
894 writel(cpu_to_be32(val32), target);
895 readl(target); /* flush */
897 /* Reset the timer */
898 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
902 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
903 unsigned char busnum, unsigned long timeout)
906 void __iomem *target;
907 unsigned int phb_shift = ~0; /* silence gcc */
910 switch (busno_to_phbid(busnum)) {
911 case 0: phb_shift = (63 - 19);
913 case 1: phb_shift = (63 - 23);
915 case 2: phb_shift = (63 - 27);
917 case 3: phb_shift = (63 - 35);
920 BUG_ON(busno_to_phbid(busnum));
923 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
924 val64 = be64_to_cpu(readq(target));
926 /* zero out this PHB's timer bits */
927 mask = ~(0xFUL << phb_shift);
929 val64 |= (timeout << phb_shift);
930 writeq(cpu_to_be64(val64), target);
931 readq(target); /* flush */
934 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
936 unsigned char busnum = dev->bus->number;
937 void __iomem *bbar = tbl->bbar;
938 void __iomem *target;
942 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
944 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
945 val = cpu_to_be32(readl(target));
947 writel(cpu_to_be32(val), target);
950 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
952 unsigned char busnum = dev->bus->number;
955 * Give split completion a longer timeout on bus 1 for aic94xx
956 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
958 if (is_calgary(dev->device) && (busnum == 1))
959 calgary_set_split_completion_timeout(tbl->bbar, busnum,
963 static void __init calgary_enable_translation(struct pci_dev *dev)
966 unsigned char busnum;
967 void __iomem *target;
969 struct iommu_table *tbl;
971 busnum = dev->bus->number;
972 tbl = pci_iommu(dev->bus);
975 /* enable TCE in PHB Config Register */
976 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
977 val32 = be32_to_cpu(readl(target));
978 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
980 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
981 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
982 "Calgary" : "CalIOC2", busnum);
983 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
986 writel(cpu_to_be32(val32), target);
987 readl(target); /* flush */
989 timer_setup(&tbl->watchdog_timer, calgary_watchdog, 0);
990 mod_timer(&tbl->watchdog_timer, jiffies);
993 static void __init calgary_disable_translation(struct pci_dev *dev)
996 unsigned char busnum;
997 void __iomem *target;
999 struct iommu_table *tbl;
1001 busnum = dev->bus->number;
1002 tbl = pci_iommu(dev->bus);
1005 /* disable TCE in PHB Config Register */
1006 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1007 val32 = be32_to_cpu(readl(target));
1008 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1010 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1011 writel(cpu_to_be32(val32), target);
1012 readl(target); /* flush */
1014 del_timer_sync(&tbl->watchdog_timer);
1017 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1020 set_pci_iommu(dev->bus, NULL);
1022 /* is the device behind a bridge? */
1023 if (dev->bus->parent)
1024 dev->bus->parent->self = dev;
1026 dev->bus->self = dev;
1029 static int __init calgary_init_one(struct pci_dev *dev)
1032 struct iommu_table *tbl;
1035 bbar = busno_to_bbar(dev->bus->number);
1036 ret = calgary_setup_tar(dev, bbar);
1042 if (dev->bus->parent) {
1043 if (dev->bus->parent->self)
1044 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1045 "bus->parent->self!\n", dev);
1046 dev->bus->parent->self = dev;
1048 dev->bus->self = dev;
1050 tbl = pci_iommu(dev->bus);
1051 tbl->chip_ops->handle_quirks(tbl, dev);
1053 calgary_enable_translation(dev);
1061 static int __init calgary_locate_bbars(void)
1064 int rioidx, phb, bus;
1066 void __iomem *target;
1067 unsigned long offset;
1068 u8 start_bus, end_bus;
1072 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1073 struct rio_detail *rio = rio_devs[rioidx];
1075 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1078 /* map entire 1MB of Calgary config space */
1079 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1083 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1084 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1085 target = calgary_reg(bbar, offset);
1087 val = be32_to_cpu(readl(target));
1089 start_bus = (u8)((val & 0x00FF0000) >> 16);
1090 end_bus = (u8)((val & 0x0000FF00) >> 8);
1093 for (bus = start_bus; bus <= end_bus; bus++) {
1094 bus_info[bus].bbar = bbar;
1095 bus_info[bus].phbid = phb;
1098 bus_info[start_bus].bbar = bbar;
1099 bus_info[start_bus].phbid = phb;
1107 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1108 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1109 if (bus_info[bus].bbar)
1110 iounmap(bus_info[bus].bbar);
1115 static int __init calgary_init(void)
1118 struct pci_dev *dev = NULL;
1119 struct calgary_bus_info *info;
1121 ret = calgary_locate_bbars();
1125 /* Purely for kdump kernel case */
1126 if (is_kdump_kernel())
1127 get_tce_space_from_tar();
1130 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1133 if (!is_cal_pci_dev(dev->device))
1136 info = &bus_info[dev->bus->number];
1137 if (info->translation_disabled) {
1138 calgary_init_one_nontraslated(dev);
1142 if (!info->tce_space && !translate_empty_slots)
1145 ret = calgary_init_one(dev);
1151 for_each_pci_dev(dev) {
1152 struct iommu_table *tbl;
1154 tbl = find_iommu_table(&dev->dev);
1156 if (translation_enabled(tbl))
1157 dev->dev.dma_ops = &calgary_dma_ops;
1164 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1167 if (!is_cal_pci_dev(dev->device))
1170 info = &bus_info[dev->bus->number];
1171 if (info->translation_disabled) {
1175 if (!info->tce_space && !translate_empty_slots)
1178 calgary_disable_translation(dev);
1179 calgary_free_bus(dev);
1180 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1181 dev->dev.dma_ops = NULL;
1187 static inline int __init determine_tce_table_size(void)
1191 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1192 return specified_table_size;
1194 if (is_kdump_kernel() && saved_max_pfn) {
1196 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1197 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1198 * larger table size has twice as many entries, so shift the
1199 * max ram address by 13 to divide by 8K and then look at the
1200 * order of the result to choose between 0-7.
1202 ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
1203 if (ret > TCE_TABLE_SIZE_8M)
1204 ret = TCE_TABLE_SIZE_8M;
1207 * Use 8M by default (suggested by Muli) if it's not
1208 * kdump kernel and saved_max_pfn isn't set.
1210 ret = TCE_TABLE_SIZE_8M;
1216 static int __init build_detail_arrays(void)
1219 unsigned numnodes, i;
1220 int scal_detail_size, rio_detail_size;
1222 numnodes = rio_table_hdr->num_scal_dev;
1223 if (numnodes > MAX_NUMNODES){
1225 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1226 "but system has %d nodes.\n",
1227 MAX_NUMNODES, numnodes);
1231 switch (rio_table_hdr->version){
1233 scal_detail_size = 11;
1234 rio_detail_size = 13;
1237 scal_detail_size = 12;
1238 rio_detail_size = 15;
1242 "Calgary: Invalid Rio Grande Table Version: %d\n",
1243 rio_table_hdr->version);
1247 ptr = ((unsigned long)rio_table_hdr) + 3;
1248 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1249 scal_devs[i] = (struct scal_detail *)ptr;
1251 for (i = 0; i < rio_table_hdr->num_rio_dev;
1252 i++, ptr += rio_detail_size)
1253 rio_devs[i] = (struct rio_detail *)ptr;
1258 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1263 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1265 * FIXME: properly scan for devices across the
1266 * PCI-to-PCI bridge on every CalIOC2 port.
1271 for (dev = 1; dev < 8; dev++) {
1272 val = read_pci_config(bus, dev, 0, 0);
1273 if (val != 0xffffffff)
1276 return (val != 0xffffffff);
1280 * calgary_init_bitmap_from_tce_table():
1281 * Function for kdump case. In the second/kdump kernel initialize
1282 * the bitmap based on the tce table entries obtained from first kernel
1284 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1288 tp = ((u64 *)tbl->it_base);
1289 for (index = 0 ; index < tbl->it_size; index++) {
1291 set_bit(index, tbl->it_map);
1297 * get_tce_space_from_tar():
1298 * Function for kdump case. Get the tce tables from first kernel
1299 * by reading the contents of the base address register of calgary iommu
1301 static void __init get_tce_space_from_tar(void)
1304 void __iomem *target;
1305 unsigned long tce_space;
1307 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1308 struct calgary_bus_info *info = &bus_info[bus];
1309 unsigned short pci_device;
1312 val = read_pci_config(bus, 0, 0, 0);
1313 pci_device = (val & 0xFFFF0000) >> 16;
1315 if (!is_cal_pci_dev(pci_device))
1317 if (info->translation_disabled)
1320 if (calgary_bus_has_devices(bus, pci_device) ||
1321 translate_empty_slots) {
1322 target = calgary_reg(bus_info[bus].bbar,
1324 tce_space = be64_to_cpu(readq(target));
1325 tce_space = tce_space & TAR_SW_BITS;
1327 tce_space = tce_space & (~specified_table_size);
1328 info->tce_space = (u64 *)__va(tce_space);
1334 static int __init calgary_iommu_init(void)
1338 /* ok, we're trying to use Calgary - let's roll */
1339 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1341 ret = calgary_init();
1343 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1344 "falling back to no_iommu\n", ret);
1351 int __init detect_calgary(void)
1355 int calgary_found = 0;
1357 unsigned int offset, prev_offset;
1361 * if the user specified iommu=off or iommu=soft or we found
1362 * another HW IOMMU already, bail out.
1364 if (no_iommu || iommu_detected)
1370 if (!early_pci_allowed())
1373 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1375 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1377 rio_table_hdr = NULL;
1381 * The next offset is stored in the 1st word.
1382 * Only parse up until the offset increases:
1384 while (offset > prev_offset) {
1385 /* The block id is stored in the 2nd word */
1386 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1387 /* set the pointer past the offset & block id */
1388 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1391 prev_offset = offset;
1392 offset = *((unsigned short *)(ptr + offset));
1394 if (!rio_table_hdr) {
1395 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1396 "in EBDA - bailing!\n");
1400 ret = build_detail_arrays();
1402 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1406 specified_table_size = determine_tce_table_size();
1408 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1409 struct calgary_bus_info *info = &bus_info[bus];
1410 unsigned short pci_device;
1413 val = read_pci_config(bus, 0, 0, 0);
1414 pci_device = (val & 0xFFFF0000) >> 16;
1416 if (!is_cal_pci_dev(pci_device))
1419 if (info->translation_disabled)
1422 if (calgary_bus_has_devices(bus, pci_device) ||
1423 translate_empty_slots) {
1425 * If it is kdump kernel, find and use tce tables
1426 * from first kernel, else allocate tce tables here
1428 if (!is_kdump_kernel()) {
1429 tbl = alloc_tce_table();
1432 info->tce_space = tbl;
1438 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1439 calgary_found ? "found" : "not found");
1441 if (calgary_found) {
1443 calgary_detected = 1;
1444 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1445 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1446 specified_table_size);
1448 x86_init.iommu.iommu_init = calgary_iommu_init;
1450 return calgary_found;
1453 for (--bus; bus >= 0; --bus) {
1454 struct calgary_bus_info *info = &bus_info[bus];
1456 if (info->tce_space)
1457 free_tce_table(info->tce_space);
1462 static int __init calgary_parse_options(char *p)
1464 unsigned int bridge;
1470 if (!strncmp(p, "64k", 3))
1471 specified_table_size = TCE_TABLE_SIZE_64K;
1472 else if (!strncmp(p, "128k", 4))
1473 specified_table_size = TCE_TABLE_SIZE_128K;
1474 else if (!strncmp(p, "256k", 4))
1475 specified_table_size = TCE_TABLE_SIZE_256K;
1476 else if (!strncmp(p, "512k", 4))
1477 specified_table_size = TCE_TABLE_SIZE_512K;
1478 else if (!strncmp(p, "1M", 2))
1479 specified_table_size = TCE_TABLE_SIZE_1M;
1480 else if (!strncmp(p, "2M", 2))
1481 specified_table_size = TCE_TABLE_SIZE_2M;
1482 else if (!strncmp(p, "4M", 2))
1483 specified_table_size = TCE_TABLE_SIZE_4M;
1484 else if (!strncmp(p, "8M", 2))
1485 specified_table_size = TCE_TABLE_SIZE_8M;
1487 len = strlen("translate_empty_slots");
1488 if (!strncmp(p, "translate_empty_slots", len))
1489 translate_empty_slots = 1;
1491 len = strlen("disable");
1492 if (!strncmp(p, "disable", len)) {
1498 ret = kstrtoul(p, 0, &val);
1503 if (bridge < MAX_PHB_BUS_NUM) {
1504 printk(KERN_INFO "Calgary: disabling "
1505 "translation for PHB %#x\n", bridge);
1506 bus_info[bridge].translation_disabled = 1;
1510 p = strpbrk(p, ",");
1518 __setup("calgary=", calgary_parse_options);
1520 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1522 struct iommu_table *tbl;
1523 unsigned int npages;
1526 tbl = pci_iommu(dev->bus);
1528 for (i = 0; i < 4; i++) {
1529 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1531 /* Don't give out TCEs that map MEM resources */
1532 if (!(r->flags & IORESOURCE_MEM))
1535 /* 0-based? we reserve the whole 1st MB anyway */
1539 /* cover the whole region */
1540 npages = resource_size(r) >> PAGE_SHIFT;
1543 iommu_range_reserve(tbl, r->start, npages);
1547 static int __init calgary_fixup_tce_spaces(void)
1549 struct pci_dev *dev = NULL;
1550 struct calgary_bus_info *info;
1552 if (no_iommu || swiotlb || !calgary_detected)
1555 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1558 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1561 if (!is_cal_pci_dev(dev->device))
1564 info = &bus_info[dev->bus->number];
1565 if (info->translation_disabled)
1568 if (!info->tce_space)
1571 calgary_fixup_one_tce_space(dev);
1579 * We need to be call after pcibios_assign_resources (fs_initcall level)
1580 * and before device_initcall.
1582 rootfs_initcall(calgary_fixup_tce_spaces);
1584 IOMMU_INIT_POST(detect_calgary);