1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <trace/events/power.h>
26 #include <linux/hw_breakpoint.h>
29 #include <asm/syscalls.h>
30 #include <linux/uaccess.h>
31 #include <asm/mwait.h>
32 #include <asm/fpu/internal.h>
33 #include <asm/debugreg.h>
35 #include <asm/tlbflush.h>
38 #include <asm/switch_to.h>
40 #include <asm/prctl.h>
41 #include <asm/spec-ctrl.h>
44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
46 * so they are allowed to end up in the .data..cacheline_aligned
47 * section. Since TSS's are completely CPU-local, we want them
48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
50 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
53 * .sp0 is only used when entering ring 0 from a lower
54 * privilege level. Since the init task never runs anything
55 * but ring 0 code, there is no need for a valid value here.
58 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
61 * .sp1 is cpu_current_top_of_stack. The init task never
62 * runs user code, but cpu_current_top_of_stack should still
63 * be well defined before the first context switch.
65 .sp1 = TOP_OF_INIT_STACK,
70 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
75 * Note that the .io_bitmap member must be extra-big. This is because
76 * the CPU will access an additional byte beyond the end of the IO
77 * permission bitmap. The extra byte must be all 1 bits, and must
78 * be within the limit.
80 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
83 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
85 DEFINE_PER_CPU(bool, __tss_limit_invalid);
86 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
89 * this gets called so that we can store lazy state into memory and copy the
90 * current task into the new thread.
92 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
94 memcpy(dst, src, arch_task_struct_size);
96 dst->thread.vm86 = NULL;
99 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
103 * Free current thread data structures etc..
105 void exit_thread(struct task_struct *tsk)
107 struct thread_struct *t = &tsk->thread;
108 unsigned long *bp = t->io_bitmap_ptr;
109 struct fpu *fpu = &t->fpu;
112 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
114 t->io_bitmap_ptr = NULL;
115 clear_thread_flag(TIF_IO_BITMAP);
117 * Careful, clear this in the TSS too:
119 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
120 t->io_bitmap_max = 0;
130 void flush_thread(void)
132 struct task_struct *tsk = current;
134 flush_ptrace_hw_breakpoint(tsk);
135 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
137 fpu__clear(&tsk->thread.fpu);
140 void disable_TSC(void)
143 if (!test_and_set_thread_flag(TIF_NOTSC))
145 * Must flip the CPU state synchronously with
146 * TIF_NOTSC in the current running context.
148 cr4_set_bits(X86_CR4_TSD);
152 static void enable_TSC(void)
155 if (test_and_clear_thread_flag(TIF_NOTSC))
157 * Must flip the CPU state synchronously with
158 * TIF_NOTSC in the current running context.
160 cr4_clear_bits(X86_CR4_TSD);
164 int get_tsc_mode(unsigned long adr)
168 if (test_thread_flag(TIF_NOTSC))
169 val = PR_TSC_SIGSEGV;
173 return put_user(val, (unsigned int __user *)adr);
176 int set_tsc_mode(unsigned int val)
178 if (val == PR_TSC_SIGSEGV)
180 else if (val == PR_TSC_ENABLE)
188 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
190 static void set_cpuid_faulting(bool on)
194 msrval = this_cpu_read(msr_misc_features_shadow);
195 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
196 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
197 this_cpu_write(msr_misc_features_shadow, msrval);
198 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
201 static void disable_cpuid(void)
204 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
206 * Must flip the CPU state synchronously with
207 * TIF_NOCPUID in the current running context.
209 set_cpuid_faulting(true);
214 static void enable_cpuid(void)
217 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
219 * Must flip the CPU state synchronously with
220 * TIF_NOCPUID in the current running context.
222 set_cpuid_faulting(false);
227 static int get_cpuid_mode(void)
229 return !test_thread_flag(TIF_NOCPUID);
232 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
234 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
246 * Called immediately after a successful exec.
248 void arch_setup_new_exec(void)
250 /* If cpuid was previously disabled for this task, re-enable it. */
251 if (test_thread_flag(TIF_NOCPUID))
255 static inline void switch_to_bitmap(struct tss_struct *tss,
256 struct thread_struct *prev,
257 struct thread_struct *next,
258 unsigned long tifp, unsigned long tifn)
260 if (tifn & _TIF_IO_BITMAP) {
262 * Copy the relevant range of the IO bitmap.
263 * Normally this is 128 bytes or less:
265 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
266 max(prev->io_bitmap_max, next->io_bitmap_max));
268 * Make sure that the TSS limit is correct for the CPU
269 * to notice the IO bitmap.
272 } else if (tifp & _TIF_IO_BITMAP) {
274 * Clear any possible leftover bits:
276 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
283 struct ssb_state *shared_state;
285 unsigned int disable_state;
286 unsigned long local_state;
291 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
293 void speculative_store_bypass_ht_init(void)
295 struct ssb_state *st = this_cpu_ptr(&ssb_state);
296 unsigned int this_cpu = smp_processor_id();
302 * Shared state setup happens once on the first bringup
303 * of the CPU. It's not destroyed on CPU hotunplug.
305 if (st->shared_state)
308 raw_spin_lock_init(&st->lock);
311 * Go over HT siblings and check whether one of them has set up the
312 * shared state pointer already.
314 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
318 if (!per_cpu(ssb_state, cpu).shared_state)
321 /* Link it to the state of the sibling: */
322 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
327 * First HT sibling to come up on the core. Link shared state of
328 * the first HT sibling to itself. The siblings on the same core
329 * which come up later will see the shared state pointer and link
330 * themself to the state of this CPU.
332 st->shared_state = st;
336 * Logic is: First HT sibling enables SSBD for both siblings in the core
337 * and last sibling to disable it, disables it for the whole core. This how
338 * MSR_SPEC_CTRL works in "hardware":
340 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
342 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
344 struct ssb_state *st = this_cpu_ptr(&ssb_state);
345 u64 msr = x86_amd_ls_cfg_base;
347 if (!static_cpu_has(X86_FEATURE_ZEN)) {
348 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
349 wrmsrl(MSR_AMD64_LS_CFG, msr);
353 if (tifn & _TIF_SSBD) {
355 * Since this can race with prctl(), block reentry on the
358 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
361 msr |= x86_amd_ls_cfg_ssbd_mask;
363 raw_spin_lock(&st->shared_state->lock);
364 /* First sibling enables SSBD: */
365 if (!st->shared_state->disable_state)
366 wrmsrl(MSR_AMD64_LS_CFG, msr);
367 st->shared_state->disable_state++;
368 raw_spin_unlock(&st->shared_state->lock);
370 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
373 raw_spin_lock(&st->shared_state->lock);
374 st->shared_state->disable_state--;
375 if (!st->shared_state->disable_state)
376 wrmsrl(MSR_AMD64_LS_CFG, msr);
377 raw_spin_unlock(&st->shared_state->lock);
381 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
383 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
385 wrmsrl(MSR_AMD64_LS_CFG, msr);
389 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
392 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
393 * so ssbd_tif_to_spec_ctrl() just works.
395 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
398 static __always_inline void intel_set_ssb_state(unsigned long tifn)
400 u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
402 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
405 static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
407 if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
408 amd_set_ssb_virt_state(tifn);
409 else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
410 amd_set_core_ssb_state(tifn);
412 intel_set_ssb_state(tifn);
415 void speculative_store_bypass_update(unsigned long tif)
418 __speculative_store_bypass_update(tif);
422 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
423 struct tss_struct *tss)
425 struct thread_struct *prev, *next;
426 unsigned long tifp, tifn;
428 prev = &prev_p->thread;
429 next = &next_p->thread;
431 tifn = READ_ONCE(task_thread_info(next_p)->flags);
432 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
433 switch_to_bitmap(tss, prev, next, tifp, tifn);
435 propagate_user_return_notify(prev_p, next_p);
437 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
438 arch_has_block_step()) {
439 unsigned long debugctl, msk;
441 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
442 debugctl &= ~DEBUGCTLMSR_BTF;
443 msk = tifn & _TIF_BLOCKSTEP;
444 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
445 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
448 if ((tifp ^ tifn) & _TIF_NOTSC)
449 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
451 if ((tifp ^ tifn) & _TIF_NOCPUID)
452 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
454 if ((tifp ^ tifn) & _TIF_SSBD)
455 __speculative_store_bypass_update(tifn);
459 * Idle related variables and functions
461 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
462 EXPORT_SYMBOL(boot_option_idle_override);
464 static void (*x86_idle)(void);
467 static inline void play_dead(void)
473 void arch_cpu_idle_enter(void)
475 tsc_verify_tsc_adjust(false);
479 void arch_cpu_idle_dead(void)
485 * Called from the generic idle code.
487 void arch_cpu_idle(void)
493 * We use this if we don't have any better idle routine..
495 void __cpuidle default_idle(void)
497 trace_cpu_idle_rcuidle(1, smp_processor_id());
499 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
501 #ifdef CONFIG_APM_MODULE
502 EXPORT_SYMBOL(default_idle);
506 bool xen_set_default_idle(void)
508 bool ret = !!x86_idle;
510 x86_idle = default_idle;
516 void stop_this_cpu(void *dummy)
522 set_cpu_online(smp_processor_id(), false);
523 disable_local_APIC();
524 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
527 * Use wbinvd on processors that support SME. This provides support
528 * for performing a successful kexec when going from SME inactive
529 * to SME active (or vice-versa). The cache must be cleared so that
530 * if there are entries with the same physical address, both with and
531 * without the encryption bit, they don't race each other when flushed
532 * and potentially end up with the wrong entry being committed to
535 if (boot_cpu_has(X86_FEATURE_SME))
539 * Use native_halt() so that memory contents don't change
540 * (stack usage and variables) after possibly issuing the
541 * native_wbinvd() above.
548 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
549 * states (local apic timer and TSC stop).
551 static void amd_e400_idle(void)
554 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
555 * gets set after static_cpu_has() places have been converted via
558 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
563 tick_broadcast_enter();
568 * The switch back from broadcast mode needs to be called with
569 * interrupts disabled.
572 tick_broadcast_exit();
577 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
578 * We can't rely on cpuidle installing MWAIT, because it will not load
579 * on systems that support only C1 -- so the boot default must be MWAIT.
581 * Some AMD machines are the opposite, they depend on using HALT.
583 * So for default C1, which is used during boot until cpuidle loads,
584 * use MWAIT-C1 on Intel HW that has it, else use HALT.
586 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
588 if (c->x86_vendor != X86_VENDOR_INTEL)
591 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
598 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
599 * with interrupts enabled and no flags, which is backwards compatible with the
600 * original MWAIT implementation.
602 static __cpuidle void mwait_idle(void)
604 if (!current_set_polling_and_test()) {
605 trace_cpu_idle_rcuidle(1, smp_processor_id());
606 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
608 clflush((void *)¤t_thread_info()->flags);
612 __monitor((void *)¤t_thread_info()->flags, 0, 0);
617 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
621 __current_clr_polling();
624 void select_idle_routine(const struct cpuinfo_x86 *c)
627 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
628 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
630 if (x86_idle || boot_option_idle_override == IDLE_POLL)
633 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
634 pr_info("using AMD E400 aware idle routine\n");
635 x86_idle = amd_e400_idle;
636 } else if (prefer_mwait_c1_over_halt(c)) {
637 pr_info("using mwait in idle threads\n");
638 x86_idle = mwait_idle;
640 x86_idle = default_idle;
643 void amd_e400_c1e_apic_setup(void)
645 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
646 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
648 tick_broadcast_force();
653 void __init arch_post_acpi_subsys_init(void)
657 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
661 * AMD E400 detection needs to happen after ACPI has been enabled. If
662 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
663 * MSR_K8_INT_PENDING_MSG.
665 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
666 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
669 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
671 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
672 mark_tsc_unstable("TSC halt in AMD C1E");
673 pr_info("System has AMD C1E enabled\n");
676 static int __init idle_setup(char *str)
681 if (!strcmp(str, "poll")) {
682 pr_info("using polling idle threads\n");
683 boot_option_idle_override = IDLE_POLL;
684 cpu_idle_poll_ctrl(true);
685 } else if (!strcmp(str, "halt")) {
687 * When the boot option of idle=halt is added, halt is
688 * forced to be used for CPU idle. In such case CPU C2/C3
689 * won't be used again.
690 * To continue to load the CPU idle driver, don't touch
691 * the boot_option_idle_override.
693 x86_idle = default_idle;
694 boot_option_idle_override = IDLE_HALT;
695 } else if (!strcmp(str, "nomwait")) {
697 * If the boot option of "idle=nomwait" is added,
698 * it means that mwait will be disabled for CPU C2/C3
699 * states. In such case it won't touch the variable
700 * of boot_option_idle_override.
702 boot_option_idle_override = IDLE_NOMWAIT;
708 early_param("idle", idle_setup);
710 unsigned long arch_align_stack(unsigned long sp)
712 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
713 sp -= get_random_int() % 8192;
717 unsigned long arch_randomize_brk(struct mm_struct *mm)
719 return randomize_page(mm->brk, 0x02000000);
723 * Called from fs/proc with a reference on @p to find the function
724 * which called into schedule(). This needs to be done carefully
725 * because the task might wake up and we might look at a stack
728 unsigned long get_wchan(struct task_struct *p)
730 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
733 if (!p || p == current || p->state == TASK_RUNNING)
736 if (!try_get_task_stack(p))
739 start = (unsigned long)task_stack_page(p);
744 * Layout of the stack page:
746 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
748 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
750 * ----------- bottom = start
752 * The tasks stack pointer points at the location where the
753 * framepointer is stored. The data on the stack is:
754 * ... IP FP ... IP FP
756 * We need to read FP and IP, so we need to adjust the upper
757 * bound by another unsigned long.
759 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
760 top -= 2 * sizeof(unsigned long);
763 sp = READ_ONCE(p->thread.sp);
764 if (sp < bottom || sp > top)
767 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
769 if (fp < bottom || fp > top)
771 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
772 if (!in_sched_functions(ip)) {
776 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
777 } while (count++ < 16 && p->state != TASK_RUNNING);
784 long do_arch_prctl_common(struct task_struct *task, int option,
785 unsigned long cpuid_enabled)
789 return get_cpuid_mode();
791 return set_cpuid_mode(task, cpuid_enabled);