1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/sched/idle.h>
11 #include <linux/sched/debug.h>
12 #include <linux/sched/task.h>
13 #include <linux/sched/task_stack.h>
14 #include <linux/init.h>
15 #include <linux/export.h>
17 #include <linux/tick.h>
18 #include <linux/random.h>
19 #include <linux/user-return-notifier.h>
20 #include <linux/dmi.h>
21 #include <linux/utsname.h>
22 #include <linux/stackprotector.h>
23 #include <linux/tick.h>
24 #include <linux/cpuidle.h>
25 #include <trace/events/power.h>
26 #include <linux/hw_breakpoint.h>
29 #include <asm/syscalls.h>
30 #include <linux/uaccess.h>
31 #include <asm/mwait.h>
32 #include <asm/fpu/internal.h>
33 #include <asm/debugreg.h>
35 #include <asm/tlbflush.h>
38 #include <asm/switch_to.h>
40 #include <asm/prctl.h>
43 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
44 * no more per-task TSS's. The TSS size is kept cacheline-aligned
45 * so they are allowed to end up in the .data..cacheline_aligned
46 * section. Since TSS's are completely CPU-local, we want them
47 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
49 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
52 * .sp0 is only used when entering ring 0 from a lower
53 * privilege level. Since the init task never runs anything
54 * but ring 0 code, there is no need for a valid value here.
57 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
61 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
66 * Note that the .io_bitmap member must be extra-big. This is because
67 * the CPU will access an additional byte beyond the end of the IO
68 * permission bitmap. The extra byte must be all 1 bits, and must
69 * be within the limit.
71 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
74 .SYSENTER_stack_canary = STACK_END_MAGIC,
77 EXPORT_PER_CPU_SYMBOL(cpu_tss);
79 DEFINE_PER_CPU(bool, __tss_limit_invalid);
80 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
83 * this gets called so that we can store lazy state into memory and copy the
84 * current task into the new thread.
86 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88 memcpy(dst, src, arch_task_struct_size);
90 dst->thread.vm86 = NULL;
93 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
97 * Free current thread data structures etc..
99 void exit_thread(struct task_struct *tsk)
101 struct thread_struct *t = &tsk->thread;
102 unsigned long *bp = t->io_bitmap_ptr;
103 struct fpu *fpu = &t->fpu;
106 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
108 t->io_bitmap_ptr = NULL;
109 clear_thread_flag(TIF_IO_BITMAP);
111 * Careful, clear this in the TSS too:
113 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
114 t->io_bitmap_max = 0;
124 void flush_thread(void)
126 struct task_struct *tsk = current;
128 flush_ptrace_hw_breakpoint(tsk);
129 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
131 fpu__clear(&tsk->thread.fpu);
134 void disable_TSC(void)
137 if (!test_and_set_thread_flag(TIF_NOTSC))
139 * Must flip the CPU state synchronously with
140 * TIF_NOTSC in the current running context.
142 cr4_set_bits(X86_CR4_TSD);
146 static void enable_TSC(void)
149 if (test_and_clear_thread_flag(TIF_NOTSC))
151 * Must flip the CPU state synchronously with
152 * TIF_NOTSC in the current running context.
154 cr4_clear_bits(X86_CR4_TSD);
158 int get_tsc_mode(unsigned long adr)
162 if (test_thread_flag(TIF_NOTSC))
163 val = PR_TSC_SIGSEGV;
167 return put_user(val, (unsigned int __user *)adr);
170 int set_tsc_mode(unsigned int val)
172 if (val == PR_TSC_SIGSEGV)
174 else if (val == PR_TSC_ENABLE)
182 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
184 static void set_cpuid_faulting(bool on)
188 msrval = this_cpu_read(msr_misc_features_shadow);
189 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
190 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
191 this_cpu_write(msr_misc_features_shadow, msrval);
192 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
195 static void disable_cpuid(void)
198 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
200 * Must flip the CPU state synchronously with
201 * TIF_NOCPUID in the current running context.
203 set_cpuid_faulting(true);
208 static void enable_cpuid(void)
211 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
213 * Must flip the CPU state synchronously with
214 * TIF_NOCPUID in the current running context.
216 set_cpuid_faulting(false);
221 static int get_cpuid_mode(void)
223 return !test_thread_flag(TIF_NOCPUID);
226 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
228 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
240 * Called immediately after a successful exec.
242 void arch_setup_new_exec(void)
244 /* If cpuid was previously disabled for this task, re-enable it. */
245 if (test_thread_flag(TIF_NOCPUID))
249 static inline void switch_to_bitmap(struct tss_struct *tss,
250 struct thread_struct *prev,
251 struct thread_struct *next,
252 unsigned long tifp, unsigned long tifn)
254 if (tifn & _TIF_IO_BITMAP) {
256 * Copy the relevant range of the IO bitmap.
257 * Normally this is 128 bytes or less:
259 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
260 max(prev->io_bitmap_max, next->io_bitmap_max));
262 * Make sure that the TSS limit is correct for the CPU
263 * to notice the IO bitmap.
266 } else if (tifp & _TIF_IO_BITMAP) {
268 * Clear any possible leftover bits:
270 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
274 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
275 struct tss_struct *tss)
277 struct thread_struct *prev, *next;
278 unsigned long tifp, tifn;
280 prev = &prev_p->thread;
281 next = &next_p->thread;
283 tifn = READ_ONCE(task_thread_info(next_p)->flags);
284 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
285 switch_to_bitmap(tss, prev, next, tifp, tifn);
287 propagate_user_return_notify(prev_p, next_p);
289 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
290 arch_has_block_step()) {
291 unsigned long debugctl, msk;
293 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
294 debugctl &= ~DEBUGCTLMSR_BTF;
295 msk = tifn & _TIF_BLOCKSTEP;
296 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
297 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
300 if ((tifp ^ tifn) & _TIF_NOTSC)
301 cr4_toggle_bits(X86_CR4_TSD);
303 if ((tifp ^ tifn) & _TIF_NOCPUID)
304 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
308 * Idle related variables and functions
310 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
311 EXPORT_SYMBOL(boot_option_idle_override);
313 static void (*x86_idle)(void);
316 static inline void play_dead(void)
322 void arch_cpu_idle_enter(void)
324 tsc_verify_tsc_adjust(false);
328 void arch_cpu_idle_dead(void)
334 * Called from the generic idle code.
336 void arch_cpu_idle(void)
342 * We use this if we don't have any better idle routine..
344 void __cpuidle default_idle(void)
346 trace_cpu_idle_rcuidle(1, smp_processor_id());
348 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
350 #ifdef CONFIG_APM_MODULE
351 EXPORT_SYMBOL(default_idle);
355 bool xen_set_default_idle(void)
357 bool ret = !!x86_idle;
359 x86_idle = default_idle;
365 void stop_this_cpu(void *dummy)
371 set_cpu_online(smp_processor_id(), false);
372 disable_local_APIC();
373 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
377 * Use wbinvd followed by hlt to stop the processor. This
378 * provides support for kexec on a processor that supports
379 * SME. With kexec, going from SME inactive to SME active
380 * requires clearing cache entries so that addresses without
381 * the encryption bit set don't corrupt the same physical
382 * address that has the encryption bit set when caches are
383 * flushed. To achieve this a wbinvd is performed followed by
384 * a hlt. Even if the processor is not in the kexec/SME
385 * scenario this only adds a wbinvd to a halting processor.
387 asm volatile("wbinvd; hlt" : : : "memory");
392 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
393 * states (local apic timer and TSC stop).
395 static void amd_e400_idle(void)
398 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
399 * gets set after static_cpu_has() places have been converted via
402 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
407 tick_broadcast_enter();
412 * The switch back from broadcast mode needs to be called with
413 * interrupts disabled.
416 tick_broadcast_exit();
421 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
422 * We can't rely on cpuidle installing MWAIT, because it will not load
423 * on systems that support only C1 -- so the boot default must be MWAIT.
425 * Some AMD machines are the opposite, they depend on using HALT.
427 * So for default C1, which is used during boot until cpuidle loads,
428 * use MWAIT-C1 on Intel HW that has it, else use HALT.
430 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
432 if (c->x86_vendor != X86_VENDOR_INTEL)
435 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
442 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
443 * with interrupts enabled and no flags, which is backwards compatible with the
444 * original MWAIT implementation.
446 static __cpuidle void mwait_idle(void)
448 if (!current_set_polling_and_test()) {
449 trace_cpu_idle_rcuidle(1, smp_processor_id());
450 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
452 clflush((void *)¤t_thread_info()->flags);
456 __monitor((void *)¤t_thread_info()->flags, 0, 0);
461 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
465 __current_clr_polling();
468 void select_idle_routine(const struct cpuinfo_x86 *c)
471 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
472 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
474 if (x86_idle || boot_option_idle_override == IDLE_POLL)
477 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
478 pr_info("using AMD E400 aware idle routine\n");
479 x86_idle = amd_e400_idle;
480 } else if (prefer_mwait_c1_over_halt(c)) {
481 pr_info("using mwait in idle threads\n");
482 x86_idle = mwait_idle;
484 x86_idle = default_idle;
487 void amd_e400_c1e_apic_setup(void)
489 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
490 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
492 tick_broadcast_force();
497 void __init arch_post_acpi_subsys_init(void)
501 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
505 * AMD E400 detection needs to happen after ACPI has been enabled. If
506 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
507 * MSR_K8_INT_PENDING_MSG.
509 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
510 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
513 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
515 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
516 mark_tsc_unstable("TSC halt in AMD C1E");
517 pr_info("System has AMD C1E enabled\n");
520 static int __init idle_setup(char *str)
525 if (!strcmp(str, "poll")) {
526 pr_info("using polling idle threads\n");
527 boot_option_idle_override = IDLE_POLL;
528 cpu_idle_poll_ctrl(true);
529 } else if (!strcmp(str, "halt")) {
531 * When the boot option of idle=halt is added, halt is
532 * forced to be used for CPU idle. In such case CPU C2/C3
533 * won't be used again.
534 * To continue to load the CPU idle driver, don't touch
535 * the boot_option_idle_override.
537 x86_idle = default_idle;
538 boot_option_idle_override = IDLE_HALT;
539 } else if (!strcmp(str, "nomwait")) {
541 * If the boot option of "idle=nomwait" is added,
542 * it means that mwait will be disabled for CPU C2/C3
543 * states. In such case it won't touch the variable
544 * of boot_option_idle_override.
546 boot_option_idle_override = IDLE_NOMWAIT;
552 early_param("idle", idle_setup);
554 unsigned long arch_align_stack(unsigned long sp)
556 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
557 sp -= get_random_int() % 8192;
561 unsigned long arch_randomize_brk(struct mm_struct *mm)
563 return randomize_page(mm->brk, 0x02000000);
567 * Called from fs/proc with a reference on @p to find the function
568 * which called into schedule(). This needs to be done carefully
569 * because the task might wake up and we might look at a stack
572 unsigned long get_wchan(struct task_struct *p)
574 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
577 if (!p || p == current || p->state == TASK_RUNNING)
580 if (!try_get_task_stack(p))
583 start = (unsigned long)task_stack_page(p);
588 * Layout of the stack page:
590 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
592 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
594 * ----------- bottom = start
596 * The tasks stack pointer points at the location where the
597 * framepointer is stored. The data on the stack is:
598 * ... IP FP ... IP FP
600 * We need to read FP and IP, so we need to adjust the upper
601 * bound by another unsigned long.
603 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
604 top -= 2 * sizeof(unsigned long);
607 sp = READ_ONCE(p->thread.sp);
608 if (sp < bottom || sp > top)
611 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
613 if (fp < bottom || fp > top)
615 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
616 if (!in_sched_functions(ip)) {
620 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
621 } while (count++ < 16 && p->state != TASK_RUNNING);
628 long do_arch_prctl_common(struct task_struct *task, int option,
629 unsigned long cpuid_enabled)
633 return get_cpuid_mode();
635 return set_cpuid_mode(task, cpuid_enabled);