2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
23 #include <linux/kernel.h>
25 #include <linux/elfcore.h>
26 #include <linux/smp.h>
27 #include <linux/slab.h>
28 #include <linux/user.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <linux/ptrace.h>
33 #include <linux/notifier.h>
34 #include <linux/kprobes.h>
35 #include <linux/kdebug.h>
36 #include <linux/prctl.h>
37 #include <linux/uaccess.h>
39 #include <linux/ftrace.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
43 #include <asm/processor.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/mmu_context.h>
46 #include <asm/prctl.h>
48 #include <asm/proto.h>
50 #include <asm/syscalls.h>
51 #include <asm/debugreg.h>
52 #include <asm/switch_to.h>
53 #include <asm/xen/hypervisor.h>
55 #include <asm/intel_rdt.h>
56 #include <asm/unistd.h>
57 #ifdef CONFIG_IA32_EMULATION
58 /* Not included via unistd.h */
59 #include <asm/unistd_32_ia32.h>
62 __visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
64 /* Prints also some state that isn't saved in the pt_regs */
65 void __show_regs(struct pt_regs *regs, int all)
67 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
68 unsigned long d0, d1, d2, d3, d6, d7;
69 unsigned int fsindex, gsindex;
70 unsigned int ds, cs, es;
72 printk(KERN_DEFAULT "RIP: %04lx:%pS\n", regs->cs, (void *)regs->ip);
73 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx", regs->ss,
74 regs->sp, regs->flags);
75 if (regs->orig_ax != -1)
76 pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax);
80 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
81 regs->ax, regs->bx, regs->cx);
82 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
83 regs->dx, regs->si, regs->di);
84 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
85 regs->bp, regs->r8, regs->r9);
86 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
87 regs->r10, regs->r11, regs->r12);
88 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
89 regs->r13, regs->r14, regs->r15);
91 asm("movl %%ds,%0" : "=r" (ds));
92 asm("movl %%cs,%0" : "=r" (cs));
93 asm("movl %%es,%0" : "=r" (es));
94 asm("movl %%fs,%0" : "=r" (fsindex));
95 asm("movl %%gs,%0" : "=r" (gsindex));
97 rdmsrl(MSR_FS_BASE, fs);
98 rdmsrl(MSR_GS_BASE, gs);
99 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
109 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
110 fs, fsindex, gs, gsindex, shadowgs);
111 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
113 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
123 /* Only print out debug registers if they are in their non-default state. */
124 if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
125 (d6 == DR6_RESERVED) && (d7 == 0x400))) {
126 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n",
128 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n",
132 if (boot_cpu_has(X86_FEATURE_OSPKE))
133 printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru());
136 void release_thread(struct task_struct *dead_task)
139 #ifdef CONFIG_MODIFY_LDT_SYSCALL
140 if (dead_task->mm->context.ldt) {
141 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
143 dead_task->mm->context.ldt->entries,
144 dead_task->mm->context.ldt->nr_entries);
151 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
152 unsigned long arg, struct task_struct *p, unsigned long tls)
155 struct pt_regs *childregs;
156 struct fork_frame *fork_frame;
157 struct inactive_task_frame *frame;
158 struct task_struct *me = current;
160 p->thread.sp0 = (unsigned long)task_stack_page(p) + THREAD_SIZE;
161 childregs = task_pt_regs(p);
162 fork_frame = container_of(childregs, struct fork_frame, regs);
163 frame = &fork_frame->frame;
165 frame->ret_addr = (unsigned long) ret_from_fork;
166 p->thread.sp = (unsigned long) fork_frame;
167 p->thread.io_bitmap_ptr = NULL;
169 savesegment(gs, p->thread.gsindex);
170 p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
171 savesegment(fs, p->thread.fsindex);
172 p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
173 savesegment(es, p->thread.es);
174 savesegment(ds, p->thread.ds);
175 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
177 if (unlikely(p->flags & PF_KTHREAD)) {
179 memset(childregs, 0, sizeof(struct pt_regs));
180 frame->bx = sp; /* function */
185 *childregs = *current_pt_regs();
192 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
193 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
194 IO_BITMAP_BYTES, GFP_KERNEL);
195 if (!p->thread.io_bitmap_ptr) {
196 p->thread.io_bitmap_max = 0;
199 set_tsk_thread_flag(p, TIF_IO_BITMAP);
203 * Set a new TLS for the child thread?
205 if (clone_flags & CLONE_SETTLS) {
206 #ifdef CONFIG_IA32_EMULATION
207 if (in_ia32_syscall())
208 err = do_set_thread_area(p, -1,
209 (struct user_desc __user *)tls, 0);
212 err = do_arch_prctl_64(p, ARCH_SET_FS, tls);
218 if (err && p->thread.io_bitmap_ptr) {
219 kfree(p->thread.io_bitmap_ptr);
220 p->thread.io_bitmap_max = 0;
227 start_thread_common(struct pt_regs *regs, unsigned long new_ip,
228 unsigned long new_sp,
229 unsigned int _cs, unsigned int _ss, unsigned int _ds)
232 loadsegment(es, _ds);
233 loadsegment(ds, _ds);
239 regs->flags = X86_EFLAGS_IF;
244 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
246 start_thread_common(regs, new_ip, new_sp,
247 __USER_CS, __USER_DS, 0);
251 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
253 start_thread_common(regs, new_ip, new_sp,
254 test_thread_flag(TIF_X32)
255 ? __USER_CS : __USER32_CS,
256 __USER_DS, __USER_DS);
261 * switch_to(x,y) should switch tasks from x to y.
263 * This could still be optimized:
264 * - fold all the options into a flag word and test it with a single test.
265 * - could test fs/gs bitsliced
267 * Kprobes not supported here. Set the probe on schedule instead.
268 * Function graph tracer not supported too.
270 __visible __notrace_funcgraph struct task_struct *
271 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
273 struct thread_struct *prev = &prev_p->thread;
274 struct thread_struct *next = &next_p->thread;
275 struct fpu *prev_fpu = &prev->fpu;
276 struct fpu *next_fpu = &next->fpu;
277 int cpu = smp_processor_id();
278 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
279 unsigned prev_fsindex, prev_gsindex;
281 WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
282 this_cpu_read(irq_count) != -1);
284 switch_fpu_prepare(prev_fpu, cpu);
286 /* We must save %fs and %gs before load_TLS() because
287 * %fs and %gs may be cleared by load_TLS().
289 * (e.g. xen_load_tls())
291 savesegment(fs, prev_fsindex);
292 savesegment(gs, prev_gsindex);
295 * Load TLS before restoring any segments so that segment loads
296 * reference the correct GDT entries.
301 * Leave lazy mode, flushing any hypercalls made here. This
302 * must be done after loading TLS entries in the GDT but before
303 * loading segments that might reference them, and and it must
304 * be done before fpu__restore(), so the TS bit is up to
307 arch_end_context_switch(next_p);
311 * Reading them only returns the selectors, but writing them (if
312 * nonzero) loads the full descriptor from the GDT or LDT. The
313 * LDT for next is loaded in switch_mm, and the GDT is loaded
316 * We therefore need to write new values to the segment
317 * registers on every context switch unless both the new and old
320 * Note that we don't need to do anything for CS and SS, as
321 * those are saved and restored as part of pt_regs.
323 savesegment(es, prev->es);
324 if (unlikely(next->es | prev->es))
325 loadsegment(es, next->es);
327 savesegment(ds, prev->ds);
328 if (unlikely(next->ds | prev->ds))
329 loadsegment(ds, next->ds);
334 * These are even more complicated than DS and ES: they have
335 * 64-bit bases are that controlled by arch_prctl. The bases
336 * don't necessarily match the selectors, as user code can do
337 * any number of things to cause them to be inconsistent.
339 * We don't promise to preserve the bases if the selectors are
340 * nonzero. We also don't promise to preserve the base if the
341 * selector is zero and the base doesn't match whatever was
342 * most recently passed to ARCH_SET_FS/GS. (If/when the
343 * FSGSBASE instructions are enabled, we'll need to offer
344 * stronger guarantees.)
347 * (fsbase != 0 && fsindex != 0) || (gsbase != 0 && gsindex != 0) is
351 /* Loading a nonzero value into FS sets the index and base. */
352 loadsegment(fs, next->fsindex);
355 /* Next index is zero but next base is nonzero. */
358 wrmsrl(MSR_FS_BASE, next->fsbase);
360 /* Next base and index are both zero. */
361 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
363 * We don't know the previous base and can't
364 * find out without RDMSR. Forcibly clear it.
366 loadsegment(fs, __USER_DS);
370 * If the previous index is zero and ARCH_SET_FS
371 * didn't change the base, then the base is
372 * also zero and we don't need to do anything.
374 if (prev->fsbase || prev_fsindex)
380 * Save the old state and preserve the invariant.
381 * NB: if prev_fsindex == 0, then we can't reliably learn the base
382 * without RDMSR because Intel user code can zero it without telling
383 * us and AMD user code can program any 32-bit value without telling
388 prev->fsindex = prev_fsindex;
391 /* Loading a nonzero value into GS sets the index and base. */
392 load_gs_index(next->gsindex);
395 /* Next index is zero but next base is nonzero. */
398 wrmsrl(MSR_KERNEL_GS_BASE, next->gsbase);
400 /* Next base and index are both zero. */
401 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
403 * We don't know the previous base and can't
404 * find out without RDMSR. Forcibly clear it.
406 * This contains a pointless SWAPGS pair.
407 * Fixing it would involve an explicit check
408 * for Xen or a new pvop.
410 load_gs_index(__USER_DS);
414 * If the previous index is zero and ARCH_SET_GS
415 * didn't change the base, then the base is
416 * also zero and we don't need to do anything.
418 if (prev->gsbase || prev_gsindex)
424 * Save the old state and preserve the invariant.
425 * NB: if prev_gsindex == 0, then we can't reliably learn the base
426 * without RDMSR because Intel user code can zero it without telling
427 * us and AMD user code can program any 32-bit value without telling
432 prev->gsindex = prev_gsindex;
434 switch_fpu_finish(next_fpu, cpu);
437 * Switch the PDA and FPU contexts.
439 this_cpu_write(current_task, next_p);
441 /* Reload esp0 and ss1. This changes current_thread_info(). */
445 * Now maybe reload the debug registers and handle I/O bitmaps
447 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
448 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
449 __switch_to_xtra(prev_p, next_p, tss);
453 * On Xen PV, IOPL bits in pt_regs->flags have no effect, and
454 * current_pt_regs()->flags may not match the current task's
455 * intended IOPL. We need to switch it manually.
457 if (unlikely(static_cpu_has(X86_FEATURE_XENPV) &&
458 prev->iopl != next->iopl))
459 xen_set_iopl_mask(next->iopl);
462 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
464 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
465 * does not update the cached descriptor. As a result, if we
466 * do SYSRET while SS is NULL, we'll end up in user mode with
467 * SS apparently equal to __USER_DS but actually unusable.
469 * The straightforward workaround would be to fix it up just
470 * before SYSRET, but that would slow down the system call
471 * fast paths. Instead, we ensure that SS is never NULL in
472 * system call context. We do this by replacing NULL SS
473 * selectors at every context switch. SYSCALL sets up a valid
474 * SS, so the only way to get NULL is to re-enter the kernel
475 * from CPL 3 through an interrupt. Since that can't happen
476 * in the same task as a running syscall, we are guaranteed to
477 * context switch between every interrupt vector entry and a
480 * We read SS first because SS reads are much faster than
481 * writes. Out of caution, we force SS to __KERNEL_DS even if
482 * it previously had a different non-NULL value.
484 unsigned short ss_sel;
485 savesegment(ss, ss_sel);
486 if (ss_sel != __KERNEL_DS)
487 loadsegment(ss, __KERNEL_DS);
490 /* Load the Intel cache allocation PQR MSR. */
491 intel_rdt_sched_in();
496 void set_personality_64bit(void)
498 /* inherit personality from parent */
500 /* Make sure to be in 64bit mode */
501 clear_thread_flag(TIF_IA32);
502 clear_thread_flag(TIF_ADDR32);
503 clear_thread_flag(TIF_X32);
504 /* Pretend that this comes from a 64bit execve */
505 task_pt_regs(current)->orig_ax = __NR_execve;
507 /* Ensure the corresponding mm is not marked. */
509 current->mm->context.ia32_compat = 0;
511 /* TBD: overwrites user setup. Should have two bits.
512 But 64bit processes have always behaved this way,
513 so it's not too bad. The main problem is just that
514 32bit childs are affected again. */
515 current->personality &= ~READ_IMPLIES_EXEC;
518 static void __set_personality_x32(void)
520 #ifdef CONFIG_X86_X32
521 clear_thread_flag(TIF_IA32);
522 set_thread_flag(TIF_X32);
524 current->mm->context.ia32_compat = TIF_X32;
525 current->personality &= ~READ_IMPLIES_EXEC;
527 * in_compat_syscall() uses the presence of the x32 syscall bit
528 * flag to determine compat status. The x86 mmap() code relies on
529 * the syscall bitness so set x32 syscall bit right here to make
530 * in_compat_syscall() work during exec().
532 * Pretend to come from a x32 execve.
534 task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT;
535 current->thread.status &= ~TS_COMPAT;
539 static void __set_personality_ia32(void)
541 #ifdef CONFIG_IA32_EMULATION
542 set_thread_flag(TIF_IA32);
543 clear_thread_flag(TIF_X32);
545 current->mm->context.ia32_compat = TIF_IA32;
546 current->personality |= force_personality32;
547 /* Prepare the first "return" to user space */
548 task_pt_regs(current)->orig_ax = __NR_ia32_execve;
549 current->thread.status |= TS_COMPAT;
553 void set_personality_ia32(bool x32)
555 /* Make sure to be in 32bit mode */
556 set_thread_flag(TIF_ADDR32);
559 __set_personality_x32();
561 __set_personality_ia32();
563 EXPORT_SYMBOL_GPL(set_personality_ia32);
565 #ifdef CONFIG_CHECKPOINT_RESTORE
566 static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr)
570 ret = map_vdso_once(image, addr);
574 return (long)image->size;
578 long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
581 int doit = task == current;
586 if (arg2 >= TASK_SIZE_MAX)
589 task->thread.gsindex = 0;
590 task->thread.gsbase = arg2;
593 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, arg2);
598 /* Not strictly needed for fs, but do it for symmetry
600 if (arg2 >= TASK_SIZE_MAX)
603 task->thread.fsindex = 0;
604 task->thread.fsbase = arg2;
606 /* set the selector to 0 to not confuse __switch_to */
608 ret = wrmsrl_safe(MSR_FS_BASE, arg2);
616 rdmsrl(MSR_FS_BASE, base);
618 base = task->thread.fsbase;
619 ret = put_user(base, (unsigned long __user *)arg2);
626 rdmsrl(MSR_KERNEL_GS_BASE, base);
628 base = task->thread.gsbase;
629 ret = put_user(base, (unsigned long __user *)arg2);
633 #ifdef CONFIG_CHECKPOINT_RESTORE
634 # ifdef CONFIG_X86_X32_ABI
635 case ARCH_MAP_VDSO_X32:
636 return prctl_map_vdso(&vdso_image_x32, arg2);
638 # if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
639 case ARCH_MAP_VDSO_32:
640 return prctl_map_vdso(&vdso_image_32, arg2);
642 case ARCH_MAP_VDSO_64:
643 return prctl_map_vdso(&vdso_image_64, arg2);
654 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
658 ret = do_arch_prctl_64(current, option, arg2);
660 ret = do_arch_prctl_common(current, option, arg2);
665 #ifdef CONFIG_IA32_EMULATION
666 COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
668 return do_arch_prctl_common(current, option, arg2);
672 unsigned long KSTK_ESP(struct task_struct *task)
674 return task_pt_regs(task)->sp;