2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/qspinlock.h>
82 /* Number of siblings per CPU package */
83 int smp_num_siblings = 1;
84 EXPORT_SYMBOL(smp_num_siblings);
86 /* Last level cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 /* Logical package management. We might want to allocate that dynamically */
104 static int *physical_to_logical_pkg __read_mostly;
105 static unsigned long *physical_package_map __read_mostly;;
106 static unsigned int max_physical_pkg_id __read_mostly;
107 unsigned int __max_logical_packages __read_mostly;
108 EXPORT_SYMBOL(__max_logical_packages);
109 static unsigned int logical_packages __read_mostly;
111 /* Maximum number of SMT threads on any online core */
112 int __max_smt_threads __read_mostly;
114 /* Flag to indicate if a complete sched domain rebuild is required */
115 bool x86_topology_update;
117 int arch_update_cpu_topology(void)
119 int retval = x86_topology_update;
121 x86_topology_update = false;
125 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
129 spin_lock_irqsave(&rtc_lock, flags);
130 CMOS_WRITE(0xa, 0xf);
131 spin_unlock_irqrestore(&rtc_lock, flags);
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
142 static inline void smpboot_restore_warm_reset_vector(void)
147 * Install writable page 0 entry to set BIOS data area.
152 * Paranoid: Set warm reset code and vector here back
155 spin_lock_irqsave(&rtc_lock, flags);
157 spin_unlock_irqrestore(&rtc_lock, flags);
159 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
163 * Report back to the Boot Processor during boot time or to the caller processor
166 static void smp_callin(void)
171 * If waken up by an INIT in an 82489DX configuration
172 * cpu_callout_mask guarantees we don't get here before
173 * an INIT_deassert IPI reaches our local APIC, so it is
174 * now safe to touch our local APIC.
176 cpuid = smp_processor_id();
179 * (This works even if the APIC is not enabled.)
181 phys_id = read_apic_id();
184 * the boot CPU has finished the init stage and is spinning
185 * on callin_map until we finish. We are free to set up this
186 * CPU, first the APIC. (this is probably redundant on most
192 * Save our processor parameters. Note: this information
193 * is needed for clock calibration.
195 smp_store_cpu_info(cpuid);
198 * The topology information must be up to date before
199 * calibrate_delay() and notify_cpu_starting().
201 set_cpu_sibling_map(raw_smp_processor_id());
205 * Update loops_per_jiffy in cpu_data. Previous call to
206 * smp_store_cpu_info() stored a value that is close but not as
207 * accurate as the value just calculated.
210 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
211 pr_debug("Stack at about %p\n", &cpuid);
215 notify_cpu_starting(cpuid);
218 * Allow the master to continue.
220 cpumask_set_cpu(cpuid, cpu_callin_mask);
223 static int cpu0_logical_apicid;
224 static int enable_start_cpu0;
226 * Activate a secondary processor.
228 static void notrace start_secondary(void *unused)
231 * Don't put *anything* except direct CPU state initialization
232 * before cpu_init(), SMP booting is too fragile that we want to
233 * limit the things done here to the most necessary things.
235 if (boot_cpu_has(X86_FEATURE_PCID))
236 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
239 /* switch away from the initial page table */
240 load_cr3(swapper_pg_dir);
245 x86_cpuinit.early_percpu_clock_init();
249 enable_start_cpu0 = 0;
251 /* otherwise gcc will move up smp_processor_id before the cpu_init */
254 * Check TSC synchronization with the boot CPU:
256 check_tsc_sync_target();
259 * Lock vector_lock, set CPU online and bring the vector
260 * allocator online. Online must be set with vector_lock held
261 * to prevent a concurrent irq setup/teardown from seeing a
262 * half valid vector space.
265 set_cpu_online(smp_processor_id(), true);
267 unlock_vector_lock();
268 cpu_set_state_online(smp_processor_id());
269 x86_platform.nmi_init();
271 /* enable local interrupts */
274 /* to prevent fake stack check failure in clock setup */
275 boot_init_stack_canary();
277 x86_cpuinit.setup_percpu_clockev();
280 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
284 * topology_update_package_map - Update the physical to logical package map
285 * @pkg: The physical package id as retrieved via CPUID
286 * @cpu: The cpu for which this is updated
288 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
292 /* Called from early boot ? */
293 if (!physical_package_map)
296 if (pkg >= max_physical_pkg_id)
299 /* Set the logical package id */
300 if (test_and_set_bit(pkg, physical_package_map))
303 if (logical_packages >= __max_logical_packages) {
304 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
305 logical_packages, cpu, __max_logical_packages);
309 new = logical_packages++;
311 pr_info("CPU %u Converting physical %u to logical package %u\n",
314 physical_to_logical_pkg[pkg] = new;
317 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
322 * topology_phys_to_logical_pkg - Map a physical package id to a logical
324 * Returns logical package id or -1 if not found
326 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
328 if (phys_pkg >= max_physical_pkg_id)
330 return physical_to_logical_pkg[phys_pkg];
332 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
334 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
340 * Today neither Intel nor AMD support heterogenous systems. That
341 * might change in the future....
343 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
344 * computation, this won't actually work since some Intel BIOSes
345 * report inconsistent HT data when they disable HT.
347 * In particular, they reduce the APIC-IDs to only include the cores,
348 * but leave the CPUID topology to say there are (2) siblings.
349 * This means we don't know how many threads there will be until
350 * after the APIC enumeration.
352 * By not including this we'll sometimes over-estimate the number of
353 * logical packages by the amount of !present siblings, but this is
354 * still better than MAX_LOCAL_APIC.
356 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
357 * on the command line leading to a similar issue as the HT disable
358 * problem because the hyperthreads are usually enumerated after the
361 ncpus = boot_cpu_data.x86_max_cores;
363 pr_warn("x86_max_cores == zero !?!?");
367 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
368 logical_packages = 0;
371 * Possibly larger than what we need as the number of apic ids per
372 * package can be smaller than the actual used apic ids.
374 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
375 size = max_physical_pkg_id * sizeof(unsigned int);
376 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
377 memset(physical_to_logical_pkg, 0xff, size);
378 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
379 physical_package_map = kzalloc(size, GFP_KERNEL);
381 pr_info("Max logical packages: %u\n", __max_logical_packages);
383 topology_update_package_map(c->phys_proc_id, cpu);
386 void __init smp_store_boot_cpu_info(void)
388 int id = 0; /* CPU 0 */
389 struct cpuinfo_x86 *c = &cpu_data(id);
393 smp_init_package_map(c, id);
397 * The bootstrap kernel entry code has set these up. Save them for
400 void smp_store_cpu_info(int id)
402 struct cpuinfo_x86 *c = &cpu_data(id);
407 * During boot time, CPU0 has this setup already. Save the info when
408 * bringing up AP or offlined CPU0.
410 identify_secondary_cpu(c);
414 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
418 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
422 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
424 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
426 return !WARN_ONCE(!topology_same_node(c, o),
427 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
428 "[node: %d != %d]. Ignoring dependency.\n",
429 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
432 #define link_mask(mfunc, c1, c2) \
434 cpumask_set_cpu((c1), mfunc(c2)); \
435 cpumask_set_cpu((c2), mfunc(c1)); \
438 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
440 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
441 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
443 if (c->phys_proc_id == o->phys_proc_id &&
444 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
445 if (c->cpu_core_id == o->cpu_core_id)
446 return topology_sane(c, o, "smt");
448 if ((c->cu_id != 0xff) &&
449 (o->cu_id != 0xff) &&
450 (c->cu_id == o->cu_id))
451 return topology_sane(c, o, "smt");
454 } else if (c->phys_proc_id == o->phys_proc_id &&
455 c->cpu_core_id == o->cpu_core_id) {
456 return topology_sane(c, o, "smt");
462 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
464 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
466 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
467 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
468 return topology_sane(c, o, "llc");
474 * Unlike the other levels, we do not enforce keeping a
475 * multicore group inside a NUMA node. If this happens, we will
476 * discard the MC level of the topology later.
478 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
480 if (c->phys_proc_id == o->phys_proc_id)
485 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
486 static inline int x86_sched_itmt_flags(void)
488 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
491 #ifdef CONFIG_SCHED_MC
492 static int x86_core_flags(void)
494 return cpu_core_flags() | x86_sched_itmt_flags();
497 #ifdef CONFIG_SCHED_SMT
498 static int x86_smt_flags(void)
500 return cpu_smt_flags() | x86_sched_itmt_flags();
505 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
506 #ifdef CONFIG_SCHED_SMT
507 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
509 #ifdef CONFIG_SCHED_MC
510 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
515 static struct sched_domain_topology_level x86_topology[] = {
516 #ifdef CONFIG_SCHED_SMT
517 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
519 #ifdef CONFIG_SCHED_MC
520 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
522 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
527 * Set if a package/die has multiple NUMA nodes inside.
528 * AMD Magny-Cours and Intel Cluster-on-Die have this.
530 static bool x86_has_numa_in_package;
532 void set_cpu_sibling_map(int cpu)
534 bool has_smt = smp_num_siblings > 1;
535 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
536 struct cpuinfo_x86 *c = &cpu_data(cpu);
537 struct cpuinfo_x86 *o;
540 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
543 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
544 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
545 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
550 for_each_cpu(i, cpu_sibling_setup_mask) {
553 if ((i == cpu) || (has_smt && match_smt(c, o)))
554 link_mask(topology_sibling_cpumask, cpu, i);
556 if ((i == cpu) || (has_mp && match_llc(c, o)))
557 link_mask(cpu_llc_shared_mask, cpu, i);
562 * This needs a separate iteration over the cpus because we rely on all
563 * topology_sibling_cpumask links to be set-up.
565 for_each_cpu(i, cpu_sibling_setup_mask) {
568 if ((i == cpu) || (has_mp && match_die(c, o))) {
569 link_mask(topology_core_cpumask, cpu, i);
572 * Does this new cpu bringup a new core?
575 topology_sibling_cpumask(cpu)) == 1) {
577 * for each core in package, increment
578 * the booted_cores for this new cpu
581 topology_sibling_cpumask(i)) == i)
584 * increment the core count for all
585 * the other cpus in this package
588 cpu_data(i).booted_cores++;
589 } else if (i != cpu && !c->booted_cores)
590 c->booted_cores = cpu_data(i).booted_cores;
592 if (match_die(c, o) && !topology_same_node(c, o))
593 x86_has_numa_in_package = true;
596 threads = cpumask_weight(topology_sibling_cpumask(cpu));
597 if (threads > __max_smt_threads)
598 __max_smt_threads = threads;
601 /* maps the cpu to the sched domain representing multi-core */
602 const struct cpumask *cpu_coregroup_mask(int cpu)
604 return cpu_llc_shared_mask(cpu);
607 static void impress_friends(void)
610 unsigned long bogosum = 0;
612 * Allow the user to impress friends.
614 pr_debug("Before bogomips\n");
615 for_each_possible_cpu(cpu)
616 if (cpumask_test_cpu(cpu, cpu_callout_mask))
617 bogosum += cpu_data(cpu).loops_per_jiffy;
618 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
621 (bogosum/(5000/HZ))%100);
623 pr_debug("Before bogocount - setting activated=1\n");
626 void __inquire_remote_apic(int apicid)
628 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
629 const char * const names[] = { "ID", "VERSION", "SPIV" };
633 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
635 for (i = 0; i < ARRAY_SIZE(regs); i++) {
636 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
641 status = safe_apic_wait_icr_idle();
643 pr_cont("a previous APIC delivery may have failed\n");
645 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
650 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
651 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
654 case APIC_ICR_RR_VALID:
655 status = apic_read(APIC_RRR);
656 pr_cont("%08x\n", status);
665 * The Multiprocessor Specification 1.4 (1997) example code suggests
666 * that there should be a 10ms delay between the BSP asserting INIT
667 * and de-asserting INIT, when starting a remote processor.
668 * But that slows boot and resume on modern processors, which include
669 * many cores and don't require that delay.
671 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
672 * Modern processor families are quirked to remove the delay entirely.
674 #define UDELAY_10MS_DEFAULT 10000
676 static unsigned int init_udelay = UINT_MAX;
678 static int __init cpu_init_udelay(char *str)
680 get_option(&str, &init_udelay);
684 early_param("cpu_init_udelay", cpu_init_udelay);
686 static void __init smp_quirk_init_udelay(void)
688 /* if cmdline changed it from default, leave it alone */
689 if (init_udelay != UINT_MAX)
692 /* if modern processor, use no delay */
693 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
694 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
698 /* else, use legacy delay */
699 init_udelay = UDELAY_10MS_DEFAULT;
703 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
704 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
705 * won't ... remember to clear down the APIC, etc later.
708 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
710 unsigned long send_status, accept_status = 0;
714 /* Boot on the stack */
715 /* Kick the second */
716 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
718 pr_debug("Waiting for send to finish...\n");
719 send_status = safe_apic_wait_icr_idle();
722 * Give the other CPU some time to accept the IPI.
725 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
726 maxlvt = lapic_get_maxlvt();
727 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
728 apic_write(APIC_ESR, 0);
729 accept_status = (apic_read(APIC_ESR) & 0xEF);
731 pr_debug("NMI sent\n");
734 pr_err("APIC never delivered???\n");
736 pr_err("APIC delivery error (%lx)\n", accept_status);
738 return (send_status | accept_status);
742 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
744 unsigned long send_status = 0, accept_status = 0;
745 int maxlvt, num_starts, j;
747 maxlvt = lapic_get_maxlvt();
750 * Be paranoid about clearing APIC errors.
752 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
753 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
754 apic_write(APIC_ESR, 0);
758 pr_debug("Asserting INIT\n");
761 * Turn INIT on target chip
766 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
769 pr_debug("Waiting for send to finish...\n");
770 send_status = safe_apic_wait_icr_idle();
774 pr_debug("Deasserting INIT\n");
778 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
780 pr_debug("Waiting for send to finish...\n");
781 send_status = safe_apic_wait_icr_idle();
786 * Should we send STARTUP IPIs ?
788 * Determine this based on the APIC version.
789 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
791 if (APIC_INTEGRATED(boot_cpu_apic_version))
797 * Run STARTUP IPI loop.
799 pr_debug("#startup loops: %d\n", num_starts);
801 for (j = 1; j <= num_starts; j++) {
802 pr_debug("Sending STARTUP #%d\n", j);
803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
804 apic_write(APIC_ESR, 0);
806 pr_debug("After apic_write\n");
813 /* Boot on the stack */
814 /* Kick the second */
815 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
819 * Give the other CPU some time to accept the IPI.
821 if (init_udelay == 0)
826 pr_debug("Startup point 1\n");
828 pr_debug("Waiting for send to finish...\n");
829 send_status = safe_apic_wait_icr_idle();
832 * Give the other CPU some time to accept the IPI.
834 if (init_udelay == 0)
839 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
840 apic_write(APIC_ESR, 0);
841 accept_status = (apic_read(APIC_ESR) & 0xEF);
842 if (send_status || accept_status)
845 pr_debug("After Startup\n");
848 pr_err("APIC never delivered???\n");
850 pr_err("APIC delivery error (%lx)\n", accept_status);
852 return (send_status | accept_status);
855 /* reduce the number of lines printed when booting a large cpu count system */
856 static void announce_cpu(int cpu, int apicid)
858 static int current_node = -1;
859 int node = early_cpu_to_node(cpu);
860 static int width, node_width;
863 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
866 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
869 printk(KERN_INFO "x86: Booting SMP configuration:\n");
871 if (system_state < SYSTEM_RUNNING) {
872 if (node != current_node) {
873 if (current_node > (-1))
877 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
878 node_width - num_digits(node), " ", node);
881 /* Add padding for the BSP */
883 pr_cont("%*s", width + 1, " ");
885 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
888 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
892 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
896 cpu = smp_processor_id();
897 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
904 * Wake up AP by INIT, INIT, STARTUP sequence.
906 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
907 * boot-strap code which is not a desired behavior for waking up BSP. To
908 * void the boot-strap code, wake up CPU0 by NMI instead.
910 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
911 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
912 * We'll change this code in the future to wake up hard offlined CPU0 if
913 * real platform and request are available.
916 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
917 int *cpu0_nmi_registered)
925 * Wake up AP by INIT, INIT, STARTUP sequence.
928 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
933 * Wake up BSP by nmi.
935 * Register a NMI handler to help wake up CPU0.
937 boot_error = register_nmi_handler(NMI_LOCAL,
938 wakeup_cpu0_nmi, 0, "wake_cpu0");
941 enable_start_cpu0 = 1;
942 *cpu0_nmi_registered = 1;
943 if (apic->dest_logical == APIC_DEST_LOGICAL)
944 id = cpu0_logical_apicid;
947 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
956 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
958 /* Just in case we booted with a single CPU. */
959 alternatives_enable_smp();
961 per_cpu(current_task, cpu) = idle;
964 /* Stack for startup_32 can be just as for start_secondary onwards */
966 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
968 initial_gs = per_cpu_offset(cpu);
973 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
974 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
975 * Returns zero if CPU booted OK, else error code from
976 * ->wakeup_secondary_cpu.
978 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
979 int *cpu0_nmi_registered)
981 volatile u32 *trampoline_status =
982 (volatile u32 *) __va(real_mode_header->trampoline_status);
983 /* start_ip had better be page-aligned! */
984 unsigned long start_ip = real_mode_header->trampoline_start;
986 unsigned long boot_error = 0;
987 unsigned long timeout;
989 idle->thread.sp = (unsigned long)task_pt_regs(idle);
990 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
991 initial_code = (unsigned long)start_secondary;
992 initial_stack = idle->thread.sp;
995 * Enable the espfix hack for this CPU
997 #ifdef CONFIG_X86_ESPFIX64
1001 /* So we see what's up */
1002 announce_cpu(cpu, apicid);
1005 * This grunge runs the startup process for
1006 * the targeted processor.
1009 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1011 pr_debug("Setting warm reset code and vector.\n");
1013 smpboot_setup_warm_reset_vector(start_ip);
1015 * Be paranoid about clearing APIC errors.
1017 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1018 apic_write(APIC_ESR, 0);
1019 apic_read(APIC_ESR);
1024 * AP might wait on cpu_callout_mask in cpu_init() with
1025 * cpu_initialized_mask set if previous attempt to online
1026 * it timed-out. Clear cpu_initialized_mask so that after
1027 * INIT/SIPI it could start with a clean state.
1029 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1033 * Wake up a CPU in difference cases:
1034 * - Use the method in the APIC driver if it's defined
1036 * - Use an INIT boot APIC message for APs or NMI for BSP.
1038 if (apic->wakeup_secondary_cpu)
1039 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1041 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1042 cpu0_nmi_registered);
1046 * Wait 10s total for first sign of life from AP
1049 timeout = jiffies + 10*HZ;
1050 while (time_before(jiffies, timeout)) {
1051 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1053 * Tell AP to proceed with initialization
1055 cpumask_set_cpu(cpu, cpu_callout_mask);
1065 * Wait till AP completes initial initialization
1067 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1069 * Allow other tasks to run while we wait for the
1070 * AP to come online. This also gives a chance
1071 * for the MTRR work(triggered by the AP coming online)
1072 * to be completed in the stop machine context.
1078 /* mark "stuck" area as not stuck */
1079 *trampoline_status = 0;
1081 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1083 * Cleanup possible dangling ends...
1085 smpboot_restore_warm_reset_vector();
1091 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1093 int apicid = apic->cpu_present_to_apicid(cpu);
1094 int cpu0_nmi_registered = 0;
1095 unsigned long flags;
1098 lockdep_assert_irqs_enabled();
1100 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1102 if (apicid == BAD_APICID ||
1103 !physid_isset(apicid, phys_cpu_present_map) ||
1104 !apic->apic_id_valid(apicid)) {
1105 pr_err("%s: bad cpu %d\n", __func__, cpu);
1110 * Already booted CPU?
1112 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1113 pr_debug("do_boot_cpu %d Already started\n", cpu);
1118 * Save current MTRR state in case it was changed since early boot
1119 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1123 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1124 err = cpu_check_up_prepare(cpu);
1125 if (err && err != -EBUSY)
1128 /* the FPU context is blank, nobody can own it */
1129 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1131 common_cpu_up(cpu, tidle);
1133 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1135 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1141 * Check TSC synchronization with the AP (keep irqs disabled
1144 local_irq_save(flags);
1145 check_tsc_sync_source(cpu);
1146 local_irq_restore(flags);
1148 while (!cpu_online(cpu)) {
1150 touch_nmi_watchdog();
1155 * Clean up the nmi handler. Do this after the callin and callout sync
1156 * to avoid impact of possible long unregister time.
1158 if (cpu0_nmi_registered)
1159 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1165 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1167 void arch_disable_smp_support(void)
1169 disable_ioapic_support();
1173 * Fall back to non SMP mode after errors.
1175 * RED-PEN audit/test this more. I bet there is more state messed up here.
1177 static __init void disable_smp(void)
1179 pr_info("SMP disabled\n");
1181 disable_ioapic_support();
1183 init_cpu_present(cpumask_of(0));
1184 init_cpu_possible(cpumask_of(0));
1186 if (smp_found_config)
1187 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1189 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1190 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1191 cpumask_set_cpu(0, topology_core_cpumask(0));
1195 * Various sanity checks.
1197 static void __init smp_sanity_check(void)
1201 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1202 if (def_to_bigsmp && nr_cpu_ids > 8) {
1206 pr_warn("More than 8 CPUs detected - skipping them\n"
1207 "Use CONFIG_X86_BIGSMP\n");
1210 for_each_present_cpu(cpu) {
1212 set_cpu_present(cpu, false);
1217 for_each_possible_cpu(cpu) {
1219 set_cpu_possible(cpu, false);
1227 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1228 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1229 hard_smp_processor_id());
1231 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1235 * Should not be necessary because the MP table should list the boot
1236 * CPU too, but we do it for the sake of robustness anyway.
1238 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1239 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1240 boot_cpu_physical_apicid);
1241 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1246 static void __init smp_cpu_index_default(void)
1249 struct cpuinfo_x86 *c;
1251 for_each_possible_cpu(i) {
1253 /* mark all to hotplug */
1254 c->cpu_index = nr_cpu_ids;
1258 static void __init smp_get_logical_apicid(void)
1261 cpu0_logical_apicid = apic_read(APIC_LDR);
1263 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1267 * Prepare for SMP bootup.
1268 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1269 * for common interface support.
1271 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1275 smp_cpu_index_default();
1278 * Setup boot CPU information
1280 smp_store_boot_cpu_info(); /* Final full version of the data */
1281 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1284 for_each_possible_cpu(i) {
1285 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1286 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1287 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1291 * Set 'default' x86 topology, this matches default_topology() in that
1292 * it has NUMA nodes as a topology level. See also
1293 * native_smp_cpus_done().
1295 * Must be done before set_cpus_sibling_map() is ran.
1297 set_sched_topology(x86_topology);
1299 set_cpu_sibling_map(0);
1303 switch (apic_intr_mode) {
1305 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1308 case APIC_SYMMETRIC_IO_NO_ROUTING:
1310 /* Setup local timer */
1311 x86_init.timers.setup_percpu_clockev();
1313 case APIC_VIRTUAL_WIRE:
1314 case APIC_SYMMETRIC_IO:
1318 /* Setup local timer */
1319 x86_init.timers.setup_percpu_clockev();
1321 smp_get_logical_apicid();
1324 print_cpu_info(&cpu_data(0));
1326 native_pv_lock_init();
1330 set_mtrr_aps_delayed_init();
1332 smp_quirk_init_udelay();
1335 void arch_enable_nonboot_cpus_begin(void)
1337 set_mtrr_aps_delayed_init();
1340 void arch_enable_nonboot_cpus_end(void)
1346 * Early setup to make printk work.
1348 void __init native_smp_prepare_boot_cpu(void)
1350 int me = smp_processor_id();
1351 switch_to_new_gdt(me);
1352 /* already set me in cpu_online_mask in boot_cpu_init() */
1353 cpumask_set_cpu(me, cpu_callout_mask);
1354 cpu_set_state_online(me);
1357 void __init native_smp_cpus_done(unsigned int max_cpus)
1359 pr_debug("Boot done\n");
1361 if (x86_has_numa_in_package)
1362 set_sched_topology(x86_numa_in_package_topology);
1369 static int __initdata setup_possible_cpus = -1;
1370 static int __init _setup_possible_cpus(char *str)
1372 get_option(&str, &setup_possible_cpus);
1375 early_param("possible_cpus", _setup_possible_cpus);
1379 * cpu_possible_mask should be static, it cannot change as cpu's
1380 * are onlined, or offlined. The reason is per-cpu data-structures
1381 * are allocated by some modules at init time, and dont expect to
1382 * do this dynamically on cpu arrival/departure.
1383 * cpu_present_mask on the other hand can change dynamically.
1384 * In case when cpu_hotplug is not compiled, then we resort to current
1385 * behaviour, which is cpu_possible == cpu_present.
1388 * Three ways to find out the number of additional hotplug CPUs:
1389 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1390 * - The user can overwrite it with possible_cpus=NUM
1391 * - Otherwise don't reserve additional CPUs.
1392 * We do this because additional CPUs waste a lot of memory.
1395 __init void prefill_possible_map(void)
1399 /* No boot processor was found in mptable or ACPI MADT */
1400 if (!num_processors) {
1401 if (boot_cpu_has(X86_FEATURE_APIC)) {
1402 int apicid = boot_cpu_physical_apicid;
1403 int cpu = hard_smp_processor_id();
1405 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1407 /* Make sure boot cpu is enumerated */
1408 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1409 apic->apic_id_valid(apicid))
1410 generic_processor_info(apicid, boot_cpu_apic_version);
1413 if (!num_processors)
1417 i = setup_max_cpus ?: 1;
1418 if (setup_possible_cpus == -1) {
1419 possible = num_processors;
1420 #ifdef CONFIG_HOTPLUG_CPU
1422 possible += disabled_cpus;
1428 possible = setup_possible_cpus;
1430 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1432 /* nr_cpu_ids could be reduced via nr_cpus= */
1433 if (possible > nr_cpu_ids) {
1434 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1435 possible, nr_cpu_ids);
1436 possible = nr_cpu_ids;
1439 #ifdef CONFIG_HOTPLUG_CPU
1440 if (!setup_max_cpus)
1443 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1444 possible, setup_max_cpus);
1448 nr_cpu_ids = possible;
1450 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1451 possible, max_t(int, possible - num_processors, 0));
1453 reset_cpu_possible_mask();
1455 for (i = 0; i < possible; i++)
1456 set_cpu_possible(i, true);
1459 #ifdef CONFIG_HOTPLUG_CPU
1461 /* Recompute SMT state for all CPUs on offline */
1462 static void recompute_smt_state(void)
1464 int max_threads, cpu;
1467 for_each_online_cpu (cpu) {
1468 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1470 if (threads > max_threads)
1471 max_threads = threads;
1473 __max_smt_threads = max_threads;
1476 static void remove_siblinginfo(int cpu)
1479 struct cpuinfo_x86 *c = &cpu_data(cpu);
1481 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1482 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1484 * last thread sibling in this cpu core going down
1486 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1487 cpu_data(sibling).booted_cores--;
1490 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1491 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1492 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1493 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1494 cpumask_clear(cpu_llc_shared_mask(cpu));
1495 cpumask_clear(topology_sibling_cpumask(cpu));
1496 cpumask_clear(topology_core_cpumask(cpu));
1497 c->phys_proc_id = 0;
1499 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1500 recompute_smt_state();
1503 static void remove_cpu_from_maps(int cpu)
1505 set_cpu_online(cpu, false);
1506 cpumask_clear_cpu(cpu, cpu_callout_mask);
1507 cpumask_clear_cpu(cpu, cpu_callin_mask);
1508 /* was set by cpu_init() */
1509 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1510 numa_remove_cpu(cpu);
1513 void cpu_disable_common(void)
1515 int cpu = smp_processor_id();
1517 remove_siblinginfo(cpu);
1519 /* It's now safe to remove this processor from the online map */
1521 remove_cpu_from_maps(cpu);
1522 unlock_vector_lock();
1527 int native_cpu_disable(void)
1531 ret = lapic_can_unplug_cpu();
1536 cpu_disable_common();
1541 int common_cpu_die(unsigned int cpu)
1545 /* We don't do anything here: idle task is faking death itself. */
1547 /* They ack this in play_dead() by setting CPU_DEAD */
1548 if (cpu_wait_death(cpu, 5)) {
1549 if (system_state == SYSTEM_RUNNING)
1550 pr_info("CPU %u is now offline\n", cpu);
1552 pr_err("CPU %u didn't die...\n", cpu);
1559 void native_cpu_die(unsigned int cpu)
1561 common_cpu_die(cpu);
1564 void play_dead_common(void)
1569 (void)cpu_report_death();
1572 * With physical CPU hotplug, we should halt the cpu
1574 local_irq_disable();
1577 static bool wakeup_cpu0(void)
1579 if (smp_processor_id() == 0 && enable_start_cpu0)
1586 * We need to flush the caches before going to sleep, lest we have
1587 * dirty data in our caches when we come back up.
1589 static inline void mwait_play_dead(void)
1591 unsigned int eax, ebx, ecx, edx;
1592 unsigned int highest_cstate = 0;
1593 unsigned int highest_subcstate = 0;
1597 if (!this_cpu_has(X86_FEATURE_MWAIT))
1599 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1601 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1604 eax = CPUID_MWAIT_LEAF;
1606 native_cpuid(&eax, &ebx, &ecx, &edx);
1609 * eax will be 0 if EDX enumeration is not valid.
1610 * Initialized below to cstate, sub_cstate value when EDX is valid.
1612 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1615 edx >>= MWAIT_SUBSTATE_SIZE;
1616 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1617 if (edx & MWAIT_SUBSTATE_MASK) {
1619 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1622 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1623 (highest_subcstate - 1);
1627 * This should be a memory location in a cache line which is
1628 * unlikely to be touched by other processors. The actual
1629 * content is immaterial as it is not actually modified in any way.
1631 mwait_ptr = ¤t_thread_info()->flags;
1637 * The CLFLUSH is a workaround for erratum AAI65 for
1638 * the Xeon 7400 series. It's not clear it is actually
1639 * needed, but it should be harmless in either case.
1640 * The WBINVD is insufficient due to the spurious-wakeup
1641 * case where we return around the loop.
1646 __monitor(mwait_ptr, 0, 0);
1650 * If NMI wants to wake up CPU0, start CPU0.
1657 void hlt_play_dead(void)
1659 if (__this_cpu_read(cpu_info.x86) >= 4)
1665 * If NMI wants to wake up CPU0, start CPU0.
1672 void native_play_dead(void)
1675 tboot_shutdown(TB_SHUTDOWN_WFS);
1677 mwait_play_dead(); /* Only returns on failure */
1678 if (cpuidle_play_dead())
1682 #else /* ... !CONFIG_HOTPLUG_CPU */
1683 int native_cpu_disable(void)
1688 void native_cpu_die(unsigned int cpu)
1690 /* We said "no" in __cpu_disable */
1694 void native_play_dead(void)