2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/qspinlock.h>
82 /* Number of siblings per CPU package */
83 int smp_num_siblings = 1;
84 EXPORT_SYMBOL(smp_num_siblings);
86 /* Last level cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 /* Logical package management. We might want to allocate that dynamically */
104 unsigned int __max_logical_packages __read_mostly;
105 EXPORT_SYMBOL(__max_logical_packages);
106 static unsigned int logical_packages __read_mostly;
108 /* Maximum number of SMT threads on any online core */
109 int __max_smt_threads __read_mostly;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update;
114 int arch_update_cpu_topology(void)
116 int retval = x86_topology_update;
118 x86_topology_update = false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
139 static inline void smpboot_restore_warm_reset_vector(void)
144 * Install writable page 0 entry to set BIOS data area.
149 * Paranoid: Set warm reset code and vector here back
152 spin_lock_irqsave(&rtc_lock, flags);
154 spin_unlock_irqrestore(&rtc_lock, flags);
156 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
160 * Report back to the Boot Processor during boot time or to the caller processor
163 static void smp_callin(void)
168 * If waken up by an INIT in an 82489DX configuration
169 * cpu_callout_mask guarantees we don't get here before
170 * an INIT_deassert IPI reaches our local APIC, so it is
171 * now safe to touch our local APIC.
173 cpuid = smp_processor_id();
176 * (This works even if the APIC is not enabled.)
178 phys_id = read_apic_id();
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
189 * Save our processor parameters. Note: this information
190 * is needed for clock calibration.
192 smp_store_cpu_info(cpuid);
195 * The topology information must be up to date before
196 * calibrate_delay() and notify_cpu_starting().
198 set_cpu_sibling_map(raw_smp_processor_id());
202 * Update loops_per_jiffy in cpu_data. Previous call to
203 * smp_store_cpu_info() stored a value that is close but not as
204 * accurate as the value just calculated.
207 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
208 pr_debug("Stack at about %p\n", &cpuid);
212 notify_cpu_starting(cpuid);
215 * Allow the master to continue.
217 cpumask_set_cpu(cpuid, cpu_callin_mask);
220 static int cpu0_logical_apicid;
221 static int enable_start_cpu0;
223 * Activate a secondary processor.
225 static void notrace start_secondary(void *unused)
228 * Don't put *anything* except direct CPU state initialization
229 * before cpu_init(), SMP booting is too fragile that we want to
230 * limit the things done here to the most necessary things.
232 if (boot_cpu_has(X86_FEATURE_PCID))
233 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
236 /* switch away from the initial page table */
237 load_cr3(swapper_pg_dir);
242 x86_cpuinit.early_percpu_clock_init();
246 enable_start_cpu0 = 0;
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the boot CPU:
253 check_tsc_sync_target();
256 * Lock vector_lock, set CPU online and bring the vector
257 * allocator online. Online must be set with vector_lock held
258 * to prevent a concurrent irq setup/teardown from seeing a
259 * half valid vector space.
262 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit.setup_percpu_clockev();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
281 * topology_phys_to_logical_pkg - Map a physical package id to a logical
283 * Returns logical package id or -1 if not found
285 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
289 for_each_possible_cpu(cpu) {
290 struct cpuinfo_x86 *c = &cpu_data(cpu);
292 if (c->initialized && c->phys_proc_id == phys_pkg)
293 return c->logical_proc_id;
297 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
300 * topology_update_package_map - Update the physical to logical package map
301 * @pkg: The physical package id as retrieved via CPUID
302 * @cpu: The cpu for which this is updated
304 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
308 /* Already available somewhere? */
309 new = topology_phys_to_logical_pkg(pkg);
313 if (logical_packages >= __max_logical_packages) {
314 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
315 logical_packages, cpu, __max_logical_packages);
319 new = logical_packages++;
321 pr_info("CPU %u Converting physical %u to logical package %u\n",
325 cpu_data(cpu).logical_proc_id = new;
329 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
334 * Today neither Intel nor AMD support heterogenous systems. That
335 * might change in the future....
337 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
338 * computation, this won't actually work since some Intel BIOSes
339 * report inconsistent HT data when they disable HT.
341 * In particular, they reduce the APIC-IDs to only include the cores,
342 * but leave the CPUID topology to say there are (2) siblings.
343 * This means we don't know how many threads there will be until
344 * after the APIC enumeration.
346 * By not including this we'll sometimes over-estimate the number of
347 * logical packages by the amount of !present siblings, but this is
348 * still better than MAX_LOCAL_APIC.
350 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
351 * on the command line leading to a similar issue as the HT disable
352 * problem because the hyperthreads are usually enumerated after the
355 ncpus = boot_cpu_data.x86_max_cores;
357 pr_warn("x86_max_cores == zero !?!?");
361 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
362 pr_info("Max logical packages: %u\n", __max_logical_packages);
364 topology_update_package_map(c->phys_proc_id, cpu);
367 void __init smp_store_boot_cpu_info(void)
369 int id = 0; /* CPU 0 */
370 struct cpuinfo_x86 *c = &cpu_data(id);
374 smp_init_package_map(c, id);
375 c->initialized = true;
379 * The bootstrap kernel entry code has set these up. Save them for
382 void smp_store_cpu_info(int id)
384 struct cpuinfo_x86 *c = &cpu_data(id);
386 /* Copy boot_cpu_data only on the first bringup */
391 * During boot time, CPU0 has this setup already. Save the info when
392 * bringing up AP or offlined CPU0.
394 identify_secondary_cpu(c);
395 c->initialized = true;
399 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
401 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
403 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
407 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
411 return !WARN_ONCE(!topology_same_node(c, o),
412 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
413 "[node: %d != %d]. Ignoring dependency.\n",
414 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
417 #define link_mask(mfunc, c1, c2) \
419 cpumask_set_cpu((c1), mfunc(c2)); \
420 cpumask_set_cpu((c2), mfunc(c1)); \
423 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
425 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
428 if (c->phys_proc_id == o->phys_proc_id &&
429 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
430 if (c->cpu_core_id == o->cpu_core_id)
431 return topology_sane(c, o, "smt");
433 if ((c->cu_id != 0xff) &&
434 (o->cu_id != 0xff) &&
435 (c->cu_id == o->cu_id))
436 return topology_sane(c, o, "smt");
439 } else if (c->phys_proc_id == o->phys_proc_id &&
440 c->cpu_core_id == o->cpu_core_id) {
441 return topology_sane(c, o, "smt");
447 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
449 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
451 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
452 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
453 return topology_sane(c, o, "llc");
459 * Unlike the other levels, we do not enforce keeping a
460 * multicore group inside a NUMA node. If this happens, we will
461 * discard the MC level of the topology later.
463 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
465 if (c->phys_proc_id == o->phys_proc_id)
470 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
471 static inline int x86_sched_itmt_flags(void)
473 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
476 #ifdef CONFIG_SCHED_MC
477 static int x86_core_flags(void)
479 return cpu_core_flags() | x86_sched_itmt_flags();
482 #ifdef CONFIG_SCHED_SMT
483 static int x86_smt_flags(void)
485 return cpu_smt_flags() | x86_sched_itmt_flags();
490 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
491 #ifdef CONFIG_SCHED_SMT
492 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
494 #ifdef CONFIG_SCHED_MC
495 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
500 static struct sched_domain_topology_level x86_topology[] = {
501 #ifdef CONFIG_SCHED_SMT
502 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
504 #ifdef CONFIG_SCHED_MC
505 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
507 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
512 * Set if a package/die has multiple NUMA nodes inside.
513 * AMD Magny-Cours and Intel Cluster-on-Die have this.
515 static bool x86_has_numa_in_package;
517 void set_cpu_sibling_map(int cpu)
519 bool has_smt = smp_num_siblings > 1;
520 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
521 struct cpuinfo_x86 *c = &cpu_data(cpu);
522 struct cpuinfo_x86 *o;
525 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
528 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
529 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
530 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
535 for_each_cpu(i, cpu_sibling_setup_mask) {
538 if ((i == cpu) || (has_smt && match_smt(c, o)))
539 link_mask(topology_sibling_cpumask, cpu, i);
541 if ((i == cpu) || (has_mp && match_llc(c, o)))
542 link_mask(cpu_llc_shared_mask, cpu, i);
547 * This needs a separate iteration over the cpus because we rely on all
548 * topology_sibling_cpumask links to be set-up.
550 for_each_cpu(i, cpu_sibling_setup_mask) {
553 if ((i == cpu) || (has_mp && match_die(c, o))) {
554 link_mask(topology_core_cpumask, cpu, i);
557 * Does this new cpu bringup a new core?
560 topology_sibling_cpumask(cpu)) == 1) {
562 * for each core in package, increment
563 * the booted_cores for this new cpu
566 topology_sibling_cpumask(i)) == i)
569 * increment the core count for all
570 * the other cpus in this package
573 cpu_data(i).booted_cores++;
574 } else if (i != cpu && !c->booted_cores)
575 c->booted_cores = cpu_data(i).booted_cores;
577 if (match_die(c, o) && !topology_same_node(c, o))
578 x86_has_numa_in_package = true;
581 threads = cpumask_weight(topology_sibling_cpumask(cpu));
582 if (threads > __max_smt_threads)
583 __max_smt_threads = threads;
586 /* maps the cpu to the sched domain representing multi-core */
587 const struct cpumask *cpu_coregroup_mask(int cpu)
589 return cpu_llc_shared_mask(cpu);
592 static void impress_friends(void)
595 unsigned long bogosum = 0;
597 * Allow the user to impress friends.
599 pr_debug("Before bogomips\n");
600 for_each_possible_cpu(cpu)
601 if (cpumask_test_cpu(cpu, cpu_callout_mask))
602 bogosum += cpu_data(cpu).loops_per_jiffy;
603 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
606 (bogosum/(5000/HZ))%100);
608 pr_debug("Before bogocount - setting activated=1\n");
611 void __inquire_remote_apic(int apicid)
613 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
614 const char * const names[] = { "ID", "VERSION", "SPIV" };
618 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
620 for (i = 0; i < ARRAY_SIZE(regs); i++) {
621 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
626 status = safe_apic_wait_icr_idle();
628 pr_cont("a previous APIC delivery may have failed\n");
630 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
635 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
636 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
639 case APIC_ICR_RR_VALID:
640 status = apic_read(APIC_RRR);
641 pr_cont("%08x\n", status);
650 * The Multiprocessor Specification 1.4 (1997) example code suggests
651 * that there should be a 10ms delay between the BSP asserting INIT
652 * and de-asserting INIT, when starting a remote processor.
653 * But that slows boot and resume on modern processors, which include
654 * many cores and don't require that delay.
656 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
657 * Modern processor families are quirked to remove the delay entirely.
659 #define UDELAY_10MS_DEFAULT 10000
661 static unsigned int init_udelay = UINT_MAX;
663 static int __init cpu_init_udelay(char *str)
665 get_option(&str, &init_udelay);
669 early_param("cpu_init_udelay", cpu_init_udelay);
671 static void __init smp_quirk_init_udelay(void)
673 /* if cmdline changed it from default, leave it alone */
674 if (init_udelay != UINT_MAX)
677 /* if modern processor, use no delay */
678 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
679 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
683 /* else, use legacy delay */
684 init_udelay = UDELAY_10MS_DEFAULT;
688 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
689 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
690 * won't ... remember to clear down the APIC, etc later.
693 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
695 unsigned long send_status, accept_status = 0;
699 /* Boot on the stack */
700 /* Kick the second */
701 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
703 pr_debug("Waiting for send to finish...\n");
704 send_status = safe_apic_wait_icr_idle();
707 * Give the other CPU some time to accept the IPI.
710 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
711 maxlvt = lapic_get_maxlvt();
712 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
713 apic_write(APIC_ESR, 0);
714 accept_status = (apic_read(APIC_ESR) & 0xEF);
716 pr_debug("NMI sent\n");
719 pr_err("APIC never delivered???\n");
721 pr_err("APIC delivery error (%lx)\n", accept_status);
723 return (send_status | accept_status);
727 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
729 unsigned long send_status = 0, accept_status = 0;
730 int maxlvt, num_starts, j;
732 maxlvt = lapic_get_maxlvt();
735 * Be paranoid about clearing APIC errors.
737 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
738 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
739 apic_write(APIC_ESR, 0);
743 pr_debug("Asserting INIT\n");
746 * Turn INIT on target chip
751 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
754 pr_debug("Waiting for send to finish...\n");
755 send_status = safe_apic_wait_icr_idle();
759 pr_debug("Deasserting INIT\n");
763 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
765 pr_debug("Waiting for send to finish...\n");
766 send_status = safe_apic_wait_icr_idle();
771 * Should we send STARTUP IPIs ?
773 * Determine this based on the APIC version.
774 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
776 if (APIC_INTEGRATED(boot_cpu_apic_version))
782 * Run STARTUP IPI loop.
784 pr_debug("#startup loops: %d\n", num_starts);
786 for (j = 1; j <= num_starts; j++) {
787 pr_debug("Sending STARTUP #%d\n", j);
788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
789 apic_write(APIC_ESR, 0);
791 pr_debug("After apic_write\n");
798 /* Boot on the stack */
799 /* Kick the second */
800 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
804 * Give the other CPU some time to accept the IPI.
806 if (init_udelay == 0)
811 pr_debug("Startup point 1\n");
813 pr_debug("Waiting for send to finish...\n");
814 send_status = safe_apic_wait_icr_idle();
817 * Give the other CPU some time to accept the IPI.
819 if (init_udelay == 0)
824 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
825 apic_write(APIC_ESR, 0);
826 accept_status = (apic_read(APIC_ESR) & 0xEF);
827 if (send_status || accept_status)
830 pr_debug("After Startup\n");
833 pr_err("APIC never delivered???\n");
835 pr_err("APIC delivery error (%lx)\n", accept_status);
837 return (send_status | accept_status);
840 /* reduce the number of lines printed when booting a large cpu count system */
841 static void announce_cpu(int cpu, int apicid)
843 static int current_node = -1;
844 int node = early_cpu_to_node(cpu);
845 static int width, node_width;
848 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
851 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
854 printk(KERN_INFO "x86: Booting SMP configuration:\n");
856 if (system_state < SYSTEM_RUNNING) {
857 if (node != current_node) {
858 if (current_node > (-1))
862 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
863 node_width - num_digits(node), " ", node);
866 /* Add padding for the BSP */
868 pr_cont("%*s", width + 1, " ");
870 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
873 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
877 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
881 cpu = smp_processor_id();
882 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
889 * Wake up AP by INIT, INIT, STARTUP sequence.
891 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
892 * boot-strap code which is not a desired behavior for waking up BSP. To
893 * void the boot-strap code, wake up CPU0 by NMI instead.
895 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
896 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
897 * We'll change this code in the future to wake up hard offlined CPU0 if
898 * real platform and request are available.
901 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
902 int *cpu0_nmi_registered)
910 * Wake up AP by INIT, INIT, STARTUP sequence.
913 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
918 * Wake up BSP by nmi.
920 * Register a NMI handler to help wake up CPU0.
922 boot_error = register_nmi_handler(NMI_LOCAL,
923 wakeup_cpu0_nmi, 0, "wake_cpu0");
926 enable_start_cpu0 = 1;
927 *cpu0_nmi_registered = 1;
928 if (apic->dest_logical == APIC_DEST_LOGICAL)
929 id = cpu0_logical_apicid;
932 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
941 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
943 /* Just in case we booted with a single CPU. */
944 alternatives_enable_smp();
946 per_cpu(current_task, cpu) = idle;
949 /* Stack for startup_32 can be just as for start_secondary onwards */
951 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
953 initial_gs = per_cpu_offset(cpu);
958 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
959 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
960 * Returns zero if CPU booted OK, else error code from
961 * ->wakeup_secondary_cpu.
963 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
964 int *cpu0_nmi_registered)
966 volatile u32 *trampoline_status =
967 (volatile u32 *) __va(real_mode_header->trampoline_status);
968 /* start_ip had better be page-aligned! */
969 unsigned long start_ip = real_mode_header->trampoline_start;
971 unsigned long boot_error = 0;
972 unsigned long timeout;
974 idle->thread.sp = (unsigned long)task_pt_regs(idle);
975 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
976 initial_code = (unsigned long)start_secondary;
977 initial_stack = idle->thread.sp;
980 * Enable the espfix hack for this CPU
982 #ifdef CONFIG_X86_ESPFIX64
986 /* So we see what's up */
987 announce_cpu(cpu, apicid);
990 * This grunge runs the startup process for
991 * the targeted processor.
994 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
996 pr_debug("Setting warm reset code and vector.\n");
998 smpboot_setup_warm_reset_vector(start_ip);
1000 * Be paranoid about clearing APIC errors.
1002 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1003 apic_write(APIC_ESR, 0);
1004 apic_read(APIC_ESR);
1009 * AP might wait on cpu_callout_mask in cpu_init() with
1010 * cpu_initialized_mask set if previous attempt to online
1011 * it timed-out. Clear cpu_initialized_mask so that after
1012 * INIT/SIPI it could start with a clean state.
1014 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1018 * Wake up a CPU in difference cases:
1019 * - Use the method in the APIC driver if it's defined
1021 * - Use an INIT boot APIC message for APs or NMI for BSP.
1023 if (apic->wakeup_secondary_cpu)
1024 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1026 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1027 cpu0_nmi_registered);
1031 * Wait 10s total for first sign of life from AP
1034 timeout = jiffies + 10*HZ;
1035 while (time_before(jiffies, timeout)) {
1036 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1038 * Tell AP to proceed with initialization
1040 cpumask_set_cpu(cpu, cpu_callout_mask);
1050 * Wait till AP completes initial initialization
1052 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1054 * Allow other tasks to run while we wait for the
1055 * AP to come online. This also gives a chance
1056 * for the MTRR work(triggered by the AP coming online)
1057 * to be completed in the stop machine context.
1063 /* mark "stuck" area as not stuck */
1064 *trampoline_status = 0;
1066 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1068 * Cleanup possible dangling ends...
1070 smpboot_restore_warm_reset_vector();
1076 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1078 int apicid = apic->cpu_present_to_apicid(cpu);
1079 int cpu0_nmi_registered = 0;
1080 unsigned long flags;
1083 lockdep_assert_irqs_enabled();
1085 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1087 if (apicid == BAD_APICID ||
1088 !physid_isset(apicid, phys_cpu_present_map) ||
1089 !apic->apic_id_valid(apicid)) {
1090 pr_err("%s: bad cpu %d\n", __func__, cpu);
1095 * Already booted CPU?
1097 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1098 pr_debug("do_boot_cpu %d Already started\n", cpu);
1103 * Save current MTRR state in case it was changed since early boot
1104 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1108 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1109 err = cpu_check_up_prepare(cpu);
1110 if (err && err != -EBUSY)
1113 /* the FPU context is blank, nobody can own it */
1114 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1116 common_cpu_up(cpu, tidle);
1118 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1120 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1126 * Check TSC synchronization with the AP (keep irqs disabled
1129 local_irq_save(flags);
1130 check_tsc_sync_source(cpu);
1131 local_irq_restore(flags);
1133 while (!cpu_online(cpu)) {
1135 touch_nmi_watchdog();
1140 * Clean up the nmi handler. Do this after the callin and callout sync
1141 * to avoid impact of possible long unregister time.
1143 if (cpu0_nmi_registered)
1144 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1150 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1152 void arch_disable_smp_support(void)
1154 disable_ioapic_support();
1158 * Fall back to non SMP mode after errors.
1160 * RED-PEN audit/test this more. I bet there is more state messed up here.
1162 static __init void disable_smp(void)
1164 pr_info("SMP disabled\n");
1166 disable_ioapic_support();
1168 init_cpu_present(cpumask_of(0));
1169 init_cpu_possible(cpumask_of(0));
1171 if (smp_found_config)
1172 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1174 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1175 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1176 cpumask_set_cpu(0, topology_core_cpumask(0));
1180 * Various sanity checks.
1182 static void __init smp_sanity_check(void)
1186 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1187 if (def_to_bigsmp && nr_cpu_ids > 8) {
1191 pr_warn("More than 8 CPUs detected - skipping them\n"
1192 "Use CONFIG_X86_BIGSMP\n");
1195 for_each_present_cpu(cpu) {
1197 set_cpu_present(cpu, false);
1202 for_each_possible_cpu(cpu) {
1204 set_cpu_possible(cpu, false);
1212 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1213 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1214 hard_smp_processor_id());
1216 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1220 * Should not be necessary because the MP table should list the boot
1221 * CPU too, but we do it for the sake of robustness anyway.
1223 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1224 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1225 boot_cpu_physical_apicid);
1226 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1231 static void __init smp_cpu_index_default(void)
1234 struct cpuinfo_x86 *c;
1236 for_each_possible_cpu(i) {
1238 /* mark all to hotplug */
1239 c->cpu_index = nr_cpu_ids;
1243 static void __init smp_get_logical_apicid(void)
1246 cpu0_logical_apicid = apic_read(APIC_LDR);
1248 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1252 * Prepare for SMP bootup.
1253 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1254 * for common interface support.
1256 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1260 smp_cpu_index_default();
1263 * Setup boot CPU information
1265 smp_store_boot_cpu_info(); /* Final full version of the data */
1266 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1269 for_each_possible_cpu(i) {
1270 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1271 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1272 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1276 * Set 'default' x86 topology, this matches default_topology() in that
1277 * it has NUMA nodes as a topology level. See also
1278 * native_smp_cpus_done().
1280 * Must be done before set_cpus_sibling_map() is ran.
1282 set_sched_topology(x86_topology);
1284 set_cpu_sibling_map(0);
1288 switch (apic_intr_mode) {
1290 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1293 case APIC_SYMMETRIC_IO_NO_ROUTING:
1295 /* Setup local timer */
1296 x86_init.timers.setup_percpu_clockev();
1298 case APIC_VIRTUAL_WIRE:
1299 case APIC_SYMMETRIC_IO:
1303 /* Setup local timer */
1304 x86_init.timers.setup_percpu_clockev();
1306 smp_get_logical_apicid();
1309 print_cpu_info(&cpu_data(0));
1311 native_pv_lock_init();
1315 set_mtrr_aps_delayed_init();
1317 smp_quirk_init_udelay();
1320 void arch_enable_nonboot_cpus_begin(void)
1322 set_mtrr_aps_delayed_init();
1325 void arch_enable_nonboot_cpus_end(void)
1331 * Early setup to make printk work.
1333 void __init native_smp_prepare_boot_cpu(void)
1335 int me = smp_processor_id();
1336 switch_to_new_gdt(me);
1337 /* already set me in cpu_online_mask in boot_cpu_init() */
1338 cpumask_set_cpu(me, cpu_callout_mask);
1339 cpu_set_state_online(me);
1342 void __init native_smp_cpus_done(unsigned int max_cpus)
1344 pr_debug("Boot done\n");
1346 if (x86_has_numa_in_package)
1347 set_sched_topology(x86_numa_in_package_topology);
1354 static int __initdata setup_possible_cpus = -1;
1355 static int __init _setup_possible_cpus(char *str)
1357 get_option(&str, &setup_possible_cpus);
1360 early_param("possible_cpus", _setup_possible_cpus);
1364 * cpu_possible_mask should be static, it cannot change as cpu's
1365 * are onlined, or offlined. The reason is per-cpu data-structures
1366 * are allocated by some modules at init time, and dont expect to
1367 * do this dynamically on cpu arrival/departure.
1368 * cpu_present_mask on the other hand can change dynamically.
1369 * In case when cpu_hotplug is not compiled, then we resort to current
1370 * behaviour, which is cpu_possible == cpu_present.
1373 * Three ways to find out the number of additional hotplug CPUs:
1374 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1375 * - The user can overwrite it with possible_cpus=NUM
1376 * - Otherwise don't reserve additional CPUs.
1377 * We do this because additional CPUs waste a lot of memory.
1380 __init void prefill_possible_map(void)
1384 /* No boot processor was found in mptable or ACPI MADT */
1385 if (!num_processors) {
1386 if (boot_cpu_has(X86_FEATURE_APIC)) {
1387 int apicid = boot_cpu_physical_apicid;
1388 int cpu = hard_smp_processor_id();
1390 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1392 /* Make sure boot cpu is enumerated */
1393 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1394 apic->apic_id_valid(apicid))
1395 generic_processor_info(apicid, boot_cpu_apic_version);
1398 if (!num_processors)
1402 i = setup_max_cpus ?: 1;
1403 if (setup_possible_cpus == -1) {
1404 possible = num_processors;
1405 #ifdef CONFIG_HOTPLUG_CPU
1407 possible += disabled_cpus;
1413 possible = setup_possible_cpus;
1415 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1417 /* nr_cpu_ids could be reduced via nr_cpus= */
1418 if (possible > nr_cpu_ids) {
1419 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1420 possible, nr_cpu_ids);
1421 possible = nr_cpu_ids;
1424 #ifdef CONFIG_HOTPLUG_CPU
1425 if (!setup_max_cpus)
1428 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1429 possible, setup_max_cpus);
1433 nr_cpu_ids = possible;
1435 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1436 possible, max_t(int, possible - num_processors, 0));
1438 reset_cpu_possible_mask();
1440 for (i = 0; i < possible; i++)
1441 set_cpu_possible(i, true);
1444 #ifdef CONFIG_HOTPLUG_CPU
1446 /* Recompute SMT state for all CPUs on offline */
1447 static void recompute_smt_state(void)
1449 int max_threads, cpu;
1452 for_each_online_cpu (cpu) {
1453 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1455 if (threads > max_threads)
1456 max_threads = threads;
1458 __max_smt_threads = max_threads;
1461 static void remove_siblinginfo(int cpu)
1464 struct cpuinfo_x86 *c = &cpu_data(cpu);
1466 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1467 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1469 * last thread sibling in this cpu core going down
1471 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1472 cpu_data(sibling).booted_cores--;
1475 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1476 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1477 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1478 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1479 cpumask_clear(cpu_llc_shared_mask(cpu));
1480 cpumask_clear(topology_sibling_cpumask(cpu));
1481 cpumask_clear(topology_core_cpumask(cpu));
1482 c->phys_proc_id = 0;
1484 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1485 recompute_smt_state();
1488 static void remove_cpu_from_maps(int cpu)
1490 set_cpu_online(cpu, false);
1491 cpumask_clear_cpu(cpu, cpu_callout_mask);
1492 cpumask_clear_cpu(cpu, cpu_callin_mask);
1493 /* was set by cpu_init() */
1494 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1495 numa_remove_cpu(cpu);
1498 void cpu_disable_common(void)
1500 int cpu = smp_processor_id();
1502 remove_siblinginfo(cpu);
1504 /* It's now safe to remove this processor from the online map */
1506 remove_cpu_from_maps(cpu);
1507 unlock_vector_lock();
1512 int native_cpu_disable(void)
1516 ret = lapic_can_unplug_cpu();
1521 cpu_disable_common();
1526 int common_cpu_die(unsigned int cpu)
1530 /* We don't do anything here: idle task is faking death itself. */
1532 /* They ack this in play_dead() by setting CPU_DEAD */
1533 if (cpu_wait_death(cpu, 5)) {
1534 if (system_state == SYSTEM_RUNNING)
1535 pr_info("CPU %u is now offline\n", cpu);
1537 pr_err("CPU %u didn't die...\n", cpu);
1544 void native_cpu_die(unsigned int cpu)
1546 common_cpu_die(cpu);
1549 void play_dead_common(void)
1554 (void)cpu_report_death();
1557 * With physical CPU hotplug, we should halt the cpu
1559 local_irq_disable();
1562 static bool wakeup_cpu0(void)
1564 if (smp_processor_id() == 0 && enable_start_cpu0)
1571 * We need to flush the caches before going to sleep, lest we have
1572 * dirty data in our caches when we come back up.
1574 static inline void mwait_play_dead(void)
1576 unsigned int eax, ebx, ecx, edx;
1577 unsigned int highest_cstate = 0;
1578 unsigned int highest_subcstate = 0;
1582 if (!this_cpu_has(X86_FEATURE_MWAIT))
1584 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1586 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1589 eax = CPUID_MWAIT_LEAF;
1591 native_cpuid(&eax, &ebx, &ecx, &edx);
1594 * eax will be 0 if EDX enumeration is not valid.
1595 * Initialized below to cstate, sub_cstate value when EDX is valid.
1597 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1600 edx >>= MWAIT_SUBSTATE_SIZE;
1601 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1602 if (edx & MWAIT_SUBSTATE_MASK) {
1604 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1607 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1608 (highest_subcstate - 1);
1612 * This should be a memory location in a cache line which is
1613 * unlikely to be touched by other processors. The actual
1614 * content is immaterial as it is not actually modified in any way.
1616 mwait_ptr = ¤t_thread_info()->flags;
1622 * The CLFLUSH is a workaround for erratum AAI65 for
1623 * the Xeon 7400 series. It's not clear it is actually
1624 * needed, but it should be harmless in either case.
1625 * The WBINVD is insufficient due to the spurious-wakeup
1626 * case where we return around the loop.
1631 __monitor(mwait_ptr, 0, 0);
1635 * If NMI wants to wake up CPU0, start CPU0.
1642 void hlt_play_dead(void)
1644 if (__this_cpu_read(cpu_info.x86) >= 4)
1650 * If NMI wants to wake up CPU0, start CPU0.
1657 void native_play_dead(void)
1660 tboot_shutdown(TB_SHUTDOWN_WFS);
1662 mwait_play_dead(); /* Only returns on failure */
1663 if (cpuidle_play_dead())
1667 #else /* ... !CONFIG_HOTPLUG_CPU */
1668 int native_cpu_disable(void)
1673 void native_cpu_die(unsigned int cpu)
1675 /* We said "no" in __cpu_disable */
1679 void native_play_dead(void)