2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/smpboot_hooks.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* State of each CPU */
82 DEFINE_PER_CPU(int, cpu_state) = { 0 };
84 /* Number of siblings per CPU package */
85 int smp_num_siblings = 1;
86 EXPORT_SYMBOL(smp_num_siblings);
88 /* Last level cache ID of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
101 /* Per CPU bogomips and other parameters */
102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103 EXPORT_PER_CPU_SYMBOL(cpu_info);
105 atomic_t init_deasserted;
108 * Report back to the Boot Processor during boot time or to the caller processor
111 static void smp_callin(void)
114 unsigned long timeout;
117 * If waken up by an INIT in an 82489DX configuration
118 * we may get here before an INIT-deassert IPI reaches
119 * our local APIC. We have to wait for the IPI or we'll
120 * lock up on an APIC access.
122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
124 cpuid = smp_processor_id();
125 if (apic->wait_for_init_deassert && cpuid)
126 while (!atomic_read(&init_deasserted))
130 * (This works even if the APIC is not enabled.)
132 phys_id = read_apic_id();
133 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
134 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
137 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
140 * STARTUP IPIs are fragile beasts as they might sometimes
141 * trigger some glue motherboard logic. Complete APIC bus
142 * silence for 1 second, this overestimates the time the
143 * boot CPU is spending to send the up to 2 STARTUP IPIs
144 * by a factor of two. This should be enough.
148 * Waiting 2s total for startup (udelay is not yet working)
150 timeout = jiffies + 2*HZ;
151 while (time_before(jiffies, timeout)) {
153 * Has the boot CPU finished it's STARTUP sequence?
155 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
160 if (!time_before(jiffies, timeout)) {
161 panic("%s: CPU%d started up but did not get a callout!\n",
166 * the boot CPU has finished the init stage and is spinning
167 * on callin_map until we finish. We are free to set up this
168 * CPU, first the APIC. (this is probably redundant on most
172 end_local_APIC_setup();
175 * Need to setup vector mappings before we enable interrupts.
177 setup_vector_irq(smp_processor_id());
180 * Save our processor parameters. Note: this information
181 * is needed for clock calibration.
183 smp_store_cpu_info(cpuid);
187 * Update loops_per_jiffy in cpu_data. Previous call to
188 * smp_store_cpu_info() stored a value that is close but not as
189 * accurate as the value just calculated.
192 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
193 pr_debug("Stack at about %p\n", &cpuid);
196 * This must be done before setting cpu_online_mask
197 * or calling notify_cpu_starting.
199 set_cpu_sibling_map(raw_smp_processor_id());
202 notify_cpu_starting(cpuid);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid, cpu_callin_mask);
210 static int cpu0_logical_apicid;
211 static int enable_start_cpu0;
213 * Activate a secondary processor.
215 static void notrace start_secondary(void *unused)
218 * Don't put *anything* before cpu_init(), SMP booting is too
219 * fragile that we want to limit the things done here to the
220 * most necessary things.
223 x86_cpuinit.early_percpu_clock_init();
227 enable_start_cpu0 = 0;
230 /* switch away from the initial page table */
231 load_cr3(swapper_pg_dir);
235 /* otherwise gcc will move up smp_processor_id before the cpu_init */
238 * Check TSC synchronization with the BP:
240 check_tsc_sync_target();
243 * Enable the espfix hack for this CPU
245 #ifdef CONFIG_X86_ESPFIX64
250 * We need to hold vector_lock so there the set of online cpus
251 * does not change while we are assigning vectors to cpus. Holding
252 * this lock ensures we don't half assign or remove an irq from a cpu.
255 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
258 x86_platform.nmi_init();
260 /* enable local interrupts */
263 /* to prevent fake stack check failure in clock setup */
264 boot_init_stack_canary();
266 x86_cpuinit.setup_percpu_clockev();
269 cpu_startup_entry(CPUHP_ONLINE);
272 void __init smp_store_boot_cpu_info(void)
274 int id = 0; /* CPU 0 */
275 struct cpuinfo_x86 *c = &cpu_data(id);
282 * The bootstrap kernel entry code has set these up. Save them for
285 void smp_store_cpu_info(int id)
287 struct cpuinfo_x86 *c = &cpu_data(id);
292 * During boot time, CPU0 has this setup already. Save the info when
293 * bringing up AP or offlined CPU0.
295 identify_secondary_cpu(c);
299 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
301 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
303 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
304 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
305 "[node: %d != %d]. Ignoring dependency.\n",
306 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
309 #define link_mask(_m, c1, c2) \
311 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
312 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
315 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
317 if (cpu_has_topoext) {
318 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
320 if (c->phys_proc_id == o->phys_proc_id &&
321 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
322 c->compute_unit_id == o->compute_unit_id)
323 return topology_sane(c, o, "smt");
325 } else if (c->phys_proc_id == o->phys_proc_id &&
326 c->cpu_core_id == o->cpu_core_id) {
327 return topology_sane(c, o, "smt");
333 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
335 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
337 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
338 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
339 return topology_sane(c, o, "llc");
344 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
346 if (c->phys_proc_id == o->phys_proc_id) {
347 if (cpu_has(c, X86_FEATURE_AMD_DCM))
350 return topology_sane(c, o, "mc");
355 void set_cpu_sibling_map(int cpu)
357 bool has_smt = smp_num_siblings > 1;
358 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
359 struct cpuinfo_x86 *c = &cpu_data(cpu);
360 struct cpuinfo_x86 *o;
363 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
366 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
367 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
368 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
373 for_each_cpu(i, cpu_sibling_setup_mask) {
376 if ((i == cpu) || (has_smt && match_smt(c, o)))
377 link_mask(sibling, cpu, i);
379 if ((i == cpu) || (has_mp && match_llc(c, o)))
380 link_mask(llc_shared, cpu, i);
385 * This needs a separate iteration over the cpus because we rely on all
386 * cpu_sibling_mask links to be set-up.
388 for_each_cpu(i, cpu_sibling_setup_mask) {
391 if ((i == cpu) || (has_mp && match_mc(c, o))) {
392 link_mask(core, cpu, i);
395 * Does this new cpu bringup a new core?
397 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
399 * for each core in package, increment
400 * the booted_cores for this new cpu
402 if (cpumask_first(cpu_sibling_mask(i)) == i)
405 * increment the core count for all
406 * the other cpus in this package
409 cpu_data(i).booted_cores++;
410 } else if (i != cpu && !c->booted_cores)
411 c->booted_cores = cpu_data(i).booted_cores;
416 /* maps the cpu to the sched domain representing multi-core */
417 const struct cpumask *cpu_coregroup_mask(int cpu)
419 return cpu_llc_shared_mask(cpu);
422 static void impress_friends(void)
425 unsigned long bogosum = 0;
427 * Allow the user to impress friends.
429 pr_debug("Before bogomips\n");
430 for_each_possible_cpu(cpu)
431 if (cpumask_test_cpu(cpu, cpu_callout_mask))
432 bogosum += cpu_data(cpu).loops_per_jiffy;
433 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
436 (bogosum/(5000/HZ))%100);
438 pr_debug("Before bogocount - setting activated=1\n");
441 void __inquire_remote_apic(int apicid)
443 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
444 const char * const names[] = { "ID", "VERSION", "SPIV" };
448 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
450 for (i = 0; i < ARRAY_SIZE(regs); i++) {
451 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
456 status = safe_apic_wait_icr_idle();
458 pr_cont("a previous APIC delivery may have failed\n");
460 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
465 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
466 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
469 case APIC_ICR_RR_VALID:
470 status = apic_read(APIC_RRR);
471 pr_cont("%08x\n", status);
480 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
481 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
482 * won't ... remember to clear down the APIC, etc later.
485 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
487 unsigned long send_status, accept_status = 0;
491 /* Boot on the stack */
492 /* Kick the second */
493 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
495 pr_debug("Waiting for send to finish...\n");
496 send_status = safe_apic_wait_icr_idle();
499 * Give the other CPU some time to accept the IPI.
502 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
503 maxlvt = lapic_get_maxlvt();
504 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
505 apic_write(APIC_ESR, 0);
506 accept_status = (apic_read(APIC_ESR) & 0xEF);
508 pr_debug("NMI sent\n");
511 pr_err("APIC never delivered???\n");
513 pr_err("APIC delivery error (%lx)\n", accept_status);
515 return (send_status | accept_status);
519 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
521 unsigned long send_status, accept_status = 0;
522 int maxlvt, num_starts, j;
524 maxlvt = lapic_get_maxlvt();
527 * Be paranoid about clearing APIC errors.
529 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
530 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
531 apic_write(APIC_ESR, 0);
535 pr_debug("Asserting INIT\n");
538 * Turn INIT on target chip
543 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
546 pr_debug("Waiting for send to finish...\n");
547 send_status = safe_apic_wait_icr_idle();
551 pr_debug("Deasserting INIT\n");
555 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
557 pr_debug("Waiting for send to finish...\n");
558 send_status = safe_apic_wait_icr_idle();
561 atomic_set(&init_deasserted, 1);
564 * Should we send STARTUP IPIs ?
566 * Determine this based on the APIC version.
567 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
569 if (APIC_INTEGRATED(apic_version[phys_apicid]))
575 * Paravirt / VMI wants a startup IPI hook here to set up the
576 * target processor state.
578 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
582 * Run STARTUP IPI loop.
584 pr_debug("#startup loops: %d\n", num_starts);
586 for (j = 1; j <= num_starts; j++) {
587 pr_debug("Sending STARTUP #%d\n", j);
588 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
589 apic_write(APIC_ESR, 0);
591 pr_debug("After apic_write\n");
598 /* Boot on the stack */
599 /* Kick the second */
600 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
604 * Give the other CPU some time to accept the IPI.
608 pr_debug("Startup point 1\n");
610 pr_debug("Waiting for send to finish...\n");
611 send_status = safe_apic_wait_icr_idle();
614 * Give the other CPU some time to accept the IPI.
617 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
618 apic_write(APIC_ESR, 0);
619 accept_status = (apic_read(APIC_ESR) & 0xEF);
620 if (send_status || accept_status)
623 pr_debug("After Startup\n");
626 pr_err("APIC never delivered???\n");
628 pr_err("APIC delivery error (%lx)\n", accept_status);
630 return (send_status | accept_status);
633 void smp_announce(void)
635 int num_nodes = num_online_nodes();
637 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
638 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
641 /* reduce the number of lines printed when booting a large cpu count system */
642 static void announce_cpu(int cpu, int apicid)
644 static int current_node = -1;
645 int node = early_cpu_to_node(cpu);
646 static int width, node_width;
649 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
652 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
655 printk(KERN_INFO "x86: Booting SMP configuration:\n");
657 if (system_state == SYSTEM_BOOTING) {
658 if (node != current_node) {
659 if (current_node > (-1))
663 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
664 node_width - num_digits(node), " ", node);
667 /* Add padding for the BSP */
669 pr_cont("%*s", width + 1, " ");
671 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
674 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
678 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
682 cpu = smp_processor_id();
683 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
690 * Wake up AP by INIT, INIT, STARTUP sequence.
692 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
693 * boot-strap code which is not a desired behavior for waking up BSP. To
694 * void the boot-strap code, wake up CPU0 by NMI instead.
696 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
697 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
698 * We'll change this code in the future to wake up hard offlined CPU0 if
699 * real platform and request are available.
702 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
703 int *cpu0_nmi_registered)
711 * Wake up AP by INIT, INIT, STARTUP sequence.
714 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
719 * Wake up BSP by nmi.
721 * Register a NMI handler to help wake up CPU0.
723 boot_error = register_nmi_handler(NMI_LOCAL,
724 wakeup_cpu0_nmi, 0, "wake_cpu0");
727 enable_start_cpu0 = 1;
728 *cpu0_nmi_registered = 1;
729 if (apic->dest_logical == APIC_DEST_LOGICAL)
730 id = cpu0_logical_apicid;
733 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
743 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
744 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
745 * Returns zero if CPU booted OK, else error code from
746 * ->wakeup_secondary_cpu.
748 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
750 volatile u32 *trampoline_status =
751 (volatile u32 *) __va(real_mode_header->trampoline_status);
752 /* start_ip had better be page-aligned! */
753 unsigned long start_ip = real_mode_header->trampoline_start;
755 unsigned long boot_error = 0;
757 int cpu0_nmi_registered = 0;
759 /* Just in case we booted with a single CPU. */
760 alternatives_enable_smp();
762 idle->thread.sp = (unsigned long) (((struct pt_regs *)
763 (THREAD_SIZE + task_stack_page(idle))) - 1);
764 per_cpu(current_task, cpu) = idle;
767 /* Stack for startup_32 can be just as for start_secondary onwards */
770 clear_tsk_thread_flag(idle, TIF_FORK);
771 initial_gs = per_cpu_offset(cpu);
773 per_cpu(kernel_stack, cpu) =
774 (unsigned long)task_stack_page(idle) -
775 KERNEL_STACK_OFFSET + THREAD_SIZE;
776 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
777 initial_code = (unsigned long)start_secondary;
778 stack_start = idle->thread.sp;
780 /* So we see what's up */
781 announce_cpu(cpu, apicid);
784 * This grunge runs the startup process for
785 * the targeted processor.
788 atomic_set(&init_deasserted, 0);
790 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
792 pr_debug("Setting warm reset code and vector.\n");
794 smpboot_setup_warm_reset_vector(start_ip);
796 * Be paranoid about clearing APIC errors.
798 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
799 apic_write(APIC_ESR, 0);
805 * Wake up a CPU in difference cases:
806 * - Use the method in the APIC driver if it's defined
808 * - Use an INIT boot APIC message for APs or NMI for BSP.
810 if (apic->wakeup_secondary_cpu)
811 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
813 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
814 &cpu0_nmi_registered);
818 * allow APs to start initializing.
820 pr_debug("Before Callout %d\n", cpu);
821 cpumask_set_cpu(cpu, cpu_callout_mask);
822 pr_debug("After Callout %d\n", cpu);
825 * Wait 5s total for a response
827 for (timeout = 0; timeout < 50000; timeout++) {
828 if (cpumask_test_cpu(cpu, cpu_callin_mask))
829 break; /* It has booted */
832 * Allow other tasks to run while we wait for the
833 * AP to come online. This also gives a chance
834 * for the MTRR work(triggered by the AP coming online)
835 * to be completed in the stop machine context.
840 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
841 print_cpu_msr(&cpu_data(cpu));
842 pr_debug("CPU%d: has booted.\n", cpu);
845 if (*trampoline_status == 0xA5A5A5A5)
846 /* trampoline started but...? */
847 pr_err("CPU%d: Stuck ??\n", cpu);
849 /* trampoline code not run */
850 pr_err("CPU%d: Not responding\n", cpu);
851 if (apic->inquire_remote_apic)
852 apic->inquire_remote_apic(apicid);
857 /* Try to put things back the way they were before ... */
858 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
860 /* was set by do_boot_cpu() */
861 cpumask_clear_cpu(cpu, cpu_callout_mask);
863 /* was set by cpu_init() */
864 cpumask_clear_cpu(cpu, cpu_initialized_mask);
867 /* mark "stuck" area as not stuck */
868 *trampoline_status = 0;
870 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
872 * Cleanup possible dangling ends...
874 smpboot_restore_warm_reset_vector();
877 * Clean up the nmi handler. Do this after the callin and callout sync
878 * to avoid impact of possible long unregister time.
880 if (cpu0_nmi_registered)
881 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
886 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
888 int apicid = apic->cpu_present_to_apicid(cpu);
892 WARN_ON(irqs_disabled());
894 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
896 if (apicid == BAD_APICID ||
897 !physid_isset(apicid, phys_cpu_present_map) ||
898 !apic->apic_id_valid(apicid)) {
899 pr_err("%s: bad cpu %d\n", __func__, cpu);
904 * Already booted CPU?
906 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
907 pr_debug("do_boot_cpu %d Already started\n", cpu);
912 * Save current MTRR state in case it was changed since early boot
913 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
917 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
919 /* the FPU context is blank, nobody can own it */
920 __cpu_disable_lazy_restore(cpu);
922 err = do_boot_cpu(apicid, cpu, tidle);
924 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
929 * Check TSC synchronization with the AP (keep irqs disabled
932 local_irq_save(flags);
933 check_tsc_sync_source(cpu);
934 local_irq_restore(flags);
936 while (!cpu_online(cpu)) {
938 touch_nmi_watchdog();
945 * arch_disable_smp_support() - disables SMP support for x86 at runtime
947 void arch_disable_smp_support(void)
949 disable_ioapic_support();
953 * Fall back to non SMP mode after errors.
955 * RED-PEN audit/test this more. I bet there is more state messed up here.
957 static __init void disable_smp(void)
959 init_cpu_present(cpumask_of(0));
960 init_cpu_possible(cpumask_of(0));
961 smpboot_clear_io_apic_irqs();
963 if (smp_found_config)
964 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
966 physid_set_mask_of_physid(0, &phys_cpu_present_map);
967 cpumask_set_cpu(0, cpu_sibling_mask(0));
968 cpumask_set_cpu(0, cpu_core_mask(0));
972 * Various sanity checks.
974 static int __init smp_sanity_check(unsigned max_cpus)
978 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
979 if (def_to_bigsmp && nr_cpu_ids > 8) {
983 pr_warn("More than 8 CPUs detected - skipping them\n"
984 "Use CONFIG_X86_BIGSMP\n");
987 for_each_present_cpu(cpu) {
989 set_cpu_present(cpu, false);
994 for_each_possible_cpu(cpu) {
996 set_cpu_possible(cpu, false);
1004 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1005 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1006 hard_smp_processor_id());
1008 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1012 * If we couldn't find an SMP configuration at boot time,
1013 * get out of here now!
1015 if (!smp_found_config && !acpi_lapic) {
1017 pr_notice("SMP motherboard not detected\n");
1019 if (APIC_init_uniprocessor())
1020 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1025 * Should not be necessary because the MP table should list the boot
1026 * CPU too, but we do it for the sake of robustness anyway.
1028 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1029 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1030 boot_cpu_physical_apicid);
1031 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1036 * If we couldn't find a local APIC, then get out of here now!
1038 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1040 if (!disable_apic) {
1041 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1042 boot_cpu_physical_apicid);
1043 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1045 smpboot_clear_io_apic();
1046 disable_ioapic_support();
1050 verify_local_APIC();
1053 * If SMP should be disabled, then really disable it!
1056 pr_info("SMP mode deactivated\n");
1057 smpboot_clear_io_apic();
1061 bsp_end_local_APIC_setup();
1068 static void __init smp_cpu_index_default(void)
1071 struct cpuinfo_x86 *c;
1073 for_each_possible_cpu(i) {
1075 /* mark all to hotplug */
1076 c->cpu_index = nr_cpu_ids;
1081 * Prepare for SMP bootup. The MP table or ACPI has been read
1082 * earlier. Just do some sanity checking here and enable APIC mode.
1084 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1089 smp_cpu_index_default();
1092 * Setup boot CPU information
1094 smp_store_boot_cpu_info(); /* Final full version of the data */
1095 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1098 current_thread_info()->cpu = 0; /* needed? */
1099 for_each_possible_cpu(i) {
1100 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1101 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1102 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1104 set_cpu_sibling_map(0);
1107 if (smp_sanity_check(max_cpus) < 0) {
1108 pr_info("SMP disabled\n");
1113 default_setup_apic_routing();
1116 if (read_apic_id() != boot_cpu_physical_apicid) {
1117 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1118 read_apic_id(), boot_cpu_physical_apicid);
1119 /* Or can we switch back to PIC here? */
1126 * Switch from PIC to APIC mode.
1131 cpu0_logical_apicid = apic_read(APIC_LDR);
1133 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1136 * Enable IO APIC before setting up error vector
1138 if (!skip_ioapic_setup && nr_ioapics)
1141 bsp_end_local_APIC_setup();
1142 smpboot_setup_io_apic();
1144 * Set up local APIC timer on boot CPU.
1147 pr_info("CPU%d: ", 0);
1148 print_cpu_info(&cpu_data(0));
1149 x86_init.timers.setup_percpu_clockev();
1154 set_mtrr_aps_delayed_init();
1159 void arch_enable_nonboot_cpus_begin(void)
1161 set_mtrr_aps_delayed_init();
1164 void arch_enable_nonboot_cpus_end(void)
1170 * Early setup to make printk work.
1172 void __init native_smp_prepare_boot_cpu(void)
1174 int me = smp_processor_id();
1175 switch_to_new_gdt(me);
1176 /* already set me in cpu_online_mask in boot_cpu_init() */
1177 cpumask_set_cpu(me, cpu_callout_mask);
1178 per_cpu(cpu_state, me) = CPU_ONLINE;
1181 void __init native_smp_cpus_done(unsigned int max_cpus)
1183 pr_debug("Boot done\n");
1187 #ifdef CONFIG_X86_IO_APIC
1188 setup_ioapic_dest();
1193 static int __initdata setup_possible_cpus = -1;
1194 static int __init _setup_possible_cpus(char *str)
1196 get_option(&str, &setup_possible_cpus);
1199 early_param("possible_cpus", _setup_possible_cpus);
1203 * cpu_possible_mask should be static, it cannot change as cpu's
1204 * are onlined, or offlined. The reason is per-cpu data-structures
1205 * are allocated by some modules at init time, and dont expect to
1206 * do this dynamically on cpu arrival/departure.
1207 * cpu_present_mask on the other hand can change dynamically.
1208 * In case when cpu_hotplug is not compiled, then we resort to current
1209 * behaviour, which is cpu_possible == cpu_present.
1212 * Three ways to find out the number of additional hotplug CPUs:
1213 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1214 * - The user can overwrite it with possible_cpus=NUM
1215 * - Otherwise don't reserve additional CPUs.
1216 * We do this because additional CPUs waste a lot of memory.
1219 __init void prefill_possible_map(void)
1223 /* no processor from mptable or madt */
1224 if (!num_processors)
1227 i = setup_max_cpus ?: 1;
1228 if (setup_possible_cpus == -1) {
1229 possible = num_processors;
1230 #ifdef CONFIG_HOTPLUG_CPU
1232 possible += disabled_cpus;
1238 possible = setup_possible_cpus;
1240 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1242 /* nr_cpu_ids could be reduced via nr_cpus= */
1243 if (possible > nr_cpu_ids) {
1244 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1245 possible, nr_cpu_ids);
1246 possible = nr_cpu_ids;
1249 #ifdef CONFIG_HOTPLUG_CPU
1250 if (!setup_max_cpus)
1253 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1254 possible, setup_max_cpus);
1258 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1259 possible, max_t(int, possible - num_processors, 0));
1261 for (i = 0; i < possible; i++)
1262 set_cpu_possible(i, true);
1263 for (; i < NR_CPUS; i++)
1264 set_cpu_possible(i, false);
1266 nr_cpu_ids = possible;
1269 #ifdef CONFIG_HOTPLUG_CPU
1271 static void remove_siblinginfo(int cpu)
1274 struct cpuinfo_x86 *c = &cpu_data(cpu);
1276 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1277 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1279 * last thread sibling in this cpu core going down
1281 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1282 cpu_data(sibling).booted_cores--;
1285 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1286 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1287 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1288 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1289 cpumask_clear(cpu_llc_shared_mask(cpu));
1290 cpumask_clear(cpu_sibling_mask(cpu));
1291 cpumask_clear(cpu_core_mask(cpu));
1292 c->phys_proc_id = 0;
1294 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1297 static void __ref remove_cpu_from_maps(int cpu)
1299 set_cpu_online(cpu, false);
1300 cpumask_clear_cpu(cpu, cpu_callout_mask);
1301 cpumask_clear_cpu(cpu, cpu_callin_mask);
1302 /* was set by cpu_init() */
1303 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1304 numa_remove_cpu(cpu);
1307 void cpu_disable_common(void)
1309 int cpu = smp_processor_id();
1311 remove_siblinginfo(cpu);
1313 /* It's now safe to remove this processor from the online map */
1315 remove_cpu_from_maps(cpu);
1316 unlock_vector_lock();
1320 int native_cpu_disable(void)
1324 ret = check_irq_vectors_for_cpu_disable();
1330 cpu_disable_common();
1334 void native_cpu_die(unsigned int cpu)
1336 /* We don't do anything here: idle task is faking death itself. */
1339 for (i = 0; i < 10; i++) {
1340 /* They ack this in play_dead by setting CPU_DEAD */
1341 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1342 if (system_state == SYSTEM_RUNNING)
1343 pr_info("CPU %u is now offline\n", cpu);
1348 pr_err("CPU %u didn't die...\n", cpu);
1351 void play_dead_common(void)
1354 reset_lazy_tlbstate();
1355 amd_e400_remove_cpu(raw_smp_processor_id());
1359 __this_cpu_write(cpu_state, CPU_DEAD);
1362 * With physical CPU hotplug, we should halt the cpu
1364 local_irq_disable();
1367 static bool wakeup_cpu0(void)
1369 if (smp_processor_id() == 0 && enable_start_cpu0)
1376 * We need to flush the caches before going to sleep, lest we have
1377 * dirty data in our caches when we come back up.
1379 static inline void mwait_play_dead(void)
1381 unsigned int eax, ebx, ecx, edx;
1382 unsigned int highest_cstate = 0;
1383 unsigned int highest_subcstate = 0;
1387 if (!this_cpu_has(X86_FEATURE_MWAIT))
1389 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1391 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1394 eax = CPUID_MWAIT_LEAF;
1396 native_cpuid(&eax, &ebx, &ecx, &edx);
1399 * eax will be 0 if EDX enumeration is not valid.
1400 * Initialized below to cstate, sub_cstate value when EDX is valid.
1402 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1405 edx >>= MWAIT_SUBSTATE_SIZE;
1406 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1407 if (edx & MWAIT_SUBSTATE_MASK) {
1409 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1412 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1413 (highest_subcstate - 1);
1417 * This should be a memory location in a cache line which is
1418 * unlikely to be touched by other processors. The actual
1419 * content is immaterial as it is not actually modified in any way.
1421 mwait_ptr = ¤t_thread_info()->flags;
1427 * The CLFLUSH is a workaround for erratum AAI65 for
1428 * the Xeon 7400 series. It's not clear it is actually
1429 * needed, but it should be harmless in either case.
1430 * The WBINVD is insufficient due to the spurious-wakeup
1431 * case where we return around the loop.
1436 __monitor(mwait_ptr, 0, 0);
1440 * If NMI wants to wake up CPU0, start CPU0.
1447 static inline void hlt_play_dead(void)
1449 if (__this_cpu_read(cpu_info.x86) >= 4)
1455 * If NMI wants to wake up CPU0, start CPU0.
1462 void native_play_dead(void)
1465 tboot_shutdown(TB_SHUTDOWN_WFS);
1467 mwait_play_dead(); /* Only returns on failure */
1468 if (cpuidle_play_dead())
1472 #else /* ... !CONFIG_HOTPLUG_CPU */
1473 int native_cpu_disable(void)
1478 void native_cpu_die(unsigned int cpu)
1480 /* We said "no" in __cpu_disable */
1484 void native_play_dead(void)