arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 #define KVM_X2APIC_CID_BITS 0
 136
 137 static void recalculate_apic_map(struct kvm *kvm)
 138 {
 139         struct kvm_apic_map *new, *old = NULL;
 140         struct kvm_vcpu *vcpu;
 141         int i;
 142
 143         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 144
 145         mutex_lock(&kvm->arch.apic_map_lock);
 146
 147         if (!new)
 148                 goto out;
 149
 150         new->ldr_bits = 8;
 151         /* flat mode is default */
 152         new->cid_shift = 8;
 153         new->cid_mask = 0;
 154         new->lid_mask = 0xff;
 155         new->broadcast = APIC_BROADCAST;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 struct kvm_lapic *apic = vcpu->arch.apic;
 159                 u16 cid, lid;
 160                 u32 ldr;
 161
 162                 if (!kvm_apic_present(vcpu))
 163                         continue;
 164
 165                 /*
 166                  * All APICs have to be configured in the same mode by an OS.
 167                  * We take advatage of this while building logical id loockup
 168                  * table. After reset APICs are in xapic/flat mode, so if we
 169                  * find apic with different setting we assume this is the mode
 170                  * OS wants all apics to be in; build lookup table accordingly.
 171                  */
 172                 if (apic_x2apic_mode(apic)) {
 173                         new->ldr_bits = 32;
 174                         new->cid_shift = 16;
 175                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 176                         new->lid_mask = 0xffff;
 177                         new->broadcast = X2APIC_BROADCAST;
 178                 } else if (kvm_apic_sw_enabled(apic) &&
 179                                 !new->cid_mask /* flat mode */ &&
 180                                 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
 181                         new->cid_shift = 4;
 182                         new->cid_mask = 0xf;
 183                         new->lid_mask = 0xf;
 184                 }
 185
 186                 new->phys_map[kvm_apic_id(apic)] = apic;
 187
 188                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 189                 cid = apic_cluster_id(new, ldr);
 190                 lid = apic_logical_id(new, ldr);
 191
 192                 if (lid)
 193                         new->logical_map[cid][ffs(lid) - 1] = apic;
 194         }
 195 out:
 196         old = rcu_dereference_protected(kvm->arch.apic_map,
 197                         lockdep_is_held(&kvm->arch.apic_map_lock));
 198         rcu_assign_pointer(kvm->arch.apic_map, new);
 199         mutex_unlock(&kvm->arch.apic_map_lock);
 200
 201         if (old)
 202                 kfree_rcu(old, rcu);
 203
 204         kvm_vcpu_request_scan_ioapic(kvm);
 205 }
 206
 207 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 208 {
 209         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 210
 211         apic_set_reg(apic, APIC_SPIV, val);
 212
 213         if (enabled != apic->sw_enabled) {
 214                 apic->sw_enabled = enabled;
 215                 if (enabled) {
 216                         static_key_slow_dec_deferred(&apic_sw_disabled);
 217                         recalculate_apic_map(apic->vcpu->kvm);
 218                 } else
 219                         static_key_slow_inc(&apic_sw_disabled.key);
 220         }
 221 }
 222
 223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 224 {
 225         apic_set_reg(apic, APIC_ID, id << 24);
 226         recalculate_apic_map(apic->vcpu->kvm);
 227 }
 228
 229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 230 {
 231         apic_set_reg(apic, APIC_LDR, id);
 232         recalculate_apic_map(apic->vcpu->kvm);
 233 }
 234
 235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 236 {
 237         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 238 }
 239
 240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 241 {
 242         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 243 }
 244
 245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 246 {
 247         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 248 }
 249
 250 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 251 {
 252         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 253 }
 254
 255 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 256 {
 257         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 258 }
 259
 260 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 261 {
 262         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 263 }
 264
 265 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 266 {
 267         struct kvm_lapic *apic = vcpu->arch.apic;
 268         struct kvm_cpuid_entry2 *feat;
 269         u32 v = APIC_VERSION;
 270
 271         if (!kvm_vcpu_has_lapic(vcpu))
 272                 return;
 273
 274         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 275         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 276                 v |= APIC_LVR_DIRECTED_EOI;
 277         apic_set_reg(apic, APIC_LVR, v);
 278 }
 279
 280 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 281         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 282         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 283         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 284         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 285         LVT_MASK                /* LVTERR */
 286 };
 287
 288 static int find_highest_vector(void *bitmap)
 289 {
 290         int vec;
 291         u32 *reg;
 292
 293         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 294              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 295                 reg = bitmap + REG_POS(vec);
 296                 if (*reg)
 297                         return fls(*reg) - 1 + vec;
 298         }
 299
 300         return -1;
 301 }
 302
 303 static u8 count_vectors(void *bitmap)
 304 {
 305         int vec;
 306         u32 *reg;
 307         u8 count = 0;
 308
 309         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 310                 reg = bitmap + REG_POS(vec);
 311                 count += hweight32(*reg);
 312         }
 313
 314         return count;
 315 }
 316
 317 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 318 {
 319         u32 i, pir_val;
 320         struct kvm_lapic *apic = vcpu->arch.apic;
 321
 322         for (i = 0; i <= 7; i++) {
 323                 pir_val = xchg(&pir[i], 0);
 324                 if (pir_val)
 325                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 326         }
 327 }
 328 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 329
 330 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 331 {
 332         apic->irr_pending = true;
 333         apic_set_vector(vec, apic->regs + APIC_IRR);
 334 }
 335
 336 static inline int apic_search_irr(struct kvm_lapic *apic)
 337 {
 338         return find_highest_vector(apic->regs + APIC_IRR);
 339 }
 340
 341 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 342 {
 343         int result;
 344
 345         /*
 346          * Note that irr_pending is just a hint. It will be always
 347          * true with virtual interrupt delivery enabled.
 348          */
 349         if (!apic->irr_pending)
 350                 return -1;
 351
 352         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 353         result = apic_search_irr(apic);
 354         ASSERT(result == -1 || result >= 16);
 355
 356         return result;
 357 }
 358
 359 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 360 {
 361         struct kvm_vcpu *vcpu;
 362
 363         vcpu = apic->vcpu;
 364
 365         apic_clear_vector(vec, apic->regs + APIC_IRR);
 366         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 367                 /* try to update RVI */
 368                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 369         else {
 370                 vec = apic_search_irr(apic);
 371                 apic->irr_pending = (vec != -1);
 372         }
 373 }
 374
 375 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 376 {
 377         struct kvm_vcpu *vcpu;
 378
 379         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 380                 return;
 381
 382         vcpu = apic->vcpu;
 383
 384         /*
 385          * With APIC virtualization enabled, all caching is disabled
 386          * because the processor can modify ISR under the hood.  Instead
 387          * just set SVI.
 388          */
 389         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 390                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 391         else {
 392                 ++apic->isr_count;
 393                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 394                 /*
 395                  * ISR (in service register) bit is set when injecting an interrupt.
 396                  * The highest vector is injected. Thus the latest bit set matches
 397                  * the highest bit in ISR.
 398                  */
 399                 apic->highest_isr_cache = vec;
 400         }
 401 }
 402
 403 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 404 {
 405         int result;
 406
 407         /*
 408          * Note that isr_count is always 1, and highest_isr_cache
 409          * is always -1, with APIC virtualization enabled.
 410          */
 411         if (!apic->isr_count)
 412                 return -1;
 413         if (likely(apic->highest_isr_cache != -1))
 414                 return apic->highest_isr_cache;
 415
 416         result = find_highest_vector(apic->regs + APIC_ISR);
 417         ASSERT(result == -1 || result >= 16);
 418
 419         return result;
 420 }
 421
 422 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 423 {
 424         struct kvm_vcpu *vcpu;
 425         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 426                 return;
 427
 428         vcpu = apic->vcpu;
 429
 430         /*
 431          * We do get here for APIC virtualization enabled if the guest
 432          * uses the Hyper-V APIC enlightenment.  In this case we may need
 433          * to trigger a new interrupt delivery by writing the SVI field;
 434          * on the other hand isr_count and highest_isr_cache are unused
 435          * and must be left alone.
 436          */
 437         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 438                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 439                                                apic_find_highest_isr(apic));
 440         else {
 441                 --apic->isr_count;
 442                 BUG_ON(apic->isr_count < 0);
 443                 apic->highest_isr_cache = -1;
 444         }
 445 }
 446
 447 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 448 {
 449         int highest_irr;
 450
 451         /* This may race with setting of irr in __apic_accept_irq() and
 452          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 453          * will cause vmexit immediately and the value will be recalculated
 454          * on the next vmentry.
 455          */
 456         if (!kvm_vcpu_has_lapic(vcpu))
 457                 return 0;
 458         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 459
 460         return highest_irr;
 461 }
 462
 463 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 464                              int vector, int level, int trig_mode,
 465                              unsigned long *dest_map);
 466
 467 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 468                 unsigned long *dest_map)
 469 {
 470         struct kvm_lapic *apic = vcpu->arch.apic;
 471
 472         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 473                         irq->level, irq->trig_mode, dest_map);
 474 }
 475
 476 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 477 {
 478
 479         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 480                                       sizeof(val));
 481 }
 482
 483 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 484 {
 485
 486         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 487                                       sizeof(*val));
 488 }
 489
 490 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 491 {
 492         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 493 }
 494
 495 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 496 {
 497         u8 val;
 498         if (pv_eoi_get_user(vcpu, &val) < 0)
 499                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 500                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 501         return val & 0x1;
 502 }
 503
 504 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 505 {
 506         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 507                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 508                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 509                 return;
 510         }
 511         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 512 }
 513
 514 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 515 {
 516         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 517                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 518                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 519                 return;
 520         }
 521         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 522 }
 523
 524 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 525 {
 526         struct kvm_lapic *apic = vcpu->arch.apic;
 527         int i;
 528
 529         for (i = 0; i < 8; i++)
 530                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 531 }
 532
 533 static void apic_update_ppr(struct kvm_lapic *apic)
 534 {
 535         u32 tpr, isrv, ppr, old_ppr;
 536         int isr;
 537
 538         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 539         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 540         isr = apic_find_highest_isr(apic);
 541         isrv = (isr != -1) ? isr : 0;
 542
 543         if ((tpr & 0xf0) >= (isrv & 0xf0))
 544                 ppr = tpr & 0xff;
 545         else
 546                 ppr = isrv & 0xf0;
 547
 548         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 549                    apic, ppr, isr, isrv);
 550
 551         if (old_ppr != ppr) {
 552                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 553                 if (ppr < old_ppr)
 554                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 555         }
 556 }
 557
 558 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 559 {
 560         apic_set_reg(apic, APIC_TASKPRI, tpr);
 561         apic_update_ppr(apic);
 562 }
 563
 564 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 565 {
 566         return dest == (apic_x2apic_mode(apic) ?
 567                         X2APIC_BROADCAST : APIC_BROADCAST);
 568 }
 569
 570 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 571 {
 572         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 573 }
 574
 575 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 576 {
 577         int result = 0;
 578         u32 logical_id;
 579
 580         if (kvm_apic_broadcast(apic, mda))
 581                 return 1;
 582
 583         if (apic_x2apic_mode(apic)) {
 584                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 585                 return logical_id & mda;
 586         }
 587
 588         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 589
 590         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 591         case APIC_DFR_FLAT:
 592                 if (logical_id & mda)
 593                         result = 1;
 594                 break;
 595         case APIC_DFR_CLUSTER:
 596                 if (((logical_id >> 4) == (mda >> 0x4))
 597                     && (logical_id & mda & 0xf))
 598                         result = 1;
 599                 break;
 600         default:
 601                 apic_debug("Bad DFR vcpu %d: %08x\n",
 602                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 603                 break;
 604         }
 605
 606         return result;
 607 }
 608
 609 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 610                            int short_hand, unsigned int dest, int dest_mode)
 611 {
 612         int result = 0;
 613         struct kvm_lapic *target = vcpu->arch.apic;
 614
 615         apic_debug("target %p, source %p, dest 0x%x, "
 616                    "dest_mode 0x%x, short_hand 0x%x\n",
 617                    target, source, dest, dest_mode, short_hand);
 618
 619         ASSERT(target);
 620         switch (short_hand) {
 621         case APIC_DEST_NOSHORT:
 622                 if (dest_mode == 0)
 623                         /* Physical mode. */
 624                         result = kvm_apic_match_physical_addr(target, dest);
 625                 else
 626                         /* Logical mode. */
 627                         result = kvm_apic_match_logical_addr(target, dest);
 628                 break;
 629         case APIC_DEST_SELF:
 630                 result = (target == source);
 631                 break;
 632         case APIC_DEST_ALLINC:
 633                 result = 1;
 634                 break;
 635         case APIC_DEST_ALLBUT:
 636                 result = (target != source);
 637                 break;
 638         default:
 639                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 640                            short_hand);
 641                 break;
 642         }
 643
 644         return result;
 645 }
 646
 647 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 648                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 649 {
 650         struct kvm_apic_map *map;
 651         unsigned long bitmap = 1;
 652         struct kvm_lapic **dst;
 653         int i;
 654         bool ret = false;
 655
 656         *r = -1;
 657
 658         if (irq->shorthand == APIC_DEST_SELF) {
 659                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 660                 return true;
 661         }
 662
 663         if (irq->shorthand)
 664                 return false;
 665
 666         rcu_read_lock();
 667         map = rcu_dereference(kvm->arch.apic_map);
 668
 669         if (!map)
 670                 goto out;
 671
 672         if (irq->dest_id == map->broadcast)
 673                 goto out;
 674
 675         if (irq->dest_mode == 0) { /* physical mode */
 676                 if (irq->delivery_mode == APIC_DM_LOWEST)
 677                         goto out;
 678                 dst = &map->phys_map[irq->dest_id & 0xff];
 679         } else {
 680                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 681
 682                 dst = map->logical_map[apic_cluster_id(map, mda)];
 683
 684                 bitmap = apic_logical_id(map, mda);
 685
 686                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 687                         int l = -1;
 688                         for_each_set_bit(i, &bitmap, 16) {
 689                                 if (!dst[i])
 690                                         continue;
 691                                 if (l < 0)
 692                                         l = i;
 693                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 694                                         l = i;
 695                         }
 696
 697                         bitmap = (l >= 0) ? 1 << l : 0;
 698                 }
 699         }
 700
 701         for_each_set_bit(i, &bitmap, 16) {
 702                 if (!dst[i])
 703                         continue;
 704                 if (*r < 0)
 705                         *r = 0;
 706                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 707         }
 708
 709         ret = true;
 710 out:
 711         rcu_read_unlock();
 712         return ret;
 713 }
 714
 715 /*
 716  * Add a pending IRQ into lapic.
 717  * Return 1 if successfully added and 0 if discarded.
 718  */
 719 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 720                              int vector, int level, int trig_mode,
 721                              unsigned long *dest_map)
 722 {
 723         int result = 0;
 724         struct kvm_vcpu *vcpu = apic->vcpu;
 725
 726         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 727                                   trig_mode, vector);
 728         switch (delivery_mode) {
 729         case APIC_DM_LOWEST:
 730                 vcpu->arch.apic_arb_prio++;
 731         case APIC_DM_FIXED:
 732                 /* FIXME add logic for vcpu on reset */
 733                 if (unlikely(!apic_enabled(apic)))
 734                         break;
 735
 736                 result = 1;
 737
 738                 if (dest_map)
 739                         __set_bit(vcpu->vcpu_id, dest_map);
 740
 741                 if (kvm_x86_ops->deliver_posted_interrupt)
 742                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 743                 else {
 744                         apic_set_irr(vector, apic);
 745
 746                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 747                         kvm_vcpu_kick(vcpu);
 748                 }
 749                 break;
 750
 751         case APIC_DM_REMRD:
 752                 result = 1;
 753                 vcpu->arch.pv.pv_unhalted = 1;
 754                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 755                 kvm_vcpu_kick(vcpu);
 756                 break;
 757
 758         case APIC_DM_SMI:
 759                 apic_debug("Ignoring guest SMI\n");
 760                 break;
 761
 762         case APIC_DM_NMI:
 763                 result = 1;
 764                 kvm_inject_nmi(vcpu);
 765                 kvm_vcpu_kick(vcpu);
 766                 break;
 767
 768         case APIC_DM_INIT:
 769                 if (!trig_mode || level) {
 770                         result = 1;
 771                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 772                         apic->pending_events = (1UL << KVM_APIC_INIT);
 773                         /* make sure pending_events is visible before sending
 774                          * the request */
 775                         smp_wmb();
 776                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 777                         kvm_vcpu_kick(vcpu);
 778                 } else {
 779                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 780                                    vcpu->vcpu_id);
 781                 }
 782                 break;
 783
 784         case APIC_DM_STARTUP:
 785                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 786                            vcpu->vcpu_id, vector);
 787                 result = 1;
 788                 apic->sipi_vector = vector;
 789                 /* make sure sipi_vector is visible for the receiver */
 790                 smp_wmb();
 791                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 792                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 793                 kvm_vcpu_kick(vcpu);
 794                 break;
 795
 796         case APIC_DM_EXTINT:
 797                 /*
 798                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 799                  * before NMI watchdog was enabled. Already handled by
 800                  * kvm_apic_accept_pic_intr().
 801                  */
 802                 break;
 803
 804         default:
 805                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 806                        delivery_mode);
 807                 break;
 808         }
 809         return result;
 810 }
 811
 812 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 813 {
 814         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 815 }
 816
 817 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 818 {
 819         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 820             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 821                 int trigger_mode;
 822                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 823                         trigger_mode = IOAPIC_LEVEL_TRIG;
 824                 else
 825                         trigger_mode = IOAPIC_EDGE_TRIG;
 826                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 827         }
 828 }
 829
 830 static int apic_set_eoi(struct kvm_lapic *apic)
 831 {
 832         int vector = apic_find_highest_isr(apic);
 833
 834         trace_kvm_eoi(apic, vector);
 835
 836         /*
 837          * Not every write EOI will has corresponding ISR,
 838          * one example is when Kernel check timer on setup_IO_APIC
 839          */
 840         if (vector == -1)
 841                 return vector;
 842
 843         apic_clear_isr(vector, apic);
 844         apic_update_ppr(apic);
 845
 846         kvm_ioapic_send_eoi(apic, vector);
 847         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 848         return vector;
 849 }
 850
 851 /*
 852  * this interface assumes a trap-like exit, which has already finished
 853  * desired side effect including vISR and vPPR update.
 854  */
 855 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 856 {
 857         struct kvm_lapic *apic = vcpu->arch.apic;
 858
 859         trace_kvm_eoi(apic, vector);
 860
 861         kvm_ioapic_send_eoi(apic, vector);
 862         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 863 }
 864 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 865
 866 static void apic_send_ipi(struct kvm_lapic *apic)
 867 {
 868         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 869         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 870         struct kvm_lapic_irq irq;
 871
 872         irq.vector = icr_low & APIC_VECTOR_MASK;
 873         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 874         irq.dest_mode = icr_low & APIC_DEST_MASK;
 875         irq.level = icr_low & APIC_INT_ASSERT;
 876         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 877         irq.shorthand = icr_low & APIC_SHORT_MASK;
 878         if (apic_x2apic_mode(apic))
 879                 irq.dest_id = icr_high;
 880         else
 881                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 882
 883         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 884
 885         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 886                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 887                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 888                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 889                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 890                    irq.vector);
 891
 892         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 893 }
 894
 895 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 896 {
 897         ktime_t remaining;
 898         s64 ns;
 899         u32 tmcct;
 900
 901         ASSERT(apic != NULL);
 902
 903         /* if initial count is 0, current count should also be 0 */
 904         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 905                 apic->lapic_timer.period == 0)
 906                 return 0;
 907
 908         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 909         if (ktime_to_ns(remaining) < 0)
 910                 remaining = ktime_set(0, 0);
 911
 912         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 913         tmcct = div64_u64(ns,
 914                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 915
 916         return tmcct;
 917 }
 918
 919 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 920 {
 921         struct kvm_vcpu *vcpu = apic->vcpu;
 922         struct kvm_run *run = vcpu->run;
 923
 924         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 925         run->tpr_access.rip = kvm_rip_read(vcpu);
 926         run->tpr_access.is_write = write;
 927 }
 928
 929 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 930 {
 931         if (apic->vcpu->arch.tpr_access_reporting)
 932                 __report_tpr_access(apic, write);
 933 }
 934
 935 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 936 {
 937         u32 val = 0;
 938
 939         if (offset >= LAPIC_MMIO_LENGTH)
 940                 return 0;
 941
 942         switch (offset) {
 943         case APIC_ID:
 944                 if (apic_x2apic_mode(apic))
 945                         val = kvm_apic_id(apic);
 946                 else
 947                         val = kvm_apic_id(apic) << 24;
 948                 break;
 949         case APIC_ARBPRI:
 950                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 951                 break;
 952
 953         case APIC_TMCCT:        /* Timer CCR */
 954                 if (apic_lvtt_tscdeadline(apic))
 955                         return 0;
 956
 957                 val = apic_get_tmcct(apic);
 958                 break;
 959         case APIC_PROCPRI:
 960                 apic_update_ppr(apic);
 961                 val = kvm_apic_get_reg(apic, offset);
 962                 break;
 963         case APIC_TASKPRI:
 964                 report_tpr_access(apic, false);
 965                 /* fall thru */
 966         default:
 967                 val = kvm_apic_get_reg(apic, offset);
 968                 break;
 969         }
 970
 971         return val;
 972 }
 973
 974 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 975 {
 976         return container_of(dev, struct kvm_lapic, dev);
 977 }
 978
 979 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 980                 void *data)
 981 {
 982         unsigned char alignment = offset & 0xf;
 983         u32 result;
 984         /* this bitmask has a bit cleared for each reserved register */
 985         static const u64 rmask = 0x43ff01ffffffe70cULL;
 986
 987         if ((alignment + len) > 4) {
 988                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 989                            offset, len);
 990                 return 1;
 991         }
 992
 993         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 994                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 995                            offset);
 996                 return 1;
 997         }
 998
 999         result = __apic_read(apic, offset & ~0xf);
1000
1001         trace_kvm_apic_read(offset, result);
1002
1003         switch (len) {
1004         case 1:
1005         case 2:
1006         case 4:
1007                 memcpy(data, (char *)&result + alignment, len);
1008                 break;
1009         default:
1010                 printk(KERN_ERR "Local APIC read with len = %x, "
1011                        "should be 1,2, or 4 instead\n", len);
1012                 break;
1013         }
1014         return 0;
1015 }
1016
1017 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1018 {
1019         return kvm_apic_hw_enabled(apic) &&
1020             addr >= apic->base_address &&
1021             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1022 }
1023
1024 static int apic_mmio_read(struct kvm_io_device *this,
1025                            gpa_t address, int len, void *data)
1026 {
1027         struct kvm_lapic *apic = to_lapic(this);
1028         u32 offset = address - apic->base_address;
1029
1030         if (!apic_mmio_in_range(apic, address))
1031                 return -EOPNOTSUPP;
1032
1033         apic_reg_read(apic, offset, len, data);
1034
1035         return 0;
1036 }
1037
1038 static void update_divide_count(struct kvm_lapic *apic)
1039 {
1040         u32 tmp1, tmp2, tdcr;
1041
1042         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1043         tmp1 = tdcr & 0xf;
1044         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1045         apic->divide_count = 0x1 << (tmp2 & 0x7);
1046
1047         apic_debug("timer divide count is 0x%x\n",
1048                                    apic->divide_count);
1049 }
1050
1051 static void apic_timer_expired(struct kvm_lapic *apic)
1052 {
1053         struct kvm_vcpu *vcpu = apic->vcpu;
1054         wait_queue_head_t *q = &vcpu->wq;
1055
1056         /*
1057          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1058          * vcpu_enter_guest.
1059          */
1060         if (atomic_read(&apic->lapic_timer.pending))
1061                 return;
1062
1063         atomic_inc(&apic->lapic_timer.pending);
1064         /* FIXME: this code should not know anything about vcpus */
1065         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1066
1067         if (waitqueue_active(q))
1068                 wake_up_interruptible(q);
1069 }
1070
1071 static void start_apic_timer(struct kvm_lapic *apic)
1072 {
1073         ktime_t now;
1074         atomic_set(&apic->lapic_timer.pending, 0);
1075
1076         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1077                 /* lapic timer in oneshot or periodic mode */
1078                 now = apic->lapic_timer.timer.base->get_time();
1079                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1080                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1081
1082                 if (!apic->lapic_timer.period)
1083                         return;
1084                 /*
1085                  * Do not allow the guest to program periodic timers with small
1086                  * interval, since the hrtimers are not throttled by the host
1087                  * scheduler.
1088                  */
1089                 if (apic_lvtt_period(apic)) {
1090                         s64 min_period = min_timer_period_us * 1000LL;
1091
1092                         if (apic->lapic_timer.period < min_period) {
1093                                 pr_info_ratelimited(
1094                                     "kvm: vcpu %i: requested %lld ns "
1095                                     "lapic timer period limited to %lld ns\n",
1096                                     apic->vcpu->vcpu_id,
1097                                     apic->lapic_timer.period, min_period);
1098                                 apic->lapic_timer.period = min_period;
1099                         }
1100                 }
1101
1102                 hrtimer_start(&apic->lapic_timer.timer,
1103                               ktime_add_ns(now, apic->lapic_timer.period),
1104                               HRTIMER_MODE_ABS);
1105
1106                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1107                            PRIx64 ", "
1108                            "timer initial count 0x%x, period %lldns, "
1109                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1110                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1111                            kvm_apic_get_reg(apic, APIC_TMICT),
1112                            apic->lapic_timer.period,
1113                            ktime_to_ns(ktime_add_ns(now,
1114                                         apic->lapic_timer.period)));
1115         } else if (apic_lvtt_tscdeadline(apic)) {
1116                 /* lapic timer in tsc deadline mode */
1117                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1118                 u64 ns = 0;
1119                 struct kvm_vcpu *vcpu = apic->vcpu;
1120                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1121                 unsigned long flags;
1122
1123                 if (unlikely(!tscdeadline || !this_tsc_khz))
1124                         return;
1125
1126                 local_irq_save(flags);
1127
1128                 now = apic->lapic_timer.timer.base->get_time();
1129                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1130                 if (likely(tscdeadline > guest_tsc)) {
1131                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1132                         do_div(ns, this_tsc_khz);
1133                         hrtimer_start(&apic->lapic_timer.timer,
1134                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1135                 } else
1136                         apic_timer_expired(apic);
1137
1138                 local_irq_restore(flags);
1139         }
1140 }
1141
1142 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1143 {
1144         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1145
1146         if (apic_lvt_nmi_mode(lvt0_val)) {
1147                 if (!nmi_wd_enabled) {
1148                         apic_debug("Receive NMI setting on APIC_LVT0 "
1149                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1150                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1151                 }
1152         } else if (nmi_wd_enabled)
1153                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1154 }
1155
1156 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1157 {
1158         int ret = 0;
1159
1160         trace_kvm_apic_write(reg, val);
1161
1162         switch (reg) {
1163         case APIC_ID:           /* Local APIC ID */
1164                 if (!apic_x2apic_mode(apic))
1165                         kvm_apic_set_id(apic, val >> 24);
1166                 else
1167                         ret = 1;
1168                 break;
1169
1170         case APIC_TASKPRI:
1171                 report_tpr_access(apic, true);
1172                 apic_set_tpr(apic, val & 0xff);
1173                 break;
1174
1175         case APIC_EOI:
1176                 apic_set_eoi(apic);
1177                 break;
1178
1179         case APIC_LDR:
1180                 if (!apic_x2apic_mode(apic))
1181                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1182                 else
1183                         ret = 1;
1184                 break;
1185
1186         case APIC_DFR:
1187                 if (!apic_x2apic_mode(apic)) {
1188                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1189                         recalculate_apic_map(apic->vcpu->kvm);
1190                 } else
1191                         ret = 1;
1192                 break;
1193
1194         case APIC_SPIV: {
1195                 u32 mask = 0x3ff;
1196                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1197                         mask |= APIC_SPIV_DIRECTED_EOI;
1198                 apic_set_spiv(apic, val & mask);
1199                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1200                         int i;
1201                         u32 lvt_val;
1202
1203                         for (i = 0; i < APIC_LVT_NUM; i++) {
1204                                 lvt_val = kvm_apic_get_reg(apic,
1205                                                        APIC_LVTT + 0x10 * i);
1206                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1207                                              lvt_val | APIC_LVT_MASKED);
1208                         }
1209                         atomic_set(&apic->lapic_timer.pending, 0);
1210
1211                 }
1212                 break;
1213         }
1214         case APIC_ICR:
1215                 /* No delay here, so we always clear the pending bit */
1216                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1217                 apic_send_ipi(apic);
1218                 break;
1219
1220         case APIC_ICR2:
1221                 if (!apic_x2apic_mode(apic))
1222                         val &= 0xff000000;
1223                 apic_set_reg(apic, APIC_ICR2, val);
1224                 break;
1225
1226         case APIC_LVT0:
1227                 apic_manage_nmi_watchdog(apic, val);
1228         case APIC_LVTTHMR:
1229         case APIC_LVTPC:
1230         case APIC_LVT1:
1231         case APIC_LVTERR:
1232                 /* TODO: Check vector */
1233                 if (!kvm_apic_sw_enabled(apic))
1234                         val |= APIC_LVT_MASKED;
1235
1236                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1237                 apic_set_reg(apic, reg, val);
1238
1239                 break;
1240
1241         case APIC_LVTT: {
1242                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1243
1244                 if (apic->lapic_timer.timer_mode != timer_mode) {
1245                         apic->lapic_timer.timer_mode = timer_mode;
1246                         hrtimer_cancel(&apic->lapic_timer.timer);
1247                 }
1248
1249                 if (!kvm_apic_sw_enabled(apic))
1250                         val |= APIC_LVT_MASKED;
1251                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1252                 apic_set_reg(apic, APIC_LVTT, val);
1253                 break;
1254         }
1255
1256         case APIC_TMICT:
1257                 if (apic_lvtt_tscdeadline(apic))
1258                         break;
1259
1260                 hrtimer_cancel(&apic->lapic_timer.timer);
1261                 apic_set_reg(apic, APIC_TMICT, val);
1262                 start_apic_timer(apic);
1263                 break;
1264
1265         case APIC_TDCR:
1266                 if (val & 4)
1267                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1268                 apic_set_reg(apic, APIC_TDCR, val);
1269                 update_divide_count(apic);
1270                 break;
1271
1272         case APIC_ESR:
1273                 if (apic_x2apic_mode(apic) && val != 0) {
1274                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1275                         ret = 1;
1276                 }
1277                 break;
1278
1279         case APIC_SELF_IPI:
1280                 if (apic_x2apic_mode(apic)) {
1281                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1282                 } else
1283                         ret = 1;
1284                 break;
1285         default:
1286                 ret = 1;
1287                 break;
1288         }
1289         if (ret)
1290                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1291         return ret;
1292 }
1293
1294 static int apic_mmio_write(struct kvm_io_device *this,
1295                             gpa_t address, int len, const void *data)
1296 {
1297         struct kvm_lapic *apic = to_lapic(this);
1298         unsigned int offset = address - apic->base_address;
1299         u32 val;
1300
1301         if (!apic_mmio_in_range(apic, address))
1302                 return -EOPNOTSUPP;
1303
1304         /*
1305          * APIC register must be aligned on 128-bits boundary.
1306          * 32/64/128 bits registers must be accessed thru 32 bits.
1307          * Refer SDM 8.4.1
1308          */
1309         if (len != 4 || (offset & 0xf)) {
1310                 /* Don't shout loud, $infamous_os would cause only noise. */
1311                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1312                 return 0;
1313         }
1314
1315         val = *(u32*)data;
1316
1317         /* too common printing */
1318         if (offset != APIC_EOI)
1319                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1320                            "0x%x\n", __func__, offset, len, val);
1321
1322         apic_reg_write(apic, offset & 0xff0, val);
1323
1324         return 0;
1325 }
1326
1327 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1328 {
1329         if (kvm_vcpu_has_lapic(vcpu))
1330                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1331 }
1332 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1333
1334 /* emulate APIC access in a trap manner */
1335 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1336 {
1337         u32 val = 0;
1338
1339         /* hw has done the conditional check and inst decode */
1340         offset &= 0xff0;
1341
1342         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1343
1344         /* TODO: optimize to just emulate side effect w/o one more write */
1345         apic_reg_write(vcpu->arch.apic, offset, val);
1346 }
1347 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1348
1349 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1350 {
1351         struct kvm_lapic *apic = vcpu->arch.apic;
1352
1353         if (!vcpu->arch.apic)
1354                 return;
1355
1356         hrtimer_cancel(&apic->lapic_timer.timer);
1357
1358         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1359                 static_key_slow_dec_deferred(&apic_hw_disabled);
1360
1361         if (!apic->sw_enabled)
1362                 static_key_slow_dec_deferred(&apic_sw_disabled);
1363
1364         if (apic->regs)
1365                 free_page((unsigned long)apic->regs);
1366
1367         kfree(apic);
1368 }
1369
1370 /*
1371  *----------------------------------------------------------------------
1372  * LAPIC interface
1373  *----------------------------------------------------------------------
1374  */
1375
1376 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1377 {
1378         struct kvm_lapic *apic = vcpu->arch.apic;
1379
1380         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1381                         apic_lvtt_period(apic))
1382                 return 0;
1383
1384         return apic->lapic_timer.tscdeadline;
1385 }
1386
1387 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1388 {
1389         struct kvm_lapic *apic = vcpu->arch.apic;
1390
1391         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1392                         apic_lvtt_period(apic))
1393                 return;
1394
1395         hrtimer_cancel(&apic->lapic_timer.timer);
1396         apic->lapic_timer.tscdeadline = data;
1397         start_apic_timer(apic);
1398 }
1399
1400 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1401 {
1402         struct kvm_lapic *apic = vcpu->arch.apic;
1403
1404         if (!kvm_vcpu_has_lapic(vcpu))
1405                 return;
1406
1407         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1408                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1409 }
1410
1411 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1412 {
1413         u64 tpr;
1414
1415         if (!kvm_vcpu_has_lapic(vcpu))
1416                 return 0;
1417
1418         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1419
1420         return (tpr & 0xf0) >> 4;
1421 }
1422
1423 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1424 {
1425         u64 old_value = vcpu->arch.apic_base;
1426         struct kvm_lapic *apic = vcpu->arch.apic;
1427
1428         if (!apic) {
1429                 value |= MSR_IA32_APICBASE_BSP;
1430                 vcpu->arch.apic_base = value;
1431                 return;
1432         }
1433
1434         if (!kvm_vcpu_is_bsp(apic->vcpu))
1435                 value &= ~MSR_IA32_APICBASE_BSP;
1436         vcpu->arch.apic_base = value;
1437
1438         /* update jump label if enable bit changes */
1439         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1440                 if (value & MSR_IA32_APICBASE_ENABLE)
1441                         static_key_slow_dec_deferred(&apic_hw_disabled);
1442                 else
1443                         static_key_slow_inc(&apic_hw_disabled.key);
1444                 recalculate_apic_map(vcpu->kvm);
1445         }
1446
1447         if ((old_value ^ value) & X2APIC_ENABLE) {
1448                 if (value & X2APIC_ENABLE) {
1449                         u32 id = kvm_apic_id(apic);
1450                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1451                         kvm_apic_set_ldr(apic, ldr);
1452                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1453                 } else
1454                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1455         }
1456
1457         apic->base_address = apic->vcpu->arch.apic_base &
1458                              MSR_IA32_APICBASE_BASE;
1459
1460         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1461              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1462                 pr_warn_once("APIC base relocation is unsupported by KVM");
1463
1464         /* with FSB delivery interrupt, we can restart APIC functionality */
1465         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1466                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1467
1468 }
1469
1470 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1471 {
1472         struct kvm_lapic *apic;
1473         int i;
1474
1475         apic_debug("%s\n", __func__);
1476
1477         ASSERT(vcpu);
1478         apic = vcpu->arch.apic;
1479         ASSERT(apic != NULL);
1480
1481         /* Stop the timer in case it's a reset to an active apic */
1482         hrtimer_cancel(&apic->lapic_timer.timer);
1483
1484         kvm_apic_set_id(apic, vcpu->vcpu_id);
1485         kvm_apic_set_version(apic->vcpu);
1486
1487         for (i = 0; i < APIC_LVT_NUM; i++)
1488                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1489         apic->lapic_timer.timer_mode = 0;
1490         apic_set_reg(apic, APIC_LVT0,
1491                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1492
1493         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1494         apic_set_spiv(apic, 0xff);
1495         apic_set_reg(apic, APIC_TASKPRI, 0);
1496         kvm_apic_set_ldr(apic, 0);
1497         apic_set_reg(apic, APIC_ESR, 0);
1498         apic_set_reg(apic, APIC_ICR, 0);
1499         apic_set_reg(apic, APIC_ICR2, 0);
1500         apic_set_reg(apic, APIC_TDCR, 0);
1501         apic_set_reg(apic, APIC_TMICT, 0);
1502         for (i = 0; i < 8; i++) {
1503                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1504                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1505                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1506         }
1507         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1508         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1509         apic->highest_isr_cache = -1;
1510         update_divide_count(apic);
1511         atomic_set(&apic->lapic_timer.pending, 0);
1512         if (kvm_vcpu_is_bsp(vcpu))
1513                 kvm_lapic_set_base(vcpu,
1514                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1515         vcpu->arch.pv_eoi.msr_val = 0;
1516         apic_update_ppr(apic);
1517
1518         vcpu->arch.apic_arb_prio = 0;
1519         vcpu->arch.apic_attention = 0;
1520
1521         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1522                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1523                    vcpu, kvm_apic_id(apic),
1524                    vcpu->arch.apic_base, apic->base_address);
1525 }
1526
1527 /*
1528  *----------------------------------------------------------------------
1529  * timer interface
1530  *----------------------------------------------------------------------
1531  */
1532
1533 static bool lapic_is_periodic(struct kvm_lapic *apic)
1534 {
1535         return apic_lvtt_period(apic);
1536 }
1537
1538 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1539 {
1540         struct kvm_lapic *apic = vcpu->arch.apic;
1541
1542         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1543                         apic_lvt_enabled(apic, APIC_LVTT))
1544                 return atomic_read(&apic->lapic_timer.pending);
1545
1546         return 0;
1547 }
1548
1549 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1550 {
1551         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1552         int vector, mode, trig_mode;
1553
1554         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1555                 vector = reg & APIC_VECTOR_MASK;
1556                 mode = reg & APIC_MODE_MASK;
1557                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1558                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1559                                         NULL);
1560         }
1561         return 0;
1562 }
1563
1564 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1565 {
1566         struct kvm_lapic *apic = vcpu->arch.apic;
1567
1568         if (apic)
1569                 kvm_apic_local_deliver(apic, APIC_LVT0);
1570 }
1571
1572 static const struct kvm_io_device_ops apic_mmio_ops = {
1573         .read     = apic_mmio_read,
1574         .write    = apic_mmio_write,
1575 };
1576
1577 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1578 {
1579         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1580         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1581
1582         apic_timer_expired(apic);
1583
1584         if (lapic_is_periodic(apic)) {
1585                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1586                 return HRTIMER_RESTART;
1587         } else
1588                 return HRTIMER_NORESTART;
1589 }
1590
1591 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1592 {
1593         struct kvm_lapic *apic;
1594
1595         ASSERT(vcpu != NULL);
1596         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1597
1598         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1599         if (!apic)
1600                 goto nomem;
1601
1602         vcpu->arch.apic = apic;
1603
1604         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1605         if (!apic->regs) {
1606                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1607                        vcpu->vcpu_id);
1608                 goto nomem_free_apic;
1609         }
1610         apic->vcpu = vcpu;
1611
1612         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1613                      HRTIMER_MODE_ABS);
1614         apic->lapic_timer.timer.function = apic_timer_fn;
1615
1616         /*
1617          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1618          * thinking that APIC satet has changed.
1619          */
1620         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1621         kvm_lapic_set_base(vcpu,
1622                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1623
1624         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1625         kvm_lapic_reset(vcpu);
1626         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1627
1628         return 0;
1629 nomem_free_apic:
1630         kfree(apic);
1631 nomem:
1632         return -ENOMEM;
1633 }
1634
1635 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1636 {
1637         struct kvm_lapic *apic = vcpu->arch.apic;
1638         int highest_irr;
1639
1640         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1641                 return -1;
1642
1643         apic_update_ppr(apic);
1644         highest_irr = apic_find_highest_irr(apic);
1645         if ((highest_irr == -1) ||
1646             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1647                 return -1;
1648         return highest_irr;
1649 }
1650
1651 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1652 {
1653         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1654         int r = 0;
1655
1656         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1657                 r = 1;
1658         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1659             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1660                 r = 1;
1661         return r;
1662 }
1663
1664 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1665 {
1666         struct kvm_lapic *apic = vcpu->arch.apic;
1667
1668         if (!kvm_vcpu_has_lapic(vcpu))
1669                 return;
1670
1671         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1672                 kvm_apic_local_deliver(apic, APIC_LVTT);
1673                 if (apic_lvtt_tscdeadline(apic))
1674                         apic->lapic_timer.tscdeadline = 0;
1675                 atomic_set(&apic->lapic_timer.pending, 0);
1676         }
1677 }
1678
1679 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1680 {
1681         int vector = kvm_apic_has_interrupt(vcpu);
1682         struct kvm_lapic *apic = vcpu->arch.apic;
1683
1684         if (vector == -1)
1685                 return -1;
1686
1687         /*
1688          * We get here even with APIC virtualization enabled, if doing
1689          * nested virtualization and L1 runs with the "acknowledge interrupt
1690          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1691          * because the process would deliver it through the IDT.
1692          */
1693
1694         apic_set_isr(vector, apic);
1695         apic_update_ppr(apic);
1696         apic_clear_irr(vector, apic);
1697         return vector;
1698 }
1699
1700 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1701                 struct kvm_lapic_state *s)
1702 {
1703         struct kvm_lapic *apic = vcpu->arch.apic;
1704
1705         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1706         /* set SPIV separately to get count of SW disabled APICs right */
1707         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1708         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1709         /* call kvm_apic_set_id() to put apic into apic_map */
1710         kvm_apic_set_id(apic, kvm_apic_id(apic));
1711         kvm_apic_set_version(vcpu);
1712
1713         apic_update_ppr(apic);
1714         hrtimer_cancel(&apic->lapic_timer.timer);
1715         update_divide_count(apic);
1716         start_apic_timer(apic);
1717         apic->irr_pending = true;
1718         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1719                                 1 : count_vectors(apic->regs + APIC_ISR);
1720         apic->highest_isr_cache = -1;
1721         if (kvm_x86_ops->hwapic_irr_update)
1722                 kvm_x86_ops->hwapic_irr_update(vcpu,
1723                                 apic_find_highest_irr(apic));
1724         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1725         kvm_make_request(KVM_REQ_EVENT, vcpu);
1726         kvm_rtc_eoi_tracking_restore_one(vcpu);
1727 }
1728
1729 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1730 {
1731         struct hrtimer *timer;
1732
1733         if (!kvm_vcpu_has_lapic(vcpu))
1734                 return;
1735
1736         timer = &vcpu->arch.apic->lapic_timer.timer;
1737         if (hrtimer_cancel(timer))
1738                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1739 }
1740
1741 /*
1742  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1743  *
1744  * Detect whether guest triggered PV EOI since the
1745  * last entry. If yes, set EOI on guests's behalf.
1746  * Clear PV EOI in guest memory in any case.
1747  */
1748 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1749                                         struct kvm_lapic *apic)
1750 {
1751         bool pending;
1752         int vector;
1753         /*
1754          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1755          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1756          *
1757          * KVM_APIC_PV_EOI_PENDING is unset:
1758          *      -> host disabled PV EOI.
1759          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1760          *      -> host enabled PV EOI, guest did not execute EOI yet.
1761          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1762          *      -> host enabled PV EOI, guest executed EOI.
1763          */
1764         BUG_ON(!pv_eoi_enabled(vcpu));
1765         pending = pv_eoi_get_pending(vcpu);
1766         /*
1767          * Clear pending bit in any case: it will be set again on vmentry.
1768          * While this might not be ideal from performance point of view,
1769          * this makes sure pv eoi is only enabled when we know it's safe.
1770          */
1771         pv_eoi_clr_pending(vcpu);
1772         if (pending)
1773                 return;
1774         vector = apic_set_eoi(apic);
1775         trace_kvm_pv_eoi(apic, vector);
1776 }
1777
1778 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1779 {
1780         u32 data;
1781
1782         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1783                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1784
1785         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1786                 return;
1787
1788         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1789                                 sizeof(u32));
1790
1791         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1792 }
1793
1794 /*
1795  * apic_sync_pv_eoi_to_guest - called before vmentry
1796  *
1797  * Detect whether it's safe to enable PV EOI and
1798  * if yes do so.
1799  */
1800 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1801                                         struct kvm_lapic *apic)
1802 {
1803         if (!pv_eoi_enabled(vcpu) ||
1804             /* IRR set or many bits in ISR: could be nested. */
1805             apic->irr_pending ||
1806             /* Cache not set: could be safe but we don't bother. */
1807             apic->highest_isr_cache == -1 ||
1808             /* Need EOI to update ioapic. */
1809             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1810                 /*
1811                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1812                  * so we need not do anything here.
1813                  */
1814                 return;
1815         }
1816
1817         pv_eoi_set_pending(apic->vcpu);
1818 }
1819
1820 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1821 {
1822         u32 data, tpr;
1823         int max_irr, max_isr;
1824         struct kvm_lapic *apic = vcpu->arch.apic;
1825
1826         apic_sync_pv_eoi_to_guest(vcpu, apic);
1827
1828         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1829                 return;
1830
1831         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1832         max_irr = apic_find_highest_irr(apic);
1833         if (max_irr < 0)
1834                 max_irr = 0;
1835         max_isr = apic_find_highest_isr(apic);
1836         if (max_isr < 0)
1837                 max_isr = 0;
1838         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1839
1840         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1841                                 sizeof(u32));
1842 }
1843
1844 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1845 {
1846         if (vapic_addr) {
1847                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1848                                         &vcpu->arch.apic->vapic_cache,
1849                                         vapic_addr, sizeof(u32)))
1850                         return -EINVAL;
1851                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1852         } else {
1853                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1854         }
1855
1856         vcpu->arch.apic->vapic_addr = vapic_addr;
1857         return 0;
1858 }
1859
1860 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1861 {
1862         struct kvm_lapic *apic = vcpu->arch.apic;
1863         u32 reg = (msr - APIC_BASE_MSR) << 4;
1864
1865         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1866                 return 1;
1867
1868         /* if this is ICR write vector before command */
1869         if (msr == 0x830)
1870                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1871         return apic_reg_write(apic, reg, (u32)data);
1872 }
1873
1874 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1875 {
1876         struct kvm_lapic *apic = vcpu->arch.apic;
1877         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1878
1879         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1880                 return 1;
1881
1882         if (apic_reg_read(apic, reg, 4, &low))
1883                 return 1;
1884         if (msr == 0x830)
1885                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1886
1887         *data = (((u64)high) << 32) | low;
1888
1889         return 0;
1890 }
1891
1892 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1893 {
1894         struct kvm_lapic *apic = vcpu->arch.apic;
1895
1896         if (!kvm_vcpu_has_lapic(vcpu))
1897                 return 1;
1898
1899         /* if this is ICR write vector before command */
1900         if (reg == APIC_ICR)
1901                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1902         return apic_reg_write(apic, reg, (u32)data);
1903 }
1904
1905 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1906 {
1907         struct kvm_lapic *apic = vcpu->arch.apic;
1908         u32 low, high = 0;
1909
1910         if (!kvm_vcpu_has_lapic(vcpu))
1911                 return 1;
1912
1913         if (apic_reg_read(apic, reg, 4, &low))
1914                 return 1;
1915         if (reg == APIC_ICR)
1916                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1917
1918         *data = (((u64)high) << 32) | low;
1919
1920         return 0;
1921 }
1922
1923 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1924 {
1925         u64 addr = data & ~KVM_MSR_ENABLED;
1926         if (!IS_ALIGNED(addr, 4))
1927                 return 1;
1928
1929         vcpu->arch.pv_eoi.msr_val = data;
1930         if (!pv_eoi_enabled(vcpu))
1931                 return 0;
1932         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1933                                          addr, sizeof(u8));
1934 }
1935
1936 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1937 {
1938         struct kvm_lapic *apic = vcpu->arch.apic;
1939         unsigned int sipi_vector;
1940         unsigned long pe;
1941
1942         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1943                 return;
1944
1945         pe = xchg(&apic->pending_events, 0);
1946
1947         if (test_bit(KVM_APIC_INIT, &pe)) {
1948                 kvm_lapic_reset(vcpu);
1949                 kvm_vcpu_reset(vcpu);
1950                 if (kvm_vcpu_is_bsp(apic->vcpu))
1951                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1952                 else
1953                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1954         }
1955         if (test_bit(KVM_APIC_SIPI, &pe) &&
1956             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1957                 /* evaluate pending_events before reading the vector */
1958                 smp_rmb();
1959                 sipi_vector = apic->sipi_vector;
1960                 apic_debug("vcpu %d received sipi with vector # %x\n",
1961                          vcpu->vcpu_id, sipi_vector);
1962                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1963                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1964         }
1965 }
1966
1967 void kvm_lapic_init(void)
1968 {
1969         /* do not patch jump label more than once per second */
1970         jump_label_rate_limit(&apic_hw_disabled, HZ);
1971         jump_label_rate_limit(&apic_sw_disabled, HZ);
1972 }