1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_LAPIC_H
3 #define __KVM_X86_LAPIC_H
7 #include <linux/kvm_host.h>
9 #define KVM_APIC_INIT 0
10 #define KVM_APIC_SIPI 1
11 #define KVM_APIC_LVT_NUM 6
13 #define KVM_APIC_SHORT_MASK 0xc0000
14 #define KVM_APIC_DEST_MASK 0x800
16 #define APIC_BUS_CYCLE_NS 1
17 #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
20 LAPIC_MODE_DISABLED = 0,
21 LAPIC_MODE_INVALID = X2APIC_ENABLE,
22 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
23 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
28 s64 period; /* unit: ns */
29 ktime_t target_expiration;
33 u64 expired_tscdeadline;
35 s64 advance_expire_delta;
36 atomic_t pending; /* accumulated triggered timers */
41 unsigned long base_address;
42 struct kvm_io_device dev;
43 struct kvm_timer lapic_timer;
45 struct kvm_vcpu *vcpu;
48 bool lvt0_in_nmi_mode;
49 /* Number of bits set in ISR. */
51 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
52 int highest_isr_cache;
54 * APIC register page. The layout matches the register layout seen by
55 * the guest 1:1, because it is accessed by the vmx microcode.
56 * Note: Only one register, the TPR, is used by the microcode.
60 struct gfn_to_hva_cache vapic_cache;
61 unsigned long pending_events;
62 unsigned int sipi_vector;
67 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
68 void kvm_free_lapic(struct kvm_vcpu *vcpu);
70 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
71 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
72 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
73 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
74 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
75 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
76 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
77 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
78 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
79 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
80 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
81 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
82 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
84 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
85 int short_hand, unsigned int dest, int dest_mode);
87 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
88 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
89 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
90 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
91 struct dest_map *dest_map);
92 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
94 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
95 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
97 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
98 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
99 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
100 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
101 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
102 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
104 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
105 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
107 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
108 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
110 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
111 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
112 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
114 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
115 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
117 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
118 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
120 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
122 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
125 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
126 void kvm_lapic_init(void);
127 void kvm_lapic_exit(void);
129 #define VEC_POS(v) ((v) & (32 - 1))
130 #define REG_POS(v) (((v) >> 5) << 4)
132 static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
134 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
137 static inline void kvm_lapic_set_vector(int vec, void *bitmap)
139 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
142 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
144 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
146 * irr_pending must be true if any interrupt is pending; set it after
147 * APIC_IRR to avoid race with apic_clear_irr
149 apic->irr_pending = true;
152 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
154 return *((u32 *) (apic->regs + reg_off));
157 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
159 *((u32 *) (apic->regs + reg_off)) = val;
162 extern struct static_key kvm_no_apic_vcpu;
164 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
166 if (static_key_false(&kvm_no_apic_vcpu))
167 return vcpu->arch.apic;
171 extern struct static_key_deferred apic_hw_disabled;
173 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
175 if (static_key_false(&apic_hw_disabled.key))
176 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
177 return MSR_IA32_APICBASE_ENABLE;
180 extern struct static_key_deferred apic_sw_disabled;
182 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
184 if (static_key_false(&apic_sw_disabled.key))
185 return apic->sw_enabled;
189 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
191 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
194 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
196 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
199 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
201 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
204 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
206 return vcpu->arch.apic && vcpu->arch.apicv_active;
209 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
211 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
214 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
216 return (irq->delivery_mode == APIC_DM_LOWEST ||
217 irq->msi_redir_hint);
220 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
222 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
225 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
227 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
229 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
230 unsigned long *vcpu_bitmap);
232 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
233 struct kvm_vcpu **dest_vcpu);
234 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
235 const unsigned long *bitmap, u32 bitmap_size);
236 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
237 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
238 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
239 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
240 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
241 bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu);
243 static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
245 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
248 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
250 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;