1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "kvm_cache_regs.h"
24 #include <linux/kvm_host.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
28 #include <linux/highmem.h>
29 #include <linux/moduleparam.h>
30 #include <linux/export.h>
31 #include <linux/swap.h>
32 #include <linux/hugetlb.h>
33 #include <linux/compiler.h>
34 #include <linux/srcu.h>
35 #include <linux/slab.h>
36 #include <linux/sched/signal.h>
37 #include <linux/uaccess.h>
38 #include <linux/hash.h>
39 #include <linux/kern_levels.h>
40 #include <linux/kthread.h>
44 #include <asm/cmpxchg.h>
45 #include <asm/e820/api.h>
48 #include <asm/kvm_page_track.h>
51 extern bool itlb_multihit_kvm_mitigation;
53 static int __read_mostly nx_huge_pages = -1;
54 #ifdef CONFIG_PREEMPT_RT
55 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
56 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
58 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
61 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
62 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
64 static struct kernel_param_ops nx_huge_pages_ops = {
65 .set = set_nx_huge_pages,
66 .get = param_get_bool,
69 static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
70 .set = set_nx_huge_pages_recovery_ratio,
71 .get = param_get_uint,
74 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
75 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
76 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
77 &nx_huge_pages_recovery_ratio, 0644);
78 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
81 * When setting this variable to true it enables Two-Dimensional-Paging
82 * where the hardware walks 2 page tables:
83 * 1. the guest-virtual to guest-physical
84 * 2. while doing 1. it walks guest-physical to host-physical
85 * If the hardware supports that we don't need to do shadow paging.
87 bool tdp_enabled = false;
91 AUDIT_POST_PAGE_FAULT,
102 module_param(dbg, bool, 0644);
104 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
105 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
106 #define MMU_WARN_ON(x) WARN_ON(x)
108 #define pgprintk(x...) do { } while (0)
109 #define rmap_printk(x...) do { } while (0)
110 #define MMU_WARN_ON(x) do { } while (0)
113 #define PTE_PREFETCH_NUM 8
115 #define PT_FIRST_AVAIL_BITS_SHIFT 10
116 #define PT64_SECOND_AVAIL_BITS_SHIFT 54
119 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
120 * Access Tracking SPTEs.
122 #define SPTE_SPECIAL_MASK (3ULL << 52)
123 #define SPTE_AD_ENABLED_MASK (0ULL << 52)
124 #define SPTE_AD_DISABLED_MASK (1ULL << 52)
125 #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
126 #define SPTE_MMIO_MASK (3ULL << 52)
128 #define PT64_LEVEL_BITS 9
130 #define PT64_LEVEL_SHIFT(level) \
131 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
133 #define PT64_INDEX(address, level)\
134 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
137 #define PT32_LEVEL_BITS 10
139 #define PT32_LEVEL_SHIFT(level) \
140 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
142 #define PT32_LVL_OFFSET_MASK(level) \
143 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
144 * PT32_LEVEL_BITS))) - 1))
146 #define PT32_INDEX(address, level)\
147 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
150 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
151 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
153 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
155 #define PT64_LVL_ADDR_MASK(level) \
156 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
157 * PT64_LEVEL_BITS))) - 1))
158 #define PT64_LVL_OFFSET_MASK(level) \
159 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
160 * PT64_LEVEL_BITS))) - 1))
162 #define PT32_BASE_ADDR_MASK PAGE_MASK
163 #define PT32_DIR_BASE_ADDR_MASK \
164 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
165 #define PT32_LVL_ADDR_MASK(level) \
166 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
167 * PT32_LEVEL_BITS))) - 1))
169 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
170 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
172 #define ACC_EXEC_MASK 1
173 #define ACC_WRITE_MASK PT_WRITABLE_MASK
174 #define ACC_USER_MASK PT_USER_MASK
175 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
177 /* The mask for the R/X bits in EPT PTEs */
178 #define PT64_EPT_READABLE_MASK 0x1ull
179 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
181 #include <trace/events/kvm.h>
183 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
184 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
186 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
188 /* make pte_list_desc fit well in cache line */
189 #define PTE_LIST_EXT 3
192 * Return values of handle_mmio_page_fault and mmu.page_fault:
193 * RET_PF_RETRY: let CPU fault again on the address.
194 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
196 * For handle_mmio_page_fault only:
197 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
205 struct pte_list_desc {
206 u64 *sptes[PTE_LIST_EXT];
207 struct pte_list_desc *more;
210 struct kvm_shadow_walk_iterator {
218 static const union kvm_mmu_page_role mmu_base_role_mask = {
220 .gpte_is_8_bytes = 1,
229 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
230 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
232 shadow_walk_okay(&(_walker)); \
233 shadow_walk_next(&(_walker)))
235 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
236 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
237 shadow_walk_okay(&(_walker)); \
238 shadow_walk_next(&(_walker)))
240 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
241 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
242 shadow_walk_okay(&(_walker)) && \
243 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
244 __shadow_walk_next(&(_walker), spte))
246 static struct kmem_cache *pte_list_desc_cache;
247 static struct kmem_cache *mmu_page_header_cache;
248 static struct percpu_counter kvm_total_used_mmu_pages;
250 static u64 __read_mostly shadow_nx_mask;
251 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
252 static u64 __read_mostly shadow_user_mask;
253 static u64 __read_mostly shadow_accessed_mask;
254 static u64 __read_mostly shadow_dirty_mask;
255 static u64 __read_mostly shadow_mmio_mask;
256 static u64 __read_mostly shadow_mmio_value;
257 static u64 __read_mostly shadow_mmio_access_mask;
258 static u64 __read_mostly shadow_present_mask;
259 static u64 __read_mostly shadow_me_mask;
262 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
263 * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
266 static u64 __read_mostly shadow_acc_track_mask;
269 * The mask/shift to use for saving the original R/X bits when marking the PTE
270 * as not-present for access tracking purposes. We do not save the W bit as the
271 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
272 * restored only when a write is attempted to the page.
274 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
275 PT64_EPT_EXECUTABLE_MASK;
276 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
279 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
280 * to guard against L1TF attacks.
282 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
285 * The number of high-order 1 bits to use in the mask above.
287 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
290 * In some cases, we need to preserve the GFN of a non-present or reserved
291 * SPTE when we usurp the upper five bits of the physical address space to
292 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
293 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
294 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
295 * high and low parts. This mask covers the lower bits of the GFN.
297 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
300 * The number of non-reserved physical address bits irrespective of features
301 * that repurpose legal bits, e.g. MKTME.
303 static u8 __read_mostly shadow_phys_bits;
305 static void mmu_spte_set(u64 *sptep, u64 spte);
306 static bool is_executable_pte(u64 spte);
307 static union kvm_mmu_page_role
308 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
310 #define CREATE_TRACE_POINTS
311 #include "mmutrace.h"
314 static inline bool kvm_available_flush_tlb_with_range(void)
316 return kvm_x86_ops->tlb_remote_flush_with_range;
319 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
320 struct kvm_tlb_range *range)
324 if (range && kvm_x86_ops->tlb_remote_flush_with_range)
325 ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range);
328 kvm_flush_remote_tlbs(kvm);
331 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
332 u64 start_gfn, u64 pages)
334 struct kvm_tlb_range range;
336 range.start_gfn = start_gfn;
339 kvm_flush_remote_tlbs_with_range(kvm, &range);
342 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value, u64 access_mask)
344 BUG_ON((u64)(unsigned)access_mask != access_mask);
345 BUG_ON((mmio_mask & mmio_value) != mmio_value);
346 shadow_mmio_value = mmio_value | SPTE_MMIO_MASK;
347 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
348 shadow_mmio_access_mask = access_mask;
350 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
352 static bool is_mmio_spte(u64 spte)
354 return (spte & shadow_mmio_mask) == shadow_mmio_value;
357 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
359 return sp->role.ad_disabled;
362 static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
365 * When using the EPT page-modification log, the GPAs in the log
366 * would come from L2 rather than L1. Therefore, we need to rely
367 * on write protection to record dirty pages. This also bypasses
368 * PML, since writes now result in a vmexit.
370 return vcpu->arch.mmu == &vcpu->arch.guest_mmu;
373 static inline bool spte_ad_enabled(u64 spte)
375 MMU_WARN_ON(is_mmio_spte(spte));
376 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK;
379 static inline bool spte_ad_need_write_protect(u64 spte)
381 MMU_WARN_ON(is_mmio_spte(spte));
382 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK;
385 static bool is_nx_huge_page_enabled(void)
387 return READ_ONCE(nx_huge_pages);
390 static inline u64 spte_shadow_accessed_mask(u64 spte)
392 MMU_WARN_ON(is_mmio_spte(spte));
393 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
396 static inline u64 spte_shadow_dirty_mask(u64 spte)
398 MMU_WARN_ON(is_mmio_spte(spte));
399 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
402 static inline bool is_access_track_spte(u64 spte)
404 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
408 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
409 * the memslots generation and is derived as follows:
411 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
412 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
414 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
415 * the MMIO generation number, as doing so would require stealing a bit from
416 * the "real" generation number and thus effectively halve the maximum number
417 * of MMIO generations that can be handled before encountering a wrap (which
418 * requires a full MMU zap). The flag is instead explicitly queried when
419 * checking for MMIO spte cache hits.
421 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0)
423 #define MMIO_SPTE_GEN_LOW_START 3
424 #define MMIO_SPTE_GEN_LOW_END 11
425 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
426 MMIO_SPTE_GEN_LOW_START)
428 #define MMIO_SPTE_GEN_HIGH_START 52
429 #define MMIO_SPTE_GEN_HIGH_END 61
430 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
431 MMIO_SPTE_GEN_HIGH_START)
432 static u64 generation_mmio_spte_mask(u64 gen)
436 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
438 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
439 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
443 static u64 get_mmio_spte_generation(u64 spte)
447 spte &= ~shadow_mmio_mask;
449 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
450 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
454 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
457 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
458 u64 mask = generation_mmio_spte_mask(gen);
459 u64 gpa = gfn << PAGE_SHIFT;
461 access &= shadow_mmio_access_mask;
462 mask |= shadow_mmio_value | access;
463 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
464 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
465 << shadow_nonpresent_or_rsvd_mask_len;
467 trace_mark_mmio_spte(sptep, gfn, access, gen);
468 mmu_spte_set(sptep, mask);
471 static gfn_t get_mmio_spte_gfn(u64 spte)
473 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
475 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
476 & shadow_nonpresent_or_rsvd_mask;
478 return gpa >> PAGE_SHIFT;
481 static unsigned get_mmio_spte_access(u64 spte)
483 return spte & shadow_mmio_access_mask;
486 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
487 kvm_pfn_t pfn, unsigned access)
489 if (unlikely(is_noslot_pfn(pfn))) {
490 mark_mmio_spte(vcpu, sptep, gfn, access);
497 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
499 u64 kvm_gen, spte_gen, gen;
501 gen = kvm_vcpu_memslots(vcpu)->generation;
502 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
505 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
506 spte_gen = get_mmio_spte_generation(spte);
508 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
509 return likely(kvm_gen == spte_gen);
513 * Sets the shadow PTE masks used by the MMU.
516 * - Setting either @accessed_mask or @dirty_mask requires setting both
517 * - At least one of @accessed_mask or @acc_track_mask must be set
519 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
520 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
521 u64 acc_track_mask, u64 me_mask)
523 BUG_ON(!dirty_mask != !accessed_mask);
524 BUG_ON(!accessed_mask && !acc_track_mask);
525 BUG_ON(acc_track_mask & SPTE_SPECIAL_MASK);
527 shadow_user_mask = user_mask;
528 shadow_accessed_mask = accessed_mask;
529 shadow_dirty_mask = dirty_mask;
530 shadow_nx_mask = nx_mask;
531 shadow_x_mask = x_mask;
532 shadow_present_mask = p_mask;
533 shadow_acc_track_mask = acc_track_mask;
534 shadow_me_mask = me_mask;
536 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
538 static u8 kvm_get_shadow_phys_bits(void)
541 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
542 * in CPU detection code, but the processor treats those reduced bits as
543 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
544 * the physical address bits reported by CPUID.
546 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
547 return cpuid_eax(0x80000008) & 0xff;
550 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
551 * custom CPUID. Proceed with whatever the kernel found since these features
552 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
554 return boot_cpu_data.x86_phys_bits;
557 static void kvm_mmu_reset_all_pte_masks(void)
561 shadow_user_mask = 0;
562 shadow_accessed_mask = 0;
563 shadow_dirty_mask = 0;
566 shadow_mmio_mask = 0;
567 shadow_present_mask = 0;
568 shadow_acc_track_mask = 0;
570 shadow_phys_bits = kvm_get_shadow_phys_bits();
573 * If the CPU has 46 or less physical address bits, then set an
574 * appropriate mask to guard against L1TF attacks. Otherwise, it is
575 * assumed that the CPU is not vulnerable to L1TF.
577 * Some Intel CPUs address the L1 cache using more PA bits than are
578 * reported by CPUID. Use the PA width of the L1 cache when possible
579 * to achieve more effective mitigation, e.g. if system RAM overlaps
580 * the most significant bits of legal physical address space.
582 shadow_nonpresent_or_rsvd_mask = 0;
583 low_phys_bits = boot_cpu_data.x86_cache_bits;
584 if (boot_cpu_data.x86_cache_bits <
585 52 - shadow_nonpresent_or_rsvd_mask_len) {
586 shadow_nonpresent_or_rsvd_mask =
587 rsvd_bits(boot_cpu_data.x86_cache_bits -
588 shadow_nonpresent_or_rsvd_mask_len,
589 boot_cpu_data.x86_cache_bits - 1);
590 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
592 WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF));
594 shadow_nonpresent_or_rsvd_lower_gfn_mask =
595 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
598 static int is_cpuid_PSE36(void)
603 static int is_nx(struct kvm_vcpu *vcpu)
605 return vcpu->arch.efer & EFER_NX;
608 static int is_shadow_present_pte(u64 pte)
610 return (pte != 0) && !is_mmio_spte(pte);
613 static int is_large_pte(u64 pte)
615 return pte & PT_PAGE_SIZE_MASK;
618 static int is_last_spte(u64 pte, int level)
620 if (level == PT_PAGE_TABLE_LEVEL)
622 if (is_large_pte(pte))
627 static bool is_executable_pte(u64 spte)
629 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
632 static kvm_pfn_t spte_to_pfn(u64 pte)
634 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
637 static gfn_t pse36_gfn_delta(u32 gpte)
639 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
641 return (gpte & PT32_DIR_PSE36_MASK) << shift;
645 static void __set_spte(u64 *sptep, u64 spte)
647 WRITE_ONCE(*sptep, spte);
650 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
652 WRITE_ONCE(*sptep, spte);
655 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
657 return xchg(sptep, spte);
660 static u64 __get_spte_lockless(u64 *sptep)
662 return READ_ONCE(*sptep);
673 static void count_spte_clear(u64 *sptep, u64 spte)
675 struct kvm_mmu_page *sp = page_header(__pa(sptep));
677 if (is_shadow_present_pte(spte))
680 /* Ensure the spte is completely set before we increase the count */
682 sp->clear_spte_count++;
685 static void __set_spte(u64 *sptep, u64 spte)
687 union split_spte *ssptep, sspte;
689 ssptep = (union split_spte *)sptep;
690 sspte = (union split_spte)spte;
692 ssptep->spte_high = sspte.spte_high;
695 * If we map the spte from nonpresent to present, We should store
696 * the high bits firstly, then set present bit, so cpu can not
697 * fetch this spte while we are setting the spte.
701 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
704 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
706 union split_spte *ssptep, sspte;
708 ssptep = (union split_spte *)sptep;
709 sspte = (union split_spte)spte;
711 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
714 * If we map the spte from present to nonpresent, we should clear
715 * present bit firstly to avoid vcpu fetch the old high bits.
719 ssptep->spte_high = sspte.spte_high;
720 count_spte_clear(sptep, spte);
723 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
725 union split_spte *ssptep, sspte, orig;
727 ssptep = (union split_spte *)sptep;
728 sspte = (union split_spte)spte;
730 /* xchg acts as a barrier before the setting of the high bits */
731 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
732 orig.spte_high = ssptep->spte_high;
733 ssptep->spte_high = sspte.spte_high;
734 count_spte_clear(sptep, spte);
740 * The idea using the light way get the spte on x86_32 guest is from
741 * gup_get_pte (mm/gup.c).
743 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
744 * coalesces them and we are running out of the MMU lock. Therefore
745 * we need to protect against in-progress updates of the spte.
747 * Reading the spte while an update is in progress may get the old value
748 * for the high part of the spte. The race is fine for a present->non-present
749 * change (because the high part of the spte is ignored for non-present spte),
750 * but for a present->present change we must reread the spte.
752 * All such changes are done in two steps (present->non-present and
753 * non-present->present), hence it is enough to count the number of
754 * present->non-present updates: if it changed while reading the spte,
755 * we might have hit the race. This is done using clear_spte_count.
757 static u64 __get_spte_lockless(u64 *sptep)
759 struct kvm_mmu_page *sp = page_header(__pa(sptep));
760 union split_spte spte, *orig = (union split_spte *)sptep;
764 count = sp->clear_spte_count;
767 spte.spte_low = orig->spte_low;
770 spte.spte_high = orig->spte_high;
773 if (unlikely(spte.spte_low != orig->spte_low ||
774 count != sp->clear_spte_count))
781 static bool spte_can_locklessly_be_made_writable(u64 spte)
783 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
784 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
787 static bool spte_has_volatile_bits(u64 spte)
789 if (!is_shadow_present_pte(spte))
793 * Always atomically update spte if it can be updated
794 * out of mmu-lock, it can ensure dirty bit is not lost,
795 * also, it can help us to get a stable is_writable_pte()
796 * to ensure tlb flush is not missed.
798 if (spte_can_locklessly_be_made_writable(spte) ||
799 is_access_track_spte(spte))
802 if (spte_ad_enabled(spte)) {
803 if ((spte & shadow_accessed_mask) == 0 ||
804 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
811 static bool is_accessed_spte(u64 spte)
813 u64 accessed_mask = spte_shadow_accessed_mask(spte);
815 return accessed_mask ? spte & accessed_mask
816 : !is_access_track_spte(spte);
819 static bool is_dirty_spte(u64 spte)
821 u64 dirty_mask = spte_shadow_dirty_mask(spte);
823 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
826 /* Rules for using mmu_spte_set:
827 * Set the sptep from nonpresent to present.
828 * Note: the sptep being assigned *must* be either not present
829 * or in a state where the hardware will not attempt to update
832 static void mmu_spte_set(u64 *sptep, u64 new_spte)
834 WARN_ON(is_shadow_present_pte(*sptep));
835 __set_spte(sptep, new_spte);
839 * Update the SPTE (excluding the PFN), but do not track changes in its
840 * accessed/dirty status.
842 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
844 u64 old_spte = *sptep;
846 WARN_ON(!is_shadow_present_pte(new_spte));
848 if (!is_shadow_present_pte(old_spte)) {
849 mmu_spte_set(sptep, new_spte);
853 if (!spte_has_volatile_bits(old_spte))
854 __update_clear_spte_fast(sptep, new_spte);
856 old_spte = __update_clear_spte_slow(sptep, new_spte);
858 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
863 /* Rules for using mmu_spte_update:
864 * Update the state bits, it means the mapped pfn is not changed.
866 * Whenever we overwrite a writable spte with a read-only one we
867 * should flush remote TLBs. Otherwise rmap_write_protect
868 * will find a read-only spte, even though the writable spte
869 * might be cached on a CPU's TLB, the return value indicates this
872 * Returns true if the TLB needs to be flushed
874 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
877 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
879 if (!is_shadow_present_pte(old_spte))
883 * For the spte updated out of mmu-lock is safe, since
884 * we always atomically update it, see the comments in
885 * spte_has_volatile_bits().
887 if (spte_can_locklessly_be_made_writable(old_spte) &&
888 !is_writable_pte(new_spte))
892 * Flush TLB when accessed/dirty states are changed in the page tables,
893 * to guarantee consistency between TLB and page tables.
896 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
898 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
901 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
903 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
910 * Rules for using mmu_spte_clear_track_bits:
911 * It sets the sptep from present to nonpresent, and track the
912 * state bits, it is used to clear the last level sptep.
913 * Returns non-zero if the PTE was previously valid.
915 static int mmu_spte_clear_track_bits(u64 *sptep)
918 u64 old_spte = *sptep;
920 if (!spte_has_volatile_bits(old_spte))
921 __update_clear_spte_fast(sptep, 0ull);
923 old_spte = __update_clear_spte_slow(sptep, 0ull);
925 if (!is_shadow_present_pte(old_spte))
928 pfn = spte_to_pfn(old_spte);
931 * KVM does not hold the refcount of the page used by
932 * kvm mmu, before reclaiming the page, we should
933 * unmap it from mmu first.
935 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
937 if (is_accessed_spte(old_spte))
938 kvm_set_pfn_accessed(pfn);
940 if (is_dirty_spte(old_spte))
941 kvm_set_pfn_dirty(pfn);
947 * Rules for using mmu_spte_clear_no_track:
948 * Directly clear spte without caring the state bits of sptep,
949 * it is used to set the upper level spte.
951 static void mmu_spte_clear_no_track(u64 *sptep)
953 __update_clear_spte_fast(sptep, 0ull);
956 static u64 mmu_spte_get_lockless(u64 *sptep)
958 return __get_spte_lockless(sptep);
961 static u64 mark_spte_for_access_track(u64 spte)
963 if (spte_ad_enabled(spte))
964 return spte & ~shadow_accessed_mask;
966 if (is_access_track_spte(spte))
970 * Making an Access Tracking PTE will result in removal of write access
971 * from the PTE. So, verify that we will be able to restore the write
972 * access in the fast page fault path later on.
974 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
975 !spte_can_locklessly_be_made_writable(spte),
976 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
978 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
979 shadow_acc_track_saved_bits_shift),
980 "kvm: Access Tracking saved bit locations are not zero\n");
982 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
983 shadow_acc_track_saved_bits_shift;
984 spte &= ~shadow_acc_track_mask;
989 /* Restore an acc-track PTE back to a regular PTE */
990 static u64 restore_acc_track_spte(u64 spte)
993 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
994 & shadow_acc_track_saved_bits_mask;
996 WARN_ON_ONCE(spte_ad_enabled(spte));
997 WARN_ON_ONCE(!is_access_track_spte(spte));
999 new_spte &= ~shadow_acc_track_mask;
1000 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
1001 shadow_acc_track_saved_bits_shift);
1002 new_spte |= saved_bits;
1007 /* Returns the Accessed status of the PTE and resets it at the same time. */
1008 static bool mmu_spte_age(u64 *sptep)
1010 u64 spte = mmu_spte_get_lockless(sptep);
1012 if (!is_accessed_spte(spte))
1015 if (spte_ad_enabled(spte)) {
1016 clear_bit((ffs(shadow_accessed_mask) - 1),
1017 (unsigned long *)sptep);
1020 * Capture the dirty status of the page, so that it doesn't get
1021 * lost when the SPTE is marked for access tracking.
1023 if (is_writable_pte(spte))
1024 kvm_set_pfn_dirty(spte_to_pfn(spte));
1026 spte = mark_spte_for_access_track(spte);
1027 mmu_spte_update_no_track(sptep, spte);
1033 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
1036 * Prevent page table teardown by making any free-er wait during
1037 * kvm_flush_remote_tlbs() IPI to all active vcpus.
1039 local_irq_disable();
1042 * Make sure a following spte read is not reordered ahead of the write
1045 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
1048 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
1051 * Make sure the write to vcpu->mode is not reordered in front of
1052 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
1053 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
1055 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
1059 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
1060 struct kmem_cache *base_cache, int min)
1064 if (cache->nobjs >= min)
1066 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1067 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
1069 return cache->nobjs >= min ? 0 : -ENOMEM;
1070 cache->objects[cache->nobjs++] = obj;
1075 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
1077 return cache->nobjs;
1080 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
1081 struct kmem_cache *cache)
1084 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
1087 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
1092 if (cache->nobjs >= min)
1094 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1095 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
1097 return cache->nobjs >= min ? 0 : -ENOMEM;
1098 cache->objects[cache->nobjs++] = page;
1103 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1106 free_page((unsigned long)mc->objects[--mc->nobjs]);
1109 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1113 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1114 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1117 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1120 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1121 mmu_page_header_cache, 4);
1126 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1128 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1129 pte_list_desc_cache);
1130 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1131 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1132 mmu_page_header_cache);
1135 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1140 p = mc->objects[--mc->nobjs];
1144 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1146 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1149 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1151 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1154 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1156 if (!sp->role.direct)
1157 return sp->gfns[index];
1159 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1162 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1164 if (!sp->role.direct) {
1165 sp->gfns[index] = gfn;
1169 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
1170 pr_err_ratelimited("gfn mismatch under direct page %llx "
1171 "(expected %llx, got %llx)\n",
1173 kvm_mmu_page_get_gfn(sp, index), gfn);
1177 * Return the pointer to the large page information for a given gfn,
1178 * handling slots that are not large page aligned.
1180 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1181 struct kvm_memory_slot *slot,
1186 idx = gfn_to_index(gfn, slot->base_gfn, level);
1187 return &slot->arch.lpage_info[level - 2][idx];
1190 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1191 gfn_t gfn, int count)
1193 struct kvm_lpage_info *linfo;
1196 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1197 linfo = lpage_info_slot(gfn, slot, i);
1198 linfo->disallow_lpage += count;
1199 WARN_ON(linfo->disallow_lpage < 0);
1203 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1205 update_gfn_disallow_lpage_count(slot, gfn, 1);
1208 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1210 update_gfn_disallow_lpage_count(slot, gfn, -1);
1213 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1215 struct kvm_memslots *slots;
1216 struct kvm_memory_slot *slot;
1219 kvm->arch.indirect_shadow_pages++;
1221 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1222 slot = __gfn_to_memslot(slots, gfn);
1224 /* the non-leaf shadow pages are keeping readonly. */
1225 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1226 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1227 KVM_PAGE_TRACK_WRITE);
1229 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1232 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1234 if (sp->lpage_disallowed)
1237 ++kvm->stat.nx_lpage_splits;
1238 list_add_tail(&sp->lpage_disallowed_link,
1239 &kvm->arch.lpage_disallowed_mmu_pages);
1240 sp->lpage_disallowed = true;
1243 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1245 struct kvm_memslots *slots;
1246 struct kvm_memory_slot *slot;
1249 kvm->arch.indirect_shadow_pages--;
1251 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1252 slot = __gfn_to_memslot(slots, gfn);
1253 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1254 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1255 KVM_PAGE_TRACK_WRITE);
1257 kvm_mmu_gfn_allow_lpage(slot, gfn);
1260 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1262 --kvm->stat.nx_lpage_splits;
1263 sp->lpage_disallowed = false;
1264 list_del(&sp->lpage_disallowed_link);
1267 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1268 struct kvm_memory_slot *slot)
1270 struct kvm_lpage_info *linfo;
1273 linfo = lpage_info_slot(gfn, slot, level);
1274 return !!linfo->disallow_lpage;
1280 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1283 struct kvm_memory_slot *slot;
1285 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1286 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1289 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1291 unsigned long page_size;
1294 page_size = kvm_host_page_size(kvm, gfn);
1296 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1297 if (page_size >= KVM_HPAGE_SIZE(i))
1306 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1309 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1311 if (no_dirty_log && slot->dirty_bitmap)
1317 static struct kvm_memory_slot *
1318 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1321 struct kvm_memory_slot *slot;
1323 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1324 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1330 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1333 int max_level = *max_levelp;
1334 struct kvm_memory_slot *slot;
1336 if (unlikely(max_level == PT_PAGE_TABLE_LEVEL))
1337 return PT_PAGE_TABLE_LEVEL;
1339 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1340 if (!memslot_valid_for_gpte(slot, true)) {
1341 *max_levelp = PT_PAGE_TABLE_LEVEL;
1342 return PT_PAGE_TABLE_LEVEL;
1345 max_level = min(max_level, kvm_x86_ops->get_lpage_level());
1346 for ( ; max_level > PT_PAGE_TABLE_LEVEL; max_level--) {
1347 if (!__mmu_gfn_lpage_is_disallowed(large_gfn, max_level, slot))
1351 *max_levelp = max_level;
1353 if (max_level == PT_PAGE_TABLE_LEVEL)
1354 return PT_PAGE_TABLE_LEVEL;
1357 * Note, host_mapping_level() does *not* handle transparent huge pages.
1358 * As suggested by "mapping", it reflects the page size established by
1359 * the associated vma, if there is one, i.e. host_mapping_level() will
1360 * return a huge page level if and only if a vma exists and the backing
1361 * implementation for the vma uses huge pages, e.g. hugetlbfs and dax.
1362 * So, do not propagate host_mapping_level() to max_level as KVM can
1363 * still promote the guest mapping to a huge page in the THP case.
1365 return host_mapping_level(vcpu->kvm, large_gfn);
1369 * About rmap_head encoding:
1371 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1372 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1373 * pte_list_desc containing more mappings.
1377 * Returns the number of pointers in the rmap chain, not counting the new one.
1379 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1380 struct kvm_rmap_head *rmap_head)
1382 struct pte_list_desc *desc;
1385 if (!rmap_head->val) {
1386 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1387 rmap_head->val = (unsigned long)spte;
1388 } else if (!(rmap_head->val & 1)) {
1389 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1390 desc = mmu_alloc_pte_list_desc(vcpu);
1391 desc->sptes[0] = (u64 *)rmap_head->val;
1392 desc->sptes[1] = spte;
1393 rmap_head->val = (unsigned long)desc | 1;
1396 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1397 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1398 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1400 count += PTE_LIST_EXT;
1402 if (desc->sptes[PTE_LIST_EXT-1]) {
1403 desc->more = mmu_alloc_pte_list_desc(vcpu);
1406 for (i = 0; desc->sptes[i]; ++i)
1408 desc->sptes[i] = spte;
1414 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1415 struct pte_list_desc *desc, int i,
1416 struct pte_list_desc *prev_desc)
1420 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1422 desc->sptes[i] = desc->sptes[j];
1423 desc->sptes[j] = NULL;
1426 if (!prev_desc && !desc->more)
1430 prev_desc->more = desc->more;
1432 rmap_head->val = (unsigned long)desc->more | 1;
1433 mmu_free_pte_list_desc(desc);
1436 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1438 struct pte_list_desc *desc;
1439 struct pte_list_desc *prev_desc;
1442 if (!rmap_head->val) {
1443 pr_err("%s: %p 0->BUG\n", __func__, spte);
1445 } else if (!(rmap_head->val & 1)) {
1446 rmap_printk("%s: %p 1->0\n", __func__, spte);
1447 if ((u64 *)rmap_head->val != spte) {
1448 pr_err("%s: %p 1->BUG\n", __func__, spte);
1453 rmap_printk("%s: %p many->many\n", __func__, spte);
1454 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1457 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1458 if (desc->sptes[i] == spte) {
1459 pte_list_desc_remove_entry(rmap_head,
1460 desc, i, prev_desc);
1467 pr_err("%s: %p many->many\n", __func__, spte);
1472 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1474 mmu_spte_clear_track_bits(sptep);
1475 __pte_list_remove(sptep, rmap_head);
1478 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1479 struct kvm_memory_slot *slot)
1483 idx = gfn_to_index(gfn, slot->base_gfn, level);
1484 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1487 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1488 struct kvm_mmu_page *sp)
1490 struct kvm_memslots *slots;
1491 struct kvm_memory_slot *slot;
1493 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1494 slot = __gfn_to_memslot(slots, gfn);
1495 return __gfn_to_rmap(gfn, sp->role.level, slot);
1498 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1500 struct kvm_mmu_memory_cache *cache;
1502 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1503 return mmu_memory_cache_free_objects(cache);
1506 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1508 struct kvm_mmu_page *sp;
1509 struct kvm_rmap_head *rmap_head;
1511 sp = page_header(__pa(spte));
1512 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1513 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1514 return pte_list_add(vcpu, spte, rmap_head);
1517 static void rmap_remove(struct kvm *kvm, u64 *spte)
1519 struct kvm_mmu_page *sp;
1521 struct kvm_rmap_head *rmap_head;
1523 sp = page_header(__pa(spte));
1524 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1525 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1526 __pte_list_remove(spte, rmap_head);
1530 * Used by the following functions to iterate through the sptes linked by a
1531 * rmap. All fields are private and not assumed to be used outside.
1533 struct rmap_iterator {
1534 /* private fields */
1535 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1536 int pos; /* index of the sptep */
1540 * Iteration must be started by this function. This should also be used after
1541 * removing/dropping sptes from the rmap link because in such cases the
1542 * information in the iterator may not be valid.
1544 * Returns sptep if found, NULL otherwise.
1546 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1547 struct rmap_iterator *iter)
1551 if (!rmap_head->val)
1554 if (!(rmap_head->val & 1)) {
1556 sptep = (u64 *)rmap_head->val;
1560 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1562 sptep = iter->desc->sptes[iter->pos];
1564 BUG_ON(!is_shadow_present_pte(*sptep));
1569 * Must be used with a valid iterator: e.g. after rmap_get_first().
1571 * Returns sptep if found, NULL otherwise.
1573 static u64 *rmap_get_next(struct rmap_iterator *iter)
1578 if (iter->pos < PTE_LIST_EXT - 1) {
1580 sptep = iter->desc->sptes[iter->pos];
1585 iter->desc = iter->desc->more;
1589 /* desc->sptes[0] cannot be NULL */
1590 sptep = iter->desc->sptes[iter->pos];
1597 BUG_ON(!is_shadow_present_pte(*sptep));
1601 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1602 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1603 _spte_; _spte_ = rmap_get_next(_iter_))
1605 static void drop_spte(struct kvm *kvm, u64 *sptep)
1607 if (mmu_spte_clear_track_bits(sptep))
1608 rmap_remove(kvm, sptep);
1612 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1614 if (is_large_pte(*sptep)) {
1615 WARN_ON(page_header(__pa(sptep))->role.level ==
1616 PT_PAGE_TABLE_LEVEL);
1617 drop_spte(kvm, sptep);
1625 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1627 if (__drop_large_spte(vcpu->kvm, sptep)) {
1628 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1630 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1631 KVM_PAGES_PER_HPAGE(sp->role.level));
1636 * Write-protect on the specified @sptep, @pt_protect indicates whether
1637 * spte write-protection is caused by protecting shadow page table.
1639 * Note: write protection is difference between dirty logging and spte
1641 * - for dirty logging, the spte can be set to writable at anytime if
1642 * its dirty bitmap is properly set.
1643 * - for spte protection, the spte can be writable only after unsync-ing
1646 * Return true if tlb need be flushed.
1648 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1652 if (!is_writable_pte(spte) &&
1653 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1656 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1659 spte &= ~SPTE_MMU_WRITEABLE;
1660 spte = spte & ~PT_WRITABLE_MASK;
1662 return mmu_spte_update(sptep, spte);
1665 static bool __rmap_write_protect(struct kvm *kvm,
1666 struct kvm_rmap_head *rmap_head,
1670 struct rmap_iterator iter;
1673 for_each_rmap_spte(rmap_head, &iter, sptep)
1674 flush |= spte_write_protect(sptep, pt_protect);
1679 static bool spte_clear_dirty(u64 *sptep)
1683 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1685 MMU_WARN_ON(!spte_ad_enabled(spte));
1686 spte &= ~shadow_dirty_mask;
1687 return mmu_spte_update(sptep, spte);
1690 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1692 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1693 (unsigned long *)sptep);
1694 if (was_writable && !spte_ad_enabled(*sptep))
1695 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1697 return was_writable;
1701 * Gets the GFN ready for another round of dirty logging by clearing the
1702 * - D bit on ad-enabled SPTEs, and
1703 * - W bit on ad-disabled SPTEs.
1704 * Returns true iff any D or W bits were cleared.
1706 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1709 struct rmap_iterator iter;
1712 for_each_rmap_spte(rmap_head, &iter, sptep)
1713 if (spte_ad_need_write_protect(*sptep))
1714 flush |= spte_wrprot_for_clear_dirty(sptep);
1716 flush |= spte_clear_dirty(sptep);
1721 static bool spte_set_dirty(u64 *sptep)
1725 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1728 * Similar to the !kvm_x86_ops->slot_disable_log_dirty case,
1729 * do not bother adding back write access to pages marked
1730 * SPTE_AD_WRPROT_ONLY_MASK.
1732 spte |= shadow_dirty_mask;
1734 return mmu_spte_update(sptep, spte);
1737 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1740 struct rmap_iterator iter;
1743 for_each_rmap_spte(rmap_head, &iter, sptep)
1744 if (spte_ad_enabled(*sptep))
1745 flush |= spte_set_dirty(sptep);
1751 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1752 * @kvm: kvm instance
1753 * @slot: slot to protect
1754 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1755 * @mask: indicates which pages we should protect
1757 * Used when we do not need to care about huge page mappings: e.g. during dirty
1758 * logging we do not have any such mappings.
1760 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1761 struct kvm_memory_slot *slot,
1762 gfn_t gfn_offset, unsigned long mask)
1764 struct kvm_rmap_head *rmap_head;
1767 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1768 PT_PAGE_TABLE_LEVEL, slot);
1769 __rmap_write_protect(kvm, rmap_head, false);
1771 /* clear the first set bit */
1777 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1778 * protect the page if the D-bit isn't supported.
1779 * @kvm: kvm instance
1780 * @slot: slot to clear D-bit
1781 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1782 * @mask: indicates which pages we should clear D-bit
1784 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1786 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1787 struct kvm_memory_slot *slot,
1788 gfn_t gfn_offset, unsigned long mask)
1790 struct kvm_rmap_head *rmap_head;
1793 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1794 PT_PAGE_TABLE_LEVEL, slot);
1795 __rmap_clear_dirty(kvm, rmap_head);
1797 /* clear the first set bit */
1801 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1804 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1807 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1808 * enable dirty logging for them.
1810 * Used when we do not need to care about huge page mappings: e.g. during dirty
1811 * logging we do not have any such mappings.
1813 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1814 struct kvm_memory_slot *slot,
1815 gfn_t gfn_offset, unsigned long mask)
1817 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1818 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1821 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1825 * kvm_arch_write_log_dirty - emulate dirty page logging
1826 * @vcpu: Guest mode vcpu
1828 * Emulate arch specific page modification logging for the
1831 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1833 if (kvm_x86_ops->write_log_dirty)
1834 return kvm_x86_ops->write_log_dirty(vcpu);
1839 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1840 struct kvm_memory_slot *slot, u64 gfn)
1842 struct kvm_rmap_head *rmap_head;
1844 bool write_protected = false;
1846 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1847 rmap_head = __gfn_to_rmap(gfn, i, slot);
1848 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1851 return write_protected;
1854 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1856 struct kvm_memory_slot *slot;
1858 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1859 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1862 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1865 struct rmap_iterator iter;
1868 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1869 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1871 pte_list_remove(rmap_head, sptep);
1878 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1879 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1882 return kvm_zap_rmapp(kvm, rmap_head);
1885 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1886 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1890 struct rmap_iterator iter;
1893 pte_t *ptep = (pte_t *)data;
1896 WARN_ON(pte_huge(*ptep));
1897 new_pfn = pte_pfn(*ptep);
1900 for_each_rmap_spte(rmap_head, &iter, sptep) {
1901 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1902 sptep, *sptep, gfn, level);
1906 if (pte_write(*ptep)) {
1907 pte_list_remove(rmap_head, sptep);
1910 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1911 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1913 new_spte &= ~PT_WRITABLE_MASK;
1914 new_spte &= ~SPTE_HOST_WRITEABLE;
1916 new_spte = mark_spte_for_access_track(new_spte);
1918 mmu_spte_clear_track_bits(sptep);
1919 mmu_spte_set(sptep, new_spte);
1923 if (need_flush && kvm_available_flush_tlb_with_range()) {
1924 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1931 struct slot_rmap_walk_iterator {
1933 struct kvm_memory_slot *slot;
1939 /* output fields. */
1941 struct kvm_rmap_head *rmap;
1944 /* private field. */
1945 struct kvm_rmap_head *end_rmap;
1949 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1951 iterator->level = level;
1952 iterator->gfn = iterator->start_gfn;
1953 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1954 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1959 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1960 struct kvm_memory_slot *slot, int start_level,
1961 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1963 iterator->slot = slot;
1964 iterator->start_level = start_level;
1965 iterator->end_level = end_level;
1966 iterator->start_gfn = start_gfn;
1967 iterator->end_gfn = end_gfn;
1969 rmap_walk_init_level(iterator, iterator->start_level);
1972 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1974 return !!iterator->rmap;
1977 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1979 if (++iterator->rmap <= iterator->end_rmap) {
1980 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1984 if (++iterator->level > iterator->end_level) {
1985 iterator->rmap = NULL;
1989 rmap_walk_init_level(iterator, iterator->level);
1992 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1993 _start_gfn, _end_gfn, _iter_) \
1994 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1995 _end_level_, _start_gfn, _end_gfn); \
1996 slot_rmap_walk_okay(_iter_); \
1997 slot_rmap_walk_next(_iter_))
1999 static int kvm_handle_hva_range(struct kvm *kvm,
2000 unsigned long start,
2003 int (*handler)(struct kvm *kvm,
2004 struct kvm_rmap_head *rmap_head,
2005 struct kvm_memory_slot *slot,
2008 unsigned long data))
2010 struct kvm_memslots *slots;
2011 struct kvm_memory_slot *memslot;
2012 struct slot_rmap_walk_iterator iterator;
2016 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
2017 slots = __kvm_memslots(kvm, i);
2018 kvm_for_each_memslot(memslot, slots) {
2019 unsigned long hva_start, hva_end;
2020 gfn_t gfn_start, gfn_end;
2022 hva_start = max(start, memslot->userspace_addr);
2023 hva_end = min(end, memslot->userspace_addr +
2024 (memslot->npages << PAGE_SHIFT));
2025 if (hva_start >= hva_end)
2028 * {gfn(page) | page intersects with [hva_start, hva_end)} =
2029 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
2031 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
2032 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
2034 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
2035 PT_MAX_HUGEPAGE_LEVEL,
2036 gfn_start, gfn_end - 1,
2038 ret |= handler(kvm, iterator.rmap, memslot,
2039 iterator.gfn, iterator.level, data);
2046 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
2048 int (*handler)(struct kvm *kvm,
2049 struct kvm_rmap_head *rmap_head,
2050 struct kvm_memory_slot *slot,
2051 gfn_t gfn, int level,
2052 unsigned long data))
2054 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
2057 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
2059 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
2062 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
2064 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
2067 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
2068 struct kvm_memory_slot *slot, gfn_t gfn, int level,
2072 struct rmap_iterator uninitialized_var(iter);
2075 for_each_rmap_spte(rmap_head, &iter, sptep)
2076 young |= mmu_spte_age(sptep);
2078 trace_kvm_age_page(gfn, level, slot, young);
2082 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
2083 struct kvm_memory_slot *slot, gfn_t gfn,
2084 int level, unsigned long data)
2087 struct rmap_iterator iter;
2089 for_each_rmap_spte(rmap_head, &iter, sptep)
2090 if (is_accessed_spte(*sptep))
2095 #define RMAP_RECYCLE_THRESHOLD 1000
2097 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
2099 struct kvm_rmap_head *rmap_head;
2100 struct kvm_mmu_page *sp;
2102 sp = page_header(__pa(spte));
2104 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
2106 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
2107 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
2108 KVM_PAGES_PER_HPAGE(sp->role.level));
2111 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
2113 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
2116 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2118 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
2122 static int is_empty_shadow_page(u64 *spt)
2127 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
2128 if (is_shadow_present_pte(*pos)) {
2129 printk(KERN_ERR "%s: %p %llx\n", __func__,
2138 * This value is the sum of all of the kvm instances's
2139 * kvm->arch.n_used_mmu_pages values. We need a global,
2140 * aggregate version in order to make the slab shrinker
2143 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
2145 kvm->arch.n_used_mmu_pages += nr;
2146 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2149 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2151 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2152 hlist_del(&sp->hash_link);
2153 list_del(&sp->link);
2154 free_page((unsigned long)sp->spt);
2155 if (!sp->role.direct)
2156 free_page((unsigned long)sp->gfns);
2157 kmem_cache_free(mmu_page_header_cache, sp);
2160 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2162 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2165 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2166 struct kvm_mmu_page *sp, u64 *parent_pte)
2171 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2174 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2177 __pte_list_remove(parent_pte, &sp->parent_ptes);
2180 static void drop_parent_pte(struct kvm_mmu_page *sp,
2183 mmu_page_remove_parent_pte(sp, parent_pte);
2184 mmu_spte_clear_no_track(parent_pte);
2187 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2189 struct kvm_mmu_page *sp;
2191 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2192 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2194 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2195 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2198 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
2199 * depends on valid pages being added to the head of the list. See
2200 * comments in kvm_zap_obsolete_pages().
2202 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2203 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2204 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2208 static void mark_unsync(u64 *spte);
2209 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2212 struct rmap_iterator iter;
2214 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2219 static void mark_unsync(u64 *spte)
2221 struct kvm_mmu_page *sp;
2224 sp = page_header(__pa(spte));
2225 index = spte - sp->spt;
2226 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2228 if (sp->unsync_children++)
2230 kvm_mmu_mark_parents_unsync(sp);
2233 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2234 struct kvm_mmu_page *sp)
2239 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2243 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2244 struct kvm_mmu_page *sp, u64 *spte,
2250 #define KVM_PAGE_ARRAY_NR 16
2252 struct kvm_mmu_pages {
2253 struct mmu_page_and_offset {
2254 struct kvm_mmu_page *sp;
2256 } page[KVM_PAGE_ARRAY_NR];
2260 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2266 for (i=0; i < pvec->nr; i++)
2267 if (pvec->page[i].sp == sp)
2270 pvec->page[pvec->nr].sp = sp;
2271 pvec->page[pvec->nr].idx = idx;
2273 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2276 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2278 --sp->unsync_children;
2279 WARN_ON((int)sp->unsync_children < 0);
2280 __clear_bit(idx, sp->unsync_child_bitmap);
2283 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2284 struct kvm_mmu_pages *pvec)
2286 int i, ret, nr_unsync_leaf = 0;
2288 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2289 struct kvm_mmu_page *child;
2290 u64 ent = sp->spt[i];
2292 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2293 clear_unsync_child_bit(sp, i);
2297 child = page_header(ent & PT64_BASE_ADDR_MASK);
2299 if (child->unsync_children) {
2300 if (mmu_pages_add(pvec, child, i))
2303 ret = __mmu_unsync_walk(child, pvec);
2305 clear_unsync_child_bit(sp, i);
2307 } else if (ret > 0) {
2308 nr_unsync_leaf += ret;
2311 } else if (child->unsync) {
2313 if (mmu_pages_add(pvec, child, i))
2316 clear_unsync_child_bit(sp, i);
2319 return nr_unsync_leaf;
2322 #define INVALID_INDEX (-1)
2324 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2325 struct kvm_mmu_pages *pvec)
2328 if (!sp->unsync_children)
2331 mmu_pages_add(pvec, sp, INVALID_INDEX);
2332 return __mmu_unsync_walk(sp, pvec);
2335 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2337 WARN_ON(!sp->unsync);
2338 trace_kvm_mmu_sync_page(sp);
2340 --kvm->stat.mmu_unsync;
2343 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2344 struct list_head *invalid_list);
2345 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2346 struct list_head *invalid_list);
2349 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2350 hlist_for_each_entry(_sp, \
2351 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2352 if (is_obsolete_sp((_kvm), (_sp))) { \
2355 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2356 for_each_valid_sp(_kvm, _sp, _gfn) \
2357 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2359 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
2361 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
2364 /* @sp->gfn should be write-protected at the call site */
2365 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2366 struct list_head *invalid_list)
2368 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
2369 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2370 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2377 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2378 struct list_head *invalid_list,
2381 if (!remote_flush && list_empty(invalid_list))
2384 if (!list_empty(invalid_list))
2385 kvm_mmu_commit_zap_page(kvm, invalid_list);
2387 kvm_flush_remote_tlbs(kvm);
2391 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2392 struct list_head *invalid_list,
2393 bool remote_flush, bool local_flush)
2395 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
2399 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2402 #ifdef CONFIG_KVM_MMU_AUDIT
2403 #include "mmu_audit.c"
2405 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2406 static void mmu_audit_disable(void) { }
2409 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2411 return sp->role.invalid ||
2412 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2415 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2416 struct list_head *invalid_list)
2418 kvm_unlink_unsync_page(vcpu->kvm, sp);
2419 return __kvm_sync_page(vcpu, sp, invalid_list);
2422 /* @gfn should be write-protected at the call site */
2423 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2424 struct list_head *invalid_list)
2426 struct kvm_mmu_page *s;
2429 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2433 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2434 ret |= kvm_sync_page(vcpu, s, invalid_list);
2440 struct mmu_page_path {
2441 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2442 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2445 #define for_each_sp(pvec, sp, parents, i) \
2446 for (i = mmu_pages_first(&pvec, &parents); \
2447 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2448 i = mmu_pages_next(&pvec, &parents, i))
2450 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2451 struct mmu_page_path *parents,
2456 for (n = i+1; n < pvec->nr; n++) {
2457 struct kvm_mmu_page *sp = pvec->page[n].sp;
2458 unsigned idx = pvec->page[n].idx;
2459 int level = sp->role.level;
2461 parents->idx[level-1] = idx;
2462 if (level == PT_PAGE_TABLE_LEVEL)
2465 parents->parent[level-2] = sp;
2471 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2472 struct mmu_page_path *parents)
2474 struct kvm_mmu_page *sp;
2480 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2482 sp = pvec->page[0].sp;
2483 level = sp->role.level;
2484 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2486 parents->parent[level-2] = sp;
2488 /* Also set up a sentinel. Further entries in pvec are all
2489 * children of sp, so this element is never overwritten.
2491 parents->parent[level-1] = NULL;
2492 return mmu_pages_next(pvec, parents, 0);
2495 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2497 struct kvm_mmu_page *sp;
2498 unsigned int level = 0;
2501 unsigned int idx = parents->idx[level];
2502 sp = parents->parent[level];
2506 WARN_ON(idx == INVALID_INDEX);
2507 clear_unsync_child_bit(sp, idx);
2509 } while (!sp->unsync_children);
2512 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2513 struct kvm_mmu_page *parent)
2516 struct kvm_mmu_page *sp;
2517 struct mmu_page_path parents;
2518 struct kvm_mmu_pages pages;
2519 LIST_HEAD(invalid_list);
2522 while (mmu_unsync_walk(parent, &pages)) {
2523 bool protected = false;
2525 for_each_sp(pages, sp, parents, i)
2526 protected |= rmap_write_protect(vcpu, sp->gfn);
2529 kvm_flush_remote_tlbs(vcpu->kvm);
2533 for_each_sp(pages, sp, parents, i) {
2534 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2535 mmu_pages_clear_parents(&parents);
2537 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2538 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2539 cond_resched_lock(&vcpu->kvm->mmu_lock);
2544 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2547 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2549 atomic_set(&sp->write_flooding_count, 0);
2552 static void clear_sp_write_flooding_count(u64 *spte)
2554 struct kvm_mmu_page *sp = page_header(__pa(spte));
2556 __clear_sp_write_flooding_count(sp);
2559 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2566 union kvm_mmu_page_role role;
2568 struct kvm_mmu_page *sp;
2569 bool need_sync = false;
2572 LIST_HEAD(invalid_list);
2574 role = vcpu->arch.mmu->mmu_role.base;
2576 role.direct = direct;
2578 role.gpte_is_8_bytes = true;
2579 role.access = access;
2580 if (!vcpu->arch.mmu->direct_map
2581 && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2582 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2583 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2584 role.quadrant = quadrant;
2586 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2587 if (sp->gfn != gfn) {
2592 if (!need_sync && sp->unsync)
2595 if (sp->role.word != role.word)
2599 /* The page is good, but __kvm_sync_page might still end
2600 * up zapping it. If so, break in order to rebuild it.
2602 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2605 WARN_ON(!list_empty(&invalid_list));
2606 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2609 if (sp->unsync_children)
2610 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2612 __clear_sp_write_flooding_count(sp);
2613 trace_kvm_mmu_get_page(sp, false);
2617 ++vcpu->kvm->stat.mmu_cache_miss;
2619 sp = kvm_mmu_alloc_page(vcpu, direct);
2623 hlist_add_head(&sp->hash_link,
2624 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2627 * we should do write protection before syncing pages
2628 * otherwise the content of the synced shadow page may
2629 * be inconsistent with guest page table.
2631 account_shadowed(vcpu->kvm, sp);
2632 if (level == PT_PAGE_TABLE_LEVEL &&
2633 rmap_write_protect(vcpu, gfn))
2634 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2636 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2637 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2639 clear_page(sp->spt);
2640 trace_kvm_mmu_get_page(sp, true);
2642 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2644 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2645 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2649 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2650 struct kvm_vcpu *vcpu, hpa_t root,
2653 iterator->addr = addr;
2654 iterator->shadow_addr = root;
2655 iterator->level = vcpu->arch.mmu->shadow_root_level;
2657 if (iterator->level == PT64_ROOT_4LEVEL &&
2658 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2659 !vcpu->arch.mmu->direct_map)
2662 if (iterator->level == PT32E_ROOT_LEVEL) {
2664 * prev_root is currently only used for 64-bit hosts. So only
2665 * the active root_hpa is valid here.
2667 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2669 iterator->shadow_addr
2670 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2671 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2673 if (!iterator->shadow_addr)
2674 iterator->level = 0;
2678 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2679 struct kvm_vcpu *vcpu, u64 addr)
2681 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2685 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2687 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2690 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2691 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2695 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2698 if (is_last_spte(spte, iterator->level)) {
2699 iterator->level = 0;
2703 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2707 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2709 __shadow_walk_next(iterator, *iterator->sptep);
2712 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2713 struct kvm_mmu_page *sp)
2717 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2719 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2720 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2722 if (sp_ad_disabled(sp))
2723 spte |= SPTE_AD_DISABLED_MASK;
2725 spte |= shadow_accessed_mask;
2727 mmu_spte_set(sptep, spte);
2729 mmu_page_add_parent_pte(vcpu, sp, sptep);
2731 if (sp->unsync_children || sp->unsync)
2735 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2736 unsigned direct_access)
2738 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2739 struct kvm_mmu_page *child;
2742 * For the direct sp, if the guest pte's dirty bit
2743 * changed form clean to dirty, it will corrupt the
2744 * sp's access: allow writable in the read-only sp,
2745 * so we should update the spte at this point to get
2746 * a new sp with the correct access.
2748 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2749 if (child->role.access == direct_access)
2752 drop_parent_pte(child, sptep);
2753 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2757 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2761 struct kvm_mmu_page *child;
2764 if (is_shadow_present_pte(pte)) {
2765 if (is_last_spte(pte, sp->role.level)) {
2766 drop_spte(kvm, spte);
2767 if (is_large_pte(pte))
2770 child = page_header(pte & PT64_BASE_ADDR_MASK);
2771 drop_parent_pte(child, spte);
2776 if (is_mmio_spte(pte))
2777 mmu_spte_clear_no_track(spte);
2782 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2783 struct kvm_mmu_page *sp)
2787 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2788 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2791 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2794 struct rmap_iterator iter;
2796 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2797 drop_parent_pte(sp, sptep);
2800 static int mmu_zap_unsync_children(struct kvm *kvm,
2801 struct kvm_mmu_page *parent,
2802 struct list_head *invalid_list)
2805 struct mmu_page_path parents;
2806 struct kvm_mmu_pages pages;
2808 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2811 while (mmu_unsync_walk(parent, &pages)) {
2812 struct kvm_mmu_page *sp;
2814 for_each_sp(pages, sp, parents, i) {
2815 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2816 mmu_pages_clear_parents(&parents);
2824 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2825 struct kvm_mmu_page *sp,
2826 struct list_head *invalid_list,
2831 trace_kvm_mmu_prepare_zap_page(sp);
2832 ++kvm->stat.mmu_shadow_zapped;
2833 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2834 kvm_mmu_page_unlink_children(kvm, sp);
2835 kvm_mmu_unlink_parents(kvm, sp);
2837 /* Zapping children means active_mmu_pages has become unstable. */
2838 list_unstable = *nr_zapped;
2840 if (!sp->role.invalid && !sp->role.direct)
2841 unaccount_shadowed(kvm, sp);
2844 kvm_unlink_unsync_page(kvm, sp);
2845 if (!sp->root_count) {
2848 list_move(&sp->link, invalid_list);
2849 kvm_mod_used_mmu_pages(kvm, -1);
2851 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2854 * Obsolete pages cannot be used on any vCPUs, see the comment
2855 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2856 * treats invalid shadow pages as being obsolete.
2858 if (!is_obsolete_sp(kvm, sp))
2859 kvm_reload_remote_mmus(kvm);
2862 if (sp->lpage_disallowed)
2863 unaccount_huge_nx_page(kvm, sp);
2865 sp->role.invalid = 1;
2866 return list_unstable;
2869 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2870 struct list_head *invalid_list)
2874 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2878 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2879 struct list_head *invalid_list)
2881 struct kvm_mmu_page *sp, *nsp;
2883 if (list_empty(invalid_list))
2887 * We need to make sure everyone sees our modifications to
2888 * the page tables and see changes to vcpu->mode here. The barrier
2889 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2890 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2892 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2893 * guest mode and/or lockless shadow page table walks.
2895 kvm_flush_remote_tlbs(kvm);
2897 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2898 WARN_ON(!sp->role.invalid || sp->root_count);
2899 kvm_mmu_free_page(sp);
2903 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2904 struct list_head *invalid_list)
2906 struct kvm_mmu_page *sp;
2908 if (list_empty(&kvm->arch.active_mmu_pages))
2911 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2912 struct kvm_mmu_page, link);
2913 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2916 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2918 LIST_HEAD(invalid_list);
2920 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
2923 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
2924 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
2927 ++vcpu->kvm->stat.mmu_recycled;
2929 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2931 if (!kvm_mmu_available_pages(vcpu->kvm))
2937 * Changing the number of mmu pages allocated to the vm
2938 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2940 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2942 LIST_HEAD(invalid_list);
2944 spin_lock(&kvm->mmu_lock);
2946 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2947 /* Need to free some mmu pages to achieve the goal. */
2948 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2949 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2952 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2953 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2956 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2958 spin_unlock(&kvm->mmu_lock);
2961 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2963 struct kvm_mmu_page *sp;
2964 LIST_HEAD(invalid_list);
2967 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2969 spin_lock(&kvm->mmu_lock);
2970 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2971 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2974 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2976 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2977 spin_unlock(&kvm->mmu_lock);
2981 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2983 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2985 trace_kvm_mmu_unsync_page(sp);
2986 ++vcpu->kvm->stat.mmu_unsync;
2989 kvm_mmu_mark_parents_unsync(sp);
2992 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2995 struct kvm_mmu_page *sp;
2997 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3000 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
3007 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
3008 kvm_unsync_page(vcpu, sp);
3012 * We need to ensure that the marking of unsync pages is visible
3013 * before the SPTE is updated to allow writes because
3014 * kvm_mmu_sync_roots() checks the unsync flags without holding
3015 * the MMU lock and so can race with this. If the SPTE was updated
3016 * before the page had been marked as unsync-ed, something like the
3017 * following could happen:
3020 * ---------------------------------------------------------------------
3021 * 1.2 Host updates SPTE
3023 * 2.1 Guest writes a GPTE for GVA X.
3024 * (GPTE being in the guest page table shadowed
3025 * by the SP from CPU 1.)
3026 * This reads SPTE during the page table walk.
3027 * Since SPTE.W is read as 1, there is no
3030 * 2.2 Guest issues TLB flush.
3031 * That causes a VM Exit.
3033 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
3034 * Since it is false, so it just returns.
3036 * 2.4 Guest accesses GVA X.
3037 * Since the mapping in the SP was not updated,
3038 * so the old mapping for GVA X incorrectly
3042 * (sp->unsync = true)
3044 * The write barrier below ensures that 1.1 happens before 1.2 and thus
3045 * the situation in 2.4 does not arise. The implicit barrier in 2.2
3046 * pairs with this write barrier.
3053 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
3056 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
3058 * Some reserved pages, such as those from NVDIMM
3059 * DAX devices, are not for MMIO, and can be mapped
3060 * with cached memory type for better performance.
3061 * However, the above check misconceives those pages
3062 * as MMIO, and results in KVM mapping them with UC
3063 * memory type, which would hurt the performance.
3064 * Therefore, we check the host memory type in addition
3065 * and only treat UC/UC-/WC pages as MMIO.
3067 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
3069 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
3070 pfn_to_hpa(pfn + 1) - 1,
3074 /* Bits which may be returned by set_spte() */
3075 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
3076 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
3078 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
3079 unsigned pte_access, int level,
3080 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
3081 bool can_unsync, bool host_writable)
3085 struct kvm_mmu_page *sp;
3087 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
3090 sp = page_header(__pa(sptep));
3091 if (sp_ad_disabled(sp))
3092 spte |= SPTE_AD_DISABLED_MASK;
3093 else if (kvm_vcpu_ad_need_write_protect(vcpu))
3094 spte |= SPTE_AD_WRPROT_ONLY_MASK;
3097 * For the EPT case, shadow_present_mask is 0 if hardware
3098 * supports exec-only page table entries. In that case,
3099 * ACC_USER_MASK and shadow_user_mask are used to represent
3100 * read access. See FNAME(gpte_access) in paging_tmpl.h.
3102 spte |= shadow_present_mask;
3104 spte |= spte_shadow_accessed_mask(spte);
3106 if (level > PT_PAGE_TABLE_LEVEL && (pte_access & ACC_EXEC_MASK) &&
3107 is_nx_huge_page_enabled()) {
3108 pte_access &= ~ACC_EXEC_MASK;
3111 if (pte_access & ACC_EXEC_MASK)
3112 spte |= shadow_x_mask;
3114 spte |= shadow_nx_mask;
3116 if (pte_access & ACC_USER_MASK)
3117 spte |= shadow_user_mask;
3119 if (level > PT_PAGE_TABLE_LEVEL)
3120 spte |= PT_PAGE_SIZE_MASK;
3122 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
3123 kvm_is_mmio_pfn(pfn));
3126 spte |= SPTE_HOST_WRITEABLE;
3128 pte_access &= ~ACC_WRITE_MASK;
3130 if (!kvm_is_mmio_pfn(pfn))
3131 spte |= shadow_me_mask;
3133 spte |= (u64)pfn << PAGE_SHIFT;
3135 if (pte_access & ACC_WRITE_MASK) {
3138 * Other vcpu creates new sp in the window between
3139 * mapping_level() and acquiring mmu-lock. We can
3140 * allow guest to retry the access, the mapping can
3141 * be fixed if guest refault.
3143 if (level > PT_PAGE_TABLE_LEVEL &&
3144 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
3147 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
3150 * Optimization: for pte sync, if spte was writable the hash
3151 * lookup is unnecessary (and expensive). Write protection
3152 * is responsibility of mmu_get_page / kvm_sync_page.
3153 * Same reasoning can be applied to dirty page accounting.
3155 if (!can_unsync && is_writable_pte(*sptep))
3158 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
3159 pgprintk("%s: found shadow page for %llx, marking ro\n",
3161 ret |= SET_SPTE_WRITE_PROTECTED_PT;
3162 pte_access &= ~ACC_WRITE_MASK;
3163 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
3167 if (pte_access & ACC_WRITE_MASK) {
3168 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3169 spte |= spte_shadow_dirty_mask(spte);
3173 spte = mark_spte_for_access_track(spte);
3176 if (mmu_spte_update(sptep, spte))
3177 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
3182 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
3183 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
3184 bool speculative, bool host_writable)
3186 int was_rmapped = 0;
3189 int ret = RET_PF_RETRY;
3192 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3193 *sptep, write_fault, gfn);
3195 if (is_shadow_present_pte(*sptep)) {
3197 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3198 * the parent of the now unreachable PTE.
3200 if (level > PT_PAGE_TABLE_LEVEL &&
3201 !is_large_pte(*sptep)) {
3202 struct kvm_mmu_page *child;
3205 child = page_header(pte & PT64_BASE_ADDR_MASK);
3206 drop_parent_pte(child, sptep);
3208 } else if (pfn != spte_to_pfn(*sptep)) {
3209 pgprintk("hfn old %llx new %llx\n",
3210 spte_to_pfn(*sptep), pfn);
3211 drop_spte(vcpu->kvm, sptep);
3217 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3218 speculative, true, host_writable);
3219 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3221 ret = RET_PF_EMULATE;
3222 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3225 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3226 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3227 KVM_PAGES_PER_HPAGE(level));
3229 if (unlikely(is_mmio_spte(*sptep)))
3230 ret = RET_PF_EMULATE;
3232 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3233 trace_kvm_mmu_set_spte(level, gfn, sptep);
3234 if (!was_rmapped && is_large_pte(*sptep))
3235 ++vcpu->kvm->stat.lpages;
3237 if (is_shadow_present_pte(*sptep)) {
3239 rmap_count = rmap_add(vcpu, sptep, gfn);
3240 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3241 rmap_recycle(vcpu, sptep, gfn);
3248 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3251 struct kvm_memory_slot *slot;
3253 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3255 return KVM_PFN_ERR_FAULT;
3257 return gfn_to_pfn_memslot_atomic(slot, gfn);
3260 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3261 struct kvm_mmu_page *sp,
3262 u64 *start, u64 *end)
3264 struct page *pages[PTE_PREFETCH_NUM];
3265 struct kvm_memory_slot *slot;
3266 unsigned access = sp->role.access;
3270 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3271 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3275 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3279 for (i = 0; i < ret; i++, gfn++, start++) {
3280 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3281 page_to_pfn(pages[i]), true, true);
3288 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3289 struct kvm_mmu_page *sp, u64 *sptep)
3291 u64 *spte, *start = NULL;
3294 WARN_ON(!sp->role.direct);
3296 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3299 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3300 if (is_shadow_present_pte(*spte) || spte == sptep) {
3303 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3311 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3313 struct kvm_mmu_page *sp;
3315 sp = page_header(__pa(sptep));
3318 * Without accessed bits, there's no way to distinguish between
3319 * actually accessed translations and prefetched, so disable pte
3320 * prefetch if accessed bits aren't available.
3322 if (sp_ad_disabled(sp))
3325 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3328 __direct_pte_prefetch(vcpu, sp, sptep);
3331 static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it,
3332 gfn_t gfn, kvm_pfn_t *pfnp, int *levelp)
3334 int level = *levelp;
3335 u64 spte = *it.sptep;
3337 if (it.level == level && level > PT_PAGE_TABLE_LEVEL &&
3338 is_nx_huge_page_enabled() &&
3339 is_shadow_present_pte(spte) &&
3340 !is_large_pte(spte)) {
3342 * A small SPTE exists for this pfn, but FNAME(fetch)
3343 * and __direct_map would like to create a large PTE
3344 * instead: just force them to go down another level,
3345 * patching back for them into pfn the next 9 bits of
3348 u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1);
3349 *pfnp |= gfn & page_mask;
3354 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write,
3355 int map_writable, int level, kvm_pfn_t pfn,
3356 bool prefault, bool lpage_disallowed)
3358 struct kvm_shadow_walk_iterator it;
3359 struct kvm_mmu_page *sp;
3361 gfn_t gfn = gpa >> PAGE_SHIFT;
3362 gfn_t base_gfn = gfn;
3364 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3365 return RET_PF_RETRY;
3367 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3368 for_each_shadow_entry(vcpu, gpa, it) {
3370 * We cannot overwrite existing page tables with an NX
3371 * large page, as the leaf could be executable.
3373 disallowed_hugepage_adjust(it, gfn, &pfn, &level);
3375 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3376 if (it.level == level)
3379 drop_large_spte(vcpu, it.sptep);
3380 if (!is_shadow_present_pte(*it.sptep)) {
3381 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3382 it.level - 1, true, ACC_ALL);
3384 link_shadow_page(vcpu, it.sptep, sp);
3385 if (lpage_disallowed)
3386 account_huge_nx_page(vcpu->kvm, sp);
3390 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3391 write, level, base_gfn, pfn, prefault,
3393 direct_pte_prefetch(vcpu, it.sptep);
3394 ++vcpu->stat.pf_fixed;
3398 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3400 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3403 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3406 * Do not cache the mmio info caused by writing the readonly gfn
3407 * into the spte otherwise read access on readonly gfn also can
3408 * caused mmio page fault and treat it as mmio access.
3410 if (pfn == KVM_PFN_ERR_RO_FAULT)
3411 return RET_PF_EMULATE;
3413 if (pfn == KVM_PFN_ERR_HWPOISON) {
3414 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3415 return RET_PF_RETRY;
3421 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3422 gfn_t gfn, kvm_pfn_t *pfnp,
3425 kvm_pfn_t pfn = *pfnp;
3426 int level = *levelp;
3429 * Check if it's a transparent hugepage. If this would be an
3430 * hugetlbfs page, level wouldn't be set to
3431 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3434 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3435 !kvm_is_zone_device_pfn(pfn) && level == PT_PAGE_TABLE_LEVEL &&
3436 PageTransCompoundMap(pfn_to_page(pfn))) {
3439 * mmu_notifier_retry was successful and we hold the
3440 * mmu_lock here, so the pmd can't become splitting
3441 * from under us, and in turn
3442 * __split_huge_page_refcount() can't run from under
3443 * us and we can safely transfer the refcount from
3444 * PG_tail to PG_head as we switch the pfn to tail to
3447 *levelp = level = PT_DIRECTORY_LEVEL;
3448 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3449 VM_BUG_ON((gfn & mask) != (pfn & mask));
3451 kvm_release_pfn_clean(pfn);
3459 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3460 kvm_pfn_t pfn, unsigned access, int *ret_val)
3462 /* The pfn is invalid, report the error! */
3463 if (unlikely(is_error_pfn(pfn))) {
3464 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3468 if (unlikely(is_noslot_pfn(pfn)))
3469 vcpu_cache_mmio_info(vcpu, gva, gfn,
3470 access & shadow_mmio_access_mask);
3475 static bool page_fault_can_be_fast(u32 error_code)
3478 * Do not fix the mmio spte with invalid generation number which
3479 * need to be updated by slow page fault path.
3481 if (unlikely(error_code & PFERR_RSVD_MASK))
3484 /* See if the page fault is due to an NX violation */
3485 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3486 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3490 * #PF can be fast if:
3491 * 1. The shadow page table entry is not present, which could mean that
3492 * the fault is potentially caused by access tracking (if enabled).
3493 * 2. The shadow page table entry is present and the fault
3494 * is caused by write-protect, that means we just need change the W
3495 * bit of the spte which can be done out of mmu-lock.
3497 * However, if access tracking is disabled we know that a non-present
3498 * page must be a genuine page fault where we have to create a new SPTE.
3499 * So, if access tracking is disabled, we return true only for write
3500 * accesses to a present page.
3503 return shadow_acc_track_mask != 0 ||
3504 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3505 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3509 * Returns true if the SPTE was fixed successfully. Otherwise,
3510 * someone else modified the SPTE from its original value.
3513 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3514 u64 *sptep, u64 old_spte, u64 new_spte)
3518 WARN_ON(!sp->role.direct);
3521 * Theoretically we could also set dirty bit (and flush TLB) here in
3522 * order to eliminate unnecessary PML logging. See comments in
3523 * set_spte. But fast_page_fault is very unlikely to happen with PML
3524 * enabled, so we do not do this. This might result in the same GPA
3525 * to be logged in PML buffer again when the write really happens, and
3526 * eventually to be called by mark_page_dirty twice. But it's also no
3527 * harm. This also avoids the TLB flush needed after setting dirty bit
3528 * so non-PML cases won't be impacted.
3530 * Compare with set_spte where instead shadow_dirty_mask is set.
3532 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3535 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3537 * The gfn of direct spte is stable since it is
3538 * calculated by sp->gfn.
3540 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3541 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3547 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3549 if (fault_err_code & PFERR_FETCH_MASK)
3550 return is_executable_pte(spte);
3552 if (fault_err_code & PFERR_WRITE_MASK)
3553 return is_writable_pte(spte);
3555 /* Fault was on Read access */
3556 return spte & PT_PRESENT_MASK;
3561 * - true: let the vcpu to access on the same address again.
3562 * - false: let the real page fault path to fix it.
3564 static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, int level,
3567 struct kvm_shadow_walk_iterator iterator;
3568 struct kvm_mmu_page *sp;
3569 bool fault_handled = false;
3571 uint retry_count = 0;
3573 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3576 if (!page_fault_can_be_fast(error_code))
3579 walk_shadow_page_lockless_begin(vcpu);
3584 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3585 if (!is_shadow_present_pte(spte) ||
3586 iterator.level < level)
3589 sp = page_header(__pa(iterator.sptep));
3590 if (!is_last_spte(spte, sp->role.level))
3594 * Check whether the memory access that caused the fault would
3595 * still cause it if it were to be performed right now. If not,
3596 * then this is a spurious fault caused by TLB lazily flushed,
3597 * or some other CPU has already fixed the PTE after the
3598 * current CPU took the fault.
3600 * Need not check the access of upper level table entries since
3601 * they are always ACC_ALL.
3603 if (is_access_allowed(error_code, spte)) {
3604 fault_handled = true;
3610 if (is_access_track_spte(spte))
3611 new_spte = restore_acc_track_spte(new_spte);
3614 * Currently, to simplify the code, write-protection can
3615 * be removed in the fast path only if the SPTE was
3616 * write-protected for dirty-logging or access tracking.
3618 if ((error_code & PFERR_WRITE_MASK) &&
3619 spte_can_locklessly_be_made_writable(spte))
3621 new_spte |= PT_WRITABLE_MASK;
3624 * Do not fix write-permission on the large spte. Since
3625 * we only dirty the first page into the dirty-bitmap in
3626 * fast_pf_fix_direct_spte(), other pages are missed
3627 * if its slot has dirty logging enabled.
3629 * Instead, we let the slow page fault path create a
3630 * normal spte to fix the access.
3632 * See the comments in kvm_arch_commit_memory_region().
3634 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3638 /* Verify that the fault can be handled in the fast path */
3639 if (new_spte == spte ||
3640 !is_access_allowed(error_code, new_spte))
3644 * Currently, fast page fault only works for direct mapping
3645 * since the gfn is not stable for indirect shadow page. See
3646 * Documentation/virt/kvm/locking.txt to get more detail.
3648 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3649 iterator.sptep, spte,
3654 if (++retry_count > 4) {
3655 printk_once(KERN_WARNING
3656 "kvm: Fast #PF retrying more than 4 times.\n");
3662 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3663 spte, fault_handled);
3664 walk_shadow_page_lockless_end(vcpu);
3666 return fault_handled;
3669 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3670 struct list_head *invalid_list)
3672 struct kvm_mmu_page *sp;
3674 if (!VALID_PAGE(*root_hpa))
3677 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3679 if (!sp->root_count && sp->role.invalid)
3680 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3682 *root_hpa = INVALID_PAGE;
3685 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3686 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3687 ulong roots_to_free)
3690 LIST_HEAD(invalid_list);
3691 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3693 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3695 /* Before acquiring the MMU lock, see if we need to do any real work. */
3696 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3697 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3698 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3699 VALID_PAGE(mmu->prev_roots[i].hpa))
3702 if (i == KVM_MMU_NUM_PREV_ROOTS)
3706 spin_lock(&vcpu->kvm->mmu_lock);
3708 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3709 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3710 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3713 if (free_active_root) {
3714 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3715 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3716 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3719 for (i = 0; i < 4; ++i)
3720 if (mmu->pae_root[i] != 0)
3721 mmu_free_root_page(vcpu->kvm,
3724 mmu->root_hpa = INVALID_PAGE;
3729 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3730 spin_unlock(&vcpu->kvm->mmu_lock);
3732 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3734 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3738 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3739 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3746 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3748 struct kvm_mmu_page *sp;
3751 if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3752 spin_lock(&vcpu->kvm->mmu_lock);
3753 if(make_mmu_pages_available(vcpu) < 0) {
3754 spin_unlock(&vcpu->kvm->mmu_lock);
3757 sp = kvm_mmu_get_page(vcpu, 0, 0,
3758 vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
3760 spin_unlock(&vcpu->kvm->mmu_lock);
3761 vcpu->arch.mmu->root_hpa = __pa(sp->spt);
3762 } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) {
3763 for (i = 0; i < 4; ++i) {
3764 hpa_t root = vcpu->arch.mmu->pae_root[i];
3766 MMU_WARN_ON(VALID_PAGE(root));
3767 spin_lock(&vcpu->kvm->mmu_lock);
3768 if (make_mmu_pages_available(vcpu) < 0) {
3769 spin_unlock(&vcpu->kvm->mmu_lock);
3772 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3773 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3774 root = __pa(sp->spt);
3776 spin_unlock(&vcpu->kvm->mmu_lock);
3777 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3779 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3782 vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3787 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3789 struct kvm_mmu_page *sp;
3791 gfn_t root_gfn, root_cr3;
3794 root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3795 root_gfn = root_cr3 >> PAGE_SHIFT;
3797 if (mmu_check_root(vcpu, root_gfn))
3801 * Do we shadow a long mode page table? If so we need to
3802 * write-protect the guests page table root.
3804 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3805 hpa_t root = vcpu->arch.mmu->root_hpa;
3807 MMU_WARN_ON(VALID_PAGE(root));
3809 spin_lock(&vcpu->kvm->mmu_lock);
3810 if (make_mmu_pages_available(vcpu) < 0) {
3811 spin_unlock(&vcpu->kvm->mmu_lock);
3814 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3815 vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
3816 root = __pa(sp->spt);
3818 spin_unlock(&vcpu->kvm->mmu_lock);
3819 vcpu->arch.mmu->root_hpa = root;
3824 * We shadow a 32 bit page table. This may be a legacy 2-level
3825 * or a PAE 3-level page table. In either case we need to be aware that
3826 * the shadow page table may be a PAE or a long mode page table.
3828 pm_mask = PT_PRESENT_MASK;
3829 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3830 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3832 for (i = 0; i < 4; ++i) {
3833 hpa_t root = vcpu->arch.mmu->pae_root[i];
3835 MMU_WARN_ON(VALID_PAGE(root));
3836 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3837 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3838 if (!(pdptr & PT_PRESENT_MASK)) {
3839 vcpu->arch.mmu->pae_root[i] = 0;
3842 root_gfn = pdptr >> PAGE_SHIFT;
3843 if (mmu_check_root(vcpu, root_gfn))
3846 spin_lock(&vcpu->kvm->mmu_lock);
3847 if (make_mmu_pages_available(vcpu) < 0) {
3848 spin_unlock(&vcpu->kvm->mmu_lock);
3851 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3853 root = __pa(sp->spt);
3855 spin_unlock(&vcpu->kvm->mmu_lock);
3857 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3859 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3862 * If we shadow a 32 bit page table with a long mode page
3863 * table we enter this path.
3865 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3866 if (vcpu->arch.mmu->lm_root == NULL) {
3868 * The additional page necessary for this is only
3869 * allocated on demand.
3874 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3875 if (lm_root == NULL)
3878 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3880 vcpu->arch.mmu->lm_root = lm_root;
3883 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3887 vcpu->arch.mmu->root_cr3 = root_cr3;
3892 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3894 if (vcpu->arch.mmu->direct_map)
3895 return mmu_alloc_direct_roots(vcpu);
3897 return mmu_alloc_shadow_roots(vcpu);
3900 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3903 struct kvm_mmu_page *sp;
3905 if (vcpu->arch.mmu->direct_map)
3908 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3911 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3913 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3914 hpa_t root = vcpu->arch.mmu->root_hpa;
3915 sp = page_header(root);
3918 * Even if another CPU was marking the SP as unsync-ed
3919 * simultaneously, any guest page table changes are not
3920 * guaranteed to be visible anyway until this VCPU issues a TLB
3921 * flush strictly after those changes are made. We only need to
3922 * ensure that the other CPU sets these flags before any actual
3923 * changes to the page tables are made. The comments in
3924 * mmu_need_write_protect() describe what could go wrong if this
3925 * requirement isn't satisfied.
3927 if (!smp_load_acquire(&sp->unsync) &&
3928 !smp_load_acquire(&sp->unsync_children))
3931 spin_lock(&vcpu->kvm->mmu_lock);
3932 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3934 mmu_sync_children(vcpu, sp);
3936 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3937 spin_unlock(&vcpu->kvm->mmu_lock);
3941 spin_lock(&vcpu->kvm->mmu_lock);
3942 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3944 for (i = 0; i < 4; ++i) {
3945 hpa_t root = vcpu->arch.mmu->pae_root[i];
3947 if (root && VALID_PAGE(root)) {
3948 root &= PT64_BASE_ADDR_MASK;
3949 sp = page_header(root);
3950 mmu_sync_children(vcpu, sp);
3954 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3955 spin_unlock(&vcpu->kvm->mmu_lock);
3957 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3959 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3960 u32 access, struct x86_exception *exception)
3963 exception->error_code = 0;
3967 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3969 struct x86_exception *exception)
3972 exception->error_code = 0;
3973 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3977 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3979 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3981 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3982 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3985 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3987 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3990 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3992 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3995 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3998 * A nested guest cannot use the MMIO cache if it is using nested
3999 * page tables, because cr2 is a nGPA while the cache stores GPAs.
4001 if (mmu_is_nested(vcpu))
4005 return vcpu_match_mmio_gpa(vcpu, addr);
4007 return vcpu_match_mmio_gva(vcpu, addr);
4010 /* return true if reserved bit is detected on spte. */
4012 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
4014 struct kvm_shadow_walk_iterator iterator;
4015 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
4017 bool reserved = false;
4019 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
4022 walk_shadow_page_lockless_begin(vcpu);
4024 for (shadow_walk_init(&iterator, vcpu, addr),
4025 leaf = root = iterator.level;
4026 shadow_walk_okay(&iterator);
4027 __shadow_walk_next(&iterator, spte)) {
4028 spte = mmu_spte_get_lockless(iterator.sptep);
4030 sptes[leaf - 1] = spte;
4033 if (!is_shadow_present_pte(spte))
4036 reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte,
4040 walk_shadow_page_lockless_end(vcpu);
4043 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
4045 while (root > leaf) {
4046 pr_err("------ spte 0x%llx level %d.\n",
4047 sptes[root - 1], root);
4056 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
4061 if (mmio_info_in_cache(vcpu, addr, direct))
4062 return RET_PF_EMULATE;
4064 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
4065 if (WARN_ON(reserved))
4068 if (is_mmio_spte(spte)) {
4069 gfn_t gfn = get_mmio_spte_gfn(spte);
4070 unsigned access = get_mmio_spte_access(spte);
4072 if (!check_mmio_spte(vcpu, spte))
4073 return RET_PF_INVALID;
4078 trace_handle_mmio_page_fault(addr, gfn, access);
4079 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
4080 return RET_PF_EMULATE;
4084 * If the page table is zapped by other cpus, let CPU fault again on
4087 return RET_PF_RETRY;
4090 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
4091 u32 error_code, gfn_t gfn)
4093 if (unlikely(error_code & PFERR_RSVD_MASK))
4096 if (!(error_code & PFERR_PRESENT_MASK) ||
4097 !(error_code & PFERR_WRITE_MASK))
4101 * guest is writing the page which is write tracked which can
4102 * not be fixed by page fault handler.
4104 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
4110 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
4112 struct kvm_shadow_walk_iterator iterator;
4115 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
4118 walk_shadow_page_lockless_begin(vcpu);
4119 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4120 clear_sp_write_flooding_count(iterator.sptep);
4121 if (!is_shadow_present_pte(spte))
4124 walk_shadow_page_lockless_end(vcpu);
4127 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
4130 struct kvm_arch_async_pf arch;
4132 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
4134 arch.direct_map = vcpu->arch.mmu->direct_map;
4135 arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu);
4137 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
4138 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
4141 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4142 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
4145 struct kvm_memory_slot *slot;
4149 * Don't expose private memslots to L2.
4151 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
4152 *pfn = KVM_PFN_NOSLOT;
4156 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4158 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4160 return false; /* *pfn has correct page already */
4162 if (!prefault && kvm_can_do_async_pf(vcpu)) {
4163 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
4164 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4165 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
4166 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4168 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
4172 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4176 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
4177 u32 error_code, bool prefault)
4182 unsigned long mmu_seq;
4183 gfn_t gfn = gpa >> PAGE_SHIFT;
4184 bool write = error_code & PFERR_WRITE_MASK;
4186 bool exec = error_code & PFERR_FETCH_MASK;
4187 bool lpage_disallowed = exec && is_nx_huge_page_enabled();
4190 /* Note, paging is disabled, ergo gva == gpa. */
4191 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
4195 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4196 return RET_PF_EMULATE;
4198 r = mmu_topup_memory_caches(vcpu);
4202 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4204 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4205 max_level = lpage_disallowed ? PT_PAGE_TABLE_LEVEL : PT_DIRECTORY_LEVEL;
4207 level = mapping_level(vcpu, gfn, &max_level);
4208 if (level > PT_PAGE_TABLE_LEVEL)
4209 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4211 if (fast_page_fault(vcpu, gpa, level, error_code))
4212 return RET_PF_RETRY;
4214 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4217 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4218 return RET_PF_RETRY;
4220 if (handle_abnormal_pfn(vcpu, gpa, gfn, pfn, ACC_ALL, &r))
4224 spin_lock(&vcpu->kvm->mmu_lock);
4225 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4227 if (make_mmu_pages_available(vcpu) < 0)
4229 if (likely(max_level > PT_PAGE_TABLE_LEVEL))
4230 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
4231 r = __direct_map(vcpu, gpa, write, map_writable, level, pfn,
4234 spin_unlock(&vcpu->kvm->mmu_lock);
4235 kvm_release_pfn_clean(pfn);
4239 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4240 u64 fault_address, char *insn, int insn_len)
4244 #ifndef CONFIG_X86_64
4245 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4246 if (WARN_ON_ONCE(fault_address >> 32))
4250 vcpu->arch.l1tf_flush_l1d = true;
4251 switch (vcpu->arch.apf.host_apf_reason) {
4253 trace_kvm_page_fault(fault_address, error_code);
4255 if (kvm_event_needs_reinjection(vcpu))
4256 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4257 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4260 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4261 vcpu->arch.apf.host_apf_reason = 0;
4262 local_irq_disable();
4263 kvm_async_pf_task_wait(fault_address, 0);
4266 case KVM_PV_REASON_PAGE_READY:
4267 vcpu->arch.apf.host_apf_reason = 0;
4268 local_irq_disable();
4269 kvm_async_pf_task_wake(fault_address);
4275 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4277 static int tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4283 gfn_t gfn = gpa >> PAGE_SHIFT;
4284 unsigned long mmu_seq;
4285 int write = error_code & PFERR_WRITE_MASK;
4287 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
4288 is_nx_huge_page_enabled();
4291 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4293 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4294 return RET_PF_EMULATE;
4296 r = mmu_topup_memory_caches(vcpu);
4300 for (max_level = PT_MAX_HUGEPAGE_LEVEL;
4301 max_level > PT_PAGE_TABLE_LEVEL;
4303 int page_num = KVM_PAGES_PER_HPAGE(max_level);
4304 gfn_t base = gfn & ~(page_num - 1);
4306 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4310 if (lpage_disallowed)
4311 max_level = PT_PAGE_TABLE_LEVEL;
4313 level = mapping_level(vcpu, gfn, &max_level);
4314 if (level > PT_PAGE_TABLE_LEVEL)
4315 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4317 if (fast_page_fault(vcpu, gpa, level, error_code))
4318 return RET_PF_RETRY;
4320 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4323 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4324 return RET_PF_RETRY;
4326 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4330 spin_lock(&vcpu->kvm->mmu_lock);
4331 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4333 if (make_mmu_pages_available(vcpu) < 0)
4335 if (likely(max_level > PT_PAGE_TABLE_LEVEL))
4336 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
4337 r = __direct_map(vcpu, gpa, write, map_writable, level, pfn,
4338 prefault, lpage_disallowed);
4340 spin_unlock(&vcpu->kvm->mmu_lock);
4341 kvm_release_pfn_clean(pfn);
4345 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4346 struct kvm_mmu *context)
4348 context->page_fault = nonpaging_page_fault;
4349 context->gva_to_gpa = nonpaging_gva_to_gpa;
4350 context->sync_page = nonpaging_sync_page;
4351 context->invlpg = nonpaging_invlpg;
4352 context->update_pte = nonpaging_update_pte;
4353 context->root_level = 0;
4354 context->shadow_root_level = PT32E_ROOT_LEVEL;
4355 context->direct_map = true;
4356 context->nx = false;
4360 * Find out if a previously cached root matching the new CR3/role is available.
4361 * The current root is also inserted into the cache.
4362 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4364 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4365 * false is returned. This root should now be freed by the caller.
4367 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4368 union kvm_mmu_page_role new_role)
4371 struct kvm_mmu_root_info root;
4372 struct kvm_mmu *mmu = vcpu->arch.mmu;
4374 root.cr3 = mmu->root_cr3;
4375 root.hpa = mmu->root_hpa;
4377 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4378 swap(root, mmu->prev_roots[i]);
4380 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4381 page_header(root.hpa) != NULL &&
4382 new_role.word == page_header(root.hpa)->role.word)
4386 mmu->root_hpa = root.hpa;
4387 mmu->root_cr3 = root.cr3;
4389 return i < KVM_MMU_NUM_PREV_ROOTS;
4392 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4393 union kvm_mmu_page_role new_role,
4394 bool skip_tlb_flush)
4396 struct kvm_mmu *mmu = vcpu->arch.mmu;
4399 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4400 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4401 * later if necessary.
4403 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4404 mmu->root_level >= PT64_ROOT_4LEVEL) {
4405 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4408 if (cached_root_available(vcpu, new_cr3, new_role)) {
4410 * It is possible that the cached previous root page is
4411 * obsolete because of a change in the MMU generation
4412 * number. However, changing the generation number is
4413 * accompanied by KVM_REQ_MMU_RELOAD, which will free
4414 * the root set here and allocate a new one.
4416 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4417 if (!skip_tlb_flush) {
4418 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4419 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4423 * The last MMIO access's GVA and GPA are cached in the
4424 * VCPU. When switching to a new CR3, that GVA->GPA
4425 * mapping may no longer be valid. So clear any cached
4426 * MMIO info even when we don't need to sync the shadow
4429 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4431 __clear_sp_write_flooding_count(
4432 page_header(mmu->root_hpa));
4441 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4442 union kvm_mmu_page_role new_role,
4443 bool skip_tlb_flush)
4445 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4446 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu,
4447 KVM_MMU_ROOT_CURRENT);
4450 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4452 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4455 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4457 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4459 return kvm_read_cr3(vcpu);
4462 static void inject_page_fault(struct kvm_vcpu *vcpu,
4463 struct x86_exception *fault)
4465 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
4468 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4469 unsigned access, int *nr_present)
4471 if (unlikely(is_mmio_spte(*sptep))) {
4472 if (gfn != get_mmio_spte_gfn(*sptep)) {
4473 mmu_spte_clear_no_track(sptep);
4478 mark_mmio_spte(vcpu, sptep, gfn, access);
4485 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4486 unsigned level, unsigned gpte)
4489 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4490 * If it is clear, there are no large pages at this level, so clear
4491 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4493 gpte &= level - mmu->last_nonleaf_level;
4496 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4497 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4498 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4500 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4502 return gpte & PT_PAGE_SIZE_MASK;
4505 #define PTTYPE_EPT 18 /* arbitrary */
4506 #define PTTYPE PTTYPE_EPT
4507 #include "paging_tmpl.h"
4511 #include "paging_tmpl.h"
4515 #include "paging_tmpl.h"
4519 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4520 struct rsvd_bits_validate *rsvd_check,
4521 int maxphyaddr, int level, bool nx, bool gbpages,
4524 u64 exb_bit_rsvd = 0;
4525 u64 gbpages_bit_rsvd = 0;
4526 u64 nonleaf_bit8_rsvd = 0;
4528 rsvd_check->bad_mt_xwr = 0;
4531 exb_bit_rsvd = rsvd_bits(63, 63);
4533 gbpages_bit_rsvd = rsvd_bits(7, 7);
4536 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4537 * leaf entries) on AMD CPUs only.
4540 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4543 case PT32_ROOT_LEVEL:
4544 /* no rsvd bits for 2 level 4K page table entries */
4545 rsvd_check->rsvd_bits_mask[0][1] = 0;
4546 rsvd_check->rsvd_bits_mask[0][0] = 0;
4547 rsvd_check->rsvd_bits_mask[1][0] =
4548 rsvd_check->rsvd_bits_mask[0][0];
4551 rsvd_check->rsvd_bits_mask[1][1] = 0;
4555 if (is_cpuid_PSE36())
4556 /* 36bits PSE 4MB page */
4557 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4559 /* 32 bits PSE 4MB page */
4560 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4562 case PT32E_ROOT_LEVEL:
4563 rsvd_check->rsvd_bits_mask[0][2] =
4564 rsvd_bits(maxphyaddr, 63) |
4565 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4566 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4567 rsvd_bits(maxphyaddr, 62); /* PDE */
4568 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4569 rsvd_bits(maxphyaddr, 62); /* PTE */
4570 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4571 rsvd_bits(maxphyaddr, 62) |
4572 rsvd_bits(13, 20); /* large page */
4573 rsvd_check->rsvd_bits_mask[1][0] =
4574 rsvd_check->rsvd_bits_mask[0][0];
4576 case PT64_ROOT_5LEVEL:
4577 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4578 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4579 rsvd_bits(maxphyaddr, 51);
4580 rsvd_check->rsvd_bits_mask[1][4] =
4581 rsvd_check->rsvd_bits_mask[0][4];
4583 case PT64_ROOT_4LEVEL:
4584 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4585 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4586 rsvd_bits(maxphyaddr, 51);
4587 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4588 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4589 rsvd_bits(maxphyaddr, 51);
4590 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4591 rsvd_bits(maxphyaddr, 51);
4592 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4593 rsvd_bits(maxphyaddr, 51);
4594 rsvd_check->rsvd_bits_mask[1][3] =
4595 rsvd_check->rsvd_bits_mask[0][3];
4596 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4597 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4599 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4600 rsvd_bits(maxphyaddr, 51) |
4601 rsvd_bits(13, 20); /* large page */
4602 rsvd_check->rsvd_bits_mask[1][0] =
4603 rsvd_check->rsvd_bits_mask[0][0];
4608 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4609 struct kvm_mmu *context)
4611 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4612 cpuid_maxphyaddr(vcpu), context->root_level,
4614 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4615 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4619 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4620 int maxphyaddr, bool execonly)
4624 rsvd_check->rsvd_bits_mask[0][4] =
4625 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4626 rsvd_check->rsvd_bits_mask[0][3] =
4627 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4628 rsvd_check->rsvd_bits_mask[0][2] =
4629 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4630 rsvd_check->rsvd_bits_mask[0][1] =
4631 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4632 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4635 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4636 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4637 rsvd_check->rsvd_bits_mask[1][2] =
4638 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4639 rsvd_check->rsvd_bits_mask[1][1] =
4640 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4641 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4643 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4644 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4645 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4646 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4647 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4649 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4650 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4652 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4655 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4656 struct kvm_mmu *context, bool execonly)
4658 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4659 cpuid_maxphyaddr(vcpu), execonly);
4663 * the page table on host is the shadow page table for the page
4664 * table in guest or amd nested guest, its mmu features completely
4665 * follow the features in guest.
4668 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4670 bool uses_nx = context->nx ||
4671 context->mmu_role.base.smep_andnot_wp;
4672 struct rsvd_bits_validate *shadow_zero_check;
4676 * Passing "true" to the last argument is okay; it adds a check
4677 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4679 shadow_zero_check = &context->shadow_zero_check;
4680 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4682 context->shadow_root_level, uses_nx,
4683 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4684 is_pse(vcpu), true);
4686 if (!shadow_me_mask)
4689 for (i = context->shadow_root_level; --i >= 0;) {
4690 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4691 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4695 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4697 static inline bool boot_cpu_is_amd(void)
4699 WARN_ON_ONCE(!tdp_enabled);
4700 return shadow_x_mask == 0;
4704 * the direct page table on host, use as much mmu features as
4705 * possible, however, kvm currently does not do execution-protection.
4708 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4709 struct kvm_mmu *context)
4711 struct rsvd_bits_validate *shadow_zero_check;
4714 shadow_zero_check = &context->shadow_zero_check;
4716 if (boot_cpu_is_amd())
4717 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4719 context->shadow_root_level, false,
4720 boot_cpu_has(X86_FEATURE_GBPAGES),
4723 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4727 if (!shadow_me_mask)
4730 for (i = context->shadow_root_level; --i >= 0;) {
4731 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4732 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4737 * as the comments in reset_shadow_zero_bits_mask() except it
4738 * is the shadow page table for intel nested guest.
4741 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4742 struct kvm_mmu *context, bool execonly)
4744 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4745 shadow_phys_bits, execonly);
4748 #define BYTE_MASK(access) \
4749 ((1 & (access) ? 2 : 0) | \
4750 (2 & (access) ? 4 : 0) | \
4751 (3 & (access) ? 8 : 0) | \
4752 (4 & (access) ? 16 : 0) | \
4753 (5 & (access) ? 32 : 0) | \
4754 (6 & (access) ? 64 : 0) | \
4755 (7 & (access) ? 128 : 0))
4758 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4759 struct kvm_mmu *mmu, bool ept)
4763 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4764 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4765 const u8 u = BYTE_MASK(ACC_USER_MASK);
4767 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4768 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4769 bool cr0_wp = is_write_protection(vcpu);
4771 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4772 unsigned pfec = byte << 1;
4775 * Each "*f" variable has a 1 bit for each UWX value
4776 * that causes a fault with the given PFEC.
4779 /* Faults from writes to non-writable pages */
4780 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4781 /* Faults from user mode accesses to supervisor pages */
4782 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4783 /* Faults from fetches of non-executable pages*/
4784 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4785 /* Faults from kernel mode fetches of user pages */
4787 /* Faults from kernel mode accesses of user pages */
4791 /* Faults from kernel mode accesses to user pages */
4792 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4794 /* Not really needed: !nx will cause pte.nx to fault */
4798 /* Allow supervisor writes if !cr0.wp */
4800 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4802 /* Disallow supervisor fetches of user code if cr4.smep */
4804 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4807 * SMAP:kernel-mode data accesses from user-mode
4808 * mappings should fault. A fault is considered
4809 * as a SMAP violation if all of the following
4810 * conditions are true:
4811 * - X86_CR4_SMAP is set in CR4
4812 * - A user page is accessed
4813 * - The access is not a fetch
4814 * - Page fault in kernel mode
4815 * - if CPL = 3 or X86_EFLAGS_AC is clear
4817 * Here, we cover the first three conditions.
4818 * The fourth is computed dynamically in permission_fault();
4819 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4820 * *not* subject to SMAP restrictions.
4823 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4826 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4831 * PKU is an additional mechanism by which the paging controls access to
4832 * user-mode addresses based on the value in the PKRU register. Protection
4833 * key violations are reported through a bit in the page fault error code.
4834 * Unlike other bits of the error code, the PK bit is not known at the
4835 * call site of e.g. gva_to_gpa; it must be computed directly in
4836 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4837 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4839 * In particular the following conditions come from the error code, the
4840 * page tables and the machine state:
4841 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4842 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4843 * - PK is always zero if U=0 in the page tables
4844 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4846 * The PKRU bitmask caches the result of these four conditions. The error
4847 * code (minus the P bit) and the page table's U bit form an index into the
4848 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4849 * with the two bits of the PKRU register corresponding to the protection key.
4850 * For the first three conditions above the bits will be 00, thus masking
4851 * away both AD and WD. For all reads or if the last condition holds, WD
4852 * only will be masked away.
4854 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4865 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4866 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4871 wp = is_write_protection(vcpu);
4873 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4874 unsigned pfec, pkey_bits;
4875 bool check_pkey, check_write, ff, uf, wf, pte_user;
4878 ff = pfec & PFERR_FETCH_MASK;
4879 uf = pfec & PFERR_USER_MASK;
4880 wf = pfec & PFERR_WRITE_MASK;
4882 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4883 pte_user = pfec & PFERR_RSVD_MASK;
4886 * Only need to check the access which is not an
4887 * instruction fetch and is to a user page.
4889 check_pkey = (!ff && pte_user);
4891 * write access is controlled by PKRU if it is a
4892 * user access or CR0.WP = 1.
4894 check_write = check_pkey && wf && (uf || wp);
4896 /* PKRU.AD stops both read and write access. */
4897 pkey_bits = !!check_pkey;
4898 /* PKRU.WD stops write access. */
4899 pkey_bits |= (!!check_write) << 1;
4901 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4905 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4907 unsigned root_level = mmu->root_level;
4909 mmu->last_nonleaf_level = root_level;
4910 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4911 mmu->last_nonleaf_level++;
4914 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4915 struct kvm_mmu *context,
4918 context->nx = is_nx(vcpu);
4919 context->root_level = level;
4921 reset_rsvds_bits_mask(vcpu, context);
4922 update_permission_bitmask(vcpu, context, false);
4923 update_pkru_bitmask(vcpu, context, false);
4924 update_last_nonleaf_level(vcpu, context);
4926 MMU_WARN_ON(!is_pae(vcpu));
4927 context->page_fault = paging64_page_fault;
4928 context->gva_to_gpa = paging64_gva_to_gpa;
4929 context->sync_page = paging64_sync_page;
4930 context->invlpg = paging64_invlpg;
4931 context->update_pte = paging64_update_pte;
4932 context->shadow_root_level = level;
4933 context->direct_map = false;
4936 static void paging64_init_context(struct kvm_vcpu *vcpu,
4937 struct kvm_mmu *context)
4939 int root_level = is_la57_mode(vcpu) ?
4940 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4942 paging64_init_context_common(vcpu, context, root_level);
4945 static void paging32_init_context(struct kvm_vcpu *vcpu,
4946 struct kvm_mmu *context)
4948 context->nx = false;
4949 context->root_level = PT32_ROOT_LEVEL;
4951 reset_rsvds_bits_mask(vcpu, context);
4952 update_permission_bitmask(vcpu, context, false);
4953 update_pkru_bitmask(vcpu, context, false);
4954 update_last_nonleaf_level(vcpu, context);
4956 context->page_fault = paging32_page_fault;
4957 context->gva_to_gpa = paging32_gva_to_gpa;
4958 context->sync_page = paging32_sync_page;
4959 context->invlpg = paging32_invlpg;
4960 context->update_pte = paging32_update_pte;
4961 context->shadow_root_level = PT32E_ROOT_LEVEL;
4962 context->direct_map = false;
4965 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4966 struct kvm_mmu *context)
4968 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4971 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4973 union kvm_mmu_extended_role ext = {0};
4975 ext.cr0_pg = !!is_paging(vcpu);
4976 ext.cr4_pae = !!is_pae(vcpu);
4977 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4978 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4979 ext.cr4_pse = !!is_pse(vcpu);
4980 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4981 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4982 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4989 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4992 union kvm_mmu_role role = {0};
4994 role.base.access = ACC_ALL;
4995 role.base.nxe = !!is_nx(vcpu);
4996 role.base.cr0_wp = is_write_protection(vcpu);
4997 role.base.smm = is_smm(vcpu);
4998 role.base.guest_mode = is_guest_mode(vcpu);
5003 role.ext = kvm_calc_mmu_role_ext(vcpu);
5008 static union kvm_mmu_role
5009 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
5011 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
5013 role.base.ad_disabled = (shadow_accessed_mask == 0);
5014 role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
5015 role.base.direct = true;
5016 role.base.gpte_is_8_bytes = true;
5021 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
5023 struct kvm_mmu *context = vcpu->arch.mmu;
5024 union kvm_mmu_role new_role =
5025 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
5027 new_role.base.word &= mmu_base_role_mask.word;
5028 if (new_role.as_u64 == context->mmu_role.as_u64)
5031 context->mmu_role.as_u64 = new_role.as_u64;
5032 context->page_fault = tdp_page_fault;
5033 context->sync_page = nonpaging_sync_page;
5034 context->invlpg = nonpaging_invlpg;
5035 context->update_pte = nonpaging_update_pte;
5036 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
5037 context->direct_map = true;
5038 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
5039 context->get_cr3 = get_cr3;
5040 context->get_pdptr = kvm_pdptr_read;
5041 context->inject_page_fault = kvm_inject_page_fault;
5043 if (!is_paging(vcpu)) {
5044 context->nx = false;
5045 context->gva_to_gpa = nonpaging_gva_to_gpa;
5046 context->root_level = 0;
5047 } else if (is_long_mode(vcpu)) {
5048 context->nx = is_nx(vcpu);
5049 context->root_level = is_la57_mode(vcpu) ?
5050 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5051 reset_rsvds_bits_mask(vcpu, context);
5052 context->gva_to_gpa = paging64_gva_to_gpa;
5053 } else if (is_pae(vcpu)) {
5054 context->nx = is_nx(vcpu);
5055 context->root_level = PT32E_ROOT_LEVEL;
5056 reset_rsvds_bits_mask(vcpu, context);
5057 context->gva_to_gpa = paging64_gva_to_gpa;
5059 context->nx = false;
5060 context->root_level = PT32_ROOT_LEVEL;
5061 reset_rsvds_bits_mask(vcpu, context);
5062 context->gva_to_gpa = paging32_gva_to_gpa;
5065 update_permission_bitmask(vcpu, context, false);
5066 update_pkru_bitmask(vcpu, context, false);
5067 update_last_nonleaf_level(vcpu, context);
5068 reset_tdp_shadow_zero_bits_mask(vcpu, context);
5071 static union kvm_mmu_role
5072 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
5074 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
5076 role.base.smep_andnot_wp = role.ext.cr4_smep &&
5077 !is_write_protection(vcpu);
5078 role.base.smap_andnot_wp = role.ext.cr4_smap &&
5079 !is_write_protection(vcpu);
5080 role.base.direct = !is_paging(vcpu);
5081 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
5083 if (!is_long_mode(vcpu))
5084 role.base.level = PT32E_ROOT_LEVEL;
5085 else if (is_la57_mode(vcpu))
5086 role.base.level = PT64_ROOT_5LEVEL;
5088 role.base.level = PT64_ROOT_4LEVEL;
5093 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
5095 struct kvm_mmu *context = vcpu->arch.mmu;
5096 union kvm_mmu_role new_role =
5097 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
5099 new_role.base.word &= mmu_base_role_mask.word;
5100 if (new_role.as_u64 == context->mmu_role.as_u64)
5103 if (!is_paging(vcpu))
5104 nonpaging_init_context(vcpu, context);
5105 else if (is_long_mode(vcpu))
5106 paging64_init_context(vcpu, context);
5107 else if (is_pae(vcpu))
5108 paging32E_init_context(vcpu, context);
5110 paging32_init_context(vcpu, context);
5112 context->mmu_role.as_u64 = new_role.as_u64;
5113 reset_shadow_zero_bits_mask(vcpu, context);
5115 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
5117 static union kvm_mmu_role
5118 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
5121 union kvm_mmu_role role = {0};
5123 /* SMM flag is inherited from root_mmu */
5124 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
5126 role.base.level = PT64_ROOT_4LEVEL;
5127 role.base.gpte_is_8_bytes = true;
5128 role.base.direct = false;
5129 role.base.ad_disabled = !accessed_dirty;
5130 role.base.guest_mode = true;
5131 role.base.access = ACC_ALL;
5134 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
5135 * SMAP variation to denote shadow EPT entries.
5137 role.base.cr0_wp = true;
5138 role.base.smap_andnot_wp = true;
5140 role.ext = kvm_calc_mmu_role_ext(vcpu);
5141 role.ext.execonly = execonly;
5146 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
5147 bool accessed_dirty, gpa_t new_eptp)
5149 struct kvm_mmu *context = vcpu->arch.mmu;
5150 union kvm_mmu_role new_role =
5151 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
5154 __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false);
5156 new_role.base.word &= mmu_base_role_mask.word;
5157 if (new_role.as_u64 == context->mmu_role.as_u64)
5160 context->shadow_root_level = PT64_ROOT_4LEVEL;
5163 context->ept_ad = accessed_dirty;
5164 context->page_fault = ept_page_fault;
5165 context->gva_to_gpa = ept_gva_to_gpa;
5166 context->sync_page = ept_sync_page;
5167 context->invlpg = ept_invlpg;
5168 context->update_pte = ept_update_pte;
5169 context->root_level = PT64_ROOT_4LEVEL;
5170 context->direct_map = false;
5171 context->mmu_role.as_u64 = new_role.as_u64;
5173 update_permission_bitmask(vcpu, context, true);
5174 update_pkru_bitmask(vcpu, context, true);
5175 update_last_nonleaf_level(vcpu, context);
5176 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
5177 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
5179 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
5181 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
5183 struct kvm_mmu *context = vcpu->arch.mmu;
5185 kvm_init_shadow_mmu(vcpu);
5186 context->set_cr3 = kvm_x86_ops->set_cr3;
5187 context->get_cr3 = get_cr3;
5188 context->get_pdptr = kvm_pdptr_read;
5189 context->inject_page_fault = kvm_inject_page_fault;
5192 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
5194 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
5195 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
5197 new_role.base.word &= mmu_base_role_mask.word;
5198 if (new_role.as_u64 == g_context->mmu_role.as_u64)
5201 g_context->mmu_role.as_u64 = new_role.as_u64;
5202 g_context->get_cr3 = get_cr3;
5203 g_context->get_pdptr = kvm_pdptr_read;
5204 g_context->inject_page_fault = kvm_inject_page_fault;
5207 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5208 * L1's nested page tables (e.g. EPT12). The nested translation
5209 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5210 * L2's page tables as the first level of translation and L1's
5211 * nested page tables as the second level of translation. Basically
5212 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5214 if (!is_paging(vcpu)) {
5215 g_context->nx = false;
5216 g_context->root_level = 0;
5217 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5218 } else if (is_long_mode(vcpu)) {
5219 g_context->nx = is_nx(vcpu);
5220 g_context->root_level = is_la57_mode(vcpu) ?
5221 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5222 reset_rsvds_bits_mask(vcpu, g_context);
5223 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5224 } else if (is_pae(vcpu)) {
5225 g_context->nx = is_nx(vcpu);
5226 g_context->root_level = PT32E_ROOT_LEVEL;
5227 reset_rsvds_bits_mask(vcpu, g_context);
5228 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5230 g_context->nx = false;
5231 g_context->root_level = PT32_ROOT_LEVEL;
5232 reset_rsvds_bits_mask(vcpu, g_context);
5233 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5236 update_permission_bitmask(vcpu, g_context, false);
5237 update_pkru_bitmask(vcpu, g_context, false);
5238 update_last_nonleaf_level(vcpu, g_context);
5241 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5246 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5248 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5249 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5252 if (mmu_is_nested(vcpu))
5253 init_kvm_nested_mmu(vcpu);
5254 else if (tdp_enabled)
5255 init_kvm_tdp_mmu(vcpu);
5257 init_kvm_softmmu(vcpu);
5259 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5261 static union kvm_mmu_page_role
5262 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5264 union kvm_mmu_role role;
5267 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5269 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5274 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5276 kvm_mmu_unload(vcpu);
5277 kvm_init_mmu(vcpu, true);
5279 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5281 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5285 r = mmu_topup_memory_caches(vcpu);
5288 r = mmu_alloc_roots(vcpu);
5289 kvm_mmu_sync_roots(vcpu);
5292 kvm_mmu_load_cr3(vcpu);
5293 kvm_x86_ops->tlb_flush(vcpu, true);
5297 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5299 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5301 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5302 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5303 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5304 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5306 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5308 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5309 struct kvm_mmu_page *sp, u64 *spte,
5312 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
5313 ++vcpu->kvm->stat.mmu_pde_zapped;
5317 ++vcpu->kvm->stat.mmu_pte_updated;
5318 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5321 static bool need_remote_flush(u64 old, u64 new)
5323 if (!is_shadow_present_pte(old))
5325 if (!is_shadow_present_pte(new))
5327 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5329 old ^= shadow_nx_mask;
5330 new ^= shadow_nx_mask;
5331 return (old & ~new & PT64_PERM_MASK) != 0;
5334 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5341 * Assume that the pte write on a page table of the same type
5342 * as the current vcpu paging mode since we update the sptes only
5343 * when they have the same mode.
5345 if (is_pae(vcpu) && *bytes == 4) {
5346 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5351 if (*bytes == 4 || *bytes == 8) {
5352 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5361 * If we're seeing too many writes to a page, it may no longer be a page table,
5362 * or we may be forking, in which case it is better to unmap the page.
5364 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5367 * Skip write-flooding detected for the sp whose level is 1, because
5368 * it can become unsync, then the guest page is not write-protected.
5370 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5373 atomic_inc(&sp->write_flooding_count);
5374 return atomic_read(&sp->write_flooding_count) >= 3;
5378 * Misaligned accesses are too much trouble to fix up; also, they usually
5379 * indicate a page is not used as a page table.
5381 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5384 unsigned offset, pte_size, misaligned;
5386 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5387 gpa, bytes, sp->role.word);
5389 offset = offset_in_page(gpa);
5390 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5393 * Sometimes, the OS only writes the last one bytes to update status
5394 * bits, for example, in linux, andb instruction is used in clear_bit().
5396 if (!(offset & (pte_size - 1)) && bytes == 1)
5399 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5400 misaligned |= bytes < 4;
5405 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5407 unsigned page_offset, quadrant;
5411 page_offset = offset_in_page(gpa);
5412 level = sp->role.level;
5414 if (!sp->role.gpte_is_8_bytes) {
5415 page_offset <<= 1; /* 32->64 */
5417 * A 32-bit pde maps 4MB while the shadow pdes map
5418 * only 2MB. So we need to double the offset again
5419 * and zap two pdes instead of one.
5421 if (level == PT32_ROOT_LEVEL) {
5422 page_offset &= ~7; /* kill rounding error */
5426 quadrant = page_offset >> PAGE_SHIFT;
5427 page_offset &= ~PAGE_MASK;
5428 if (quadrant != sp->role.quadrant)
5432 spte = &sp->spt[page_offset / sizeof(*spte)];
5436 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5437 const u8 *new, int bytes,
5438 struct kvm_page_track_notifier_node *node)
5440 gfn_t gfn = gpa >> PAGE_SHIFT;
5441 struct kvm_mmu_page *sp;
5442 LIST_HEAD(invalid_list);
5443 u64 entry, gentry, *spte;
5445 bool remote_flush, local_flush;
5448 * If we don't have indirect shadow pages, it means no page is
5449 * write-protected, so we can exit simply.
5451 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5454 remote_flush = local_flush = false;
5456 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5459 * No need to care whether allocation memory is successful
5460 * or not since pte prefetch is skiped if it does not have
5461 * enough objects in the cache.
5463 mmu_topup_memory_caches(vcpu);
5465 spin_lock(&vcpu->kvm->mmu_lock);
5467 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5469 ++vcpu->kvm->stat.mmu_pte_write;
5470 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5472 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5473 if (detect_write_misaligned(sp, gpa, bytes) ||
5474 detect_write_flooding(sp)) {
5475 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5476 ++vcpu->kvm->stat.mmu_flooded;
5480 spte = get_written_sptes(sp, gpa, &npte);
5486 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5489 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5491 !((sp->role.word ^ base_role)
5492 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5493 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5494 if (need_remote_flush(entry, *spte))
5495 remote_flush = true;
5499 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5500 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5501 spin_unlock(&vcpu->kvm->mmu_lock);
5504 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5509 if (vcpu->arch.mmu->direct_map)
5512 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5514 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5518 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5520 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5521 void *insn, int insn_len)
5523 int r, emulation_type = 0;
5524 bool direct = vcpu->arch.mmu->direct_map;
5526 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5527 if (vcpu->arch.mmu->direct_map) {
5528 vcpu->arch.gpa_available = true;
5529 vcpu->arch.gpa_val = cr2_or_gpa;
5533 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5534 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5535 if (r == RET_PF_EMULATE)
5539 if (r == RET_PF_INVALID) {
5540 r = vcpu->arch.mmu->page_fault(vcpu, cr2_or_gpa,
5541 lower_32_bits(error_code),
5543 WARN_ON(r == RET_PF_INVALID);
5546 if (r == RET_PF_RETRY)
5552 * Before emulating the instruction, check if the error code
5553 * was due to a RO violation while translating the guest page.
5554 * This can occur when using nested virtualization with nested
5555 * paging in both guests. If true, we simply unprotect the page
5556 * and resume the guest.
5558 if (vcpu->arch.mmu->direct_map &&
5559 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5560 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5565 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5566 * optimistically try to just unprotect the page and let the processor
5567 * re-execute the instruction that caused the page fault. Do not allow
5568 * retrying MMIO emulation, as it's not only pointless but could also
5569 * cause us to enter an infinite loop because the processor will keep
5570 * faulting on the non-existent MMIO address. Retrying an instruction
5571 * from a nested guest is also pointless and dangerous as we are only
5572 * explicitly shadowing L1's page tables, i.e. unprotecting something
5573 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5575 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5576 emulation_type = EMULTYPE_ALLOW_RETRY;
5579 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5580 * This can happen if a guest gets a page-fault on data access but the HW
5581 * table walker is not able to read the instruction page (e.g instruction
5582 * page is not present in memory). In those cases we simply restart the
5583 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5585 if (unlikely(insn && !insn_len)) {
5586 if (!kvm_x86_ops->need_emulation_on_page_fault(vcpu))
5590 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5593 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5595 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5597 struct kvm_mmu *mmu = vcpu->arch.mmu;
5600 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5601 if (is_noncanonical_address(gva, vcpu))
5604 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5607 * INVLPG is required to invalidate any global mappings for the VA,
5608 * irrespective of PCID. Since it would take us roughly similar amount
5609 * of work to determine whether any of the prev_root mappings of the VA
5610 * is marked global, or to just sync it blindly, so we might as well
5611 * just always sync it.
5613 * Mappings not reachable via the current cr3 or the prev_roots will be
5614 * synced when switching to that cr3, so nothing needs to be done here
5617 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5618 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5619 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5621 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5622 ++vcpu->stat.invlpg;
5624 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5626 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5628 struct kvm_mmu *mmu = vcpu->arch.mmu;
5629 bool tlb_flush = false;
5632 if (pcid == kvm_get_active_pcid(vcpu)) {
5633 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5637 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5638 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5639 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5640 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5646 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5648 ++vcpu->stat.invlpg;
5651 * Mappings not reachable via the current cr3 or the prev_roots will be
5652 * synced when switching to that cr3, so nothing needs to be done here
5656 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5658 void kvm_enable_tdp(void)
5662 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5664 void kvm_disable_tdp(void)
5666 tdp_enabled = false;
5668 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5671 /* The return value indicates if tlb flush on all vcpus is needed. */
5672 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5674 /* The caller should hold mmu-lock before calling this function. */
5675 static __always_inline bool
5676 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5677 slot_level_handler fn, int start_level, int end_level,
5678 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5680 struct slot_rmap_walk_iterator iterator;
5683 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5684 end_gfn, &iterator) {
5686 flush |= fn(kvm, iterator.rmap);
5688 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5689 if (flush && lock_flush_tlb) {
5690 kvm_flush_remote_tlbs_with_address(kvm,
5692 iterator.gfn - start_gfn + 1);
5695 cond_resched_lock(&kvm->mmu_lock);
5699 if (flush && lock_flush_tlb) {
5700 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5701 end_gfn - start_gfn + 1);
5708 static __always_inline bool
5709 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5710 slot_level_handler fn, int start_level, int end_level,
5711 bool lock_flush_tlb)
5713 return slot_handle_level_range(kvm, memslot, fn, start_level,
5714 end_level, memslot->base_gfn,
5715 memslot->base_gfn + memslot->npages - 1,
5719 static __always_inline bool
5720 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5721 slot_level_handler fn, bool lock_flush_tlb)
5723 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5724 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5727 static __always_inline bool
5728 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5729 slot_level_handler fn, bool lock_flush_tlb)
5731 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5732 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5735 static __always_inline bool
5736 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5737 slot_level_handler fn, bool lock_flush_tlb)
5739 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5740 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5743 static void free_mmu_pages(struct kvm_mmu *mmu)
5745 free_page((unsigned long)mmu->pae_root);
5746 free_page((unsigned long)mmu->lm_root);
5749 static int alloc_mmu_pages(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5755 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5756 * while the PDP table is a per-vCPU construct that's allocated at MMU
5757 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5758 * x86_64. Therefore we need to allocate the PDP table in the first
5759 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5760 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5761 * skip allocating the PDP table.
5763 if (tdp_enabled && kvm_x86_ops->get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5766 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5770 mmu->pae_root = page_address(page);
5771 for (i = 0; i < 4; ++i)
5772 mmu->pae_root[i] = INVALID_PAGE;
5777 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5782 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5783 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5785 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5786 vcpu->arch.root_mmu.root_cr3 = 0;
5787 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5788 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5789 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5791 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5792 vcpu->arch.guest_mmu.root_cr3 = 0;
5793 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5794 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5795 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5797 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5799 ret = alloc_mmu_pages(vcpu, &vcpu->arch.guest_mmu);
5803 ret = alloc_mmu_pages(vcpu, &vcpu->arch.root_mmu);
5805 goto fail_allocate_root;
5809 free_mmu_pages(&vcpu->arch.guest_mmu);
5813 #define BATCH_ZAP_PAGES 10
5814 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5816 struct kvm_mmu_page *sp, *node;
5817 int nr_zapped, batch = 0;
5820 list_for_each_entry_safe_reverse(sp, node,
5821 &kvm->arch.active_mmu_pages, link) {
5823 * No obsolete valid page exists before a newly created page
5824 * since active_mmu_pages is a FIFO list.
5826 if (!is_obsolete_sp(kvm, sp))
5830 * Skip invalid pages with a non-zero root count, zapping pages
5831 * with a non-zero root count will never succeed, i.e. the page
5832 * will get thrown back on active_mmu_pages and we'll get stuck
5833 * in an infinite loop.
5835 if (sp->role.invalid && sp->root_count)
5839 * No need to flush the TLB since we're only zapping shadow
5840 * pages with an obsolete generation number and all vCPUS have
5841 * loaded a new root, i.e. the shadow pages being zapped cannot
5842 * be in active use by the guest.
5844 if (batch >= BATCH_ZAP_PAGES &&
5845 cond_resched_lock(&kvm->mmu_lock)) {
5850 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5851 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5858 * Trigger a remote TLB flush before freeing the page tables to ensure
5859 * KVM is not in the middle of a lockless shadow page table walk, which
5860 * may reference the pages.
5862 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5866 * Fast invalidate all shadow pages and use lock-break technique
5867 * to zap obsolete pages.
5869 * It's required when memslot is being deleted or VM is being
5870 * destroyed, in these cases, we should ensure that KVM MMU does
5871 * not use any resource of the being-deleted slot or all slots
5872 * after calling the function.
5874 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5876 lockdep_assert_held(&kvm->slots_lock);
5878 spin_lock(&kvm->mmu_lock);
5879 trace_kvm_mmu_zap_all_fast(kvm);
5882 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5883 * held for the entire duration of zapping obsolete pages, it's
5884 * impossible for there to be multiple invalid generations associated
5885 * with *valid* shadow pages at any given time, i.e. there is exactly
5886 * one valid generation and (at most) one invalid generation.
5888 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5891 * Notify all vcpus to reload its shadow page table and flush TLB.
5892 * Then all vcpus will switch to new shadow page table with the new
5895 * Note: we need to do this under the protection of mmu_lock,
5896 * otherwise, vcpu would purge shadow page but miss tlb flush.
5898 kvm_reload_remote_mmus(kvm);
5900 kvm_zap_obsolete_pages(kvm);
5901 spin_unlock(&kvm->mmu_lock);
5904 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5906 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5909 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5910 struct kvm_memory_slot *slot,
5911 struct kvm_page_track_notifier_node *node)
5913 kvm_mmu_zap_all_fast(kvm);
5916 void kvm_mmu_init_vm(struct kvm *kvm)
5918 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5920 node->track_write = kvm_mmu_pte_write;
5921 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5922 kvm_page_track_register_notifier(kvm, node);
5925 void kvm_mmu_uninit_vm(struct kvm *kvm)
5927 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5929 kvm_page_track_unregister_notifier(kvm, node);
5932 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5934 struct kvm_memslots *slots;
5935 struct kvm_memory_slot *memslot;
5938 spin_lock(&kvm->mmu_lock);
5939 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5940 slots = __kvm_memslots(kvm, i);
5941 kvm_for_each_memslot(memslot, slots) {
5944 start = max(gfn_start, memslot->base_gfn);
5945 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5949 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5950 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5951 start, end - 1, true);
5955 spin_unlock(&kvm->mmu_lock);
5958 static bool slot_rmap_write_protect(struct kvm *kvm,
5959 struct kvm_rmap_head *rmap_head)
5961 return __rmap_write_protect(kvm, rmap_head, false);
5964 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5965 struct kvm_memory_slot *memslot)
5969 spin_lock(&kvm->mmu_lock);
5970 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5972 spin_unlock(&kvm->mmu_lock);
5975 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5976 * which do tlb flush out of mmu-lock should be serialized by
5977 * kvm->slots_lock otherwise tlb flush would be missed.
5979 lockdep_assert_held(&kvm->slots_lock);
5982 * We can flush all the TLBs out of the mmu lock without TLB
5983 * corruption since we just change the spte from writable to
5984 * readonly so that we only need to care the case of changing
5985 * spte from present to present (changing the spte from present
5986 * to nonpresent will flush all the TLBs immediately), in other
5987 * words, the only case we care is mmu_spte_update() where we
5988 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5989 * instead of PT_WRITABLE_MASK, that means it does not depend
5990 * on PT_WRITABLE_MASK anymore.
5993 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5997 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5998 struct kvm_rmap_head *rmap_head)
6001 struct rmap_iterator iter;
6002 int need_tlb_flush = 0;
6004 struct kvm_mmu_page *sp;
6007 for_each_rmap_spte(rmap_head, &iter, sptep) {
6008 sp = page_header(__pa(sptep));
6009 pfn = spte_to_pfn(*sptep);
6012 * We cannot do huge page mapping for indirect shadow pages,
6013 * which are found on the last rmap (level = 1) when not using
6014 * tdp; such shadow pages are synced with the page table in
6015 * the guest, and the guest page table is using 4K page size
6016 * mapping if the indirect sp has level = 1.
6018 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
6019 !kvm_is_zone_device_pfn(pfn) &&
6020 PageTransCompoundMap(pfn_to_page(pfn))) {
6021 pte_list_remove(rmap_head, sptep);
6023 if (kvm_available_flush_tlb_with_range())
6024 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
6025 KVM_PAGES_PER_HPAGE(sp->role.level));
6033 return need_tlb_flush;
6036 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
6037 const struct kvm_memory_slot *memslot)
6039 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
6040 spin_lock(&kvm->mmu_lock);
6041 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
6042 kvm_mmu_zap_collapsible_spte, true);
6043 spin_unlock(&kvm->mmu_lock);
6046 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
6047 struct kvm_memory_slot *memslot)
6051 spin_lock(&kvm->mmu_lock);
6052 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
6053 spin_unlock(&kvm->mmu_lock);
6055 lockdep_assert_held(&kvm->slots_lock);
6058 * It's also safe to flush TLBs out of mmu lock here as currently this
6059 * function is only used for dirty logging, in which case flushing TLB
6060 * out of mmu lock also guarantees no dirty pages will be lost in
6064 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6067 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
6069 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
6070 struct kvm_memory_slot *memslot)
6074 spin_lock(&kvm->mmu_lock);
6075 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
6077 spin_unlock(&kvm->mmu_lock);
6079 /* see kvm_mmu_slot_remove_write_access */
6080 lockdep_assert_held(&kvm->slots_lock);
6083 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6086 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
6088 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
6089 struct kvm_memory_slot *memslot)
6093 spin_lock(&kvm->mmu_lock);
6094 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
6095 spin_unlock(&kvm->mmu_lock);
6097 lockdep_assert_held(&kvm->slots_lock);
6099 /* see kvm_mmu_slot_leaf_clear_dirty */
6101 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
6104 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
6106 void kvm_mmu_zap_all(struct kvm *kvm)
6108 struct kvm_mmu_page *sp, *node;
6109 LIST_HEAD(invalid_list);
6112 spin_lock(&kvm->mmu_lock);
6114 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
6115 if (sp->role.invalid && sp->root_count)
6117 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
6119 if (cond_resched_lock(&kvm->mmu_lock))
6123 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6124 spin_unlock(&kvm->mmu_lock);
6127 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
6129 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
6131 gen &= MMIO_SPTE_GEN_MASK;
6134 * Generation numbers are incremented in multiples of the number of
6135 * address spaces in order to provide unique generations across all
6136 * address spaces. Strip what is effectively the address space
6137 * modifier prior to checking for a wrap of the MMIO generation so
6138 * that a wrap in any address space is detected.
6140 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
6143 * The very rare case: if the MMIO generation number has wrapped,
6144 * zap all shadow pages.
6146 if (unlikely(gen == 0)) {
6147 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
6148 kvm_mmu_zap_all_fast(kvm);
6152 static unsigned long
6153 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
6156 int nr_to_scan = sc->nr_to_scan;
6157 unsigned long freed = 0;
6159 mutex_lock(&kvm_lock);
6161 list_for_each_entry(kvm, &vm_list, vm_list) {
6163 LIST_HEAD(invalid_list);
6166 * Never scan more than sc->nr_to_scan VM instances.
6167 * Will not hit this condition practically since we do not try
6168 * to shrink more than one VM and it is very unlikely to see
6169 * !n_used_mmu_pages so many times.
6174 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6175 * here. We may skip a VM instance errorneosly, but we do not
6176 * want to shrink a VM that only started to populate its MMU
6179 if (!kvm->arch.n_used_mmu_pages &&
6180 !kvm_has_zapped_obsolete_pages(kvm))
6183 idx = srcu_read_lock(&kvm->srcu);
6184 spin_lock(&kvm->mmu_lock);
6186 if (kvm_has_zapped_obsolete_pages(kvm)) {
6187 kvm_mmu_commit_zap_page(kvm,
6188 &kvm->arch.zapped_obsolete_pages);
6192 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
6194 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6197 spin_unlock(&kvm->mmu_lock);
6198 srcu_read_unlock(&kvm->srcu, idx);
6201 * unfair on small ones
6202 * per-vm shrinkers cry out
6203 * sadness comes quickly
6205 list_move_tail(&kvm->vm_list, &vm_list);
6209 mutex_unlock(&kvm_lock);
6213 static unsigned long
6214 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6216 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
6219 static struct shrinker mmu_shrinker = {
6220 .count_objects = mmu_shrink_count,
6221 .scan_objects = mmu_shrink_scan,
6222 .seeks = DEFAULT_SEEKS * 10,
6225 static void mmu_destroy_caches(void)
6227 kmem_cache_destroy(pte_list_desc_cache);
6228 kmem_cache_destroy(mmu_page_header_cache);
6231 static void kvm_set_mmio_spte_mask(void)
6236 * Set the reserved bits and the present bit of an paging-structure
6237 * entry to generate page fault with PFER.RSV = 1.
6241 * Mask the uppermost physical address bit, which would be reserved as
6242 * long as the supported physical address width is less than 52.
6246 /* Set the present bit. */
6250 * If reserved bit is not supported, clear the present bit to disable
6253 if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52)
6256 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);
6259 static bool get_nx_auto_mode(void)
6261 /* Return true when CPU has the bug, and mitigations are ON */
6262 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6265 static void __set_nx_huge_pages(bool val)
6267 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6270 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6272 bool old_val = nx_huge_pages;
6275 /* In "auto" mode deploy workaround only if CPU has the bug. */
6276 if (sysfs_streq(val, "off"))
6278 else if (sysfs_streq(val, "force"))
6280 else if (sysfs_streq(val, "auto"))
6281 new_val = get_nx_auto_mode();
6282 else if (strtobool(val, &new_val) < 0)
6285 __set_nx_huge_pages(new_val);
6287 if (new_val != old_val) {
6290 mutex_lock(&kvm_lock);
6292 list_for_each_entry(kvm, &vm_list, vm_list) {
6293 mutex_lock(&kvm->slots_lock);
6294 kvm_mmu_zap_all_fast(kvm);
6295 mutex_unlock(&kvm->slots_lock);
6297 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6299 mutex_unlock(&kvm_lock);
6305 int kvm_mmu_module_init(void)
6309 if (nx_huge_pages == -1)
6310 __set_nx_huge_pages(get_nx_auto_mode());
6313 * MMU roles use union aliasing which is, generally speaking, an
6314 * undefined behavior. However, we supposedly know how compilers behave
6315 * and the current status quo is unlikely to change. Guardians below are
6316 * supposed to let us know if the assumption becomes false.
6318 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6319 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6320 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6322 kvm_mmu_reset_all_pte_masks();
6324 kvm_set_mmio_spte_mask();
6326 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6327 sizeof(struct pte_list_desc),
6328 0, SLAB_ACCOUNT, NULL);
6329 if (!pte_list_desc_cache)
6332 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6333 sizeof(struct kvm_mmu_page),
6334 0, SLAB_ACCOUNT, NULL);
6335 if (!mmu_page_header_cache)
6338 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6341 ret = register_shrinker(&mmu_shrinker);
6348 mmu_destroy_caches();
6353 * Calculate mmu pages needed for kvm.
6355 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6357 unsigned long nr_mmu_pages;
6358 unsigned long nr_pages = 0;
6359 struct kvm_memslots *slots;
6360 struct kvm_memory_slot *memslot;
6363 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6364 slots = __kvm_memslots(kvm, i);
6366 kvm_for_each_memslot(memslot, slots)
6367 nr_pages += memslot->npages;
6370 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6371 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6373 return nr_mmu_pages;
6376 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6378 kvm_mmu_unload(vcpu);
6379 free_mmu_pages(&vcpu->arch.root_mmu);
6380 free_mmu_pages(&vcpu->arch.guest_mmu);
6381 mmu_free_memory_caches(vcpu);
6384 void kvm_mmu_module_exit(void)
6386 mmu_destroy_caches();
6387 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6388 unregister_shrinker(&mmu_shrinker);
6389 mmu_audit_disable();
6392 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6394 unsigned int old_val;
6397 old_val = nx_huge_pages_recovery_ratio;
6398 err = param_set_uint(val, kp);
6402 if (READ_ONCE(nx_huge_pages) &&
6403 !old_val && nx_huge_pages_recovery_ratio) {
6406 mutex_lock(&kvm_lock);
6408 list_for_each_entry(kvm, &vm_list, vm_list)
6409 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6411 mutex_unlock(&kvm_lock);
6417 static void kvm_recover_nx_lpages(struct kvm *kvm)
6420 struct kvm_mmu_page *sp;
6422 LIST_HEAD(invalid_list);
6425 rcu_idx = srcu_read_lock(&kvm->srcu);
6426 spin_lock(&kvm->mmu_lock);
6428 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6429 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
6430 while (to_zap && !list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) {
6432 * We use a separate list instead of just using active_mmu_pages
6433 * because the number of lpage_disallowed pages is expected to
6434 * be relatively small compared to the total.
6436 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6437 struct kvm_mmu_page,
6438 lpage_disallowed_link);
6439 WARN_ON_ONCE(!sp->lpage_disallowed);
6440 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6441 WARN_ON_ONCE(sp->lpage_disallowed);
6443 if (!--to_zap || need_resched() || spin_needbreak(&kvm->mmu_lock)) {
6444 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6446 cond_resched_lock(&kvm->mmu_lock);
6450 spin_unlock(&kvm->mmu_lock);
6451 srcu_read_unlock(&kvm->srcu, rcu_idx);
6454 static long get_nx_lpage_recovery_timeout(u64 start_time)
6456 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6457 ? start_time + 60 * HZ - get_jiffies_64()
6458 : MAX_SCHEDULE_TIMEOUT;
6461 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6464 long remaining_time;
6467 start_time = get_jiffies_64();
6468 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6470 set_current_state(TASK_INTERRUPTIBLE);
6471 while (!kthread_should_stop() && remaining_time > 0) {
6472 schedule_timeout(remaining_time);
6473 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6474 set_current_state(TASK_INTERRUPTIBLE);
6477 set_current_state(TASK_RUNNING);
6479 if (kthread_should_stop())
6482 kvm_recover_nx_lpages(kvm);
6486 int kvm_mmu_post_init_vm(struct kvm *kvm)
6490 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6491 "kvm-nx-lpage-recovery",
6492 &kvm->arch.nx_lpage_recovery_thread);
6494 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6499 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6501 if (kvm->arch.nx_lpage_recovery_thread)
6502 kthread_stop(kvm->arch.nx_lpage_recovery_thread);