2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
52 bool tdp_enabled = false;
56 AUDIT_POST_PAGE_FAULT,
67 module_param(dbg, bool, 0644);
69 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
70 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define MMU_WARN_ON(x) WARN_ON(x)
73 #define pgprintk(x...) do { } while (0)
74 #define rmap_printk(x...) do { } while (0)
75 #define MMU_WARN_ON(x) do { } while (0)
78 #define PTE_PREFETCH_NUM 8
80 #define PT_FIRST_AVAIL_BITS_SHIFT 10
81 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
83 #define PT64_LEVEL_BITS 9
85 #define PT64_LEVEL_SHIFT(level) \
86 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
88 #define PT64_INDEX(address, level)\
89 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
92 #define PT32_LEVEL_BITS 10
94 #define PT32_LEVEL_SHIFT(level) \
95 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
97 #define PT32_LVL_OFFSET_MASK(level) \
98 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
99 * PT32_LEVEL_BITS))) - 1))
101 #define PT32_INDEX(address, level)\
102 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
105 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
106 #define PT64_DIR_BASE_ADDR_MASK \
107 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
108 #define PT64_LVL_ADDR_MASK(level) \
109 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
110 * PT64_LEVEL_BITS))) - 1))
111 #define PT64_LVL_OFFSET_MASK(level) \
112 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT64_LEVEL_BITS))) - 1))
115 #define PT32_BASE_ADDR_MASK PAGE_MASK
116 #define PT32_DIR_BASE_ADDR_MASK \
117 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
118 #define PT32_LVL_ADDR_MASK(level) \
119 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT32_LEVEL_BITS))) - 1))
122 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
123 | shadow_x_mask | shadow_nx_mask)
125 #define ACC_EXEC_MASK 1
126 #define ACC_WRITE_MASK PT_WRITABLE_MASK
127 #define ACC_USER_MASK PT_USER_MASK
128 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
130 #include <trace/events/kvm.h>
132 #define CREATE_TRACE_POINTS
133 #include "mmutrace.h"
135 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
136 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
138 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
140 /* make pte_list_desc fit well in cache line */
141 #define PTE_LIST_EXT 3
143 struct pte_list_desc {
144 u64 *sptes[PTE_LIST_EXT];
145 struct pte_list_desc *more;
148 struct kvm_shadow_walk_iterator {
156 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
157 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
158 shadow_walk_okay(&(_walker)); \
159 shadow_walk_next(&(_walker)))
161 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
162 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
163 shadow_walk_okay(&(_walker)) && \
164 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
165 __shadow_walk_next(&(_walker), spte))
167 static struct kmem_cache *pte_list_desc_cache;
168 static struct kmem_cache *mmu_page_header_cache;
169 static struct percpu_counter kvm_total_used_mmu_pages;
171 static u64 __read_mostly shadow_nx_mask;
172 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
173 static u64 __read_mostly shadow_user_mask;
174 static u64 __read_mostly shadow_accessed_mask;
175 static u64 __read_mostly shadow_dirty_mask;
176 static u64 __read_mostly shadow_mmio_mask;
178 static void mmu_spte_set(u64 *sptep, u64 spte);
179 static void mmu_free_roots(struct kvm_vcpu *vcpu);
181 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
183 shadow_mmio_mask = mmio_mask;
185 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
188 * the low bit of the generation number is always presumed to be zero.
189 * This disables mmio caching during memslot updates. The concept is
190 * similar to a seqcount but instead of retrying the access we just punt
191 * and ignore the cache.
193 * spte bits 3-11 are used as bits 1-9 of the generation number,
194 * the bits 52-61 are used as bits 10-19 of the generation number.
196 #define MMIO_SPTE_GEN_LOW_SHIFT 2
197 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
199 #define MMIO_GEN_SHIFT 20
200 #define MMIO_GEN_LOW_SHIFT 10
201 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
202 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
204 static u64 generation_mmio_spte_mask(unsigned int gen)
208 WARN_ON(gen & ~MMIO_GEN_MASK);
210 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
211 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
215 static unsigned int get_mmio_spte_generation(u64 spte)
219 spte &= ~shadow_mmio_mask;
221 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
222 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
226 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
228 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
231 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
234 unsigned int gen = kvm_current_mmio_generation(vcpu);
235 u64 mask = generation_mmio_spte_mask(gen);
237 access &= ACC_WRITE_MASK | ACC_USER_MASK;
238 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
240 trace_mark_mmio_spte(sptep, gfn, access, gen);
241 mmu_spte_set(sptep, mask);
244 static bool is_mmio_spte(u64 spte)
246 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
249 static gfn_t get_mmio_spte_gfn(u64 spte)
251 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
252 return (spte & ~mask) >> PAGE_SHIFT;
255 static unsigned get_mmio_spte_access(u64 spte)
257 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
258 return (spte & ~mask) & ~PAGE_MASK;
261 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
262 pfn_t pfn, unsigned access)
264 if (unlikely(is_noslot_pfn(pfn))) {
265 mark_mmio_spte(vcpu, sptep, gfn, access);
272 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
274 unsigned int kvm_gen, spte_gen;
276 kvm_gen = kvm_current_mmio_generation(vcpu);
277 spte_gen = get_mmio_spte_generation(spte);
279 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
280 return likely(kvm_gen == spte_gen);
283 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
284 u64 dirty_mask, u64 nx_mask, u64 x_mask)
286 shadow_user_mask = user_mask;
287 shadow_accessed_mask = accessed_mask;
288 shadow_dirty_mask = dirty_mask;
289 shadow_nx_mask = nx_mask;
290 shadow_x_mask = x_mask;
292 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
294 static int is_cpuid_PSE36(void)
299 static int is_nx(struct kvm_vcpu *vcpu)
301 return vcpu->arch.efer & EFER_NX;
304 static int is_shadow_present_pte(u64 pte)
306 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
309 static int is_large_pte(u64 pte)
311 return pte & PT_PAGE_SIZE_MASK;
314 static int is_rmap_spte(u64 pte)
316 return is_shadow_present_pte(pte);
319 static int is_last_spte(u64 pte, int level)
321 if (level == PT_PAGE_TABLE_LEVEL)
323 if (is_large_pte(pte))
328 static pfn_t spte_to_pfn(u64 pte)
330 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
333 static gfn_t pse36_gfn_delta(u32 gpte)
335 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
337 return (gpte & PT32_DIR_PSE36_MASK) << shift;
341 static void __set_spte(u64 *sptep, u64 spte)
346 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
351 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
353 return xchg(sptep, spte);
356 static u64 __get_spte_lockless(u64 *sptep)
358 return ACCESS_ONCE(*sptep);
369 static void count_spte_clear(u64 *sptep, u64 spte)
371 struct kvm_mmu_page *sp = page_header(__pa(sptep));
373 if (is_shadow_present_pte(spte))
376 /* Ensure the spte is completely set before we increase the count */
378 sp->clear_spte_count++;
381 static void __set_spte(u64 *sptep, u64 spte)
383 union split_spte *ssptep, sspte;
385 ssptep = (union split_spte *)sptep;
386 sspte = (union split_spte)spte;
388 ssptep->spte_high = sspte.spte_high;
391 * If we map the spte from nonpresent to present, We should store
392 * the high bits firstly, then set present bit, so cpu can not
393 * fetch this spte while we are setting the spte.
397 ssptep->spte_low = sspte.spte_low;
400 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
402 union split_spte *ssptep, sspte;
404 ssptep = (union split_spte *)sptep;
405 sspte = (union split_spte)spte;
407 ssptep->spte_low = sspte.spte_low;
410 * If we map the spte from present to nonpresent, we should clear
411 * present bit firstly to avoid vcpu fetch the old high bits.
415 ssptep->spte_high = sspte.spte_high;
416 count_spte_clear(sptep, spte);
419 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
421 union split_spte *ssptep, sspte, orig;
423 ssptep = (union split_spte *)sptep;
424 sspte = (union split_spte)spte;
426 /* xchg acts as a barrier before the setting of the high bits */
427 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
428 orig.spte_high = ssptep->spte_high;
429 ssptep->spte_high = sspte.spte_high;
430 count_spte_clear(sptep, spte);
436 * The idea using the light way get the spte on x86_32 guest is from
437 * gup_get_pte(arch/x86/mm/gup.c).
439 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
440 * coalesces them and we are running out of the MMU lock. Therefore
441 * we need to protect against in-progress updates of the spte.
443 * Reading the spte while an update is in progress may get the old value
444 * for the high part of the spte. The race is fine for a present->non-present
445 * change (because the high part of the spte is ignored for non-present spte),
446 * but for a present->present change we must reread the spte.
448 * All such changes are done in two steps (present->non-present and
449 * non-present->present), hence it is enough to count the number of
450 * present->non-present updates: if it changed while reading the spte,
451 * we might have hit the race. This is done using clear_spte_count.
453 static u64 __get_spte_lockless(u64 *sptep)
455 struct kvm_mmu_page *sp = page_header(__pa(sptep));
456 union split_spte spte, *orig = (union split_spte *)sptep;
460 count = sp->clear_spte_count;
463 spte.spte_low = orig->spte_low;
466 spte.spte_high = orig->spte_high;
469 if (unlikely(spte.spte_low != orig->spte_low ||
470 count != sp->clear_spte_count))
477 static bool spte_is_locklessly_modifiable(u64 spte)
479 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
480 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
483 static bool spte_has_volatile_bits(u64 spte)
486 * Always atomicly update spte if it can be updated
487 * out of mmu-lock, it can ensure dirty bit is not lost,
488 * also, it can help us to get a stable is_writable_pte()
489 * to ensure tlb flush is not missed.
491 if (spte_is_locklessly_modifiable(spte))
494 if (!shadow_accessed_mask)
497 if (!is_shadow_present_pte(spte))
500 if ((spte & shadow_accessed_mask) &&
501 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
507 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
509 return (old_spte & bit_mask) && !(new_spte & bit_mask);
512 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
514 return (old_spte & bit_mask) != (new_spte & bit_mask);
517 /* Rules for using mmu_spte_set:
518 * Set the sptep from nonpresent to present.
519 * Note: the sptep being assigned *must* be either not present
520 * or in a state where the hardware will not attempt to update
523 static void mmu_spte_set(u64 *sptep, u64 new_spte)
525 WARN_ON(is_shadow_present_pte(*sptep));
526 __set_spte(sptep, new_spte);
529 /* Rules for using mmu_spte_update:
530 * Update the state bits, it means the mapped pfn is not changged.
532 * Whenever we overwrite a writable spte with a read-only one we
533 * should flush remote TLBs. Otherwise rmap_write_protect
534 * will find a read-only spte, even though the writable spte
535 * might be cached on a CPU's TLB, the return value indicates this
538 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
540 u64 old_spte = *sptep;
543 WARN_ON(!is_rmap_spte(new_spte));
545 if (!is_shadow_present_pte(old_spte)) {
546 mmu_spte_set(sptep, new_spte);
550 if (!spte_has_volatile_bits(old_spte))
551 __update_clear_spte_fast(sptep, new_spte);
553 old_spte = __update_clear_spte_slow(sptep, new_spte);
556 * For the spte updated out of mmu-lock is safe, since
557 * we always atomicly update it, see the comments in
558 * spte_has_volatile_bits().
560 if (spte_is_locklessly_modifiable(old_spte) &&
561 !is_writable_pte(new_spte))
564 if (!shadow_accessed_mask)
568 * Flush TLB when accessed/dirty bits are changed in the page tables,
569 * to guarantee consistency between TLB and page tables.
571 if (spte_is_bit_changed(old_spte, new_spte,
572 shadow_accessed_mask | shadow_dirty_mask))
575 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
576 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
577 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
578 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
584 * Rules for using mmu_spte_clear_track_bits:
585 * It sets the sptep from present to nonpresent, and track the
586 * state bits, it is used to clear the last level sptep.
588 static int mmu_spte_clear_track_bits(u64 *sptep)
591 u64 old_spte = *sptep;
593 if (!spte_has_volatile_bits(old_spte))
594 __update_clear_spte_fast(sptep, 0ull);
596 old_spte = __update_clear_spte_slow(sptep, 0ull);
598 if (!is_rmap_spte(old_spte))
601 pfn = spte_to_pfn(old_spte);
604 * KVM does not hold the refcount of the page used by
605 * kvm mmu, before reclaiming the page, we should
606 * unmap it from mmu first.
608 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
610 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
611 kvm_set_pfn_accessed(pfn);
612 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
613 kvm_set_pfn_dirty(pfn);
618 * Rules for using mmu_spte_clear_no_track:
619 * Directly clear spte without caring the state bits of sptep,
620 * it is used to set the upper level spte.
622 static void mmu_spte_clear_no_track(u64 *sptep)
624 __update_clear_spte_fast(sptep, 0ull);
627 static u64 mmu_spte_get_lockless(u64 *sptep)
629 return __get_spte_lockless(sptep);
632 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
635 * Prevent page table teardown by making any free-er wait during
636 * kvm_flush_remote_tlbs() IPI to all active vcpus.
639 vcpu->mode = READING_SHADOW_PAGE_TABLES;
641 * Make sure a following spte read is not reordered ahead of the write
647 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
650 * Make sure the write to vcpu->mode is not reordered in front of
651 * reads to sptes. If it does, kvm_commit_zap_page() can see us
652 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
655 vcpu->mode = OUTSIDE_GUEST_MODE;
659 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
660 struct kmem_cache *base_cache, int min)
664 if (cache->nobjs >= min)
666 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
667 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
670 cache->objects[cache->nobjs++] = obj;
675 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
680 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
681 struct kmem_cache *cache)
684 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
687 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
692 if (cache->nobjs >= min)
694 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
695 page = (void *)__get_free_page(GFP_KERNEL);
698 cache->objects[cache->nobjs++] = page;
703 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
706 free_page((unsigned long)mc->objects[--mc->nobjs]);
709 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
713 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
714 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
717 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
720 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
721 mmu_page_header_cache, 4);
726 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
728 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
729 pte_list_desc_cache);
730 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
731 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
732 mmu_page_header_cache);
735 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
740 p = mc->objects[--mc->nobjs];
744 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
746 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
749 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
751 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
754 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
756 if (!sp->role.direct)
757 return sp->gfns[index];
759 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
762 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
765 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
767 sp->gfns[index] = gfn;
771 * Return the pointer to the large page information for a given gfn,
772 * handling slots that are not large page aligned.
774 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
775 struct kvm_memory_slot *slot,
780 idx = gfn_to_index(gfn, slot->base_gfn, level);
781 return &slot->arch.lpage_info[level - 2][idx];
784 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
786 struct kvm_memslots *slots;
787 struct kvm_memory_slot *slot;
788 struct kvm_lpage_info *linfo;
793 slots = kvm_memslots_for_spte_role(kvm, sp->role);
794 slot = __gfn_to_memslot(slots, gfn);
795 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
796 linfo = lpage_info_slot(gfn, slot, i);
797 linfo->write_count += 1;
799 kvm->arch.indirect_shadow_pages++;
802 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
804 struct kvm_memslots *slots;
805 struct kvm_memory_slot *slot;
806 struct kvm_lpage_info *linfo;
811 slots = kvm_memslots_for_spte_role(kvm, sp->role);
812 slot = __gfn_to_memslot(slots, gfn);
813 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
814 linfo = lpage_info_slot(gfn, slot, i);
815 linfo->write_count -= 1;
816 WARN_ON(linfo->write_count < 0);
818 kvm->arch.indirect_shadow_pages--;
821 static int __has_wrprotected_page(gfn_t gfn, int level,
822 struct kvm_memory_slot *slot)
824 struct kvm_lpage_info *linfo;
827 linfo = lpage_info_slot(gfn, slot, level);
828 return linfo->write_count;
834 static int has_wrprotected_page(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
836 struct kvm_memory_slot *slot;
838 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
839 return __has_wrprotected_page(gfn, level, slot);
842 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
844 unsigned long page_size;
847 page_size = kvm_host_page_size(kvm, gfn);
849 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
850 if (page_size >= KVM_HPAGE_SIZE(i))
859 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
862 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
864 if (no_dirty_log && slot->dirty_bitmap)
870 static struct kvm_memory_slot *
871 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
874 struct kvm_memory_slot *slot;
876 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
877 if (!memslot_valid_for_gpte(slot, no_dirty_log))
883 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
884 bool *force_pt_level)
886 int host_level, level, max_level;
887 struct kvm_memory_slot *slot;
889 if (unlikely(*force_pt_level))
890 return PT_PAGE_TABLE_LEVEL;
892 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
893 *force_pt_level = !memslot_valid_for_gpte(slot, true);
894 if (unlikely(*force_pt_level))
895 return PT_PAGE_TABLE_LEVEL;
897 host_level = host_mapping_level(vcpu->kvm, large_gfn);
899 if (host_level == PT_PAGE_TABLE_LEVEL)
902 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
904 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
905 if (__has_wrprotected_page(large_gfn, level, slot))
912 * Pte mapping structures:
914 * If pte_list bit zero is zero, then pte_list point to the spte.
916 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
917 * pte_list_desc containing more mappings.
919 * Returns the number of pte entries before the spte was added or zero if
920 * the spte was not added.
923 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
924 unsigned long *pte_list)
926 struct pte_list_desc *desc;
930 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
931 *pte_list = (unsigned long)spte;
932 } else if (!(*pte_list & 1)) {
933 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
934 desc = mmu_alloc_pte_list_desc(vcpu);
935 desc->sptes[0] = (u64 *)*pte_list;
936 desc->sptes[1] = spte;
937 *pte_list = (unsigned long)desc | 1;
940 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
941 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
942 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
944 count += PTE_LIST_EXT;
946 if (desc->sptes[PTE_LIST_EXT-1]) {
947 desc->more = mmu_alloc_pte_list_desc(vcpu);
950 for (i = 0; desc->sptes[i]; ++i)
952 desc->sptes[i] = spte;
958 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
959 int i, struct pte_list_desc *prev_desc)
963 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
965 desc->sptes[i] = desc->sptes[j];
966 desc->sptes[j] = NULL;
969 if (!prev_desc && !desc->more)
970 *pte_list = (unsigned long)desc->sptes[0];
973 prev_desc->more = desc->more;
975 *pte_list = (unsigned long)desc->more | 1;
976 mmu_free_pte_list_desc(desc);
979 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
981 struct pte_list_desc *desc;
982 struct pte_list_desc *prev_desc;
986 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
988 } else if (!(*pte_list & 1)) {
989 rmap_printk("pte_list_remove: %p 1->0\n", spte);
990 if ((u64 *)*pte_list != spte) {
991 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
996 rmap_printk("pte_list_remove: %p many->many\n", spte);
997 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1000 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1001 if (desc->sptes[i] == spte) {
1002 pte_list_desc_remove_entry(pte_list,
1010 pr_err("pte_list_remove: %p many->many\n", spte);
1015 typedef void (*pte_list_walk_fn) (u64 *spte);
1016 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1018 struct pte_list_desc *desc;
1024 if (!(*pte_list & 1))
1025 return fn((u64 *)*pte_list);
1027 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1029 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1035 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1036 struct kvm_memory_slot *slot)
1040 idx = gfn_to_index(gfn, slot->base_gfn, level);
1041 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1045 * Take gfn and return the reverse mapping to it.
1047 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, struct kvm_mmu_page *sp)
1049 struct kvm_memslots *slots;
1050 struct kvm_memory_slot *slot;
1052 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1053 slot = __gfn_to_memslot(slots, gfn);
1054 return __gfn_to_rmap(gfn, sp->role.level, slot);
1057 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1059 struct kvm_mmu_memory_cache *cache;
1061 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1062 return mmu_memory_cache_free_objects(cache);
1065 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1067 struct kvm_mmu_page *sp;
1068 unsigned long *rmapp;
1070 sp = page_header(__pa(spte));
1071 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1072 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp);
1073 return pte_list_add(vcpu, spte, rmapp);
1076 static void rmap_remove(struct kvm *kvm, u64 *spte)
1078 struct kvm_mmu_page *sp;
1080 unsigned long *rmapp;
1082 sp = page_header(__pa(spte));
1083 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1084 rmapp = gfn_to_rmap(kvm, gfn, sp);
1085 pte_list_remove(spte, rmapp);
1089 * Used by the following functions to iterate through the sptes linked by a
1090 * rmap. All fields are private and not assumed to be used outside.
1092 struct rmap_iterator {
1093 /* private fields */
1094 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1095 int pos; /* index of the sptep */
1099 * Iteration must be started by this function. This should also be used after
1100 * removing/dropping sptes from the rmap link because in such cases the
1101 * information in the itererator may not be valid.
1103 * Returns sptep if found, NULL otherwise.
1105 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1115 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1117 return iter->desc->sptes[iter->pos];
1121 * Must be used with a valid iterator: e.g. after rmap_get_first().
1123 * Returns sptep if found, NULL otherwise.
1125 static u64 *rmap_get_next(struct rmap_iterator *iter)
1128 if (iter->pos < PTE_LIST_EXT - 1) {
1132 sptep = iter->desc->sptes[iter->pos];
1137 iter->desc = iter->desc->more;
1141 /* desc->sptes[0] cannot be NULL */
1142 return iter->desc->sptes[iter->pos];
1149 #define for_each_rmap_spte(_rmap_, _iter_, _spte_) \
1150 for (_spte_ = rmap_get_first(*_rmap_, _iter_); \
1151 _spte_ && ({BUG_ON(!is_shadow_present_pte(*_spte_)); 1;}); \
1152 _spte_ = rmap_get_next(_iter_))
1154 static void drop_spte(struct kvm *kvm, u64 *sptep)
1156 if (mmu_spte_clear_track_bits(sptep))
1157 rmap_remove(kvm, sptep);
1161 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1163 if (is_large_pte(*sptep)) {
1164 WARN_ON(page_header(__pa(sptep))->role.level ==
1165 PT_PAGE_TABLE_LEVEL);
1166 drop_spte(kvm, sptep);
1174 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1176 if (__drop_large_spte(vcpu->kvm, sptep))
1177 kvm_flush_remote_tlbs(vcpu->kvm);
1181 * Write-protect on the specified @sptep, @pt_protect indicates whether
1182 * spte write-protection is caused by protecting shadow page table.
1184 * Note: write protection is difference between dirty logging and spte
1186 * - for dirty logging, the spte can be set to writable at anytime if
1187 * its dirty bitmap is properly set.
1188 * - for spte protection, the spte can be writable only after unsync-ing
1191 * Return true if tlb need be flushed.
1193 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1197 if (!is_writable_pte(spte) &&
1198 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1201 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1204 spte &= ~SPTE_MMU_WRITEABLE;
1205 spte = spte & ~PT_WRITABLE_MASK;
1207 return mmu_spte_update(sptep, spte);
1210 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1214 struct rmap_iterator iter;
1217 for_each_rmap_spte(rmapp, &iter, sptep)
1218 flush |= spte_write_protect(kvm, sptep, pt_protect);
1223 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1227 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1229 spte &= ~shadow_dirty_mask;
1231 return mmu_spte_update(sptep, spte);
1234 static bool __rmap_clear_dirty(struct kvm *kvm, unsigned long *rmapp)
1237 struct rmap_iterator iter;
1240 for_each_rmap_spte(rmapp, &iter, sptep)
1241 flush |= spte_clear_dirty(kvm, sptep);
1246 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1250 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1252 spte |= shadow_dirty_mask;
1254 return mmu_spte_update(sptep, spte);
1257 static bool __rmap_set_dirty(struct kvm *kvm, unsigned long *rmapp)
1260 struct rmap_iterator iter;
1263 for_each_rmap_spte(rmapp, &iter, sptep)
1264 flush |= spte_set_dirty(kvm, sptep);
1270 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1271 * @kvm: kvm instance
1272 * @slot: slot to protect
1273 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1274 * @mask: indicates which pages we should protect
1276 * Used when we do not need to care about huge page mappings: e.g. during dirty
1277 * logging we do not have any such mappings.
1279 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1280 struct kvm_memory_slot *slot,
1281 gfn_t gfn_offset, unsigned long mask)
1283 unsigned long *rmapp;
1286 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1287 PT_PAGE_TABLE_LEVEL, slot);
1288 __rmap_write_protect(kvm, rmapp, false);
1290 /* clear the first set bit */
1296 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1297 * @kvm: kvm instance
1298 * @slot: slot to clear D-bit
1299 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1300 * @mask: indicates which pages we should clear D-bit
1302 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1304 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1305 struct kvm_memory_slot *slot,
1306 gfn_t gfn_offset, unsigned long mask)
1308 unsigned long *rmapp;
1311 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1312 PT_PAGE_TABLE_LEVEL, slot);
1313 __rmap_clear_dirty(kvm, rmapp);
1315 /* clear the first set bit */
1319 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1322 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1325 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1326 * enable dirty logging for them.
1328 * Used when we do not need to care about huge page mappings: e.g. during dirty
1329 * logging we do not have any such mappings.
1331 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1332 struct kvm_memory_slot *slot,
1333 gfn_t gfn_offset, unsigned long mask)
1335 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1336 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1339 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1342 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1344 struct kvm_memory_slot *slot;
1345 unsigned long *rmapp;
1347 bool write_protected = false;
1349 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1351 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1352 rmapp = __gfn_to_rmap(gfn, i, slot);
1353 write_protected |= __rmap_write_protect(vcpu->kvm, rmapp, true);
1356 return write_protected;
1359 static bool kvm_zap_rmapp(struct kvm *kvm, unsigned long *rmapp)
1362 struct rmap_iterator iter;
1365 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1366 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1367 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1369 drop_spte(kvm, sptep);
1376 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1377 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1380 return kvm_zap_rmapp(kvm, rmapp);
1383 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1384 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1388 struct rmap_iterator iter;
1391 pte_t *ptep = (pte_t *)data;
1394 WARN_ON(pte_huge(*ptep));
1395 new_pfn = pte_pfn(*ptep);
1398 for_each_rmap_spte(rmapp, &iter, sptep) {
1399 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1400 sptep, *sptep, gfn, level);
1404 if (pte_write(*ptep)) {
1405 drop_spte(kvm, sptep);
1408 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1409 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1411 new_spte &= ~PT_WRITABLE_MASK;
1412 new_spte &= ~SPTE_HOST_WRITEABLE;
1413 new_spte &= ~shadow_accessed_mask;
1415 mmu_spte_clear_track_bits(sptep);
1416 mmu_spte_set(sptep, new_spte);
1421 kvm_flush_remote_tlbs(kvm);
1426 struct slot_rmap_walk_iterator {
1428 struct kvm_memory_slot *slot;
1434 /* output fields. */
1436 unsigned long *rmap;
1439 /* private field. */
1440 unsigned long *end_rmap;
1444 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1446 iterator->level = level;
1447 iterator->gfn = iterator->start_gfn;
1448 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1449 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1454 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1455 struct kvm_memory_slot *slot, int start_level,
1456 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1458 iterator->slot = slot;
1459 iterator->start_level = start_level;
1460 iterator->end_level = end_level;
1461 iterator->start_gfn = start_gfn;
1462 iterator->end_gfn = end_gfn;
1464 rmap_walk_init_level(iterator, iterator->start_level);
1467 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1469 return !!iterator->rmap;
1472 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1474 if (++iterator->rmap <= iterator->end_rmap) {
1475 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1479 if (++iterator->level > iterator->end_level) {
1480 iterator->rmap = NULL;
1484 rmap_walk_init_level(iterator, iterator->level);
1487 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1488 _start_gfn, _end_gfn, _iter_) \
1489 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1490 _end_level_, _start_gfn, _end_gfn); \
1491 slot_rmap_walk_okay(_iter_); \
1492 slot_rmap_walk_next(_iter_))
1494 static int kvm_handle_hva_range(struct kvm *kvm,
1495 unsigned long start,
1498 int (*handler)(struct kvm *kvm,
1499 unsigned long *rmapp,
1500 struct kvm_memory_slot *slot,
1503 unsigned long data))
1505 struct kvm_memslots *slots;
1506 struct kvm_memory_slot *memslot;
1507 struct slot_rmap_walk_iterator iterator;
1511 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1512 slots = __kvm_memslots(kvm, i);
1513 kvm_for_each_memslot(memslot, slots) {
1514 unsigned long hva_start, hva_end;
1515 gfn_t gfn_start, gfn_end;
1517 hva_start = max(start, memslot->userspace_addr);
1518 hva_end = min(end, memslot->userspace_addr +
1519 (memslot->npages << PAGE_SHIFT));
1520 if (hva_start >= hva_end)
1523 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1524 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1526 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1527 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1529 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1530 PT_MAX_HUGEPAGE_LEVEL,
1531 gfn_start, gfn_end - 1,
1533 ret |= handler(kvm, iterator.rmap, memslot,
1534 iterator.gfn, iterator.level, data);
1541 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1543 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1544 struct kvm_memory_slot *slot,
1545 gfn_t gfn, int level,
1546 unsigned long data))
1548 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1551 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1553 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1556 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1558 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1561 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1563 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1566 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1567 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1571 struct rmap_iterator uninitialized_var(iter);
1574 BUG_ON(!shadow_accessed_mask);
1576 for_each_rmap_spte(rmapp, &iter, sptep)
1577 if (*sptep & shadow_accessed_mask) {
1579 clear_bit((ffs(shadow_accessed_mask) - 1),
1580 (unsigned long *)sptep);
1583 trace_kvm_age_page(gfn, level, slot, young);
1587 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1588 struct kvm_memory_slot *slot, gfn_t gfn,
1589 int level, unsigned long data)
1592 struct rmap_iterator iter;
1596 * If there's no access bit in the secondary pte set by the
1597 * hardware it's up to gup-fast/gup to set the access bit in
1598 * the primary pte or in the page structure.
1600 if (!shadow_accessed_mask)
1603 for_each_rmap_spte(rmapp, &iter, sptep)
1604 if (*sptep & shadow_accessed_mask) {
1612 #define RMAP_RECYCLE_THRESHOLD 1000
1614 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1616 unsigned long *rmapp;
1617 struct kvm_mmu_page *sp;
1619 sp = page_header(__pa(spte));
1621 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp);
1623 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0);
1624 kvm_flush_remote_tlbs(vcpu->kvm);
1627 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1630 * In case of absence of EPT Access and Dirty Bits supports,
1631 * emulate the accessed bit for EPT, by checking if this page has
1632 * an EPT mapping, and clearing it if it does. On the next access,
1633 * a new EPT mapping will be established.
1634 * This has some overhead, but not as much as the cost of swapping
1635 * out actively used pages or breaking up actively used hugepages.
1637 if (!shadow_accessed_mask) {
1639 * We are holding the kvm->mmu_lock, and we are blowing up
1640 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1641 * This is correct as long as we don't decouple the mmu_lock
1642 * protected regions (like invalidate_range_start|end does).
1644 kvm->mmu_notifier_seq++;
1645 return kvm_handle_hva_range(kvm, start, end, 0,
1649 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1652 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1654 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1658 static int is_empty_shadow_page(u64 *spt)
1663 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1664 if (is_shadow_present_pte(*pos)) {
1665 printk(KERN_ERR "%s: %p %llx\n", __func__,
1674 * This value is the sum of all of the kvm instances's
1675 * kvm->arch.n_used_mmu_pages values. We need a global,
1676 * aggregate version in order to make the slab shrinker
1679 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1681 kvm->arch.n_used_mmu_pages += nr;
1682 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1685 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1687 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1688 hlist_del(&sp->hash_link);
1689 list_del(&sp->link);
1690 free_page((unsigned long)sp->spt);
1691 if (!sp->role.direct)
1692 free_page((unsigned long)sp->gfns);
1693 kmem_cache_free(mmu_page_header_cache, sp);
1696 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1698 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1701 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1702 struct kvm_mmu_page *sp, u64 *parent_pte)
1707 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1710 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1713 pte_list_remove(parent_pte, &sp->parent_ptes);
1716 static void drop_parent_pte(struct kvm_mmu_page *sp,
1719 mmu_page_remove_parent_pte(sp, parent_pte);
1720 mmu_spte_clear_no_track(parent_pte);
1723 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1724 u64 *parent_pte, int direct)
1726 struct kvm_mmu_page *sp;
1728 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1729 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1731 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1732 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1735 * The active_mmu_pages list is the FIFO list, do not move the
1736 * page until it is zapped. kvm_zap_obsolete_pages depends on
1737 * this feature. See the comments in kvm_zap_obsolete_pages().
1739 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1740 sp->parent_ptes = 0;
1741 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1742 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1746 static void mark_unsync(u64 *spte);
1747 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1749 pte_list_walk(&sp->parent_ptes, mark_unsync);
1752 static void mark_unsync(u64 *spte)
1754 struct kvm_mmu_page *sp;
1757 sp = page_header(__pa(spte));
1758 index = spte - sp->spt;
1759 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1761 if (sp->unsync_children++)
1763 kvm_mmu_mark_parents_unsync(sp);
1766 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1767 struct kvm_mmu_page *sp)
1772 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1776 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1777 struct kvm_mmu_page *sp, u64 *spte,
1783 #define KVM_PAGE_ARRAY_NR 16
1785 struct kvm_mmu_pages {
1786 struct mmu_page_and_offset {
1787 struct kvm_mmu_page *sp;
1789 } page[KVM_PAGE_ARRAY_NR];
1793 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1799 for (i=0; i < pvec->nr; i++)
1800 if (pvec->page[i].sp == sp)
1803 pvec->page[pvec->nr].sp = sp;
1804 pvec->page[pvec->nr].idx = idx;
1806 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1809 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1810 struct kvm_mmu_pages *pvec)
1812 int i, ret, nr_unsync_leaf = 0;
1814 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1815 struct kvm_mmu_page *child;
1816 u64 ent = sp->spt[i];
1818 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1819 goto clear_child_bitmap;
1821 child = page_header(ent & PT64_BASE_ADDR_MASK);
1823 if (child->unsync_children) {
1824 if (mmu_pages_add(pvec, child, i))
1827 ret = __mmu_unsync_walk(child, pvec);
1829 goto clear_child_bitmap;
1831 nr_unsync_leaf += ret;
1834 } else if (child->unsync) {
1836 if (mmu_pages_add(pvec, child, i))
1839 goto clear_child_bitmap;
1844 __clear_bit(i, sp->unsync_child_bitmap);
1845 sp->unsync_children--;
1846 WARN_ON((int)sp->unsync_children < 0);
1850 return nr_unsync_leaf;
1853 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1854 struct kvm_mmu_pages *pvec)
1856 if (!sp->unsync_children)
1859 mmu_pages_add(pvec, sp, 0);
1860 return __mmu_unsync_walk(sp, pvec);
1863 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1865 WARN_ON(!sp->unsync);
1866 trace_kvm_mmu_sync_page(sp);
1868 --kvm->stat.mmu_unsync;
1871 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1872 struct list_head *invalid_list);
1873 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1874 struct list_head *invalid_list);
1877 * NOTE: we should pay more attention on the zapped-obsolete page
1878 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1879 * since it has been deleted from active_mmu_pages but still can be found
1882 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1883 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1884 * all the obsolete pages.
1886 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1887 hlist_for_each_entry(_sp, \
1888 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1889 if ((_sp)->gfn != (_gfn)) {} else
1891 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1892 for_each_gfn_sp(_kvm, _sp, _gfn) \
1893 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1895 /* @sp->gfn should be write-protected at the call site */
1896 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1897 struct list_head *invalid_list, bool clear_unsync)
1899 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1900 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1905 kvm_unlink_unsync_page(vcpu->kvm, sp);
1907 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1908 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1912 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1916 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1917 struct kvm_mmu_page *sp)
1919 LIST_HEAD(invalid_list);
1922 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1924 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1929 #ifdef CONFIG_KVM_MMU_AUDIT
1930 #include "mmu_audit.c"
1932 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1933 static void mmu_audit_disable(void) { }
1936 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1937 struct list_head *invalid_list)
1939 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1942 /* @gfn should be write-protected at the call site */
1943 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1945 struct kvm_mmu_page *s;
1946 LIST_HEAD(invalid_list);
1949 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1953 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1954 kvm_unlink_unsync_page(vcpu->kvm, s);
1955 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1956 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1957 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1963 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1965 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1968 struct mmu_page_path {
1969 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1970 unsigned int idx[PT64_ROOT_LEVEL-1];
1973 #define for_each_sp(pvec, sp, parents, i) \
1974 for (i = mmu_pages_next(&pvec, &parents, -1), \
1975 sp = pvec.page[i].sp; \
1976 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1977 i = mmu_pages_next(&pvec, &parents, i))
1979 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1980 struct mmu_page_path *parents,
1985 for (n = i+1; n < pvec->nr; n++) {
1986 struct kvm_mmu_page *sp = pvec->page[n].sp;
1988 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1989 parents->idx[0] = pvec->page[n].idx;
1993 parents->parent[sp->role.level-2] = sp;
1994 parents->idx[sp->role.level-1] = pvec->page[n].idx;
2000 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2002 struct kvm_mmu_page *sp;
2003 unsigned int level = 0;
2006 unsigned int idx = parents->idx[level];
2008 sp = parents->parent[level];
2012 --sp->unsync_children;
2013 WARN_ON((int)sp->unsync_children < 0);
2014 __clear_bit(idx, sp->unsync_child_bitmap);
2016 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
2019 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
2020 struct mmu_page_path *parents,
2021 struct kvm_mmu_pages *pvec)
2023 parents->parent[parent->role.level-1] = NULL;
2027 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2028 struct kvm_mmu_page *parent)
2031 struct kvm_mmu_page *sp;
2032 struct mmu_page_path parents;
2033 struct kvm_mmu_pages pages;
2034 LIST_HEAD(invalid_list);
2036 kvm_mmu_pages_init(parent, &parents, &pages);
2037 while (mmu_unsync_walk(parent, &pages)) {
2038 bool protected = false;
2040 for_each_sp(pages, sp, parents, i)
2041 protected |= rmap_write_protect(vcpu, sp->gfn);
2044 kvm_flush_remote_tlbs(vcpu->kvm);
2046 for_each_sp(pages, sp, parents, i) {
2047 kvm_sync_page(vcpu, sp, &invalid_list);
2048 mmu_pages_clear_parents(&parents);
2050 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2051 cond_resched_lock(&vcpu->kvm->mmu_lock);
2052 kvm_mmu_pages_init(parent, &parents, &pages);
2056 static void init_shadow_page_table(struct kvm_mmu_page *sp)
2060 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2064 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2066 sp->write_flooding_count = 0;
2069 static void clear_sp_write_flooding_count(u64 *spte)
2071 struct kvm_mmu_page *sp = page_header(__pa(spte));
2073 __clear_sp_write_flooding_count(sp);
2076 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2078 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2081 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2089 union kvm_mmu_page_role role;
2091 struct kvm_mmu_page *sp;
2092 bool need_sync = false;
2094 role = vcpu->arch.mmu.base_role;
2096 role.direct = direct;
2099 role.access = access;
2100 if (!vcpu->arch.mmu.direct_map
2101 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2102 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2103 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2104 role.quadrant = quadrant;
2106 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
2107 if (is_obsolete_sp(vcpu->kvm, sp))
2110 if (!need_sync && sp->unsync)
2113 if (sp->role.word != role.word)
2116 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
2119 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
2120 if (sp->unsync_children) {
2121 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2122 kvm_mmu_mark_parents_unsync(sp);
2123 } else if (sp->unsync)
2124 kvm_mmu_mark_parents_unsync(sp);
2126 __clear_sp_write_flooding_count(sp);
2127 trace_kvm_mmu_get_page(sp, false);
2130 ++vcpu->kvm->stat.mmu_cache_miss;
2131 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
2136 hlist_add_head(&sp->hash_link,
2137 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2139 if (rmap_write_protect(vcpu, gfn))
2140 kvm_flush_remote_tlbs(vcpu->kvm);
2141 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2142 kvm_sync_pages(vcpu, gfn);
2144 account_shadowed(vcpu->kvm, sp);
2146 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2147 init_shadow_page_table(sp);
2148 trace_kvm_mmu_get_page(sp, true);
2152 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2153 struct kvm_vcpu *vcpu, u64 addr)
2155 iterator->addr = addr;
2156 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2157 iterator->level = vcpu->arch.mmu.shadow_root_level;
2159 if (iterator->level == PT64_ROOT_LEVEL &&
2160 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2161 !vcpu->arch.mmu.direct_map)
2164 if (iterator->level == PT32E_ROOT_LEVEL) {
2165 iterator->shadow_addr
2166 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2167 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2169 if (!iterator->shadow_addr)
2170 iterator->level = 0;
2174 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2176 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2179 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2180 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2184 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2187 if (is_last_spte(spte, iterator->level)) {
2188 iterator->level = 0;
2192 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2196 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2198 return __shadow_walk_next(iterator, *iterator->sptep);
2201 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2205 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2206 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2208 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2209 shadow_user_mask | shadow_x_mask;
2212 spte |= shadow_accessed_mask;
2214 mmu_spte_set(sptep, spte);
2217 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2218 unsigned direct_access)
2220 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2221 struct kvm_mmu_page *child;
2224 * For the direct sp, if the guest pte's dirty bit
2225 * changed form clean to dirty, it will corrupt the
2226 * sp's access: allow writable in the read-only sp,
2227 * so we should update the spte at this point to get
2228 * a new sp with the correct access.
2230 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2231 if (child->role.access == direct_access)
2234 drop_parent_pte(child, sptep);
2235 kvm_flush_remote_tlbs(vcpu->kvm);
2239 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2243 struct kvm_mmu_page *child;
2246 if (is_shadow_present_pte(pte)) {
2247 if (is_last_spte(pte, sp->role.level)) {
2248 drop_spte(kvm, spte);
2249 if (is_large_pte(pte))
2252 child = page_header(pte & PT64_BASE_ADDR_MASK);
2253 drop_parent_pte(child, spte);
2258 if (is_mmio_spte(pte))
2259 mmu_spte_clear_no_track(spte);
2264 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2265 struct kvm_mmu_page *sp)
2269 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2270 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2273 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2275 mmu_page_remove_parent_pte(sp, parent_pte);
2278 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2281 struct rmap_iterator iter;
2283 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2284 drop_parent_pte(sp, sptep);
2287 static int mmu_zap_unsync_children(struct kvm *kvm,
2288 struct kvm_mmu_page *parent,
2289 struct list_head *invalid_list)
2292 struct mmu_page_path parents;
2293 struct kvm_mmu_pages pages;
2295 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2298 kvm_mmu_pages_init(parent, &parents, &pages);
2299 while (mmu_unsync_walk(parent, &pages)) {
2300 struct kvm_mmu_page *sp;
2302 for_each_sp(pages, sp, parents, i) {
2303 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2304 mmu_pages_clear_parents(&parents);
2307 kvm_mmu_pages_init(parent, &parents, &pages);
2313 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2314 struct list_head *invalid_list)
2318 trace_kvm_mmu_prepare_zap_page(sp);
2319 ++kvm->stat.mmu_shadow_zapped;
2320 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2321 kvm_mmu_page_unlink_children(kvm, sp);
2322 kvm_mmu_unlink_parents(kvm, sp);
2324 if (!sp->role.invalid && !sp->role.direct)
2325 unaccount_shadowed(kvm, sp);
2328 kvm_unlink_unsync_page(kvm, sp);
2329 if (!sp->root_count) {
2332 list_move(&sp->link, invalid_list);
2333 kvm_mod_used_mmu_pages(kvm, -1);
2335 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2338 * The obsolete pages can not be used on any vcpus.
2339 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2341 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2342 kvm_reload_remote_mmus(kvm);
2345 sp->role.invalid = 1;
2349 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2350 struct list_head *invalid_list)
2352 struct kvm_mmu_page *sp, *nsp;
2354 if (list_empty(invalid_list))
2358 * wmb: make sure everyone sees our modifications to the page tables
2359 * rmb: make sure we see changes to vcpu->mode
2364 * Wait for all vcpus to exit guest mode and/or lockless shadow
2367 kvm_flush_remote_tlbs(kvm);
2369 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2370 WARN_ON(!sp->role.invalid || sp->root_count);
2371 kvm_mmu_free_page(sp);
2375 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2376 struct list_head *invalid_list)
2378 struct kvm_mmu_page *sp;
2380 if (list_empty(&kvm->arch.active_mmu_pages))
2383 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2384 struct kvm_mmu_page, link);
2385 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2391 * Changing the number of mmu pages allocated to the vm
2392 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2394 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2396 LIST_HEAD(invalid_list);
2398 spin_lock(&kvm->mmu_lock);
2400 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2401 /* Need to free some mmu pages to achieve the goal. */
2402 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2403 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2406 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2407 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2410 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2412 spin_unlock(&kvm->mmu_lock);
2415 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2417 struct kvm_mmu_page *sp;
2418 LIST_HEAD(invalid_list);
2421 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2423 spin_lock(&kvm->mmu_lock);
2424 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2425 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2428 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2430 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2431 spin_unlock(&kvm->mmu_lock);
2435 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2437 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2439 trace_kvm_mmu_unsync_page(sp);
2440 ++vcpu->kvm->stat.mmu_unsync;
2443 kvm_mmu_mark_parents_unsync(sp);
2446 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2448 struct kvm_mmu_page *s;
2450 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2453 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2454 __kvm_unsync_page(vcpu, s);
2458 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2461 struct kvm_mmu_page *s;
2462 bool need_unsync = false;
2464 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2468 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2475 kvm_unsync_pages(vcpu, gfn);
2479 static bool kvm_is_mmio_pfn(pfn_t pfn)
2482 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2487 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2488 unsigned pte_access, int level,
2489 gfn_t gfn, pfn_t pfn, bool speculative,
2490 bool can_unsync, bool host_writable)
2495 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2498 spte = PT_PRESENT_MASK;
2500 spte |= shadow_accessed_mask;
2502 if (pte_access & ACC_EXEC_MASK)
2503 spte |= shadow_x_mask;
2505 spte |= shadow_nx_mask;
2507 if (pte_access & ACC_USER_MASK)
2508 spte |= shadow_user_mask;
2510 if (level > PT_PAGE_TABLE_LEVEL)
2511 spte |= PT_PAGE_SIZE_MASK;
2513 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2514 kvm_is_mmio_pfn(pfn));
2517 spte |= SPTE_HOST_WRITEABLE;
2519 pte_access &= ~ACC_WRITE_MASK;
2521 spte |= (u64)pfn << PAGE_SHIFT;
2523 if (pte_access & ACC_WRITE_MASK) {
2526 * Other vcpu creates new sp in the window between
2527 * mapping_level() and acquiring mmu-lock. We can
2528 * allow guest to retry the access, the mapping can
2529 * be fixed if guest refault.
2531 if (level > PT_PAGE_TABLE_LEVEL &&
2532 has_wrprotected_page(vcpu, gfn, level))
2535 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2538 * Optimization: for pte sync, if spte was writable the hash
2539 * lookup is unnecessary (and expensive). Write protection
2540 * is responsibility of mmu_get_page / kvm_sync_page.
2541 * Same reasoning can be applied to dirty page accounting.
2543 if (!can_unsync && is_writable_pte(*sptep))
2546 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2547 pgprintk("%s: found shadow page for %llx, marking ro\n",
2550 pte_access &= ~ACC_WRITE_MASK;
2551 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2555 if (pte_access & ACC_WRITE_MASK) {
2556 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2557 spte |= shadow_dirty_mask;
2561 if (mmu_spte_update(sptep, spte))
2562 kvm_flush_remote_tlbs(vcpu->kvm);
2567 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2568 unsigned pte_access, int write_fault, int *emulate,
2569 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2572 int was_rmapped = 0;
2575 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2576 *sptep, write_fault, gfn);
2578 if (is_rmap_spte(*sptep)) {
2580 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2581 * the parent of the now unreachable PTE.
2583 if (level > PT_PAGE_TABLE_LEVEL &&
2584 !is_large_pte(*sptep)) {
2585 struct kvm_mmu_page *child;
2588 child = page_header(pte & PT64_BASE_ADDR_MASK);
2589 drop_parent_pte(child, sptep);
2590 kvm_flush_remote_tlbs(vcpu->kvm);
2591 } else if (pfn != spte_to_pfn(*sptep)) {
2592 pgprintk("hfn old %llx new %llx\n",
2593 spte_to_pfn(*sptep), pfn);
2594 drop_spte(vcpu->kvm, sptep);
2595 kvm_flush_remote_tlbs(vcpu->kvm);
2600 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2601 true, host_writable)) {
2604 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2607 if (unlikely(is_mmio_spte(*sptep) && emulate))
2610 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2611 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2612 is_large_pte(*sptep)? "2MB" : "4kB",
2613 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2615 if (!was_rmapped && is_large_pte(*sptep))
2616 ++vcpu->kvm->stat.lpages;
2618 if (is_shadow_present_pte(*sptep)) {
2620 rmap_count = rmap_add(vcpu, sptep, gfn);
2621 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2622 rmap_recycle(vcpu, sptep, gfn);
2626 kvm_release_pfn_clean(pfn);
2629 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2632 struct kvm_memory_slot *slot;
2634 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2636 return KVM_PFN_ERR_FAULT;
2638 return gfn_to_pfn_memslot_atomic(slot, gfn);
2641 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2642 struct kvm_mmu_page *sp,
2643 u64 *start, u64 *end)
2645 struct page *pages[PTE_PREFETCH_NUM];
2646 struct kvm_memory_slot *slot;
2647 unsigned access = sp->role.access;
2651 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2652 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2656 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2660 for (i = 0; i < ret; i++, gfn++, start++)
2661 mmu_set_spte(vcpu, start, access, 0, NULL,
2662 sp->role.level, gfn, page_to_pfn(pages[i]),
2668 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2669 struct kvm_mmu_page *sp, u64 *sptep)
2671 u64 *spte, *start = NULL;
2674 WARN_ON(!sp->role.direct);
2676 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2679 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2680 if (is_shadow_present_pte(*spte) || spte == sptep) {
2683 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2691 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2693 struct kvm_mmu_page *sp;
2696 * Since it's no accessed bit on EPT, it's no way to
2697 * distinguish between actually accessed translations
2698 * and prefetched, so disable pte prefetch if EPT is
2701 if (!shadow_accessed_mask)
2704 sp = page_header(__pa(sptep));
2705 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2708 __direct_pte_prefetch(vcpu, sp, sptep);
2711 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2712 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2715 struct kvm_shadow_walk_iterator iterator;
2716 struct kvm_mmu_page *sp;
2720 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2723 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2724 if (iterator.level == level) {
2725 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2726 write, &emulate, level, gfn, pfn,
2727 prefault, map_writable);
2728 direct_pte_prefetch(vcpu, iterator.sptep);
2729 ++vcpu->stat.pf_fixed;
2733 drop_large_spte(vcpu, iterator.sptep);
2734 if (!is_shadow_present_pte(*iterator.sptep)) {
2735 u64 base_addr = iterator.addr;
2737 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2738 pseudo_gfn = base_addr >> PAGE_SHIFT;
2739 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2741 1, ACC_ALL, iterator.sptep);
2743 link_shadow_page(iterator.sptep, sp, true);
2749 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2753 info.si_signo = SIGBUS;
2755 info.si_code = BUS_MCEERR_AR;
2756 info.si_addr = (void __user *)address;
2757 info.si_addr_lsb = PAGE_SHIFT;
2759 send_sig_info(SIGBUS, &info, tsk);
2762 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2765 * Do not cache the mmio info caused by writing the readonly gfn
2766 * into the spte otherwise read access on readonly gfn also can
2767 * caused mmio page fault and treat it as mmio access.
2768 * Return 1 to tell kvm to emulate it.
2770 if (pfn == KVM_PFN_ERR_RO_FAULT)
2773 if (pfn == KVM_PFN_ERR_HWPOISON) {
2774 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2781 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2782 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2786 int level = *levelp;
2789 * Check if it's a transparent hugepage. If this would be an
2790 * hugetlbfs page, level wouldn't be set to
2791 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2794 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2795 level == PT_PAGE_TABLE_LEVEL &&
2796 PageTransCompound(pfn_to_page(pfn)) &&
2797 !has_wrprotected_page(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2800 * mmu_notifier_retry was successful and we hold the
2801 * mmu_lock here, so the pmd can't become splitting
2802 * from under us, and in turn
2803 * __split_huge_page_refcount() can't run from under
2804 * us and we can safely transfer the refcount from
2805 * PG_tail to PG_head as we switch the pfn to tail to
2808 *levelp = level = PT_DIRECTORY_LEVEL;
2809 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2810 VM_BUG_ON((gfn & mask) != (pfn & mask));
2814 kvm_release_pfn_clean(pfn);
2822 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2823 pfn_t pfn, unsigned access, int *ret_val)
2827 /* The pfn is invalid, report the error! */
2828 if (unlikely(is_error_pfn(pfn))) {
2829 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2833 if (unlikely(is_noslot_pfn(pfn)))
2834 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2841 static bool page_fault_can_be_fast(u32 error_code)
2844 * Do not fix the mmio spte with invalid generation number which
2845 * need to be updated by slow page fault path.
2847 if (unlikely(error_code & PFERR_RSVD_MASK))
2851 * #PF can be fast only if the shadow page table is present and it
2852 * is caused by write-protect, that means we just need change the
2853 * W bit of the spte which can be done out of mmu-lock.
2855 if (!(error_code & PFERR_PRESENT_MASK) ||
2856 !(error_code & PFERR_WRITE_MASK))
2863 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2864 u64 *sptep, u64 spte)
2868 WARN_ON(!sp->role.direct);
2871 * The gfn of direct spte is stable since it is calculated
2874 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2877 * Theoretically we could also set dirty bit (and flush TLB) here in
2878 * order to eliminate unnecessary PML logging. See comments in
2879 * set_spte. But fast_page_fault is very unlikely to happen with PML
2880 * enabled, so we do not do this. This might result in the same GPA
2881 * to be logged in PML buffer again when the write really happens, and
2882 * eventually to be called by mark_page_dirty twice. But it's also no
2883 * harm. This also avoids the TLB flush needed after setting dirty bit
2884 * so non-PML cases won't be impacted.
2886 * Compare with set_spte where instead shadow_dirty_mask is set.
2888 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2889 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2896 * - true: let the vcpu to access on the same address again.
2897 * - false: let the real page fault path to fix it.
2899 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2902 struct kvm_shadow_walk_iterator iterator;
2903 struct kvm_mmu_page *sp;
2907 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2910 if (!page_fault_can_be_fast(error_code))
2913 walk_shadow_page_lockless_begin(vcpu);
2914 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2915 if (!is_shadow_present_pte(spte) || iterator.level < level)
2919 * If the mapping has been changed, let the vcpu fault on the
2920 * same address again.
2922 if (!is_rmap_spte(spte)) {
2927 sp = page_header(__pa(iterator.sptep));
2928 if (!is_last_spte(spte, sp->role.level))
2932 * Check if it is a spurious fault caused by TLB lazily flushed.
2934 * Need not check the access of upper level table entries since
2935 * they are always ACC_ALL.
2937 if (is_writable_pte(spte)) {
2943 * Currently, to simplify the code, only the spte write-protected
2944 * by dirty-log can be fast fixed.
2946 if (!spte_is_locklessly_modifiable(spte))
2950 * Do not fix write-permission on the large spte since we only dirty
2951 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2952 * that means other pages are missed if its slot is dirty-logged.
2954 * Instead, we let the slow page fault path create a normal spte to
2957 * See the comments in kvm_arch_commit_memory_region().
2959 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2963 * Currently, fast page fault only works for direct mapping since
2964 * the gfn is not stable for indirect shadow page.
2965 * See Documentation/virtual/kvm/locking.txt to get more detail.
2967 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2969 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2971 walk_shadow_page_lockless_end(vcpu);
2976 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2977 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2978 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2980 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2981 gfn_t gfn, bool prefault)
2985 bool force_pt_level = false;
2987 unsigned long mmu_seq;
2988 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2990 level = mapping_level(vcpu, gfn, &force_pt_level);
2991 if (likely(!force_pt_level)) {
2993 * This path builds a PAE pagetable - so we can map
2994 * 2mb pages at maximum. Therefore check if the level
2995 * is larger than that.
2997 if (level > PT_DIRECTORY_LEVEL)
2998 level = PT_DIRECTORY_LEVEL;
3000 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3003 if (fast_page_fault(vcpu, v, level, error_code))
3006 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3009 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3012 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3015 spin_lock(&vcpu->kvm->mmu_lock);
3016 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3018 make_mmu_pages_available(vcpu);
3019 if (likely(!force_pt_level))
3020 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3021 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
3023 spin_unlock(&vcpu->kvm->mmu_lock);
3029 spin_unlock(&vcpu->kvm->mmu_lock);
3030 kvm_release_pfn_clean(pfn);
3035 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3038 struct kvm_mmu_page *sp;
3039 LIST_HEAD(invalid_list);
3041 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3044 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3045 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3046 vcpu->arch.mmu.direct_map)) {
3047 hpa_t root = vcpu->arch.mmu.root_hpa;
3049 spin_lock(&vcpu->kvm->mmu_lock);
3050 sp = page_header(root);
3052 if (!sp->root_count && sp->role.invalid) {
3053 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3054 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3056 spin_unlock(&vcpu->kvm->mmu_lock);
3057 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3061 spin_lock(&vcpu->kvm->mmu_lock);
3062 for (i = 0; i < 4; ++i) {
3063 hpa_t root = vcpu->arch.mmu.pae_root[i];
3066 root &= PT64_BASE_ADDR_MASK;
3067 sp = page_header(root);
3069 if (!sp->root_count && sp->role.invalid)
3070 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3073 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3075 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3076 spin_unlock(&vcpu->kvm->mmu_lock);
3077 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3080 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3084 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3085 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3092 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3094 struct kvm_mmu_page *sp;
3097 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3098 spin_lock(&vcpu->kvm->mmu_lock);
3099 make_mmu_pages_available(vcpu);
3100 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3103 spin_unlock(&vcpu->kvm->mmu_lock);
3104 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3105 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3106 for (i = 0; i < 4; ++i) {
3107 hpa_t root = vcpu->arch.mmu.pae_root[i];
3109 MMU_WARN_ON(VALID_PAGE(root));
3110 spin_lock(&vcpu->kvm->mmu_lock);
3111 make_mmu_pages_available(vcpu);
3112 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3114 PT32_ROOT_LEVEL, 1, ACC_ALL,
3116 root = __pa(sp->spt);
3118 spin_unlock(&vcpu->kvm->mmu_lock);
3119 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3121 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3128 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3130 struct kvm_mmu_page *sp;
3135 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3137 if (mmu_check_root(vcpu, root_gfn))
3141 * Do we shadow a long mode page table? If so we need to
3142 * write-protect the guests page table root.
3144 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3145 hpa_t root = vcpu->arch.mmu.root_hpa;
3147 MMU_WARN_ON(VALID_PAGE(root));
3149 spin_lock(&vcpu->kvm->mmu_lock);
3150 make_mmu_pages_available(vcpu);
3151 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3153 root = __pa(sp->spt);
3155 spin_unlock(&vcpu->kvm->mmu_lock);
3156 vcpu->arch.mmu.root_hpa = root;
3161 * We shadow a 32 bit page table. This may be a legacy 2-level
3162 * or a PAE 3-level page table. In either case we need to be aware that
3163 * the shadow page table may be a PAE or a long mode page table.
3165 pm_mask = PT_PRESENT_MASK;
3166 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3167 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3169 for (i = 0; i < 4; ++i) {
3170 hpa_t root = vcpu->arch.mmu.pae_root[i];
3172 MMU_WARN_ON(VALID_PAGE(root));
3173 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3174 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3175 if (!is_present_gpte(pdptr)) {
3176 vcpu->arch.mmu.pae_root[i] = 0;
3179 root_gfn = pdptr >> PAGE_SHIFT;
3180 if (mmu_check_root(vcpu, root_gfn))
3183 spin_lock(&vcpu->kvm->mmu_lock);
3184 make_mmu_pages_available(vcpu);
3185 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3188 root = __pa(sp->spt);
3190 spin_unlock(&vcpu->kvm->mmu_lock);
3192 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3194 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3197 * If we shadow a 32 bit page table with a long mode page
3198 * table we enter this path.
3200 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3201 if (vcpu->arch.mmu.lm_root == NULL) {
3203 * The additional page necessary for this is only
3204 * allocated on demand.
3209 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3210 if (lm_root == NULL)
3213 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3215 vcpu->arch.mmu.lm_root = lm_root;
3218 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3224 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3226 if (vcpu->arch.mmu.direct_map)
3227 return mmu_alloc_direct_roots(vcpu);
3229 return mmu_alloc_shadow_roots(vcpu);
3232 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3235 struct kvm_mmu_page *sp;
3237 if (vcpu->arch.mmu.direct_map)
3240 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3243 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3244 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3245 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3246 hpa_t root = vcpu->arch.mmu.root_hpa;
3247 sp = page_header(root);
3248 mmu_sync_children(vcpu, sp);
3249 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3252 for (i = 0; i < 4; ++i) {
3253 hpa_t root = vcpu->arch.mmu.pae_root[i];
3255 if (root && VALID_PAGE(root)) {
3256 root &= PT64_BASE_ADDR_MASK;
3257 sp = page_header(root);
3258 mmu_sync_children(vcpu, sp);
3261 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3264 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3266 spin_lock(&vcpu->kvm->mmu_lock);
3267 mmu_sync_roots(vcpu);
3268 spin_unlock(&vcpu->kvm->mmu_lock);
3270 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3272 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3273 u32 access, struct x86_exception *exception)
3276 exception->error_code = 0;
3280 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3282 struct x86_exception *exception)
3285 exception->error_code = 0;
3286 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3290 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3292 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3294 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3295 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3298 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3300 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3303 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3305 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3308 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3311 return vcpu_match_mmio_gpa(vcpu, addr);
3313 return vcpu_match_mmio_gva(vcpu, addr);
3316 /* return true if reserved bit is detected on spte. */
3318 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3320 struct kvm_shadow_walk_iterator iterator;
3321 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3323 bool reserved = false;
3325 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3328 walk_shadow_page_lockless_begin(vcpu);
3330 for (shadow_walk_init(&iterator, vcpu, addr),
3331 leaf = root = iterator.level;
3332 shadow_walk_okay(&iterator);
3333 __shadow_walk_next(&iterator, spte)) {
3334 spte = mmu_spte_get_lockless(iterator.sptep);
3336 sptes[leaf - 1] = spte;
3339 if (!is_shadow_present_pte(spte))
3342 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3346 walk_shadow_page_lockless_end(vcpu);
3349 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3351 while (root > leaf) {
3352 pr_err("------ spte 0x%llx level %d.\n",
3353 sptes[root - 1], root);
3362 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3367 if (quickly_check_mmio_pf(vcpu, addr, direct))
3368 return RET_MMIO_PF_EMULATE;
3370 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3371 if (WARN_ON(reserved))
3372 return RET_MMIO_PF_BUG;
3374 if (is_mmio_spte(spte)) {
3375 gfn_t gfn = get_mmio_spte_gfn(spte);
3376 unsigned access = get_mmio_spte_access(spte);
3378 if (!check_mmio_spte(vcpu, spte))
3379 return RET_MMIO_PF_INVALID;
3384 trace_handle_mmio_page_fault(addr, gfn, access);
3385 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3386 return RET_MMIO_PF_EMULATE;
3390 * If the page table is zapped by other cpus, let CPU fault again on
3393 return RET_MMIO_PF_RETRY;
3395 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3397 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3398 u32 error_code, bool prefault)
3403 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3405 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3406 r = handle_mmio_page_fault(vcpu, gva, true);
3408 if (likely(r != RET_MMIO_PF_INVALID))
3412 r = mmu_topup_memory_caches(vcpu);
3416 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3418 gfn = gva >> PAGE_SHIFT;
3420 return nonpaging_map(vcpu, gva & PAGE_MASK,
3421 error_code, gfn, prefault);
3424 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3426 struct kvm_arch_async_pf arch;
3428 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3430 arch.direct_map = vcpu->arch.mmu.direct_map;
3431 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3433 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3436 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3438 if (unlikely(!lapic_in_kernel(vcpu) ||
3439 kvm_event_needs_reinjection(vcpu)))
3442 return kvm_x86_ops->interrupt_allowed(vcpu);
3445 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3446 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3448 struct kvm_memory_slot *slot;
3451 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3453 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3455 return false; /* *pfn has correct page already */
3457 if (!prefault && can_do_async_pf(vcpu)) {
3458 trace_kvm_try_async_get_page(gva, gfn);
3459 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3460 trace_kvm_async_pf_doublefault(gva, gfn);
3461 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3463 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3467 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3472 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3474 int page_num = KVM_PAGES_PER_HPAGE(level);
3476 gfn &= ~(page_num - 1);
3478 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3481 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3487 bool force_pt_level;
3488 gfn_t gfn = gpa >> PAGE_SHIFT;
3489 unsigned long mmu_seq;
3490 int write = error_code & PFERR_WRITE_MASK;
3493 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3495 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3496 r = handle_mmio_page_fault(vcpu, gpa, true);
3498 if (likely(r != RET_MMIO_PF_INVALID))
3502 r = mmu_topup_memory_caches(vcpu);
3506 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3507 PT_DIRECTORY_LEVEL);
3508 level = mapping_level(vcpu, gfn, &force_pt_level);
3509 if (likely(!force_pt_level)) {
3510 if (level > PT_DIRECTORY_LEVEL &&
3511 !check_hugepage_cache_consistency(vcpu, gfn, level))
3512 level = PT_DIRECTORY_LEVEL;
3513 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3516 if (fast_page_fault(vcpu, gpa, level, error_code))
3519 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3522 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3525 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3528 spin_lock(&vcpu->kvm->mmu_lock);
3529 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3531 make_mmu_pages_available(vcpu);
3532 if (likely(!force_pt_level))
3533 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3534 r = __direct_map(vcpu, gpa, write, map_writable,
3535 level, gfn, pfn, prefault);
3536 spin_unlock(&vcpu->kvm->mmu_lock);
3541 spin_unlock(&vcpu->kvm->mmu_lock);
3542 kvm_release_pfn_clean(pfn);
3546 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3547 struct kvm_mmu *context)
3549 context->page_fault = nonpaging_page_fault;
3550 context->gva_to_gpa = nonpaging_gva_to_gpa;
3551 context->sync_page = nonpaging_sync_page;
3552 context->invlpg = nonpaging_invlpg;
3553 context->update_pte = nonpaging_update_pte;
3554 context->root_level = 0;
3555 context->shadow_root_level = PT32E_ROOT_LEVEL;
3556 context->root_hpa = INVALID_PAGE;
3557 context->direct_map = true;
3558 context->nx = false;
3561 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3563 mmu_free_roots(vcpu);
3566 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3568 return kvm_read_cr3(vcpu);
3571 static void inject_page_fault(struct kvm_vcpu *vcpu,
3572 struct x86_exception *fault)
3574 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3577 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3578 unsigned access, int *nr_present)
3580 if (unlikely(is_mmio_spte(*sptep))) {
3581 if (gfn != get_mmio_spte_gfn(*sptep)) {
3582 mmu_spte_clear_no_track(sptep);
3587 mark_mmio_spte(vcpu, sptep, gfn, access);
3594 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3599 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3600 return mmu->last_pte_bitmap & (1 << index);
3603 #define PTTYPE_EPT 18 /* arbitrary */
3604 #define PTTYPE PTTYPE_EPT
3605 #include "paging_tmpl.h"
3609 #include "paging_tmpl.h"
3613 #include "paging_tmpl.h"
3617 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3618 struct rsvd_bits_validate *rsvd_check,
3619 int maxphyaddr, int level, bool nx, bool gbpages,
3622 u64 exb_bit_rsvd = 0;
3623 u64 gbpages_bit_rsvd = 0;
3624 u64 nonleaf_bit8_rsvd = 0;
3626 rsvd_check->bad_mt_xwr = 0;
3629 exb_bit_rsvd = rsvd_bits(63, 63);
3631 gbpages_bit_rsvd = rsvd_bits(7, 7);
3634 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3635 * leaf entries) on AMD CPUs only.
3638 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3641 case PT32_ROOT_LEVEL:
3642 /* no rsvd bits for 2 level 4K page table entries */
3643 rsvd_check->rsvd_bits_mask[0][1] = 0;
3644 rsvd_check->rsvd_bits_mask[0][0] = 0;
3645 rsvd_check->rsvd_bits_mask[1][0] =
3646 rsvd_check->rsvd_bits_mask[0][0];
3649 rsvd_check->rsvd_bits_mask[1][1] = 0;
3653 if (is_cpuid_PSE36())
3654 /* 36bits PSE 4MB page */
3655 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3657 /* 32 bits PSE 4MB page */
3658 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3660 case PT32E_ROOT_LEVEL:
3661 rsvd_check->rsvd_bits_mask[0][2] =
3662 rsvd_bits(maxphyaddr, 63) |
3663 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3664 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3665 rsvd_bits(maxphyaddr, 62); /* PDE */
3666 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3667 rsvd_bits(maxphyaddr, 62); /* PTE */
3668 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3669 rsvd_bits(maxphyaddr, 62) |
3670 rsvd_bits(13, 20); /* large page */
3671 rsvd_check->rsvd_bits_mask[1][0] =
3672 rsvd_check->rsvd_bits_mask[0][0];
3674 case PT64_ROOT_LEVEL:
3675 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3676 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3677 rsvd_bits(maxphyaddr, 51);
3678 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3679 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3680 rsvd_bits(maxphyaddr, 51);
3681 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3682 rsvd_bits(maxphyaddr, 51);
3683 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3684 rsvd_bits(maxphyaddr, 51);
3685 rsvd_check->rsvd_bits_mask[1][3] =
3686 rsvd_check->rsvd_bits_mask[0][3];
3687 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3688 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3690 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3691 rsvd_bits(maxphyaddr, 51) |
3692 rsvd_bits(13, 20); /* large page */
3693 rsvd_check->rsvd_bits_mask[1][0] =
3694 rsvd_check->rsvd_bits_mask[0][0];
3699 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3700 struct kvm_mmu *context)
3702 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3703 cpuid_maxphyaddr(vcpu), context->root_level,
3704 context->nx, guest_cpuid_has_gbpages(vcpu),
3705 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3709 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3710 int maxphyaddr, bool execonly)
3714 rsvd_check->rsvd_bits_mask[0][3] =
3715 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3716 rsvd_check->rsvd_bits_mask[0][2] =
3717 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3718 rsvd_check->rsvd_bits_mask[0][1] =
3719 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3720 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3723 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3724 rsvd_check->rsvd_bits_mask[1][2] =
3725 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3726 rsvd_check->rsvd_bits_mask[1][1] =
3727 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3728 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3730 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3731 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3732 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3733 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3734 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3736 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3737 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3739 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3742 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3743 struct kvm_mmu *context, bool execonly)
3745 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3746 cpuid_maxphyaddr(vcpu), execonly);
3750 * the page table on host is the shadow page table for the page
3751 * table in guest or amd nested guest, its mmu features completely
3752 * follow the features in guest.
3755 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3758 * Passing "true" to the last argument is okay; it adds a check
3759 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3761 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3762 boot_cpu_data.x86_phys_bits,
3763 context->shadow_root_level, context->nx,
3764 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3767 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3769 static inline bool boot_cpu_is_amd(void)
3771 WARN_ON_ONCE(!tdp_enabled);
3772 return shadow_x_mask == 0;
3776 * the direct page table on host, use as much mmu features as
3777 * possible, however, kvm currently does not do execution-protection.
3780 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3781 struct kvm_mmu *context)
3783 if (boot_cpu_is_amd())
3784 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3785 boot_cpu_data.x86_phys_bits,
3786 context->shadow_root_level, false,
3787 cpu_has_gbpages, true, true);
3789 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3790 boot_cpu_data.x86_phys_bits,
3796 * as the comments in reset_shadow_zero_bits_mask() except it
3797 * is the shadow page table for intel nested guest.
3800 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3801 struct kvm_mmu *context, bool execonly)
3803 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3804 boot_cpu_data.x86_phys_bits, execonly);
3807 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3808 struct kvm_mmu *mmu, bool ept)
3810 unsigned bit, byte, pfec;
3812 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3814 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3815 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3816 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3819 wf = pfec & PFERR_WRITE_MASK;
3820 uf = pfec & PFERR_USER_MASK;
3821 ff = pfec & PFERR_FETCH_MASK;
3823 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3824 * subject to SMAP restrictions, and cleared otherwise. The
3825 * bit is only meaningful if the SMAP bit is set in CR4.
3827 smapf = !(pfec & PFERR_RSVD_MASK);
3828 for (bit = 0; bit < 8; ++bit) {
3829 x = bit & ACC_EXEC_MASK;
3830 w = bit & ACC_WRITE_MASK;
3831 u = bit & ACC_USER_MASK;
3834 /* Not really needed: !nx will cause pte.nx to fault */
3836 /* Allow supervisor writes if !cr0.wp */
3837 w |= !is_write_protection(vcpu) && !uf;
3838 /* Disallow supervisor fetches of user code if cr4.smep */
3839 x &= !(cr4_smep && u && !uf);
3842 * SMAP:kernel-mode data accesses from user-mode
3843 * mappings should fault. A fault is considered
3844 * as a SMAP violation if all of the following
3845 * conditions are ture:
3846 * - X86_CR4_SMAP is set in CR4
3847 * - An user page is accessed
3848 * - Page fault in kernel mode
3849 * - if CPL = 3 or X86_EFLAGS_AC is clear
3851 * Here, we cover the first three conditions.
3852 * The fourth is computed dynamically in
3853 * permission_fault() and is in smapf.
3855 * Also, SMAP does not affect instruction
3856 * fetches, add the !ff check here to make it
3859 smap = cr4_smap && u && !uf && !ff;
3861 /* Not really needed: no U/S accesses on ept */
3864 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3866 map |= fault << bit;
3868 mmu->permissions[byte] = map;
3872 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3875 unsigned level, root_level = mmu->root_level;
3876 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3878 if (root_level == PT32E_ROOT_LEVEL)
3880 /* PT_PAGE_TABLE_LEVEL always terminates */
3881 map = 1 | (1 << ps_set_index);
3882 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3883 if (level <= PT_PDPE_LEVEL
3884 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3885 map |= 1 << (ps_set_index | (level - 1));
3887 mmu->last_pte_bitmap = map;
3890 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3891 struct kvm_mmu *context,
3894 context->nx = is_nx(vcpu);
3895 context->root_level = level;
3897 reset_rsvds_bits_mask(vcpu, context);
3898 update_permission_bitmask(vcpu, context, false);
3899 update_last_pte_bitmap(vcpu, context);
3901 MMU_WARN_ON(!is_pae(vcpu));
3902 context->page_fault = paging64_page_fault;
3903 context->gva_to_gpa = paging64_gva_to_gpa;
3904 context->sync_page = paging64_sync_page;
3905 context->invlpg = paging64_invlpg;
3906 context->update_pte = paging64_update_pte;
3907 context->shadow_root_level = level;
3908 context->root_hpa = INVALID_PAGE;
3909 context->direct_map = false;
3912 static void paging64_init_context(struct kvm_vcpu *vcpu,
3913 struct kvm_mmu *context)
3915 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3918 static void paging32_init_context(struct kvm_vcpu *vcpu,
3919 struct kvm_mmu *context)
3921 context->nx = false;
3922 context->root_level = PT32_ROOT_LEVEL;
3924 reset_rsvds_bits_mask(vcpu, context);
3925 update_permission_bitmask(vcpu, context, false);
3926 update_last_pte_bitmap(vcpu, context);
3928 context->page_fault = paging32_page_fault;
3929 context->gva_to_gpa = paging32_gva_to_gpa;
3930 context->sync_page = paging32_sync_page;
3931 context->invlpg = paging32_invlpg;
3932 context->update_pte = paging32_update_pte;
3933 context->shadow_root_level = PT32E_ROOT_LEVEL;
3934 context->root_hpa = INVALID_PAGE;
3935 context->direct_map = false;
3938 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3939 struct kvm_mmu *context)
3941 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3944 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3946 struct kvm_mmu *context = &vcpu->arch.mmu;
3948 context->base_role.word = 0;
3949 context->base_role.smm = is_smm(vcpu);
3950 context->page_fault = tdp_page_fault;
3951 context->sync_page = nonpaging_sync_page;
3952 context->invlpg = nonpaging_invlpg;
3953 context->update_pte = nonpaging_update_pte;
3954 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3955 context->root_hpa = INVALID_PAGE;
3956 context->direct_map = true;
3957 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3958 context->get_cr3 = get_cr3;
3959 context->get_pdptr = kvm_pdptr_read;
3960 context->inject_page_fault = kvm_inject_page_fault;
3962 if (!is_paging(vcpu)) {
3963 context->nx = false;
3964 context->gva_to_gpa = nonpaging_gva_to_gpa;
3965 context->root_level = 0;
3966 } else if (is_long_mode(vcpu)) {
3967 context->nx = is_nx(vcpu);
3968 context->root_level = PT64_ROOT_LEVEL;
3969 reset_rsvds_bits_mask(vcpu, context);
3970 context->gva_to_gpa = paging64_gva_to_gpa;
3971 } else if (is_pae(vcpu)) {
3972 context->nx = is_nx(vcpu);
3973 context->root_level = PT32E_ROOT_LEVEL;
3974 reset_rsvds_bits_mask(vcpu, context);
3975 context->gva_to_gpa = paging64_gva_to_gpa;
3977 context->nx = false;
3978 context->root_level = PT32_ROOT_LEVEL;
3979 reset_rsvds_bits_mask(vcpu, context);
3980 context->gva_to_gpa = paging32_gva_to_gpa;
3983 update_permission_bitmask(vcpu, context, false);
3984 update_last_pte_bitmap(vcpu, context);
3985 reset_tdp_shadow_zero_bits_mask(vcpu, context);
3988 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
3990 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3991 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3992 struct kvm_mmu *context = &vcpu->arch.mmu;
3994 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
3996 if (!is_paging(vcpu))
3997 nonpaging_init_context(vcpu, context);
3998 else if (is_long_mode(vcpu))
3999 paging64_init_context(vcpu, context);
4000 else if (is_pae(vcpu))
4001 paging32E_init_context(vcpu, context);
4003 paging32_init_context(vcpu, context);
4005 context->base_role.nxe = is_nx(vcpu);
4006 context->base_role.cr4_pae = !!is_pae(vcpu);
4007 context->base_role.cr0_wp = is_write_protection(vcpu);
4008 context->base_role.smep_andnot_wp
4009 = smep && !is_write_protection(vcpu);
4010 context->base_role.smap_andnot_wp
4011 = smap && !is_write_protection(vcpu);
4012 context->base_role.smm = is_smm(vcpu);
4013 reset_shadow_zero_bits_mask(vcpu, context);
4015 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4017 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4019 struct kvm_mmu *context = &vcpu->arch.mmu;
4021 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4023 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4026 context->page_fault = ept_page_fault;
4027 context->gva_to_gpa = ept_gva_to_gpa;
4028 context->sync_page = ept_sync_page;
4029 context->invlpg = ept_invlpg;
4030 context->update_pte = ept_update_pte;
4031 context->root_level = context->shadow_root_level;
4032 context->root_hpa = INVALID_PAGE;
4033 context->direct_map = false;
4035 update_permission_bitmask(vcpu, context, true);
4036 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4037 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4039 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4041 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4043 struct kvm_mmu *context = &vcpu->arch.mmu;
4045 kvm_init_shadow_mmu(vcpu);
4046 context->set_cr3 = kvm_x86_ops->set_cr3;
4047 context->get_cr3 = get_cr3;
4048 context->get_pdptr = kvm_pdptr_read;
4049 context->inject_page_fault = kvm_inject_page_fault;
4052 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4054 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4056 g_context->get_cr3 = get_cr3;
4057 g_context->get_pdptr = kvm_pdptr_read;
4058 g_context->inject_page_fault = kvm_inject_page_fault;
4061 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
4062 * translation of l2_gpa to l1_gpa addresses is done using the
4063 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
4064 * functions between mmu and nested_mmu are swapped.
4066 if (!is_paging(vcpu)) {
4067 g_context->nx = false;
4068 g_context->root_level = 0;
4069 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4070 } else if (is_long_mode(vcpu)) {
4071 g_context->nx = is_nx(vcpu);
4072 g_context->root_level = PT64_ROOT_LEVEL;
4073 reset_rsvds_bits_mask(vcpu, g_context);
4074 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4075 } else if (is_pae(vcpu)) {
4076 g_context->nx = is_nx(vcpu);
4077 g_context->root_level = PT32E_ROOT_LEVEL;
4078 reset_rsvds_bits_mask(vcpu, g_context);
4079 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4081 g_context->nx = false;
4082 g_context->root_level = PT32_ROOT_LEVEL;
4083 reset_rsvds_bits_mask(vcpu, g_context);
4084 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4087 update_permission_bitmask(vcpu, g_context, false);
4088 update_last_pte_bitmap(vcpu, g_context);
4091 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4093 if (mmu_is_nested(vcpu))
4094 init_kvm_nested_mmu(vcpu);
4095 else if (tdp_enabled)
4096 init_kvm_tdp_mmu(vcpu);
4098 init_kvm_softmmu(vcpu);
4101 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4103 kvm_mmu_unload(vcpu);
4106 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4108 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4112 r = mmu_topup_memory_caches(vcpu);
4115 r = mmu_alloc_roots(vcpu);
4116 kvm_mmu_sync_roots(vcpu);
4119 /* set_cr3() should ensure TLB has been flushed */
4120 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4124 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4126 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4128 mmu_free_roots(vcpu);
4129 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4131 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4133 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4134 struct kvm_mmu_page *sp, u64 *spte,
4137 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4138 ++vcpu->kvm->stat.mmu_pde_zapped;
4142 ++vcpu->kvm->stat.mmu_pte_updated;
4143 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4146 static bool need_remote_flush(u64 old, u64 new)
4148 if (!is_shadow_present_pte(old))
4150 if (!is_shadow_present_pte(new))
4152 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4154 old ^= shadow_nx_mask;
4155 new ^= shadow_nx_mask;
4156 return (old & ~new & PT64_PERM_MASK) != 0;
4159 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
4160 bool remote_flush, bool local_flush)
4166 kvm_flush_remote_tlbs(vcpu->kvm);
4167 else if (local_flush)
4168 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4171 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4172 const u8 *new, int *bytes)
4178 * Assume that the pte write on a page table of the same type
4179 * as the current vcpu paging mode since we update the sptes only
4180 * when they have the same mode.
4182 if (is_pae(vcpu) && *bytes == 4) {
4183 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4186 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4189 new = (const u8 *)&gentry;
4194 gentry = *(const u32 *)new;
4197 gentry = *(const u64 *)new;
4208 * If we're seeing too many writes to a page, it may no longer be a page table,
4209 * or we may be forking, in which case it is better to unmap the page.
4211 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4214 * Skip write-flooding detected for the sp whose level is 1, because
4215 * it can become unsync, then the guest page is not write-protected.
4217 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4220 return ++sp->write_flooding_count >= 3;
4224 * Misaligned accesses are too much trouble to fix up; also, they usually
4225 * indicate a page is not used as a page table.
4227 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4230 unsigned offset, pte_size, misaligned;
4232 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4233 gpa, bytes, sp->role.word);
4235 offset = offset_in_page(gpa);
4236 pte_size = sp->role.cr4_pae ? 8 : 4;
4239 * Sometimes, the OS only writes the last one bytes to update status
4240 * bits, for example, in linux, andb instruction is used in clear_bit().
4242 if (!(offset & (pte_size - 1)) && bytes == 1)
4245 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4246 misaligned |= bytes < 4;
4251 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4253 unsigned page_offset, quadrant;
4257 page_offset = offset_in_page(gpa);
4258 level = sp->role.level;
4260 if (!sp->role.cr4_pae) {
4261 page_offset <<= 1; /* 32->64 */
4263 * A 32-bit pde maps 4MB while the shadow pdes map
4264 * only 2MB. So we need to double the offset again
4265 * and zap two pdes instead of one.
4267 if (level == PT32_ROOT_LEVEL) {
4268 page_offset &= ~7; /* kill rounding error */
4272 quadrant = page_offset >> PAGE_SHIFT;
4273 page_offset &= ~PAGE_MASK;
4274 if (quadrant != sp->role.quadrant)
4278 spte = &sp->spt[page_offset / sizeof(*spte)];
4282 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4283 const u8 *new, int bytes)
4285 gfn_t gfn = gpa >> PAGE_SHIFT;
4286 struct kvm_mmu_page *sp;
4287 LIST_HEAD(invalid_list);
4288 u64 entry, gentry, *spte;
4290 bool remote_flush, local_flush, zap_page;
4291 union kvm_mmu_page_role mask = { };
4296 mask.smep_andnot_wp = 1;
4297 mask.smap_andnot_wp = 1;
4301 * If we don't have indirect shadow pages, it means no page is
4302 * write-protected, so we can exit simply.
4304 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4307 zap_page = remote_flush = local_flush = false;
4309 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4311 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4314 * No need to care whether allocation memory is successful
4315 * or not since pte prefetch is skiped if it does not have
4316 * enough objects in the cache.
4318 mmu_topup_memory_caches(vcpu);
4320 spin_lock(&vcpu->kvm->mmu_lock);
4321 ++vcpu->kvm->stat.mmu_pte_write;
4322 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4324 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4325 if (detect_write_misaligned(sp, gpa, bytes) ||
4326 detect_write_flooding(sp)) {
4327 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4329 ++vcpu->kvm->stat.mmu_flooded;
4333 spte = get_written_sptes(sp, gpa, &npte);
4340 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4342 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4343 & mask.word) && rmap_can_add(vcpu))
4344 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4345 if (need_remote_flush(entry, *spte))
4346 remote_flush = true;
4350 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4351 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4352 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4353 spin_unlock(&vcpu->kvm->mmu_lock);
4356 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4361 if (vcpu->arch.mmu.direct_map)
4364 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4366 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4370 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4372 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4374 LIST_HEAD(invalid_list);
4376 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4379 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4380 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4383 ++vcpu->kvm->stat.mmu_recycled;
4385 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4388 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4390 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4391 return vcpu_match_mmio_gpa(vcpu, addr);
4393 return vcpu_match_mmio_gva(vcpu, addr);
4396 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4397 void *insn, int insn_len)
4399 int r, emulation_type = EMULTYPE_RETRY;
4400 enum emulation_result er;
4402 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4411 if (is_mmio_page_fault(vcpu, cr2))
4414 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4419 case EMULATE_USER_EXIT:
4420 ++vcpu->stat.mmio_exits;
4430 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4432 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4434 vcpu->arch.mmu.invlpg(vcpu, gva);
4435 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4436 ++vcpu->stat.invlpg;
4438 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4440 void kvm_enable_tdp(void)
4444 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4446 void kvm_disable_tdp(void)
4448 tdp_enabled = false;
4450 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4452 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4454 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4455 if (vcpu->arch.mmu.lm_root != NULL)
4456 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4459 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4465 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4466 * Therefore we need to allocate shadow page tables in the first
4467 * 4GB of memory, which happens to fit the DMA32 zone.
4469 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4473 vcpu->arch.mmu.pae_root = page_address(page);
4474 for (i = 0; i < 4; ++i)
4475 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4480 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4482 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4483 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4484 vcpu->arch.mmu.translate_gpa = translate_gpa;
4485 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4487 return alloc_mmu_pages(vcpu);
4490 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4492 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4497 /* The return value indicates if tlb flush on all vcpus is needed. */
4498 typedef bool (*slot_level_handler) (struct kvm *kvm, unsigned long *rmap);
4500 /* The caller should hold mmu-lock before calling this function. */
4502 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4503 slot_level_handler fn, int start_level, int end_level,
4504 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4506 struct slot_rmap_walk_iterator iterator;
4509 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4510 end_gfn, &iterator) {
4512 flush |= fn(kvm, iterator.rmap);
4514 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4515 if (flush && lock_flush_tlb) {
4516 kvm_flush_remote_tlbs(kvm);
4519 cond_resched_lock(&kvm->mmu_lock);
4523 if (flush && lock_flush_tlb) {
4524 kvm_flush_remote_tlbs(kvm);
4532 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4533 slot_level_handler fn, int start_level, int end_level,
4534 bool lock_flush_tlb)
4536 return slot_handle_level_range(kvm, memslot, fn, start_level,
4537 end_level, memslot->base_gfn,
4538 memslot->base_gfn + memslot->npages - 1,
4543 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4544 slot_level_handler fn, bool lock_flush_tlb)
4546 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4547 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4551 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4552 slot_level_handler fn, bool lock_flush_tlb)
4554 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4555 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4559 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4560 slot_level_handler fn, bool lock_flush_tlb)
4562 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4563 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4566 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4568 struct kvm_memslots *slots;
4569 struct kvm_memory_slot *memslot;
4572 spin_lock(&kvm->mmu_lock);
4573 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4574 slots = __kvm_memslots(kvm, i);
4575 kvm_for_each_memslot(memslot, slots) {
4578 start = max(gfn_start, memslot->base_gfn);
4579 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4583 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4584 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4585 start, end - 1, true);
4589 spin_unlock(&kvm->mmu_lock);
4592 static bool slot_rmap_write_protect(struct kvm *kvm, unsigned long *rmapp)
4594 return __rmap_write_protect(kvm, rmapp, false);
4597 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4598 struct kvm_memory_slot *memslot)
4602 spin_lock(&kvm->mmu_lock);
4603 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4605 spin_unlock(&kvm->mmu_lock);
4608 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4609 * which do tlb flush out of mmu-lock should be serialized by
4610 * kvm->slots_lock otherwise tlb flush would be missed.
4612 lockdep_assert_held(&kvm->slots_lock);
4615 * We can flush all the TLBs out of the mmu lock without TLB
4616 * corruption since we just change the spte from writable to
4617 * readonly so that we only need to care the case of changing
4618 * spte from present to present (changing the spte from present
4619 * to nonpresent will flush all the TLBs immediately), in other
4620 * words, the only case we care is mmu_spte_update() where we
4621 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4622 * instead of PT_WRITABLE_MASK, that means it does not depend
4623 * on PT_WRITABLE_MASK anymore.
4626 kvm_flush_remote_tlbs(kvm);
4629 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4630 unsigned long *rmapp)
4633 struct rmap_iterator iter;
4634 int need_tlb_flush = 0;
4636 struct kvm_mmu_page *sp;
4639 for_each_rmap_spte(rmapp, &iter, sptep) {
4640 sp = page_header(__pa(sptep));
4641 pfn = spte_to_pfn(*sptep);
4644 * We cannot do huge page mapping for indirect shadow pages,
4645 * which are found on the last rmap (level = 1) when not using
4646 * tdp; such shadow pages are synced with the page table in
4647 * the guest, and the guest page table is using 4K page size
4648 * mapping if the indirect sp has level = 1.
4650 if (sp->role.direct &&
4651 !kvm_is_reserved_pfn(pfn) &&
4652 PageTransCompound(pfn_to_page(pfn))) {
4653 drop_spte(kvm, sptep);
4659 return need_tlb_flush;
4662 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4663 const struct kvm_memory_slot *memslot)
4665 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4666 spin_lock(&kvm->mmu_lock);
4667 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4668 kvm_mmu_zap_collapsible_spte, true);
4669 spin_unlock(&kvm->mmu_lock);
4672 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4673 struct kvm_memory_slot *memslot)
4677 spin_lock(&kvm->mmu_lock);
4678 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4679 spin_unlock(&kvm->mmu_lock);
4681 lockdep_assert_held(&kvm->slots_lock);
4684 * It's also safe to flush TLBs out of mmu lock here as currently this
4685 * function is only used for dirty logging, in which case flushing TLB
4686 * out of mmu lock also guarantees no dirty pages will be lost in
4690 kvm_flush_remote_tlbs(kvm);
4692 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4694 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4695 struct kvm_memory_slot *memslot)
4699 spin_lock(&kvm->mmu_lock);
4700 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4702 spin_unlock(&kvm->mmu_lock);
4704 /* see kvm_mmu_slot_remove_write_access */
4705 lockdep_assert_held(&kvm->slots_lock);
4708 kvm_flush_remote_tlbs(kvm);
4710 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4712 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4713 struct kvm_memory_slot *memslot)
4717 spin_lock(&kvm->mmu_lock);
4718 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4719 spin_unlock(&kvm->mmu_lock);
4721 lockdep_assert_held(&kvm->slots_lock);
4723 /* see kvm_mmu_slot_leaf_clear_dirty */
4725 kvm_flush_remote_tlbs(kvm);
4727 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4729 #define BATCH_ZAP_PAGES 10
4730 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4732 struct kvm_mmu_page *sp, *node;
4736 list_for_each_entry_safe_reverse(sp, node,
4737 &kvm->arch.active_mmu_pages, link) {
4741 * No obsolete page exists before new created page since
4742 * active_mmu_pages is the FIFO list.
4744 if (!is_obsolete_sp(kvm, sp))
4748 * Since we are reversely walking the list and the invalid
4749 * list will be moved to the head, skip the invalid page
4750 * can help us to avoid the infinity list walking.
4752 if (sp->role.invalid)
4756 * Need not flush tlb since we only zap the sp with invalid
4757 * generation number.
4759 if (batch >= BATCH_ZAP_PAGES &&
4760 cond_resched_lock(&kvm->mmu_lock)) {
4765 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4766 &kvm->arch.zapped_obsolete_pages);
4774 * Should flush tlb before free page tables since lockless-walking
4775 * may use the pages.
4777 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4781 * Fast invalidate all shadow pages and use lock-break technique
4782 * to zap obsolete pages.
4784 * It's required when memslot is being deleted or VM is being
4785 * destroyed, in these cases, we should ensure that KVM MMU does
4786 * not use any resource of the being-deleted slot or all slots
4787 * after calling the function.
4789 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4791 spin_lock(&kvm->mmu_lock);
4792 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4793 kvm->arch.mmu_valid_gen++;
4796 * Notify all vcpus to reload its shadow page table
4797 * and flush TLB. Then all vcpus will switch to new
4798 * shadow page table with the new mmu_valid_gen.
4800 * Note: we should do this under the protection of
4801 * mmu-lock, otherwise, vcpu would purge shadow page
4802 * but miss tlb flush.
4804 kvm_reload_remote_mmus(kvm);
4806 kvm_zap_obsolete_pages(kvm);
4807 spin_unlock(&kvm->mmu_lock);
4810 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4812 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4815 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4818 * The very rare case: if the generation-number is round,
4819 * zap all shadow pages.
4821 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4822 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4823 kvm_mmu_invalidate_zap_all_pages(kvm);
4827 static unsigned long
4828 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4831 int nr_to_scan = sc->nr_to_scan;
4832 unsigned long freed = 0;
4834 spin_lock(&kvm_lock);
4836 list_for_each_entry(kvm, &vm_list, vm_list) {
4838 LIST_HEAD(invalid_list);
4841 * Never scan more than sc->nr_to_scan VM instances.
4842 * Will not hit this condition practically since we do not try
4843 * to shrink more than one VM and it is very unlikely to see
4844 * !n_used_mmu_pages so many times.
4849 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4850 * here. We may skip a VM instance errorneosly, but we do not
4851 * want to shrink a VM that only started to populate its MMU
4854 if (!kvm->arch.n_used_mmu_pages &&
4855 !kvm_has_zapped_obsolete_pages(kvm))
4858 idx = srcu_read_lock(&kvm->srcu);
4859 spin_lock(&kvm->mmu_lock);
4861 if (kvm_has_zapped_obsolete_pages(kvm)) {
4862 kvm_mmu_commit_zap_page(kvm,
4863 &kvm->arch.zapped_obsolete_pages);
4867 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4869 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4872 spin_unlock(&kvm->mmu_lock);
4873 srcu_read_unlock(&kvm->srcu, idx);
4876 * unfair on small ones
4877 * per-vm shrinkers cry out
4878 * sadness comes quickly
4880 list_move_tail(&kvm->vm_list, &vm_list);
4884 spin_unlock(&kvm_lock);
4888 static unsigned long
4889 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4891 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4894 static struct shrinker mmu_shrinker = {
4895 .count_objects = mmu_shrink_count,
4896 .scan_objects = mmu_shrink_scan,
4897 .seeks = DEFAULT_SEEKS * 10,
4900 static void mmu_destroy_caches(void)
4902 if (pte_list_desc_cache)
4903 kmem_cache_destroy(pte_list_desc_cache);
4904 if (mmu_page_header_cache)
4905 kmem_cache_destroy(mmu_page_header_cache);
4908 int kvm_mmu_module_init(void)
4910 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4911 sizeof(struct pte_list_desc),
4913 if (!pte_list_desc_cache)
4916 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4917 sizeof(struct kvm_mmu_page),
4919 if (!mmu_page_header_cache)
4922 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
4925 register_shrinker(&mmu_shrinker);
4930 mmu_destroy_caches();
4935 * Caculate mmu pages needed for kvm.
4937 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4939 unsigned int nr_mmu_pages;
4940 unsigned int nr_pages = 0;
4941 struct kvm_memslots *slots;
4942 struct kvm_memory_slot *memslot;
4945 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4946 slots = __kvm_memslots(kvm, i);
4948 kvm_for_each_memslot(memslot, slots)
4949 nr_pages += memslot->npages;
4952 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4953 nr_mmu_pages = max(nr_mmu_pages,
4954 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4956 return nr_mmu_pages;
4959 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4961 kvm_mmu_unload(vcpu);
4962 free_mmu_pages(vcpu);
4963 mmu_free_memory_caches(vcpu);
4966 void kvm_mmu_module_exit(void)
4968 mmu_destroy_caches();
4969 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4970 unregister_shrinker(&mmu_shrinker);
4971 mmu_audit_disable();