1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
43 #include <asm/perf_event.h>
44 #include <asm/tlbflush.h>
46 #include <asm/debugreg.h>
47 #include <asm/kvm_para.h>
48 #include <asm/irq_remapping.h>
49 #include <asm/spec-ctrl.h>
51 #include <asm/virtext.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id svm_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_SVM),
63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
65 #define IOPM_ALLOC_ORDER 2
66 #define MSRPM_ALLOC_ORDER 1
68 #define SEG_TYPE_LDT 2
69 #define SEG_TYPE_BUSY_TSS16 3
71 #define SVM_FEATURE_LBRV (1 << 1)
72 #define SVM_FEATURE_SVML (1 << 2)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
79 #define SVM_AVIC_DOORBELL 0xc001011b
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
116 static bool erratum_383_found __read_mostly;
118 static const u32 host_save_user_msrs[] = {
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
129 struct kvm_sev_info {
130 bool active; /* SEV enabled guest */
131 unsigned int asid; /* ASID used for this guest */
132 unsigned int handle; /* SEV firmware handle */
133 int fd; /* SEV device fd */
134 unsigned long pages_locked; /* Number of pages locked */
135 struct list_head regions_list; /* List of registered regions */
141 /* Struct members for AVIC */
143 struct page *avic_logical_id_table_page;
144 struct page *avic_physical_id_table_page;
145 struct hlist_node hnode;
147 struct kvm_sev_info sev_info;
152 struct nested_state {
158 /* These are the merged vectors */
161 /* gpa pointers to the real vectors */
165 /* A VMEXIT is required but not yet emulated */
168 /* cache for intercepts of the guest */
171 u32 intercept_exceptions;
174 /* Nested Paging related state */
178 #define MSRPM_OFFSETS 16
179 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
182 * Set osvw_len to higher value when updated Revision Guides
183 * are published and we know what the new status bits are
185 static uint64_t osvw_len = 4, osvw_status;
188 struct kvm_vcpu vcpu;
190 unsigned long vmcb_pa;
191 struct svm_cpu_data *svm_data;
192 uint64_t asid_generation;
193 uint64_t sysenter_esp;
194 uint64_t sysenter_eip;
201 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
211 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
212 * translated into the appropriate L2_CFG bits on the host to
213 * perform speculative control.
221 struct nested_state nested;
224 u64 nmi_singlestep_guest_rflags;
226 unsigned int3_injected;
227 unsigned long int3_rip;
229 /* cached guest cpuid flags for faster access */
230 bool nrips_enabled : 1;
234 struct page *avic_backing_page;
235 u64 *avic_physical_id_cache;
236 bool avic_is_running;
239 * Per-vcpu list of struct amd_svm_iommu_ir:
240 * This is used mainly to store interrupt remapping information used
241 * when update the vcpu affinity. This avoids the need to scan for
242 * IRTE and try to match ga_tag in the IOMMU driver.
244 struct list_head ir_list;
245 spinlock_t ir_list_lock;
247 /* which host CPU was used for running this vcpu */
248 unsigned int last_cpu;
252 * This is a wrapper of struct amd_iommu_ir_data.
254 struct amd_svm_iommu_ir {
255 struct list_head node; /* Used by SVM for per-vcpu ir_list */
256 void *data; /* Storing pointer to struct amd_ir_data */
259 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
260 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
261 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
263 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
264 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
265 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
266 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
268 static DEFINE_PER_CPU(u64, current_tsc_ratio);
269 #define TSC_RATIO_DEFAULT 0x0100000000ULL
271 #define MSR_INVALID 0xffffffffU
273 static const struct svm_direct_access_msrs {
274 u32 index; /* Index of the MSR */
275 bool always; /* True if intercept is always on */
276 } direct_access_msrs[] = {
277 { .index = MSR_STAR, .always = true },
278 { .index = MSR_IA32_SYSENTER_CS, .always = true },
280 { .index = MSR_GS_BASE, .always = true },
281 { .index = MSR_FS_BASE, .always = true },
282 { .index = MSR_KERNEL_GS_BASE, .always = true },
283 { .index = MSR_LSTAR, .always = true },
284 { .index = MSR_CSTAR, .always = true },
285 { .index = MSR_SYSCALL_MASK, .always = true },
287 { .index = MSR_IA32_SPEC_CTRL, .always = false },
288 { .index = MSR_IA32_PRED_CMD, .always = false },
289 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
290 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
291 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
292 { .index = MSR_IA32_LASTINTTOIP, .always = false },
293 { .index = MSR_INVALID, .always = false },
296 /* enable NPT for AMD64 and X86 with PAE */
297 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
298 static bool npt_enabled = true;
300 static bool npt_enabled;
304 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
305 * pause_filter_count: On processors that support Pause filtering(indicated
306 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
307 * count value. On VMRUN this value is loaded into an internal counter.
308 * Each time a pause instruction is executed, this counter is decremented
309 * until it reaches zero at which time a #VMEXIT is generated if pause
310 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
311 * Intercept Filtering for more details.
312 * This also indicate if ple logic enabled.
314 * pause_filter_thresh: In addition, some processor families support advanced
315 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
316 * the amount of time a guest is allowed to execute in a pause loop.
317 * In this mode, a 16-bit pause filter threshold field is added in the
318 * VMCB. The threshold value is a cycle count that is used to reset the
319 * pause counter. As with simple pause filtering, VMRUN loads the pause
320 * count value from VMCB into an internal counter. Then, on each pause
321 * instruction the hardware checks the elapsed number of cycles since
322 * the most recent pause instruction against the pause filter threshold.
323 * If the elapsed cycle count is greater than the pause filter threshold,
324 * then the internal pause count is reloaded from the VMCB and execution
325 * continues. If the elapsed cycle count is less than the pause filter
326 * threshold, then the internal pause count is decremented. If the count
327 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
328 * triggered. If advanced pause filtering is supported and pause filter
329 * threshold field is set to zero, the filter will operate in the simpler,
333 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
334 module_param(pause_filter_thresh, ushort, 0444);
336 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
337 module_param(pause_filter_count, ushort, 0444);
339 /* Default doubles per-vcpu window every exit. */
340 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
341 module_param(pause_filter_count_grow, ushort, 0444);
343 /* Default resets per-vcpu window every exit to pause_filter_count. */
344 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
345 module_param(pause_filter_count_shrink, ushort, 0444);
347 /* Default is to compute the maximum so we can never overflow. */
348 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
349 module_param(pause_filter_count_max, ushort, 0444);
351 /* allow nested paging (virtualized MMU) for all guests */
352 static int npt = true;
353 module_param(npt, int, S_IRUGO);
355 /* allow nested virtualization in KVM/SVM */
356 static int nested = true;
357 module_param(nested, int, S_IRUGO);
359 /* enable / disable AVIC */
361 #ifdef CONFIG_X86_LOCAL_APIC
362 module_param(avic, int, S_IRUGO);
365 /* enable/disable Next RIP Save */
366 static int nrips = true;
367 module_param(nrips, int, 0444);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls = true;
371 module_param(vls, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif = true;
375 module_param(vgif, int, 0444);
377 /* enable/disable SEV support */
378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
379 module_param(sev, int, 0444);
381 static bool __read_mostly dump_invalid_vmcb = 0;
382 module_param(dump_invalid_vmcb, bool, 0644);
384 static u8 rsm_ins_bytes[] = "\x0f\xaa";
386 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
387 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
388 static void svm_complete_interrupts(struct vcpu_svm *svm);
390 static int nested_svm_exit_handled(struct vcpu_svm *svm);
391 static int nested_svm_intercept(struct vcpu_svm *svm);
392 static int nested_svm_vmexit(struct vcpu_svm *svm);
393 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
394 bool has_error_code, u32 error_code);
397 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
398 pause filter count */
399 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
400 VMCB_ASID, /* ASID */
401 VMCB_INTR, /* int_ctl, int_vector */
402 VMCB_NPT, /* npt_en, nCR3, gPAT */
403 VMCB_CR, /* CR0, CR3, CR4, EFER */
404 VMCB_DR, /* DR6, DR7 */
405 VMCB_DT, /* GDT, IDT */
406 VMCB_SEG, /* CS, DS, SS, ES, CPL */
407 VMCB_CR2, /* CR2 only */
408 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
409 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
410 * AVIC PHYSICAL_TABLE pointer,
411 * AVIC LOGICAL_TABLE pointer
416 /* TPR and CR2 are always written before VMRUN */
417 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
419 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
421 static unsigned int max_sev_asid;
422 static unsigned int min_sev_asid;
423 static unsigned long *sev_asid_bitmap;
424 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
427 struct list_head list;
428 unsigned long npages;
435 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
437 return container_of(kvm, struct kvm_svm, kvm);
440 static inline bool svm_sev_enabled(void)
442 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
445 static inline bool sev_guest(struct kvm *kvm)
447 #ifdef CONFIG_KVM_AMD_SEV
448 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
456 static inline int sev_get_asid(struct kvm *kvm)
458 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
463 static inline void mark_all_dirty(struct vmcb *vmcb)
465 vmcb->control.clean = 0;
468 static inline void mark_all_clean(struct vmcb *vmcb)
470 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
471 & ~VMCB_ALWAYS_DIRTY_MASK;
474 static inline void mark_dirty(struct vmcb *vmcb, int bit)
476 vmcb->control.clean &= ~(1 << bit);
479 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
481 return container_of(vcpu, struct vcpu_svm, vcpu);
484 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
486 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
487 mark_dirty(svm->vmcb, VMCB_AVIC);
490 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
492 struct vcpu_svm *svm = to_svm(vcpu);
493 u64 *entry = svm->avic_physical_id_cache;
498 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
501 static void recalc_intercepts(struct vcpu_svm *svm)
503 struct vmcb_control_area *c, *h;
504 struct nested_state *g;
506 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
508 if (!is_guest_mode(&svm->vcpu))
511 c = &svm->vmcb->control;
512 h = &svm->nested.hsave->control;
515 c->intercept_cr = h->intercept_cr | g->intercept_cr;
516 c->intercept_dr = h->intercept_dr | g->intercept_dr;
517 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
518 c->intercept = h->intercept | g->intercept;
521 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
523 if (is_guest_mode(&svm->vcpu))
524 return svm->nested.hsave;
529 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
531 struct vmcb *vmcb = get_host_vmcb(svm);
533 vmcb->control.intercept_cr |= (1U << bit);
535 recalc_intercepts(svm);
538 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
540 struct vmcb *vmcb = get_host_vmcb(svm);
542 vmcb->control.intercept_cr &= ~(1U << bit);
544 recalc_intercepts(svm);
547 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
549 struct vmcb *vmcb = get_host_vmcb(svm);
551 return vmcb->control.intercept_cr & (1U << bit);
554 static inline void set_dr_intercepts(struct vcpu_svm *svm)
556 struct vmcb *vmcb = get_host_vmcb(svm);
558 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
559 | (1 << INTERCEPT_DR1_READ)
560 | (1 << INTERCEPT_DR2_READ)
561 | (1 << INTERCEPT_DR3_READ)
562 | (1 << INTERCEPT_DR4_READ)
563 | (1 << INTERCEPT_DR5_READ)
564 | (1 << INTERCEPT_DR6_READ)
565 | (1 << INTERCEPT_DR7_READ)
566 | (1 << INTERCEPT_DR0_WRITE)
567 | (1 << INTERCEPT_DR1_WRITE)
568 | (1 << INTERCEPT_DR2_WRITE)
569 | (1 << INTERCEPT_DR3_WRITE)
570 | (1 << INTERCEPT_DR4_WRITE)
571 | (1 << INTERCEPT_DR5_WRITE)
572 | (1 << INTERCEPT_DR6_WRITE)
573 | (1 << INTERCEPT_DR7_WRITE);
575 recalc_intercepts(svm);
578 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
580 struct vmcb *vmcb = get_host_vmcb(svm);
582 vmcb->control.intercept_dr = 0;
584 recalc_intercepts(svm);
587 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
589 struct vmcb *vmcb = get_host_vmcb(svm);
591 vmcb->control.intercept_exceptions |= (1U << bit);
593 recalc_intercepts(svm);
596 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
598 struct vmcb *vmcb = get_host_vmcb(svm);
600 vmcb->control.intercept_exceptions &= ~(1U << bit);
602 recalc_intercepts(svm);
605 static inline void set_intercept(struct vcpu_svm *svm, int bit)
607 struct vmcb *vmcb = get_host_vmcb(svm);
609 vmcb->control.intercept |= (1ULL << bit);
611 recalc_intercepts(svm);
614 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
616 struct vmcb *vmcb = get_host_vmcb(svm);
618 vmcb->control.intercept &= ~(1ULL << bit);
620 recalc_intercepts(svm);
623 static inline bool vgif_enabled(struct vcpu_svm *svm)
625 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
628 static inline void enable_gif(struct vcpu_svm *svm)
630 if (vgif_enabled(svm))
631 svm->vmcb->control.int_ctl |= V_GIF_MASK;
633 svm->vcpu.arch.hflags |= HF_GIF_MASK;
636 static inline void disable_gif(struct vcpu_svm *svm)
638 if (vgif_enabled(svm))
639 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
641 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
644 static inline bool gif_set(struct vcpu_svm *svm)
646 if (vgif_enabled(svm))
647 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
649 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
652 static unsigned long iopm_base;
654 struct kvm_ldttss_desc {
657 unsigned base1:8, type:5, dpl:2, p:1;
658 unsigned limit1:4, zero0:3, g:1, base2:8;
661 } __attribute__((packed));
663 struct svm_cpu_data {
670 struct kvm_ldttss_desc *tss_desc;
672 struct page *save_area;
673 struct vmcb *current_vmcb;
675 /* index = sev_asid, value = vmcb pointer */
676 struct vmcb **sev_vmcbs;
679 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
681 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
683 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
684 #define MSRS_RANGE_SIZE 2048
685 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
687 static u32 svm_msrpm_offset(u32 msr)
692 for (i = 0; i < NUM_MSR_MAPS; i++) {
693 if (msr < msrpm_ranges[i] ||
694 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
697 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
698 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
700 /* Now we have the u8 offset - but need the u32 offset */
704 /* MSR not in any range */
708 #define MAX_INST_SIZE 15
710 static inline void clgi(void)
712 asm volatile (__ex("clgi"));
715 static inline void stgi(void)
717 asm volatile (__ex("stgi"));
720 static inline void invlpga(unsigned long addr, u32 asid)
722 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
725 static int get_npt_level(struct kvm_vcpu *vcpu)
728 return PT64_ROOT_4LEVEL;
730 return PT32E_ROOT_LEVEL;
734 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
736 vcpu->arch.efer = efer;
737 if (!npt_enabled && !(efer & EFER_LMA))
740 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
741 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
744 static int is_external_interrupt(u32 info)
746 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
747 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
750 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
752 struct vcpu_svm *svm = to_svm(vcpu);
755 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
756 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
760 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
762 struct vcpu_svm *svm = to_svm(vcpu);
765 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
767 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
771 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
773 struct vcpu_svm *svm = to_svm(vcpu);
775 if (nrips && svm->vmcb->control.next_rip != 0) {
776 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
777 svm->next_rip = svm->vmcb->control.next_rip;
781 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP);
783 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
784 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
785 __func__, kvm_rip_read(vcpu), svm->next_rip);
787 kvm_rip_write(vcpu, svm->next_rip);
788 svm_set_interrupt_shadow(vcpu, 0);
793 static void svm_queue_exception(struct kvm_vcpu *vcpu)
795 struct vcpu_svm *svm = to_svm(vcpu);
796 unsigned nr = vcpu->arch.exception.nr;
797 bool has_error_code = vcpu->arch.exception.has_error_code;
798 bool reinject = vcpu->arch.exception.injected;
799 u32 error_code = vcpu->arch.exception.error_code;
802 * If we are within a nested VM we'd better #VMEXIT and let the guest
803 * handle the exception
806 nested_svm_check_exception(svm, nr, has_error_code, error_code))
809 kvm_deliver_exception_payload(&svm->vcpu);
811 if (nr == BP_VECTOR && !nrips) {
812 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
815 * For guest debugging where we have to reinject #BP if some
816 * INT3 is guest-owned:
817 * Emulate nRIP by moving RIP forward. Will fail if injection
818 * raises a fault that is not intercepted. Still better than
819 * failing in all cases.
821 (void)skip_emulated_instruction(&svm->vcpu);
822 rip = kvm_rip_read(&svm->vcpu);
823 svm->int3_rip = rip + svm->vmcb->save.cs.base;
824 svm->int3_injected = rip - old_rip;
827 svm->vmcb->control.event_inj = nr
829 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
830 | SVM_EVTINJ_TYPE_EXEPT;
831 svm->vmcb->control.event_inj_err = error_code;
834 static void svm_init_erratum_383(void)
840 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
843 /* Use _safe variants to not break nested virtualization */
844 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
850 low = lower_32_bits(val);
851 high = upper_32_bits(val);
853 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
855 erratum_383_found = true;
858 static void svm_init_osvw(struct kvm_vcpu *vcpu)
861 * Guests should see errata 400 and 415 as fixed (assuming that
862 * HLT and IO instructions are intercepted).
864 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
865 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
868 * By increasing VCPU's osvw.length to 3 we are telling the guest that
869 * all osvw.status bits inside that length, including bit 0 (which is
870 * reserved for erratum 298), are valid. However, if host processor's
871 * osvw_len is 0 then osvw_status[0] carries no information. We need to
872 * be conservative here and therefore we tell the guest that erratum 298
873 * is present (because we really don't know).
875 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
876 vcpu->arch.osvw.status |= 1;
879 static int has_svm(void)
883 if (!cpu_has_svm(&msg)) {
884 printk(KERN_INFO "has_svm: %s\n", msg);
891 static void svm_hardware_disable(void)
893 /* Make sure we clean up behind us */
894 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
895 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
899 amd_pmu_disable_virt();
902 static int svm_hardware_enable(void)
905 struct svm_cpu_data *sd;
907 struct desc_struct *gdt;
908 int me = raw_smp_processor_id();
910 rdmsrl(MSR_EFER, efer);
911 if (efer & EFER_SVME)
915 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
918 sd = per_cpu(svm_data, me);
920 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
924 sd->asid_generation = 1;
925 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
926 sd->next_asid = sd->max_asid + 1;
927 sd->min_asid = max_sev_asid + 1;
929 gdt = get_current_gdt_rw();
930 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
932 wrmsrl(MSR_EFER, efer | EFER_SVME);
934 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
936 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
937 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
938 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
945 * Note that it is possible to have a system with mixed processor
946 * revisions and therefore different OSVW bits. If bits are not the same
947 * on different processors then choose the worst case (i.e. if erratum
948 * is present on one processor and not on another then assume that the
949 * erratum is present everywhere).
951 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
952 uint64_t len, status = 0;
955 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
957 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
961 osvw_status = osvw_len = 0;
965 osvw_status |= status;
966 osvw_status &= (1ULL << osvw_len) - 1;
969 osvw_status = osvw_len = 0;
971 svm_init_erratum_383();
973 amd_pmu_enable_virt();
978 static void svm_cpu_uninit(int cpu)
980 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
985 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
986 kfree(sd->sev_vmcbs);
987 __free_page(sd->save_area);
991 static int svm_cpu_init(int cpu)
993 struct svm_cpu_data *sd;
996 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1001 sd->save_area = alloc_page(GFP_KERNEL);
1005 if (svm_sev_enabled()) {
1007 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1014 per_cpu(svm_data, cpu) = sd;
1024 static bool valid_msr_intercept(u32 index)
1028 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1029 if (direct_access_msrs[i].index == index)
1035 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1042 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1043 to_svm(vcpu)->msrpm;
1045 offset = svm_msrpm_offset(msr);
1046 bit_write = 2 * (msr & 0x0f) + 1;
1047 tmp = msrpm[offset];
1049 BUG_ON(offset == MSR_INVALID);
1051 return !!test_bit(bit_write, &tmp);
1054 static void set_msr_interception(u32 *msrpm, unsigned msr,
1055 int read, int write)
1057 u8 bit_read, bit_write;
1062 * If this warning triggers extend the direct_access_msrs list at the
1063 * beginning of the file
1065 WARN_ON(!valid_msr_intercept(msr));
1067 offset = svm_msrpm_offset(msr);
1068 bit_read = 2 * (msr & 0x0f);
1069 bit_write = 2 * (msr & 0x0f) + 1;
1070 tmp = msrpm[offset];
1072 BUG_ON(offset == MSR_INVALID);
1074 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1075 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1077 msrpm[offset] = tmp;
1080 static void svm_vcpu_init_msrpm(u32 *msrpm)
1084 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1086 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1087 if (!direct_access_msrs[i].always)
1090 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1094 static void add_msr_offset(u32 offset)
1098 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1100 /* Offset already in list? */
1101 if (msrpm_offsets[i] == offset)
1104 /* Slot used by another offset? */
1105 if (msrpm_offsets[i] != MSR_INVALID)
1108 /* Add offset to list */
1109 msrpm_offsets[i] = offset;
1115 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1116 * increase MSRPM_OFFSETS in this case.
1121 static void init_msrpm_offsets(void)
1125 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1127 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1130 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1131 BUG_ON(offset == MSR_INVALID);
1133 add_msr_offset(offset);
1137 static void svm_enable_lbrv(struct vcpu_svm *svm)
1139 u32 *msrpm = svm->msrpm;
1141 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1142 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1143 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1144 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1145 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1148 static void svm_disable_lbrv(struct vcpu_svm *svm)
1150 u32 *msrpm = svm->msrpm;
1152 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1153 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1154 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1155 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1156 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1159 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1161 svm->nmi_singlestep = false;
1163 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1164 /* Clear our flags if they were not set by the guest */
1165 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1166 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1167 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1168 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1173 * This hash table is used to map VM_ID to a struct kvm_svm,
1174 * when handling AMD IOMMU GALOG notification to schedule in
1175 * a particular vCPU.
1177 #define SVM_VM_DATA_HASH_BITS 8
1178 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1179 static u32 next_vm_id = 0;
1180 static bool next_vm_id_wrapped = 0;
1181 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1184 * This function is called from IOMMU driver to notify
1185 * SVM to schedule in a particular vCPU of a particular VM.
1187 static int avic_ga_log_notifier(u32 ga_tag)
1189 unsigned long flags;
1190 struct kvm_svm *kvm_svm;
1191 struct kvm_vcpu *vcpu = NULL;
1192 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1193 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1195 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1197 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1198 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1199 if (kvm_svm->avic_vm_id != vm_id)
1201 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1204 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1207 * At this point, the IOMMU should have already set the pending
1208 * bit in the vAPIC backing page. So, we just need to schedule
1212 kvm_vcpu_wake_up(vcpu);
1217 static __init int sev_hardware_setup(void)
1219 struct sev_user_data_status *status;
1222 /* Maximum number of encrypted guests supported simultaneously */
1223 max_sev_asid = cpuid_ecx(0x8000001F);
1228 /* Minimum ASID value that should be used for SEV guest */
1229 min_sev_asid = cpuid_edx(0x8000001F);
1231 /* Initialize SEV ASID bitmap */
1232 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1233 if (!sev_asid_bitmap)
1236 status = kmalloc(sizeof(*status), GFP_KERNEL);
1241 * Check SEV platform status.
1243 * PLATFORM_STATUS can be called in any state, if we failed to query
1244 * the PLATFORM status then either PSP firmware does not support SEV
1245 * feature or SEV firmware is dead.
1247 rc = sev_platform_status(status, NULL);
1251 pr_info("SEV supported\n");
1258 static void grow_ple_window(struct kvm_vcpu *vcpu)
1260 struct vcpu_svm *svm = to_svm(vcpu);
1261 struct vmcb_control_area *control = &svm->vmcb->control;
1262 int old = control->pause_filter_count;
1264 control->pause_filter_count = __grow_ple_window(old,
1266 pause_filter_count_grow,
1267 pause_filter_count_max);
1269 if (control->pause_filter_count != old) {
1270 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1271 trace_kvm_ple_window_update(vcpu->vcpu_id,
1272 control->pause_filter_count, old);
1276 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1278 struct vcpu_svm *svm = to_svm(vcpu);
1279 struct vmcb_control_area *control = &svm->vmcb->control;
1280 int old = control->pause_filter_count;
1282 control->pause_filter_count =
1283 __shrink_ple_window(old,
1285 pause_filter_count_shrink,
1286 pause_filter_count);
1287 if (control->pause_filter_count != old) {
1288 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1289 trace_kvm_ple_window_update(vcpu->vcpu_id,
1290 control->pause_filter_count, old);
1294 static __init int svm_hardware_setup(void)
1297 struct page *iopm_pages;
1301 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1306 iopm_va = page_address(iopm_pages);
1307 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1308 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1310 init_msrpm_offsets();
1312 if (boot_cpu_has(X86_FEATURE_NX))
1313 kvm_enable_efer_bits(EFER_NX);
1315 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1316 kvm_enable_efer_bits(EFER_FFXSR);
1318 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1319 kvm_has_tsc_control = true;
1320 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1321 kvm_tsc_scaling_ratio_frac_bits = 32;
1324 /* Check for pause filtering support */
1325 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1326 pause_filter_count = 0;
1327 pause_filter_thresh = 0;
1328 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1329 pause_filter_thresh = 0;
1333 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1334 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1338 if (boot_cpu_has(X86_FEATURE_SEV) &&
1339 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1340 r = sev_hardware_setup();
1348 for_each_possible_cpu(cpu) {
1349 r = svm_cpu_init(cpu);
1354 if (!boot_cpu_has(X86_FEATURE_NPT))
1355 npt_enabled = false;
1357 if (npt_enabled && !npt) {
1358 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1359 npt_enabled = false;
1363 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1369 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1375 !boot_cpu_has(X86_FEATURE_AVIC) ||
1376 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1379 pr_info("AVIC enabled\n");
1381 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1387 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1388 !IS_ENABLED(CONFIG_X86_64)) {
1391 pr_info("Virtual VMLOAD VMSAVE supported\n");
1396 if (!boot_cpu_has(X86_FEATURE_VGIF))
1399 pr_info("Virtual GIF supported\n");
1405 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1410 static __exit void svm_hardware_unsetup(void)
1414 if (svm_sev_enabled())
1415 bitmap_free(sev_asid_bitmap);
1417 for_each_possible_cpu(cpu)
1418 svm_cpu_uninit(cpu);
1420 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1424 static void init_seg(struct vmcb_seg *seg)
1427 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1428 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1429 seg->limit = 0xffff;
1433 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1436 seg->attrib = SVM_SELECTOR_P_MASK | type;
1437 seg->limit = 0xffff;
1441 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1443 struct vcpu_svm *svm = to_svm(vcpu);
1445 if (is_guest_mode(vcpu))
1446 return svm->nested.hsave->control.tsc_offset;
1448 return vcpu->arch.tsc_offset;
1451 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1453 struct vcpu_svm *svm = to_svm(vcpu);
1454 u64 g_tsc_offset = 0;
1456 if (is_guest_mode(vcpu)) {
1457 /* Write L1's TSC offset. */
1458 g_tsc_offset = svm->vmcb->control.tsc_offset -
1459 svm->nested.hsave->control.tsc_offset;
1460 svm->nested.hsave->control.tsc_offset = offset;
1463 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1464 svm->vmcb->control.tsc_offset - g_tsc_offset,
1467 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1469 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1470 return svm->vmcb->control.tsc_offset;
1473 static void avic_init_vmcb(struct vcpu_svm *svm)
1475 struct vmcb *vmcb = svm->vmcb;
1476 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1477 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1478 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1479 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1481 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1482 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1483 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1484 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1485 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1488 static void init_vmcb(struct vcpu_svm *svm)
1490 struct vmcb_control_area *control = &svm->vmcb->control;
1491 struct vmcb_save_area *save = &svm->vmcb->save;
1493 svm->vcpu.arch.hflags = 0;
1495 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1496 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1497 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1498 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1499 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1500 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1501 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1502 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1504 set_dr_intercepts(svm);
1506 set_exception_intercept(svm, PF_VECTOR);
1507 set_exception_intercept(svm, UD_VECTOR);
1508 set_exception_intercept(svm, MC_VECTOR);
1509 set_exception_intercept(svm, AC_VECTOR);
1510 set_exception_intercept(svm, DB_VECTOR);
1512 * Guest access to VMware backdoor ports could legitimately
1513 * trigger #GP because of TSS I/O permission bitmap.
1514 * We intercept those #GP and allow access to them anyway
1517 if (enable_vmware_backdoor)
1518 set_exception_intercept(svm, GP_VECTOR);
1520 set_intercept(svm, INTERCEPT_INTR);
1521 set_intercept(svm, INTERCEPT_NMI);
1522 set_intercept(svm, INTERCEPT_SMI);
1523 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1524 set_intercept(svm, INTERCEPT_RDPMC);
1525 set_intercept(svm, INTERCEPT_CPUID);
1526 set_intercept(svm, INTERCEPT_INVD);
1527 set_intercept(svm, INTERCEPT_INVLPG);
1528 set_intercept(svm, INTERCEPT_INVLPGA);
1529 set_intercept(svm, INTERCEPT_IOIO_PROT);
1530 set_intercept(svm, INTERCEPT_MSR_PROT);
1531 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1532 set_intercept(svm, INTERCEPT_SHUTDOWN);
1533 set_intercept(svm, INTERCEPT_VMRUN);
1534 set_intercept(svm, INTERCEPT_VMMCALL);
1535 set_intercept(svm, INTERCEPT_VMLOAD);
1536 set_intercept(svm, INTERCEPT_VMSAVE);
1537 set_intercept(svm, INTERCEPT_STGI);
1538 set_intercept(svm, INTERCEPT_CLGI);
1539 set_intercept(svm, INTERCEPT_SKINIT);
1540 set_intercept(svm, INTERCEPT_WBINVD);
1541 set_intercept(svm, INTERCEPT_XSETBV);
1542 set_intercept(svm, INTERCEPT_RSM);
1544 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1545 set_intercept(svm, INTERCEPT_MONITOR);
1546 set_intercept(svm, INTERCEPT_MWAIT);
1549 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1550 set_intercept(svm, INTERCEPT_HLT);
1552 control->iopm_base_pa = __sme_set(iopm_base);
1553 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1554 control->int_ctl = V_INTR_MASKING_MASK;
1556 init_seg(&save->es);
1557 init_seg(&save->ss);
1558 init_seg(&save->ds);
1559 init_seg(&save->fs);
1560 init_seg(&save->gs);
1562 save->cs.selector = 0xf000;
1563 save->cs.base = 0xffff0000;
1564 /* Executable/Readable Code Segment */
1565 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1566 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1567 save->cs.limit = 0xffff;
1569 save->gdtr.limit = 0xffff;
1570 save->idtr.limit = 0xffff;
1572 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1573 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1575 svm_set_efer(&svm->vcpu, 0);
1576 save->dr6 = 0xffff0ff0;
1577 kvm_set_rflags(&svm->vcpu, 2);
1578 save->rip = 0x0000fff0;
1579 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1582 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1583 * It also updates the guest-visible cr0 value.
1585 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1586 kvm_mmu_reset_context(&svm->vcpu);
1588 save->cr4 = X86_CR4_PAE;
1592 /* Setup VMCB for Nested Paging */
1593 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1594 clr_intercept(svm, INTERCEPT_INVLPG);
1595 clr_exception_intercept(svm, PF_VECTOR);
1596 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1597 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1598 save->g_pat = svm->vcpu.arch.pat;
1602 svm->asid_generation = 0;
1604 svm->nested.vmcb = 0;
1605 svm->vcpu.arch.hflags = 0;
1607 if (pause_filter_count) {
1608 control->pause_filter_count = pause_filter_count;
1609 if (pause_filter_thresh)
1610 control->pause_filter_thresh = pause_filter_thresh;
1611 set_intercept(svm, INTERCEPT_PAUSE);
1613 clr_intercept(svm, INTERCEPT_PAUSE);
1616 if (kvm_vcpu_apicv_active(&svm->vcpu))
1617 avic_init_vmcb(svm);
1620 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1621 * in VMCB and clear intercepts to avoid #VMEXIT.
1624 clr_intercept(svm, INTERCEPT_VMLOAD);
1625 clr_intercept(svm, INTERCEPT_VMSAVE);
1626 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1630 clr_intercept(svm, INTERCEPT_STGI);
1631 clr_intercept(svm, INTERCEPT_CLGI);
1632 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1635 if (sev_guest(svm->vcpu.kvm)) {
1636 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1637 clr_exception_intercept(svm, UD_VECTOR);
1640 mark_all_dirty(svm->vmcb);
1646 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1649 u64 *avic_physical_id_table;
1650 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1652 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1655 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1657 return &avic_physical_id_table[index];
1662 * AVIC hardware walks the nested page table to check permissions,
1663 * but does not use the SPA address specified in the leaf page
1664 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1665 * field of the VMCB. Therefore, we set up the
1666 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1668 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1670 struct kvm *kvm = vcpu->kvm;
1673 mutex_lock(&kvm->slots_lock);
1674 if (kvm->arch.apic_access_page_done)
1677 ret = __x86_set_memory_region(kvm,
1678 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1679 APIC_DEFAULT_PHYS_BASE,
1684 kvm->arch.apic_access_page_done = true;
1686 mutex_unlock(&kvm->slots_lock);
1690 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1693 u64 *entry, new_entry;
1694 int id = vcpu->vcpu_id;
1695 struct vcpu_svm *svm = to_svm(vcpu);
1697 ret = avic_init_access_page(vcpu);
1701 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1704 if (!svm->vcpu.arch.apic->regs)
1707 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1709 /* Setting AVIC backing page address in the phy APIC ID table */
1710 entry = avic_get_physical_id_entry(vcpu, id);
1714 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1715 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1716 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1717 WRITE_ONCE(*entry, new_entry);
1719 svm->avic_physical_id_cache = entry;
1724 static void __sev_asid_free(int asid)
1726 struct svm_cpu_data *sd;
1730 clear_bit(pos, sev_asid_bitmap);
1732 for_each_possible_cpu(cpu) {
1733 sd = per_cpu(svm_data, cpu);
1734 sd->sev_vmcbs[pos] = NULL;
1738 static void sev_asid_free(struct kvm *kvm)
1740 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1742 __sev_asid_free(sev->asid);
1745 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1747 struct sev_data_decommission *decommission;
1748 struct sev_data_deactivate *data;
1753 data = kzalloc(sizeof(*data), GFP_KERNEL);
1757 /* deactivate handle */
1758 data->handle = handle;
1759 sev_guest_deactivate(data, NULL);
1761 wbinvd_on_all_cpus();
1762 sev_guest_df_flush(NULL);
1765 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1769 /* decommission handle */
1770 decommission->handle = handle;
1771 sev_guest_decommission(decommission, NULL);
1773 kfree(decommission);
1776 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1777 unsigned long ulen, unsigned long *n,
1780 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1781 unsigned long npages, npinned, size;
1782 unsigned long locked, lock_limit;
1783 struct page **pages;
1784 unsigned long first, last;
1786 if (ulen == 0 || uaddr + ulen < uaddr)
1789 /* Calculate number of pages. */
1790 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1791 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1792 npages = (last - first + 1);
1794 locked = sev->pages_locked + npages;
1795 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1796 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1797 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1801 /* Avoid using vmalloc for smaller buffers. */
1802 size = npages * sizeof(struct page *);
1803 if (size > PAGE_SIZE)
1804 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1807 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1812 /* Pin the user virtual address. */
1813 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1814 if (npinned != npages) {
1815 pr_err("SEV: Failure locking %lu pages.\n", npages);
1820 sev->pages_locked = locked;
1826 release_pages(pages, npinned);
1832 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1833 unsigned long npages)
1835 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1837 release_pages(pages, npages);
1839 sev->pages_locked -= npages;
1842 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1844 uint8_t *page_virtual;
1847 if (npages == 0 || pages == NULL)
1850 for (i = 0; i < npages; i++) {
1851 page_virtual = kmap_atomic(pages[i]);
1852 clflush_cache_range(page_virtual, PAGE_SIZE);
1853 kunmap_atomic(page_virtual);
1857 static void __unregister_enc_region_locked(struct kvm *kvm,
1858 struct enc_region *region)
1861 * The guest may change the memory encryption attribute from C=0 -> C=1
1862 * or vice versa for this memory range. Lets make sure caches are
1863 * flushed to ensure that guest data gets written into memory with
1866 sev_clflush_pages(region->pages, region->npages);
1868 sev_unpin_memory(kvm, region->pages, region->npages);
1869 list_del(®ion->list);
1873 static struct kvm *svm_vm_alloc(void)
1875 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1876 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1878 return &kvm_svm->kvm;
1881 static void svm_vm_free(struct kvm *kvm)
1883 vfree(to_kvm_svm(kvm));
1886 static void sev_vm_destroy(struct kvm *kvm)
1888 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1889 struct list_head *head = &sev->regions_list;
1890 struct list_head *pos, *q;
1892 if (!sev_guest(kvm))
1895 mutex_lock(&kvm->lock);
1898 * if userspace was terminated before unregistering the memory regions
1899 * then lets unpin all the registered memory.
1901 if (!list_empty(head)) {
1902 list_for_each_safe(pos, q, head) {
1903 __unregister_enc_region_locked(kvm,
1904 list_entry(pos, struct enc_region, list));
1908 mutex_unlock(&kvm->lock);
1910 sev_unbind_asid(kvm, sev->handle);
1914 static void avic_vm_destroy(struct kvm *kvm)
1916 unsigned long flags;
1917 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1922 if (kvm_svm->avic_logical_id_table_page)
1923 __free_page(kvm_svm->avic_logical_id_table_page);
1924 if (kvm_svm->avic_physical_id_table_page)
1925 __free_page(kvm_svm->avic_physical_id_table_page);
1927 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1928 hash_del(&kvm_svm->hnode);
1929 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1932 static void svm_vm_destroy(struct kvm *kvm)
1934 avic_vm_destroy(kvm);
1935 sev_vm_destroy(kvm);
1938 static int avic_vm_init(struct kvm *kvm)
1940 unsigned long flags;
1942 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1944 struct page *p_page;
1945 struct page *l_page;
1951 /* Allocating physical APIC ID table (4KB) */
1952 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1956 kvm_svm->avic_physical_id_table_page = p_page;
1957 clear_page(page_address(p_page));
1959 /* Allocating logical APIC ID table (4KB) */
1960 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1964 kvm_svm->avic_logical_id_table_page = l_page;
1965 clear_page(page_address(l_page));
1967 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1969 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1970 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1971 next_vm_id_wrapped = 1;
1974 /* Is it still in use? Only possible if wrapped at least once */
1975 if (next_vm_id_wrapped) {
1976 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1977 if (k2->avic_vm_id == vm_id)
1981 kvm_svm->avic_vm_id = vm_id;
1982 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1983 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1988 avic_vm_destroy(kvm);
1993 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1996 unsigned long flags;
1997 struct amd_svm_iommu_ir *ir;
1998 struct vcpu_svm *svm = to_svm(vcpu);
2000 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2004 * Here, we go through the per-vcpu ir_list to update all existing
2005 * interrupt remapping table entry targeting this vcpu.
2007 spin_lock_irqsave(&svm->ir_list_lock, flags);
2009 if (list_empty(&svm->ir_list))
2012 list_for_each_entry(ir, &svm->ir_list, node) {
2013 ret = amd_iommu_update_ga(cpu, r, ir->data);
2018 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2022 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2025 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2026 int h_physical_id = kvm_cpu_get_apicid(cpu);
2027 struct vcpu_svm *svm = to_svm(vcpu);
2029 if (!kvm_vcpu_apicv_active(vcpu))
2033 * Since the host physical APIC id is 8 bits,
2034 * we can support host APIC ID upto 255.
2036 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2039 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2040 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2042 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2043 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2045 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2046 if (svm->avic_is_running)
2047 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2049 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2050 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2051 svm->avic_is_running);
2054 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2057 struct vcpu_svm *svm = to_svm(vcpu);
2059 if (!kvm_vcpu_apicv_active(vcpu))
2062 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2063 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2064 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2066 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2067 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2071 * This function is called during VCPU halt/unhalt.
2073 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2075 struct vcpu_svm *svm = to_svm(vcpu);
2077 svm->avic_is_running = is_run;
2079 avic_vcpu_load(vcpu, vcpu->cpu);
2081 avic_vcpu_put(vcpu);
2084 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2086 struct vcpu_svm *svm = to_svm(vcpu);
2090 vcpu->arch.microcode_version = 0x01000065;
2092 svm->virt_spec_ctrl = 0;
2095 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2096 MSR_IA32_APICBASE_ENABLE;
2097 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2098 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2102 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2103 kvm_rdx_write(vcpu, eax);
2105 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2106 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2109 static int avic_init_vcpu(struct vcpu_svm *svm)
2113 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2116 ret = avic_init_backing_page(&svm->vcpu);
2120 INIT_LIST_HEAD(&svm->ir_list);
2121 spin_lock_init(&svm->ir_list_lock);
2122 svm->dfr_reg = APIC_DFR_FLAT;
2127 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2129 struct vcpu_svm *svm;
2131 struct page *msrpm_pages;
2132 struct page *hsave_page;
2133 struct page *nested_msrpm_pages;
2136 BUILD_BUG_ON_MSG(offsetof(struct vcpu_svm, vcpu) != 0,
2137 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
2139 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2145 svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
2146 GFP_KERNEL_ACCOUNT);
2147 if (!svm->vcpu.arch.user_fpu) {
2148 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
2150 goto free_partial_svm;
2153 svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2154 GFP_KERNEL_ACCOUNT);
2155 if (!svm->vcpu.arch.guest_fpu) {
2156 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2161 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2166 page = alloc_page(GFP_KERNEL_ACCOUNT);
2170 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2174 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2175 if (!nested_msrpm_pages)
2178 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2182 err = avic_init_vcpu(svm);
2186 /* We initialize this flag to true to make sure that the is_running
2187 * bit would be set the first time the vcpu is loaded.
2189 svm->avic_is_running = true;
2191 svm->nested.hsave = page_address(hsave_page);
2193 svm->msrpm = page_address(msrpm_pages);
2194 svm_vcpu_init_msrpm(svm->msrpm);
2196 svm->nested.msrpm = page_address(nested_msrpm_pages);
2197 svm_vcpu_init_msrpm(svm->nested.msrpm);
2199 svm->vmcb = page_address(page);
2200 clear_page(svm->vmcb);
2201 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2202 svm->asid_generation = 0;
2205 svm_init_osvw(&svm->vcpu);
2210 __free_page(hsave_page);
2212 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2214 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2218 kvm_vcpu_uninit(&svm->vcpu);
2220 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2222 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2224 kmem_cache_free(kvm_vcpu_cache, svm);
2226 return ERR_PTR(err);
2229 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2233 for_each_online_cpu(i)
2234 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2237 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2239 struct vcpu_svm *svm = to_svm(vcpu);
2242 * The vmcb page can be recycled, causing a false negative in
2243 * svm_vcpu_load(). So, ensure that no logical CPU has this
2244 * vmcb page recorded as its current vmcb.
2246 svm_clear_current_vmcb(svm->vmcb);
2248 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2249 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2250 __free_page(virt_to_page(svm->nested.hsave));
2251 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2252 kvm_vcpu_uninit(vcpu);
2253 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2254 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2255 kmem_cache_free(kvm_vcpu_cache, svm);
2258 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2260 struct vcpu_svm *svm = to_svm(vcpu);
2261 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2264 if (unlikely(cpu != vcpu->cpu)) {
2265 svm->asid_generation = 0;
2266 mark_all_dirty(svm->vmcb);
2269 #ifdef CONFIG_X86_64
2270 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2272 savesegment(fs, svm->host.fs);
2273 savesegment(gs, svm->host.gs);
2274 svm->host.ldt = kvm_read_ldt();
2276 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2277 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2279 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2280 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2281 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2282 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2283 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2286 /* This assumes that the kernel never uses MSR_TSC_AUX */
2287 if (static_cpu_has(X86_FEATURE_RDTSCP))
2288 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2290 if (sd->current_vmcb != svm->vmcb) {
2291 sd->current_vmcb = svm->vmcb;
2292 indirect_branch_prediction_barrier();
2294 avic_vcpu_load(vcpu, cpu);
2297 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2299 struct vcpu_svm *svm = to_svm(vcpu);
2302 avic_vcpu_put(vcpu);
2304 ++vcpu->stat.host_state_reload;
2305 kvm_load_ldt(svm->host.ldt);
2306 #ifdef CONFIG_X86_64
2307 loadsegment(fs, svm->host.fs);
2308 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2309 load_gs_index(svm->host.gs);
2311 #ifdef CONFIG_X86_32_LAZY_GS
2312 loadsegment(gs, svm->host.gs);
2315 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2316 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2319 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2321 avic_set_running(vcpu, false);
2324 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2326 avic_set_running(vcpu, true);
2329 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2331 struct vcpu_svm *svm = to_svm(vcpu);
2332 unsigned long rflags = svm->vmcb->save.rflags;
2334 if (svm->nmi_singlestep) {
2335 /* Hide our flags if they were not set by the guest */
2336 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2337 rflags &= ~X86_EFLAGS_TF;
2338 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2339 rflags &= ~X86_EFLAGS_RF;
2344 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2346 if (to_svm(vcpu)->nmi_singlestep)
2347 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2350 * Any change of EFLAGS.VM is accompanied by a reload of SS
2351 * (caused by either a task switch or an inter-privilege IRET),
2352 * so we do not need to update the CPL here.
2354 to_svm(vcpu)->vmcb->save.rflags = rflags;
2357 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2360 case VCPU_EXREG_PDPTR:
2361 BUG_ON(!npt_enabled);
2362 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2369 static void svm_set_vintr(struct vcpu_svm *svm)
2371 set_intercept(svm, INTERCEPT_VINTR);
2374 static void svm_clear_vintr(struct vcpu_svm *svm)
2376 clr_intercept(svm, INTERCEPT_VINTR);
2379 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2381 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2384 case VCPU_SREG_CS: return &save->cs;
2385 case VCPU_SREG_DS: return &save->ds;
2386 case VCPU_SREG_ES: return &save->es;
2387 case VCPU_SREG_FS: return &save->fs;
2388 case VCPU_SREG_GS: return &save->gs;
2389 case VCPU_SREG_SS: return &save->ss;
2390 case VCPU_SREG_TR: return &save->tr;
2391 case VCPU_SREG_LDTR: return &save->ldtr;
2397 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2399 struct vmcb_seg *s = svm_seg(vcpu, seg);
2404 static void svm_get_segment(struct kvm_vcpu *vcpu,
2405 struct kvm_segment *var, int seg)
2407 struct vmcb_seg *s = svm_seg(vcpu, seg);
2409 var->base = s->base;
2410 var->limit = s->limit;
2411 var->selector = s->selector;
2412 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2413 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2414 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2415 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2416 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2417 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2418 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2421 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2422 * However, the SVM spec states that the G bit is not observed by the
2423 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2424 * So let's synthesize a legal G bit for all segments, this helps
2425 * running KVM nested. It also helps cross-vendor migration, because
2426 * Intel's vmentry has a check on the 'G' bit.
2428 var->g = s->limit > 0xfffff;
2431 * AMD's VMCB does not have an explicit unusable field, so emulate it
2432 * for cross vendor migration purposes by "not present"
2434 var->unusable = !var->present;
2439 * Work around a bug where the busy flag in the tr selector
2449 * The accessed bit must always be set in the segment
2450 * descriptor cache, although it can be cleared in the
2451 * descriptor, the cached bit always remains at 1. Since
2452 * Intel has a check on this, set it here to support
2453 * cross-vendor migration.
2460 * On AMD CPUs sometimes the DB bit in the segment
2461 * descriptor is left as 1, although the whole segment has
2462 * been made unusable. Clear it here to pass an Intel VMX
2463 * entry check when cross vendor migrating.
2467 /* This is symmetric with svm_set_segment() */
2468 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2473 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2475 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2480 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2482 struct vcpu_svm *svm = to_svm(vcpu);
2484 dt->size = svm->vmcb->save.idtr.limit;
2485 dt->address = svm->vmcb->save.idtr.base;
2488 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2490 struct vcpu_svm *svm = to_svm(vcpu);
2492 svm->vmcb->save.idtr.limit = dt->size;
2493 svm->vmcb->save.idtr.base = dt->address ;
2494 mark_dirty(svm->vmcb, VMCB_DT);
2497 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2499 struct vcpu_svm *svm = to_svm(vcpu);
2501 dt->size = svm->vmcb->save.gdtr.limit;
2502 dt->address = svm->vmcb->save.gdtr.base;
2505 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2507 struct vcpu_svm *svm = to_svm(vcpu);
2509 svm->vmcb->save.gdtr.limit = dt->size;
2510 svm->vmcb->save.gdtr.base = dt->address ;
2511 mark_dirty(svm->vmcb, VMCB_DT);
2514 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2518 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2522 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2526 static void update_cr0_intercept(struct vcpu_svm *svm)
2528 ulong gcr0 = svm->vcpu.arch.cr0;
2529 u64 *hcr0 = &svm->vmcb->save.cr0;
2531 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2532 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2534 mark_dirty(svm->vmcb, VMCB_CR);
2536 if (gcr0 == *hcr0) {
2537 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2538 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2540 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2541 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2545 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2547 struct vcpu_svm *svm = to_svm(vcpu);
2549 #ifdef CONFIG_X86_64
2550 if (vcpu->arch.efer & EFER_LME) {
2551 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2552 vcpu->arch.efer |= EFER_LMA;
2553 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2556 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2557 vcpu->arch.efer &= ~EFER_LMA;
2558 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2562 vcpu->arch.cr0 = cr0;
2565 cr0 |= X86_CR0_PG | X86_CR0_WP;
2568 * re-enable caching here because the QEMU bios
2569 * does not do it - this results in some delay at
2572 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2573 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2574 svm->vmcb->save.cr0 = cr0;
2575 mark_dirty(svm->vmcb, VMCB_CR);
2576 update_cr0_intercept(svm);
2579 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2581 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2582 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2584 if (cr4 & X86_CR4_VMXE)
2587 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2588 svm_flush_tlb(vcpu, true);
2590 vcpu->arch.cr4 = cr4;
2593 cr4 |= host_cr4_mce;
2594 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2595 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2599 static void svm_set_segment(struct kvm_vcpu *vcpu,
2600 struct kvm_segment *var, int seg)
2602 struct vcpu_svm *svm = to_svm(vcpu);
2603 struct vmcb_seg *s = svm_seg(vcpu, seg);
2605 s->base = var->base;
2606 s->limit = var->limit;
2607 s->selector = var->selector;
2608 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2609 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2610 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2611 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2612 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2613 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2614 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2615 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2618 * This is always accurate, except if SYSRET returned to a segment
2619 * with SS.DPL != 3. Intel does not have this quirk, and always
2620 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2621 * would entail passing the CPL to userspace and back.
2623 if (seg == VCPU_SREG_SS)
2624 /* This is symmetric with svm_get_segment() */
2625 svm->vmcb->save.cpl = (var->dpl & 3);
2627 mark_dirty(svm->vmcb, VMCB_SEG);
2630 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2632 struct vcpu_svm *svm = to_svm(vcpu);
2634 clr_exception_intercept(svm, BP_VECTOR);
2636 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2637 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2638 set_exception_intercept(svm, BP_VECTOR);
2640 vcpu->guest_debug = 0;
2643 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2645 if (sd->next_asid > sd->max_asid) {
2646 ++sd->asid_generation;
2647 sd->next_asid = sd->min_asid;
2648 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2651 svm->asid_generation = sd->asid_generation;
2652 svm->vmcb->control.asid = sd->next_asid++;
2654 mark_dirty(svm->vmcb, VMCB_ASID);
2657 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2659 return to_svm(vcpu)->vmcb->save.dr6;
2662 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2664 struct vcpu_svm *svm = to_svm(vcpu);
2666 svm->vmcb->save.dr6 = value;
2667 mark_dirty(svm->vmcb, VMCB_DR);
2670 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2672 struct vcpu_svm *svm = to_svm(vcpu);
2674 get_debugreg(vcpu->arch.db[0], 0);
2675 get_debugreg(vcpu->arch.db[1], 1);
2676 get_debugreg(vcpu->arch.db[2], 2);
2677 get_debugreg(vcpu->arch.db[3], 3);
2678 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2679 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2681 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2682 set_dr_intercepts(svm);
2685 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2687 struct vcpu_svm *svm = to_svm(vcpu);
2689 svm->vmcb->save.dr7 = value;
2690 mark_dirty(svm->vmcb, VMCB_DR);
2693 static int pf_interception(struct vcpu_svm *svm)
2695 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2696 u64 error_code = svm->vmcb->control.exit_info_1;
2698 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2699 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2700 svm->vmcb->control.insn_bytes : NULL,
2701 svm->vmcb->control.insn_len);
2704 static int npf_interception(struct vcpu_svm *svm)
2706 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2707 u64 error_code = svm->vmcb->control.exit_info_1;
2709 trace_kvm_page_fault(fault_address, error_code);
2710 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2711 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2712 svm->vmcb->control.insn_bytes : NULL,
2713 svm->vmcb->control.insn_len);
2716 static int db_interception(struct vcpu_svm *svm)
2718 struct kvm_run *kvm_run = svm->vcpu.run;
2719 struct kvm_vcpu *vcpu = &svm->vcpu;
2721 if (!(svm->vcpu.guest_debug &
2722 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2723 !svm->nmi_singlestep) {
2724 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2728 if (svm->nmi_singlestep) {
2729 disable_nmi_singlestep(svm);
2730 /* Make sure we check for pending NMIs upon entry */
2731 kvm_make_request(KVM_REQ_EVENT, vcpu);
2734 if (svm->vcpu.guest_debug &
2735 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2736 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2737 kvm_run->debug.arch.pc =
2738 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2739 kvm_run->debug.arch.exception = DB_VECTOR;
2746 static int bp_interception(struct vcpu_svm *svm)
2748 struct kvm_run *kvm_run = svm->vcpu.run;
2750 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2751 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2752 kvm_run->debug.arch.exception = BP_VECTOR;
2756 static int ud_interception(struct vcpu_svm *svm)
2758 return handle_ud(&svm->vcpu);
2761 static int ac_interception(struct vcpu_svm *svm)
2763 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2767 static int gp_interception(struct vcpu_svm *svm)
2769 struct kvm_vcpu *vcpu = &svm->vcpu;
2770 u32 error_code = svm->vmcb->control.exit_info_1;
2773 WARN_ON_ONCE(!enable_vmware_backdoor);
2776 * VMware backdoor emulation on #GP interception only handles IN{S},
2777 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2780 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2783 er = kvm_emulate_instruction(vcpu,
2784 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2785 if (er == EMULATE_USER_EXIT)
2787 else if (er != EMULATE_DONE)
2788 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2792 static bool is_erratum_383(void)
2797 if (!erratum_383_found)
2800 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2804 /* Bit 62 may or may not be set for this mce */
2805 value &= ~(1ULL << 62);
2807 if (value != 0xb600000000010015ULL)
2810 /* Clear MCi_STATUS registers */
2811 for (i = 0; i < 6; ++i)
2812 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2814 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2818 value &= ~(1ULL << 2);
2819 low = lower_32_bits(value);
2820 high = upper_32_bits(value);
2822 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2825 /* Flush tlb to evict multi-match entries */
2831 static void svm_handle_mce(struct vcpu_svm *svm)
2833 if (is_erratum_383()) {
2835 * Erratum 383 triggered. Guest state is corrupt so kill the
2838 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2840 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2846 * On an #MC intercept the MCE handler is not called automatically in
2847 * the host. So do it by hand here.
2851 /* not sure if we ever come back to this point */
2856 static int mc_interception(struct vcpu_svm *svm)
2861 static int shutdown_interception(struct vcpu_svm *svm)
2863 struct kvm_run *kvm_run = svm->vcpu.run;
2866 * VMCB is undefined after a SHUTDOWN intercept
2867 * so reinitialize it.
2869 clear_page(svm->vmcb);
2872 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2876 static int io_interception(struct vcpu_svm *svm)
2878 struct kvm_vcpu *vcpu = &svm->vcpu;
2879 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2880 int size, in, string;
2883 ++svm->vcpu.stat.io_exits;
2884 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2885 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2887 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2889 port = io_info >> 16;
2890 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2891 svm->next_rip = svm->vmcb->control.exit_info_2;
2893 return kvm_fast_pio(&svm->vcpu, size, port, in);
2896 static int nmi_interception(struct vcpu_svm *svm)
2901 static int intr_interception(struct vcpu_svm *svm)
2903 ++svm->vcpu.stat.irq_exits;
2907 static int nop_on_interception(struct vcpu_svm *svm)
2912 static int halt_interception(struct vcpu_svm *svm)
2914 return kvm_emulate_halt(&svm->vcpu);
2917 static int vmmcall_interception(struct vcpu_svm *svm)
2919 return kvm_emulate_hypercall(&svm->vcpu);
2922 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2924 struct vcpu_svm *svm = to_svm(vcpu);
2926 return svm->nested.nested_cr3;
2929 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2931 struct vcpu_svm *svm = to_svm(vcpu);
2932 u64 cr3 = svm->nested.nested_cr3;
2936 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2937 offset_in_page(cr3) + index * 8, 8);
2943 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2946 struct vcpu_svm *svm = to_svm(vcpu);
2948 svm->vmcb->control.nested_cr3 = __sme_set(root);
2949 mark_dirty(svm->vmcb, VMCB_NPT);
2952 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2953 struct x86_exception *fault)
2955 struct vcpu_svm *svm = to_svm(vcpu);
2957 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2959 * TODO: track the cause of the nested page fault, and
2960 * correctly fill in the high bits of exit_info_1.
2962 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2963 svm->vmcb->control.exit_code_hi = 0;
2964 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2965 svm->vmcb->control.exit_info_2 = fault->address;
2968 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2969 svm->vmcb->control.exit_info_1 |= fault->error_code;
2972 * The present bit is always zero for page structure faults on real
2975 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2976 svm->vmcb->control.exit_info_1 &= ~1;
2978 nested_svm_vmexit(svm);
2981 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2983 WARN_ON(mmu_is_nested(vcpu));
2985 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2986 kvm_init_shadow_mmu(vcpu);
2987 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
2988 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
2989 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
2990 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2991 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2992 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2993 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2996 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2998 vcpu->arch.mmu = &vcpu->arch.root_mmu;
2999 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3002 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3004 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3005 !is_paging(&svm->vcpu)) {
3006 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3010 if (svm->vmcb->save.cpl) {
3011 kvm_inject_gp(&svm->vcpu, 0);
3018 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3019 bool has_error_code, u32 error_code)
3023 if (!is_guest_mode(&svm->vcpu))
3026 vmexit = nested_svm_intercept(svm);
3027 if (vmexit != NESTED_EXIT_DONE)
3030 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3031 svm->vmcb->control.exit_code_hi = 0;
3032 svm->vmcb->control.exit_info_1 = error_code;
3035 * EXITINFO2 is undefined for all exception intercepts other
3038 if (svm->vcpu.arch.exception.nested_apf)
3039 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3040 else if (svm->vcpu.arch.exception.has_payload)
3041 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3043 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3045 svm->nested.exit_required = true;
3049 /* This function returns true if it is save to enable the irq window */
3050 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3052 if (!is_guest_mode(&svm->vcpu))
3055 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3058 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3062 * if vmexit was already requested (by intercepted exception
3063 * for instance) do not overwrite it with "external interrupt"
3066 if (svm->nested.exit_required)
3069 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3070 svm->vmcb->control.exit_info_1 = 0;
3071 svm->vmcb->control.exit_info_2 = 0;
3073 if (svm->nested.intercept & 1ULL) {
3075 * The #vmexit can't be emulated here directly because this
3076 * code path runs with irqs and preemption disabled. A
3077 * #vmexit emulation might sleep. Only signal request for
3080 svm->nested.exit_required = true;
3081 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3088 /* This function returns true if it is save to enable the nmi window */
3089 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3091 if (!is_guest_mode(&svm->vcpu))
3094 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3097 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3098 svm->nested.exit_required = true;
3103 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3105 unsigned port, size, iopm_len;
3110 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3111 return NESTED_EXIT_HOST;
3113 port = svm->vmcb->control.exit_info_1 >> 16;
3114 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3115 SVM_IOIO_SIZE_SHIFT;
3116 gpa = svm->nested.vmcb_iopm + (port / 8);
3117 start_bit = port % 8;
3118 iopm_len = (start_bit + size > 8) ? 2 : 1;
3119 mask = (0xf >> (4 - size)) << start_bit;
3122 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3123 return NESTED_EXIT_DONE;
3125 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3128 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3130 u32 offset, msr, value;
3133 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3134 return NESTED_EXIT_HOST;
3136 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3137 offset = svm_msrpm_offset(msr);
3138 write = svm->vmcb->control.exit_info_1 & 1;
3139 mask = 1 << ((2 * (msr & 0xf)) + write);
3141 if (offset == MSR_INVALID)
3142 return NESTED_EXIT_DONE;
3144 /* Offset is in 32 bit units but need in 8 bit units */
3147 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3148 return NESTED_EXIT_DONE;
3150 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3153 /* DB exceptions for our internal use must not cause vmexit */
3154 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3158 /* if we're not singlestepping, it's not ours */
3159 if (!svm->nmi_singlestep)
3160 return NESTED_EXIT_DONE;
3162 /* if it's not a singlestep exception, it's not ours */
3163 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3164 return NESTED_EXIT_DONE;
3165 if (!(dr6 & DR6_BS))
3166 return NESTED_EXIT_DONE;
3168 /* if the guest is singlestepping, it should get the vmexit */
3169 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3170 disable_nmi_singlestep(svm);
3171 return NESTED_EXIT_DONE;
3174 /* it's ours, the nested hypervisor must not see this one */
3175 return NESTED_EXIT_HOST;
3178 static int nested_svm_exit_special(struct vcpu_svm *svm)
3180 u32 exit_code = svm->vmcb->control.exit_code;
3182 switch (exit_code) {
3185 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3186 return NESTED_EXIT_HOST;
3188 /* For now we are always handling NPFs when using them */
3190 return NESTED_EXIT_HOST;
3192 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3193 /* When we're shadowing, trap PFs, but not async PF */
3194 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3195 return NESTED_EXIT_HOST;
3201 return NESTED_EXIT_CONTINUE;
3205 * If this function returns true, this #vmexit was already handled
3207 static int nested_svm_intercept(struct vcpu_svm *svm)
3209 u32 exit_code = svm->vmcb->control.exit_code;
3210 int vmexit = NESTED_EXIT_HOST;
3212 switch (exit_code) {
3214 vmexit = nested_svm_exit_handled_msr(svm);
3217 vmexit = nested_svm_intercept_ioio(svm);
3219 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3220 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3221 if (svm->nested.intercept_cr & bit)
3222 vmexit = NESTED_EXIT_DONE;
3225 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3226 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3227 if (svm->nested.intercept_dr & bit)
3228 vmexit = NESTED_EXIT_DONE;
3231 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3232 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3233 if (svm->nested.intercept_exceptions & excp_bits) {
3234 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3235 vmexit = nested_svm_intercept_db(svm);
3237 vmexit = NESTED_EXIT_DONE;
3239 /* async page fault always cause vmexit */
3240 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3241 svm->vcpu.arch.exception.nested_apf != 0)
3242 vmexit = NESTED_EXIT_DONE;
3245 case SVM_EXIT_ERR: {
3246 vmexit = NESTED_EXIT_DONE;
3250 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3251 if (svm->nested.intercept & exit_bits)
3252 vmexit = NESTED_EXIT_DONE;
3259 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3263 vmexit = nested_svm_intercept(svm);
3265 if (vmexit == NESTED_EXIT_DONE)
3266 nested_svm_vmexit(svm);
3271 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3273 struct vmcb_control_area *dst = &dst_vmcb->control;
3274 struct vmcb_control_area *from = &from_vmcb->control;
3276 dst->intercept_cr = from->intercept_cr;
3277 dst->intercept_dr = from->intercept_dr;
3278 dst->intercept_exceptions = from->intercept_exceptions;
3279 dst->intercept = from->intercept;
3280 dst->iopm_base_pa = from->iopm_base_pa;
3281 dst->msrpm_base_pa = from->msrpm_base_pa;
3282 dst->tsc_offset = from->tsc_offset;
3283 dst->asid = from->asid;
3284 dst->tlb_ctl = from->tlb_ctl;
3285 dst->int_ctl = from->int_ctl;
3286 dst->int_vector = from->int_vector;
3287 dst->int_state = from->int_state;
3288 dst->exit_code = from->exit_code;
3289 dst->exit_code_hi = from->exit_code_hi;
3290 dst->exit_info_1 = from->exit_info_1;
3291 dst->exit_info_2 = from->exit_info_2;
3292 dst->exit_int_info = from->exit_int_info;
3293 dst->exit_int_info_err = from->exit_int_info_err;
3294 dst->nested_ctl = from->nested_ctl;
3295 dst->event_inj = from->event_inj;
3296 dst->event_inj_err = from->event_inj_err;
3297 dst->nested_cr3 = from->nested_cr3;
3298 dst->virt_ext = from->virt_ext;
3299 dst->pause_filter_count = from->pause_filter_count;
3300 dst->pause_filter_thresh = from->pause_filter_thresh;
3303 static int nested_svm_vmexit(struct vcpu_svm *svm)
3306 struct vmcb *nested_vmcb;
3307 struct vmcb *hsave = svm->nested.hsave;
3308 struct vmcb *vmcb = svm->vmcb;
3309 struct kvm_host_map map;
3311 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3312 vmcb->control.exit_info_1,
3313 vmcb->control.exit_info_2,
3314 vmcb->control.exit_int_info,
3315 vmcb->control.exit_int_info_err,
3318 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3321 kvm_inject_gp(&svm->vcpu, 0);
3325 nested_vmcb = map.hva;
3327 /* Exit Guest-Mode */
3328 leave_guest_mode(&svm->vcpu);
3329 svm->nested.vmcb = 0;
3331 /* Give the current vmcb to the guest */
3334 nested_vmcb->save.es = vmcb->save.es;
3335 nested_vmcb->save.cs = vmcb->save.cs;
3336 nested_vmcb->save.ss = vmcb->save.ss;
3337 nested_vmcb->save.ds = vmcb->save.ds;
3338 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3339 nested_vmcb->save.idtr = vmcb->save.idtr;
3340 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3341 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3342 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3343 nested_vmcb->save.cr2 = vmcb->save.cr2;
3344 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3345 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3346 nested_vmcb->save.rip = vmcb->save.rip;
3347 nested_vmcb->save.rsp = vmcb->save.rsp;
3348 nested_vmcb->save.rax = vmcb->save.rax;
3349 nested_vmcb->save.dr7 = vmcb->save.dr7;
3350 nested_vmcb->save.dr6 = vmcb->save.dr6;
3351 nested_vmcb->save.cpl = vmcb->save.cpl;
3353 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3354 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3355 nested_vmcb->control.int_state = vmcb->control.int_state;
3356 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3357 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3358 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3359 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3360 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3361 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3363 if (svm->nrips_enabled)
3364 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3367 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3368 * to make sure that we do not lose injected events. So check event_inj
3369 * here and copy it to exit_int_info if it is valid.
3370 * Exit_int_info and event_inj can't be both valid because the case
3371 * below only happens on a VMRUN instruction intercept which has
3372 * no valid exit_int_info set.
3374 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3375 struct vmcb_control_area *nc = &nested_vmcb->control;
3377 nc->exit_int_info = vmcb->control.event_inj;
3378 nc->exit_int_info_err = vmcb->control.event_inj_err;
3381 nested_vmcb->control.tlb_ctl = 0;
3382 nested_vmcb->control.event_inj = 0;
3383 nested_vmcb->control.event_inj_err = 0;
3385 nested_vmcb->control.pause_filter_count =
3386 svm->vmcb->control.pause_filter_count;
3387 nested_vmcb->control.pause_filter_thresh =
3388 svm->vmcb->control.pause_filter_thresh;
3390 /* We always set V_INTR_MASKING and remember the old value in hflags */
3391 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3392 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3394 /* Restore the original control entries */
3395 copy_vmcb_control_area(vmcb, hsave);
3397 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3398 kvm_clear_exception_queue(&svm->vcpu);
3399 kvm_clear_interrupt_queue(&svm->vcpu);
3401 svm->nested.nested_cr3 = 0;
3403 /* Restore selected save entries */
3404 svm->vmcb->save.es = hsave->save.es;
3405 svm->vmcb->save.cs = hsave->save.cs;
3406 svm->vmcb->save.ss = hsave->save.ss;
3407 svm->vmcb->save.ds = hsave->save.ds;
3408 svm->vmcb->save.gdtr = hsave->save.gdtr;
3409 svm->vmcb->save.idtr = hsave->save.idtr;
3410 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3411 svm_set_efer(&svm->vcpu, hsave->save.efer);
3412 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3413 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3415 svm->vmcb->save.cr3 = hsave->save.cr3;
3416 svm->vcpu.arch.cr3 = hsave->save.cr3;
3418 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3420 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3421 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3422 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3423 svm->vmcb->save.dr7 = 0;
3424 svm->vmcb->save.cpl = 0;
3425 svm->vmcb->control.exit_int_info = 0;
3427 mark_all_dirty(svm->vmcb);
3429 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3431 nested_svm_uninit_mmu_context(&svm->vcpu);
3432 kvm_mmu_reset_context(&svm->vcpu);
3433 kvm_mmu_load(&svm->vcpu);
3436 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3437 * doesn't end up in L1.
3439 svm->vcpu.arch.nmi_injected = false;
3440 kvm_clear_exception_queue(&svm->vcpu);
3441 kvm_clear_interrupt_queue(&svm->vcpu);
3446 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3449 * This function merges the msr permission bitmaps of kvm and the
3450 * nested vmcb. It is optimized in that it only merges the parts where
3451 * the kvm msr permission bitmap may contain zero bits
3455 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3458 for (i = 0; i < MSRPM_OFFSETS; i++) {
3462 if (msrpm_offsets[i] == 0xffffffff)
3465 p = msrpm_offsets[i];
3466 offset = svm->nested.vmcb_msrpm + (p * 4);
3468 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3471 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3474 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3479 static bool nested_vmcb_checks(struct vmcb *vmcb)
3481 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3484 if (vmcb->control.asid == 0)
3487 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3494 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3495 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3497 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3498 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3500 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3502 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3503 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3504 nested_svm_init_mmu_context(&svm->vcpu);
3507 /* Load the nested guest state */
3508 svm->vmcb->save.es = nested_vmcb->save.es;
3509 svm->vmcb->save.cs = nested_vmcb->save.cs;
3510 svm->vmcb->save.ss = nested_vmcb->save.ss;
3511 svm->vmcb->save.ds = nested_vmcb->save.ds;
3512 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3513 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3514 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3515 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3516 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3517 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3519 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3520 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3522 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3524 /* Guest paging mode is active - reset mmu */
3525 kvm_mmu_reset_context(&svm->vcpu);
3527 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3528 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3529 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3530 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3532 /* In case we don't even reach vcpu_run, the fields are not updated */
3533 svm->vmcb->save.rax = nested_vmcb->save.rax;
3534 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3535 svm->vmcb->save.rip = nested_vmcb->save.rip;
3536 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3537 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3538 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3540 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3541 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3543 /* cache intercepts */
3544 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3545 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3546 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3547 svm->nested.intercept = nested_vmcb->control.intercept;
3549 svm_flush_tlb(&svm->vcpu, true);
3550 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3551 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3552 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3554 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3556 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3557 /* We only want the cr8 intercept bits of the guest */
3558 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3559 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3562 /* We don't want to see VMMCALLs from a nested guest */
3563 clr_intercept(svm, INTERCEPT_VMMCALL);
3565 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3566 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3568 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3569 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3570 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3571 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3572 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3574 svm->vmcb->control.pause_filter_count =
3575 nested_vmcb->control.pause_filter_count;
3576 svm->vmcb->control.pause_filter_thresh =
3577 nested_vmcb->control.pause_filter_thresh;
3579 kvm_vcpu_unmap(&svm->vcpu, map, true);
3581 /* Enter Guest-Mode */
3582 enter_guest_mode(&svm->vcpu);
3585 * Merge guest and host intercepts - must be called with vcpu in
3586 * guest-mode to take affect here
3588 recalc_intercepts(svm);
3590 svm->nested.vmcb = vmcb_gpa;
3594 mark_all_dirty(svm->vmcb);
3597 static int nested_svm_vmrun(struct vcpu_svm *svm)
3600 struct vmcb *nested_vmcb;
3601 struct vmcb *hsave = svm->nested.hsave;
3602 struct vmcb *vmcb = svm->vmcb;
3603 struct kvm_host_map map;
3606 vmcb_gpa = svm->vmcb->save.rax;
3608 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3609 if (ret == -EINVAL) {
3610 kvm_inject_gp(&svm->vcpu, 0);
3613 return kvm_skip_emulated_instruction(&svm->vcpu);
3616 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3618 nested_vmcb = map.hva;
3620 if (!nested_vmcb_checks(nested_vmcb)) {
3621 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3622 nested_vmcb->control.exit_code_hi = 0;
3623 nested_vmcb->control.exit_info_1 = 0;
3624 nested_vmcb->control.exit_info_2 = 0;
3626 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3631 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3632 nested_vmcb->save.rip,
3633 nested_vmcb->control.int_ctl,
3634 nested_vmcb->control.event_inj,
3635 nested_vmcb->control.nested_ctl);
3637 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3638 nested_vmcb->control.intercept_cr >> 16,
3639 nested_vmcb->control.intercept_exceptions,
3640 nested_vmcb->control.intercept);
3642 /* Clear internal status */
3643 kvm_clear_exception_queue(&svm->vcpu);
3644 kvm_clear_interrupt_queue(&svm->vcpu);
3647 * Save the old vmcb, so we don't need to pick what we save, but can
3648 * restore everything when a VMEXIT occurs
3650 hsave->save.es = vmcb->save.es;
3651 hsave->save.cs = vmcb->save.cs;
3652 hsave->save.ss = vmcb->save.ss;
3653 hsave->save.ds = vmcb->save.ds;
3654 hsave->save.gdtr = vmcb->save.gdtr;
3655 hsave->save.idtr = vmcb->save.idtr;
3656 hsave->save.efer = svm->vcpu.arch.efer;
3657 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3658 hsave->save.cr4 = svm->vcpu.arch.cr4;
3659 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3660 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3661 hsave->save.rsp = vmcb->save.rsp;
3662 hsave->save.rax = vmcb->save.rax;
3664 hsave->save.cr3 = vmcb->save.cr3;
3666 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3668 copy_vmcb_control_area(hsave, vmcb);
3670 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3672 if (!nested_svm_vmrun_msrpm(svm)) {
3673 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3674 svm->vmcb->control.exit_code_hi = 0;
3675 svm->vmcb->control.exit_info_1 = 0;
3676 svm->vmcb->control.exit_info_2 = 0;
3678 nested_svm_vmexit(svm);
3684 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3686 to_vmcb->save.fs = from_vmcb->save.fs;
3687 to_vmcb->save.gs = from_vmcb->save.gs;
3688 to_vmcb->save.tr = from_vmcb->save.tr;
3689 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3690 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3691 to_vmcb->save.star = from_vmcb->save.star;
3692 to_vmcb->save.lstar = from_vmcb->save.lstar;
3693 to_vmcb->save.cstar = from_vmcb->save.cstar;
3694 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3695 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3696 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3697 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3700 static int vmload_interception(struct vcpu_svm *svm)
3702 struct vmcb *nested_vmcb;
3703 struct kvm_host_map map;
3706 if (nested_svm_check_permissions(svm))
3709 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3712 kvm_inject_gp(&svm->vcpu, 0);
3716 nested_vmcb = map.hva;
3718 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3720 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3721 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3726 static int vmsave_interception(struct vcpu_svm *svm)
3728 struct vmcb *nested_vmcb;
3729 struct kvm_host_map map;
3732 if (nested_svm_check_permissions(svm))
3735 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3738 kvm_inject_gp(&svm->vcpu, 0);
3742 nested_vmcb = map.hva;
3744 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3746 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3747 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3752 static int vmrun_interception(struct vcpu_svm *svm)
3754 if (nested_svm_check_permissions(svm))
3757 return nested_svm_vmrun(svm);
3760 static int stgi_interception(struct vcpu_svm *svm)
3764 if (nested_svm_check_permissions(svm))
3768 * If VGIF is enabled, the STGI intercept is only added to
3769 * detect the opening of the SMI/NMI window; remove it now.
3771 if (vgif_enabled(svm))
3772 clr_intercept(svm, INTERCEPT_STGI);
3774 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3775 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3782 static int clgi_interception(struct vcpu_svm *svm)
3786 if (nested_svm_check_permissions(svm))
3789 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3793 /* After a CLGI no interrupts should come */
3794 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3795 svm_clear_vintr(svm);
3796 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3797 mark_dirty(svm->vmcb, VMCB_INTR);
3803 static int invlpga_interception(struct vcpu_svm *svm)
3805 struct kvm_vcpu *vcpu = &svm->vcpu;
3807 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3808 kvm_rax_read(&svm->vcpu));
3810 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3811 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3813 return kvm_skip_emulated_instruction(&svm->vcpu);
3816 static int skinit_interception(struct vcpu_svm *svm)
3818 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3820 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3824 static int wbinvd_interception(struct vcpu_svm *svm)
3826 return kvm_emulate_wbinvd(&svm->vcpu);
3829 static int xsetbv_interception(struct vcpu_svm *svm)
3831 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3832 u32 index = kvm_rcx_read(&svm->vcpu);
3834 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3835 return kvm_skip_emulated_instruction(&svm->vcpu);
3841 static int task_switch_interception(struct vcpu_svm *svm)
3845 int int_type = svm->vmcb->control.exit_int_info &
3846 SVM_EXITINTINFO_TYPE_MASK;
3847 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3849 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3851 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3852 bool has_error_code = false;
3855 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3857 if (svm->vmcb->control.exit_info_2 &
3858 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3859 reason = TASK_SWITCH_IRET;
3860 else if (svm->vmcb->control.exit_info_2 &
3861 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3862 reason = TASK_SWITCH_JMP;
3864 reason = TASK_SWITCH_GATE;
3866 reason = TASK_SWITCH_CALL;
3868 if (reason == TASK_SWITCH_GATE) {
3870 case SVM_EXITINTINFO_TYPE_NMI:
3871 svm->vcpu.arch.nmi_injected = false;
3873 case SVM_EXITINTINFO_TYPE_EXEPT:
3874 if (svm->vmcb->control.exit_info_2 &
3875 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3876 has_error_code = true;
3878 (u32)svm->vmcb->control.exit_info_2;
3880 kvm_clear_exception_queue(&svm->vcpu);
3882 case SVM_EXITINTINFO_TYPE_INTR:
3883 kvm_clear_interrupt_queue(&svm->vcpu);
3890 if (reason != TASK_SWITCH_GATE ||
3891 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3892 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3893 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3894 if (skip_emulated_instruction(&svm->vcpu) != EMULATE_DONE)
3898 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3901 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3902 has_error_code, error_code) == EMULATE_FAIL)
3908 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3909 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3910 svm->vcpu.run->internal.ndata = 0;
3914 static int cpuid_interception(struct vcpu_svm *svm)
3916 return kvm_emulate_cpuid(&svm->vcpu);
3919 static int iret_interception(struct vcpu_svm *svm)
3921 ++svm->vcpu.stat.nmi_window_exits;
3922 clr_intercept(svm, INTERCEPT_IRET);
3923 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3924 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3925 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3929 static int invlpg_interception(struct vcpu_svm *svm)
3931 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3932 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3934 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3935 return kvm_skip_emulated_instruction(&svm->vcpu);
3938 static int emulate_on_interception(struct vcpu_svm *svm)
3940 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3943 static int rsm_interception(struct vcpu_svm *svm)
3945 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3946 rsm_ins_bytes, 2) == EMULATE_DONE;
3949 static int rdpmc_interception(struct vcpu_svm *svm)
3954 return emulate_on_interception(svm);
3956 err = kvm_rdpmc(&svm->vcpu);
3957 return kvm_complete_insn_gp(&svm->vcpu, err);
3960 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3963 unsigned long cr0 = svm->vcpu.arch.cr0;
3967 intercept = svm->nested.intercept;
3969 if (!is_guest_mode(&svm->vcpu) ||
3970 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3973 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3974 val &= ~SVM_CR0_SELECTIVE_MASK;
3977 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3978 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3984 #define CR_VALID (1ULL << 63)
3986 static int cr_interception(struct vcpu_svm *svm)
3992 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3993 return emulate_on_interception(svm);
3995 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3996 return emulate_on_interception(svm);
3998 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3999 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4000 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4002 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4005 if (cr >= 16) { /* mov to cr */
4007 val = kvm_register_read(&svm->vcpu, reg);
4010 if (!check_selective_cr0_intercepted(svm, val))
4011 err = kvm_set_cr0(&svm->vcpu, val);
4017 err = kvm_set_cr3(&svm->vcpu, val);
4020 err = kvm_set_cr4(&svm->vcpu, val);
4023 err = kvm_set_cr8(&svm->vcpu, val);
4026 WARN(1, "unhandled write to CR%d", cr);
4027 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4030 } else { /* mov from cr */
4033 val = kvm_read_cr0(&svm->vcpu);
4036 val = svm->vcpu.arch.cr2;
4039 val = kvm_read_cr3(&svm->vcpu);
4042 val = kvm_read_cr4(&svm->vcpu);
4045 val = kvm_get_cr8(&svm->vcpu);
4048 WARN(1, "unhandled read from CR%d", cr);
4049 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4052 kvm_register_write(&svm->vcpu, reg, val);
4054 return kvm_complete_insn_gp(&svm->vcpu, err);
4057 static int dr_interception(struct vcpu_svm *svm)
4062 if (svm->vcpu.guest_debug == 0) {
4064 * No more DR vmexits; force a reload of the debug registers
4065 * and reenter on this instruction. The next vmexit will
4066 * retrieve the full state of the debug registers.
4068 clr_dr_intercepts(svm);
4069 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4073 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4074 return emulate_on_interception(svm);
4076 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4077 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4079 if (dr >= 16) { /* mov to DRn */
4080 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4082 val = kvm_register_read(&svm->vcpu, reg);
4083 kvm_set_dr(&svm->vcpu, dr - 16, val);
4085 if (!kvm_require_dr(&svm->vcpu, dr))
4087 kvm_get_dr(&svm->vcpu, dr, &val);
4088 kvm_register_write(&svm->vcpu, reg, val);
4091 return kvm_skip_emulated_instruction(&svm->vcpu);
4094 static int cr8_write_interception(struct vcpu_svm *svm)
4096 struct kvm_run *kvm_run = svm->vcpu.run;
4099 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4100 /* instruction emulation calls kvm_set_cr8() */
4101 r = cr_interception(svm);
4102 if (lapic_in_kernel(&svm->vcpu))
4104 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4106 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4110 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4114 switch (msr->index) {
4115 case MSR_F10H_DECFG:
4116 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4117 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4126 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4128 struct vcpu_svm *svm = to_svm(vcpu);
4130 switch (msr_info->index) {
4132 msr_info->data = svm->vmcb->save.star;
4134 #ifdef CONFIG_X86_64
4136 msr_info->data = svm->vmcb->save.lstar;
4139 msr_info->data = svm->vmcb->save.cstar;
4141 case MSR_KERNEL_GS_BASE:
4142 msr_info->data = svm->vmcb->save.kernel_gs_base;
4144 case MSR_SYSCALL_MASK:
4145 msr_info->data = svm->vmcb->save.sfmask;
4148 case MSR_IA32_SYSENTER_CS:
4149 msr_info->data = svm->vmcb->save.sysenter_cs;
4151 case MSR_IA32_SYSENTER_EIP:
4152 msr_info->data = svm->sysenter_eip;
4154 case MSR_IA32_SYSENTER_ESP:
4155 msr_info->data = svm->sysenter_esp;
4158 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4160 msr_info->data = svm->tsc_aux;
4163 * Nobody will change the following 5 values in the VMCB so we can
4164 * safely return them on rdmsr. They will always be 0 until LBRV is
4167 case MSR_IA32_DEBUGCTLMSR:
4168 msr_info->data = svm->vmcb->save.dbgctl;
4170 case MSR_IA32_LASTBRANCHFROMIP:
4171 msr_info->data = svm->vmcb->save.br_from;
4173 case MSR_IA32_LASTBRANCHTOIP:
4174 msr_info->data = svm->vmcb->save.br_to;
4176 case MSR_IA32_LASTINTFROMIP:
4177 msr_info->data = svm->vmcb->save.last_excp_from;
4179 case MSR_IA32_LASTINTTOIP:
4180 msr_info->data = svm->vmcb->save.last_excp_to;
4182 case MSR_VM_HSAVE_PA:
4183 msr_info->data = svm->nested.hsave_msr;
4186 msr_info->data = svm->nested.vm_cr_msr;
4188 case MSR_IA32_SPEC_CTRL:
4189 if (!msr_info->host_initiated &&
4190 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4191 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4194 msr_info->data = svm->spec_ctrl;
4196 case MSR_AMD64_VIRT_SPEC_CTRL:
4197 if (!msr_info->host_initiated &&
4198 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4201 msr_info->data = svm->virt_spec_ctrl;
4203 case MSR_F15H_IC_CFG: {
4207 family = guest_cpuid_family(vcpu);
4208 model = guest_cpuid_model(vcpu);
4210 if (family < 0 || model < 0)
4211 return kvm_get_msr_common(vcpu, msr_info);
4215 if (family == 0x15 &&
4216 (model >= 0x2 && model < 0x20))
4217 msr_info->data = 0x1E;
4220 case MSR_F10H_DECFG:
4221 msr_info->data = svm->msr_decfg;
4224 return kvm_get_msr_common(vcpu, msr_info);
4229 static int rdmsr_interception(struct vcpu_svm *svm)
4231 return kvm_emulate_rdmsr(&svm->vcpu);
4234 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4236 struct vcpu_svm *svm = to_svm(vcpu);
4237 int svm_dis, chg_mask;
4239 if (data & ~SVM_VM_CR_VALID_MASK)
4242 chg_mask = SVM_VM_CR_VALID_MASK;
4244 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4245 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4247 svm->nested.vm_cr_msr &= ~chg_mask;
4248 svm->nested.vm_cr_msr |= (data & chg_mask);
4250 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4252 /* check for svm_disable while efer.svme is set */
4253 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4259 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4261 struct vcpu_svm *svm = to_svm(vcpu);
4263 u32 ecx = msr->index;
4264 u64 data = msr->data;
4266 case MSR_IA32_CR_PAT:
4267 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4269 vcpu->arch.pat = data;
4270 svm->vmcb->save.g_pat = data;
4271 mark_dirty(svm->vmcb, VMCB_NPT);
4273 case MSR_IA32_SPEC_CTRL:
4274 if (!msr->host_initiated &&
4275 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4276 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4279 /* The STIBP bit doesn't fault even if it's not advertised */
4280 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4283 svm->spec_ctrl = data;
4290 * When it's written (to non-zero) for the first time, pass
4294 * The handling of the MSR bitmap for L2 guests is done in
4295 * nested_svm_vmrun_msrpm.
4296 * We update the L1 MSR bit as well since it will end up
4297 * touching the MSR anyway now.
4299 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4301 case MSR_IA32_PRED_CMD:
4302 if (!msr->host_initiated &&
4303 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4306 if (data & ~PRED_CMD_IBPB)
4312 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4313 if (is_guest_mode(vcpu))
4315 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4317 case MSR_AMD64_VIRT_SPEC_CTRL:
4318 if (!msr->host_initiated &&
4319 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4322 if (data & ~SPEC_CTRL_SSBD)
4325 svm->virt_spec_ctrl = data;
4328 svm->vmcb->save.star = data;
4330 #ifdef CONFIG_X86_64
4332 svm->vmcb->save.lstar = data;
4335 svm->vmcb->save.cstar = data;
4337 case MSR_KERNEL_GS_BASE:
4338 svm->vmcb->save.kernel_gs_base = data;
4340 case MSR_SYSCALL_MASK:
4341 svm->vmcb->save.sfmask = data;
4344 case MSR_IA32_SYSENTER_CS:
4345 svm->vmcb->save.sysenter_cs = data;
4347 case MSR_IA32_SYSENTER_EIP:
4348 svm->sysenter_eip = data;
4349 svm->vmcb->save.sysenter_eip = data;
4351 case MSR_IA32_SYSENTER_ESP:
4352 svm->sysenter_esp = data;
4353 svm->vmcb->save.sysenter_esp = data;
4356 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4360 * This is rare, so we update the MSR here instead of using
4361 * direct_access_msrs. Doing that would require a rdmsr in
4364 svm->tsc_aux = data;
4365 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4367 case MSR_IA32_DEBUGCTLMSR:
4368 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4369 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4373 if (data & DEBUGCTL_RESERVED_BITS)
4376 svm->vmcb->save.dbgctl = data;
4377 mark_dirty(svm->vmcb, VMCB_LBR);
4378 if (data & (1ULL<<0))
4379 svm_enable_lbrv(svm);
4381 svm_disable_lbrv(svm);
4383 case MSR_VM_HSAVE_PA:
4384 svm->nested.hsave_msr = data;
4387 return svm_set_vm_cr(vcpu, data);
4389 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4391 case MSR_F10H_DECFG: {
4392 struct kvm_msr_entry msr_entry;
4394 msr_entry.index = msr->index;
4395 if (svm_get_msr_feature(&msr_entry))
4398 /* Check the supported bits */
4399 if (data & ~msr_entry.data)
4402 /* Don't allow the guest to change a bit, #GP */
4403 if (!msr->host_initiated && (data ^ msr_entry.data))
4406 svm->msr_decfg = data;
4409 case MSR_IA32_APICBASE:
4410 if (kvm_vcpu_apicv_active(vcpu))
4411 avic_update_vapic_bar(to_svm(vcpu), data);
4414 return kvm_set_msr_common(vcpu, msr);
4419 static int wrmsr_interception(struct vcpu_svm *svm)
4421 return kvm_emulate_wrmsr(&svm->vcpu);
4424 static int msr_interception(struct vcpu_svm *svm)
4426 if (svm->vmcb->control.exit_info_1)
4427 return wrmsr_interception(svm);
4429 return rdmsr_interception(svm);
4432 static int interrupt_window_interception(struct vcpu_svm *svm)
4434 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4435 svm_clear_vintr(svm);
4436 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4437 mark_dirty(svm->vmcb, VMCB_INTR);
4438 ++svm->vcpu.stat.irq_window_exits;
4442 static int pause_interception(struct vcpu_svm *svm)
4444 struct kvm_vcpu *vcpu = &svm->vcpu;
4445 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4447 if (pause_filter_thresh)
4448 grow_ple_window(vcpu);
4450 kvm_vcpu_on_spin(vcpu, in_kernel);
4454 static int nop_interception(struct vcpu_svm *svm)
4456 return kvm_skip_emulated_instruction(&(svm->vcpu));
4459 static int monitor_interception(struct vcpu_svm *svm)
4461 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4462 return nop_interception(svm);
4465 static int mwait_interception(struct vcpu_svm *svm)
4467 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4468 return nop_interception(svm);
4471 enum avic_ipi_failure_cause {
4472 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4473 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4474 AVIC_IPI_FAILURE_INVALID_TARGET,
4475 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4478 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4480 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4481 u32 icrl = svm->vmcb->control.exit_info_1;
4482 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4483 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4484 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4486 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4489 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4491 * AVIC hardware handles the generation of
4492 * IPIs when the specified Message Type is Fixed
4493 * (also known as fixed delivery mode) and
4494 * the Trigger Mode is edge-triggered. The hardware
4495 * also supports self and broadcast delivery modes
4496 * specified via the Destination Shorthand(DSH)
4497 * field of the ICRL. Logical and physical APIC ID
4498 * formats are supported. All other IPI types cause
4499 * a #VMEXIT, which needs to emulated.
4501 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4502 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4504 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4506 struct kvm_vcpu *vcpu;
4507 struct kvm *kvm = svm->vcpu.kvm;
4508 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4511 * At this point, we expect that the AVIC HW has already
4512 * set the appropriate IRR bits on the valid target
4513 * vcpus. So, we just need to kick the appropriate vcpu.
4515 kvm_for_each_vcpu(i, vcpu, kvm) {
4516 bool m = kvm_apic_match_dest(vcpu, apic,
4517 icrl & KVM_APIC_SHORT_MASK,
4518 GET_APIC_DEST_FIELD(icrh),
4519 icrl & KVM_APIC_DEST_MASK);
4521 if (m && !avic_vcpu_is_running(vcpu))
4522 kvm_vcpu_wake_up(vcpu);
4526 case AVIC_IPI_FAILURE_INVALID_TARGET:
4527 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4528 index, svm->vcpu.vcpu_id, icrh, icrl);
4530 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4531 WARN_ONCE(1, "Invalid backing page\n");
4534 pr_err("Unknown IPI interception\n");
4540 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4542 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4544 u32 *logical_apic_id_table;
4545 int dlid = GET_APIC_LOGICAL_ID(ldr);
4550 if (flat) { /* flat */
4551 index = ffs(dlid) - 1;
4554 } else { /* cluster */
4555 int cluster = (dlid & 0xf0) >> 4;
4556 int apic = ffs(dlid & 0x0f) - 1;
4558 if ((apic < 0) || (apic > 7) ||
4561 index = (cluster << 2) + apic;
4564 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4566 return &logical_apic_id_table[index];
4569 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4572 u32 *entry, new_entry;
4574 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4575 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4579 new_entry = READ_ONCE(*entry);
4580 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4581 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4582 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4583 WRITE_ONCE(*entry, new_entry);
4588 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4590 struct vcpu_svm *svm = to_svm(vcpu);
4591 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4592 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4595 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4598 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4601 struct vcpu_svm *svm = to_svm(vcpu);
4602 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4604 if (ldr == svm->ldr_reg)
4607 avic_invalidate_logical_id_entry(vcpu);
4610 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4618 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4621 struct vcpu_svm *svm = to_svm(vcpu);
4622 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4623 u32 id = (apic_id_reg >> 24) & 0xff;
4625 if (vcpu->vcpu_id == id)
4628 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4629 new = avic_get_physical_id_entry(vcpu, id);
4633 /* We need to move physical_id_entry to new offset */
4636 to_svm(vcpu)->avic_physical_id_cache = new;
4639 * Also update the guest physical APIC ID in the logical
4640 * APIC ID table entry if already setup the LDR.
4643 avic_handle_ldr_update(vcpu);
4648 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4650 struct vcpu_svm *svm = to_svm(vcpu);
4651 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4653 if (svm->dfr_reg == dfr)
4656 avic_invalidate_logical_id_entry(vcpu);
4660 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4662 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4663 u32 offset = svm->vmcb->control.exit_info_1 &
4664 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4668 if (avic_handle_apic_id_update(&svm->vcpu))
4672 if (avic_handle_ldr_update(&svm->vcpu))
4676 avic_handle_dfr_update(&svm->vcpu);
4682 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4687 static bool is_avic_unaccelerated_access_trap(u32 offset)
4716 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4719 u32 offset = svm->vmcb->control.exit_info_1 &
4720 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4721 u32 vector = svm->vmcb->control.exit_info_2 &
4722 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4723 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4724 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4725 bool trap = is_avic_unaccelerated_access_trap(offset);
4727 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4728 trap, write, vector);
4731 WARN_ONCE(!write, "svm: Handling trap read.\n");
4732 ret = avic_unaccel_trap_write(svm);
4734 /* Handling Fault */
4735 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4741 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4742 [SVM_EXIT_READ_CR0] = cr_interception,
4743 [SVM_EXIT_READ_CR3] = cr_interception,
4744 [SVM_EXIT_READ_CR4] = cr_interception,
4745 [SVM_EXIT_READ_CR8] = cr_interception,
4746 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4747 [SVM_EXIT_WRITE_CR0] = cr_interception,
4748 [SVM_EXIT_WRITE_CR3] = cr_interception,
4749 [SVM_EXIT_WRITE_CR4] = cr_interception,
4750 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4751 [SVM_EXIT_READ_DR0] = dr_interception,
4752 [SVM_EXIT_READ_DR1] = dr_interception,
4753 [SVM_EXIT_READ_DR2] = dr_interception,
4754 [SVM_EXIT_READ_DR3] = dr_interception,
4755 [SVM_EXIT_READ_DR4] = dr_interception,
4756 [SVM_EXIT_READ_DR5] = dr_interception,
4757 [SVM_EXIT_READ_DR6] = dr_interception,
4758 [SVM_EXIT_READ_DR7] = dr_interception,
4759 [SVM_EXIT_WRITE_DR0] = dr_interception,
4760 [SVM_EXIT_WRITE_DR1] = dr_interception,
4761 [SVM_EXIT_WRITE_DR2] = dr_interception,
4762 [SVM_EXIT_WRITE_DR3] = dr_interception,
4763 [SVM_EXIT_WRITE_DR4] = dr_interception,
4764 [SVM_EXIT_WRITE_DR5] = dr_interception,
4765 [SVM_EXIT_WRITE_DR6] = dr_interception,
4766 [SVM_EXIT_WRITE_DR7] = dr_interception,
4767 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4768 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4769 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4770 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4771 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4772 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4773 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4774 [SVM_EXIT_INTR] = intr_interception,
4775 [SVM_EXIT_NMI] = nmi_interception,
4776 [SVM_EXIT_SMI] = nop_on_interception,
4777 [SVM_EXIT_INIT] = nop_on_interception,
4778 [SVM_EXIT_VINTR] = interrupt_window_interception,
4779 [SVM_EXIT_RDPMC] = rdpmc_interception,
4780 [SVM_EXIT_CPUID] = cpuid_interception,
4781 [SVM_EXIT_IRET] = iret_interception,
4782 [SVM_EXIT_INVD] = emulate_on_interception,
4783 [SVM_EXIT_PAUSE] = pause_interception,
4784 [SVM_EXIT_HLT] = halt_interception,
4785 [SVM_EXIT_INVLPG] = invlpg_interception,
4786 [SVM_EXIT_INVLPGA] = invlpga_interception,
4787 [SVM_EXIT_IOIO] = io_interception,
4788 [SVM_EXIT_MSR] = msr_interception,
4789 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4790 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4791 [SVM_EXIT_VMRUN] = vmrun_interception,
4792 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4793 [SVM_EXIT_VMLOAD] = vmload_interception,
4794 [SVM_EXIT_VMSAVE] = vmsave_interception,
4795 [SVM_EXIT_STGI] = stgi_interception,
4796 [SVM_EXIT_CLGI] = clgi_interception,
4797 [SVM_EXIT_SKINIT] = skinit_interception,
4798 [SVM_EXIT_WBINVD] = wbinvd_interception,
4799 [SVM_EXIT_MONITOR] = monitor_interception,
4800 [SVM_EXIT_MWAIT] = mwait_interception,
4801 [SVM_EXIT_XSETBV] = xsetbv_interception,
4802 [SVM_EXIT_NPF] = npf_interception,
4803 [SVM_EXIT_RSM] = rsm_interception,
4804 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4805 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4808 static void dump_vmcb(struct kvm_vcpu *vcpu)
4810 struct vcpu_svm *svm = to_svm(vcpu);
4811 struct vmcb_control_area *control = &svm->vmcb->control;
4812 struct vmcb_save_area *save = &svm->vmcb->save;
4814 if (!dump_invalid_vmcb) {
4815 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4819 pr_err("VMCB Control Area:\n");
4820 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4821 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4822 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4823 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4824 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4825 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4826 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4827 pr_err("%-20s%d\n", "pause filter threshold:",
4828 control->pause_filter_thresh);
4829 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4830 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4831 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4832 pr_err("%-20s%d\n", "asid:", control->asid);
4833 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4834 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4835 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4836 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4837 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4838 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4839 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4840 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4841 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4842 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4843 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4844 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4845 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4846 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4847 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4848 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4849 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4850 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4851 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4852 pr_err("VMCB State Save Area:\n");
4853 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4855 save->es.selector, save->es.attrib,
4856 save->es.limit, save->es.base);
4857 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4859 save->cs.selector, save->cs.attrib,
4860 save->cs.limit, save->cs.base);
4861 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4863 save->ss.selector, save->ss.attrib,
4864 save->ss.limit, save->ss.base);
4865 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4867 save->ds.selector, save->ds.attrib,
4868 save->ds.limit, save->ds.base);
4869 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4871 save->fs.selector, save->fs.attrib,
4872 save->fs.limit, save->fs.base);
4873 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4875 save->gs.selector, save->gs.attrib,
4876 save->gs.limit, save->gs.base);
4877 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4879 save->gdtr.selector, save->gdtr.attrib,
4880 save->gdtr.limit, save->gdtr.base);
4881 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4883 save->ldtr.selector, save->ldtr.attrib,
4884 save->ldtr.limit, save->ldtr.base);
4885 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4887 save->idtr.selector, save->idtr.attrib,
4888 save->idtr.limit, save->idtr.base);
4889 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4891 save->tr.selector, save->tr.attrib,
4892 save->tr.limit, save->tr.base);
4893 pr_err("cpl: %d efer: %016llx\n",
4894 save->cpl, save->efer);
4895 pr_err("%-15s %016llx %-13s %016llx\n",
4896 "cr0:", save->cr0, "cr2:", save->cr2);
4897 pr_err("%-15s %016llx %-13s %016llx\n",
4898 "cr3:", save->cr3, "cr4:", save->cr4);
4899 pr_err("%-15s %016llx %-13s %016llx\n",
4900 "dr6:", save->dr6, "dr7:", save->dr7);
4901 pr_err("%-15s %016llx %-13s %016llx\n",
4902 "rip:", save->rip, "rflags:", save->rflags);
4903 pr_err("%-15s %016llx %-13s %016llx\n",
4904 "rsp:", save->rsp, "rax:", save->rax);
4905 pr_err("%-15s %016llx %-13s %016llx\n",
4906 "star:", save->star, "lstar:", save->lstar);
4907 pr_err("%-15s %016llx %-13s %016llx\n",
4908 "cstar:", save->cstar, "sfmask:", save->sfmask);
4909 pr_err("%-15s %016llx %-13s %016llx\n",
4910 "kernel_gs_base:", save->kernel_gs_base,
4911 "sysenter_cs:", save->sysenter_cs);
4912 pr_err("%-15s %016llx %-13s %016llx\n",
4913 "sysenter_esp:", save->sysenter_esp,
4914 "sysenter_eip:", save->sysenter_eip);
4915 pr_err("%-15s %016llx %-13s %016llx\n",
4916 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4917 pr_err("%-15s %016llx %-13s %016llx\n",
4918 "br_from:", save->br_from, "br_to:", save->br_to);
4919 pr_err("%-15s %016llx %-13s %016llx\n",
4920 "excp_from:", save->last_excp_from,
4921 "excp_to:", save->last_excp_to);
4924 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4926 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4928 *info1 = control->exit_info_1;
4929 *info2 = control->exit_info_2;
4932 static int handle_exit(struct kvm_vcpu *vcpu)
4934 struct vcpu_svm *svm = to_svm(vcpu);
4935 struct kvm_run *kvm_run = vcpu->run;
4936 u32 exit_code = svm->vmcb->control.exit_code;
4938 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4940 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4941 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4943 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4945 if (unlikely(svm->nested.exit_required)) {
4946 nested_svm_vmexit(svm);
4947 svm->nested.exit_required = false;
4952 if (is_guest_mode(vcpu)) {
4955 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4956 svm->vmcb->control.exit_info_1,
4957 svm->vmcb->control.exit_info_2,
4958 svm->vmcb->control.exit_int_info,
4959 svm->vmcb->control.exit_int_info_err,
4962 vmexit = nested_svm_exit_special(svm);
4964 if (vmexit == NESTED_EXIT_CONTINUE)
4965 vmexit = nested_svm_exit_handled(svm);
4967 if (vmexit == NESTED_EXIT_DONE)
4971 svm_complete_interrupts(svm);
4973 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4974 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4975 kvm_run->fail_entry.hardware_entry_failure_reason
4976 = svm->vmcb->control.exit_code;
4981 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4982 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4983 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4984 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4985 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4987 __func__, svm->vmcb->control.exit_int_info,
4990 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4991 || !svm_exit_handlers[exit_code]) {
4992 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
4994 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4995 vcpu->run->internal.suberror =
4996 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
4997 vcpu->run->internal.ndata = 1;
4998 vcpu->run->internal.data[0] = exit_code;
5002 return svm_exit_handlers[exit_code](svm);
5005 static void reload_tss(struct kvm_vcpu *vcpu)
5007 int cpu = raw_smp_processor_id();
5009 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5010 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5014 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5016 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5017 int asid = sev_get_asid(svm->vcpu.kvm);
5019 /* Assign the asid allocated with this SEV guest */
5020 svm->vmcb->control.asid = asid;
5025 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5026 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5028 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5029 svm->last_cpu == cpu)
5032 svm->last_cpu = cpu;
5033 sd->sev_vmcbs[asid] = svm->vmcb;
5034 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5035 mark_dirty(svm->vmcb, VMCB_ASID);
5038 static void pre_svm_run(struct vcpu_svm *svm)
5040 int cpu = raw_smp_processor_id();
5042 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5044 if (sev_guest(svm->vcpu.kvm))
5045 return pre_sev_run(svm, cpu);
5047 /* FIXME: handle wraparound of asid_generation */
5048 if (svm->asid_generation != sd->asid_generation)
5052 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5054 struct vcpu_svm *svm = to_svm(vcpu);
5056 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5057 vcpu->arch.hflags |= HF_NMI_MASK;
5058 set_intercept(svm, INTERCEPT_IRET);
5059 ++vcpu->stat.nmi_injections;
5062 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5064 struct vmcb_control_area *control;
5066 /* The following fields are ignored when AVIC is enabled */
5067 control = &svm->vmcb->control;
5068 control->int_vector = irq;
5069 control->int_ctl &= ~V_INTR_PRIO_MASK;
5070 control->int_ctl |= V_IRQ_MASK |
5071 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5072 mark_dirty(svm->vmcb, VMCB_INTR);
5075 static void svm_set_irq(struct kvm_vcpu *vcpu)
5077 struct vcpu_svm *svm = to_svm(vcpu);
5079 BUG_ON(!(gif_set(svm)));
5081 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5082 ++vcpu->stat.irq_injections;
5084 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5085 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5088 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5090 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5093 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5095 struct vcpu_svm *svm = to_svm(vcpu);
5097 if (svm_nested_virtualize_tpr(vcpu) ||
5098 kvm_vcpu_apicv_active(vcpu))
5101 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5107 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5110 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5115 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5117 return avic && irqchip_split(vcpu->kvm);
5120 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5124 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5128 /* Note: Currently only used by Hyper-V. */
5129 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5131 struct vcpu_svm *svm = to_svm(vcpu);
5132 struct vmcb *vmcb = svm->vmcb;
5134 if (kvm_vcpu_apicv_active(vcpu))
5135 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5137 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5138 mark_dirty(vmcb, VMCB_AVIC);
5141 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5146 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5148 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5149 smp_mb__after_atomic();
5151 if (avic_vcpu_is_running(vcpu)) {
5152 int cpuid = vcpu->cpu;
5154 if (cpuid != get_cpu())
5155 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5158 kvm_vcpu_wake_up(vcpu);
5161 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5166 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5168 unsigned long flags;
5169 struct amd_svm_iommu_ir *cur;
5171 spin_lock_irqsave(&svm->ir_list_lock, flags);
5172 list_for_each_entry(cur, &svm->ir_list, node) {
5173 if (cur->data != pi->ir_data)
5175 list_del(&cur->node);
5179 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5182 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5185 unsigned long flags;
5186 struct amd_svm_iommu_ir *ir;
5189 * In some cases, the existing irte is updaed and re-set,
5190 * so we need to check here if it's already been * added
5193 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5194 struct kvm *kvm = svm->vcpu.kvm;
5195 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5196 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5197 struct vcpu_svm *prev_svm;
5204 prev_svm = to_svm(prev_vcpu);
5205 svm_ir_list_del(prev_svm, pi);
5209 * Allocating new amd_iommu_pi_data, which will get
5210 * add to the per-vcpu ir_list.
5212 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5217 ir->data = pi->ir_data;
5219 spin_lock_irqsave(&svm->ir_list_lock, flags);
5220 list_add(&ir->node, &svm->ir_list);
5221 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5228 * The HW cannot support posting multicast/broadcast
5229 * interrupts to a vCPU. So, we still use legacy interrupt
5230 * remapping for these kind of interrupts.
5232 * For lowest-priority interrupts, we only support
5233 * those with single CPU as the destination, e.g. user
5234 * configures the interrupts via /proc/irq or uses
5235 * irqbalance to make the interrupts single-CPU.
5238 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5239 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5241 struct kvm_lapic_irq irq;
5242 struct kvm_vcpu *vcpu = NULL;
5244 kvm_set_msi_irq(kvm, e, &irq);
5246 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5247 !kvm_irq_is_postable(&irq)) {
5248 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5249 __func__, irq.vector);
5253 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5255 *svm = to_svm(vcpu);
5256 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5257 vcpu_info->vector = irq.vector;
5263 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5266 * @host_irq: host irq of the interrupt
5267 * @guest_irq: gsi of the interrupt
5268 * @set: set or unset PI
5269 * returns 0 on success, < 0 on failure
5271 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5272 uint32_t guest_irq, bool set)
5274 struct kvm_kernel_irq_routing_entry *e;
5275 struct kvm_irq_routing_table *irq_rt;
5276 int idx, ret = -EINVAL;
5278 if (!kvm_arch_has_assigned_device(kvm) ||
5279 !irq_remapping_cap(IRQ_POSTING_CAP))
5282 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5283 __func__, host_irq, guest_irq, set);
5285 idx = srcu_read_lock(&kvm->irq_srcu);
5286 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5287 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5289 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5290 struct vcpu_data vcpu_info;
5291 struct vcpu_svm *svm = NULL;
5293 if (e->type != KVM_IRQ_ROUTING_MSI)
5297 * Here, we setup with legacy mode in the following cases:
5298 * 1. When cannot target interrupt to a specific vcpu.
5299 * 2. Unsetting posted interrupt.
5300 * 3. APIC virtialization is disabled for the vcpu.
5301 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5303 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5304 kvm_vcpu_apicv_active(&svm->vcpu)) {
5305 struct amd_iommu_pi_data pi;
5307 /* Try to enable guest_mode in IRTE */
5308 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5310 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5312 pi.is_guest_mode = true;
5313 pi.vcpu_data = &vcpu_info;
5314 ret = irq_set_vcpu_affinity(host_irq, &pi);
5317 * Here, we successfully setting up vcpu affinity in
5318 * IOMMU guest mode. Now, we need to store the posted
5319 * interrupt information in a per-vcpu ir_list so that
5320 * we can reference to them directly when we update vcpu
5321 * scheduling information in IOMMU irte.
5323 if (!ret && pi.is_guest_mode)
5324 svm_ir_list_add(svm, &pi);
5326 /* Use legacy mode in IRTE */
5327 struct amd_iommu_pi_data pi;
5330 * Here, pi is used to:
5331 * - Tell IOMMU to use legacy mode for this interrupt.
5332 * - Retrieve ga_tag of prior interrupt remapping data.
5334 pi.is_guest_mode = false;
5335 ret = irq_set_vcpu_affinity(host_irq, &pi);
5338 * Check if the posted interrupt was previously
5339 * setup with the guest_mode by checking if the ga_tag
5340 * was cached. If so, we need to clean up the per-vcpu
5343 if (!ret && pi.prev_ga_tag) {
5344 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5345 struct kvm_vcpu *vcpu;
5347 vcpu = kvm_get_vcpu_by_id(kvm, id);
5349 svm_ir_list_del(to_svm(vcpu), &pi);
5354 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5355 e->gsi, vcpu_info.vector,
5356 vcpu_info.pi_desc_addr, set);
5360 pr_err("%s: failed to update PI IRTE\n", __func__);
5367 srcu_read_unlock(&kvm->irq_srcu, idx);
5371 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5373 struct vcpu_svm *svm = to_svm(vcpu);
5374 struct vmcb *vmcb = svm->vmcb;
5376 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5377 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5378 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5383 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5385 struct vcpu_svm *svm = to_svm(vcpu);
5387 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5390 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5392 struct vcpu_svm *svm = to_svm(vcpu);
5395 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5396 set_intercept(svm, INTERCEPT_IRET);
5398 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5399 clr_intercept(svm, INTERCEPT_IRET);
5403 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5405 struct vcpu_svm *svm = to_svm(vcpu);
5406 struct vmcb *vmcb = svm->vmcb;
5409 if (!gif_set(svm) ||
5410 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5413 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5415 if (is_guest_mode(vcpu))
5416 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5421 static void enable_irq_window(struct kvm_vcpu *vcpu)
5423 struct vcpu_svm *svm = to_svm(vcpu);
5425 if (kvm_vcpu_apicv_active(vcpu))
5429 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5430 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5431 * get that intercept, this function will be called again though and
5432 * we'll get the vintr intercept. However, if the vGIF feature is
5433 * enabled, the STGI interception will not occur. Enable the irq
5434 * window under the assumption that the hardware will set the GIF.
5436 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5438 svm_inject_irq(svm, 0x0);
5442 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5444 struct vcpu_svm *svm = to_svm(vcpu);
5446 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5448 return; /* IRET will cause a vm exit */
5450 if (!gif_set(svm)) {
5451 if (vgif_enabled(svm))
5452 set_intercept(svm, INTERCEPT_STGI);
5453 return; /* STGI will cause a vm exit */
5456 if (svm->nested.exit_required)
5457 return; /* we're not going to run the guest yet */
5460 * Something prevents NMI from been injected. Single step over possible
5461 * problem (IRET or exception injection or interrupt shadow)
5463 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5464 svm->nmi_singlestep = true;
5465 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5468 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5473 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5478 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5480 struct vcpu_svm *svm = to_svm(vcpu);
5482 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5483 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5485 svm->asid_generation--;
5488 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5490 struct vcpu_svm *svm = to_svm(vcpu);
5492 invlpga(gva, svm->vmcb->control.asid);
5495 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5499 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5501 struct vcpu_svm *svm = to_svm(vcpu);
5503 if (svm_nested_virtualize_tpr(vcpu))
5506 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5507 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5508 kvm_set_cr8(vcpu, cr8);
5512 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5514 struct vcpu_svm *svm = to_svm(vcpu);
5517 if (svm_nested_virtualize_tpr(vcpu) ||
5518 kvm_vcpu_apicv_active(vcpu))
5521 cr8 = kvm_get_cr8(vcpu);
5522 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5523 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5526 static void svm_complete_interrupts(struct vcpu_svm *svm)
5530 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5531 unsigned int3_injected = svm->int3_injected;
5533 svm->int3_injected = 0;
5536 * If we've made progress since setting HF_IRET_MASK, we've
5537 * executed an IRET and can allow NMI injection.
5539 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5540 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5541 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5542 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5545 svm->vcpu.arch.nmi_injected = false;
5546 kvm_clear_exception_queue(&svm->vcpu);
5547 kvm_clear_interrupt_queue(&svm->vcpu);
5549 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5552 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5554 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5555 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5558 case SVM_EXITINTINFO_TYPE_NMI:
5559 svm->vcpu.arch.nmi_injected = true;
5561 case SVM_EXITINTINFO_TYPE_EXEPT:
5563 * In case of software exceptions, do not reinject the vector,
5564 * but re-execute the instruction instead. Rewind RIP first
5565 * if we emulated INT3 before.
5567 if (kvm_exception_is_soft(vector)) {
5568 if (vector == BP_VECTOR && int3_injected &&
5569 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5570 kvm_rip_write(&svm->vcpu,
5571 kvm_rip_read(&svm->vcpu) -
5575 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5576 u32 err = svm->vmcb->control.exit_int_info_err;
5577 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5580 kvm_requeue_exception(&svm->vcpu, vector);
5582 case SVM_EXITINTINFO_TYPE_INTR:
5583 kvm_queue_interrupt(&svm->vcpu, vector, false);
5590 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5592 struct vcpu_svm *svm = to_svm(vcpu);
5593 struct vmcb_control_area *control = &svm->vmcb->control;
5595 control->exit_int_info = control->event_inj;
5596 control->exit_int_info_err = control->event_inj_err;
5597 control->event_inj = 0;
5598 svm_complete_interrupts(svm);
5601 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5603 struct vcpu_svm *svm = to_svm(vcpu);
5605 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5606 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5607 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5610 * A vmexit emulation is required before the vcpu can be executed
5613 if (unlikely(svm->nested.exit_required))
5617 * Disable singlestep if we're injecting an interrupt/exception.
5618 * We don't want our modified rflags to be pushed on the stack where
5619 * we might not be able to easily reset them if we disabled NMI
5622 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5624 * Event injection happens before external interrupts cause a
5625 * vmexit and interrupts are disabled here, so smp_send_reschedule
5626 * is enough to force an immediate vmexit.
5628 disable_nmi_singlestep(svm);
5629 smp_send_reschedule(vcpu->cpu);
5634 sync_lapic_to_cr8(vcpu);
5636 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5639 kvm_load_guest_xcr0(vcpu);
5641 if (lapic_in_kernel(vcpu) &&
5642 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5643 kvm_wait_lapic_expire(vcpu);
5646 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5647 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5648 * is no need to worry about the conditional branch over the wrmsr
5649 * being speculatively taken.
5651 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5656 "push %%" _ASM_BP "; \n\t"
5657 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5658 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5659 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5660 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5661 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5662 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5663 #ifdef CONFIG_X86_64
5664 "mov %c[r8](%[svm]), %%r8 \n\t"
5665 "mov %c[r9](%[svm]), %%r9 \n\t"
5666 "mov %c[r10](%[svm]), %%r10 \n\t"
5667 "mov %c[r11](%[svm]), %%r11 \n\t"
5668 "mov %c[r12](%[svm]), %%r12 \n\t"
5669 "mov %c[r13](%[svm]), %%r13 \n\t"
5670 "mov %c[r14](%[svm]), %%r14 \n\t"
5671 "mov %c[r15](%[svm]), %%r15 \n\t"
5674 /* Enter guest mode */
5675 "push %%" _ASM_AX " \n\t"
5676 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5677 __ex("vmload %%" _ASM_AX) "\n\t"
5678 __ex("vmrun %%" _ASM_AX) "\n\t"
5679 __ex("vmsave %%" _ASM_AX) "\n\t"
5680 "pop %%" _ASM_AX " \n\t"
5682 /* Save guest registers, load host registers */
5683 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5684 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5685 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5686 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5687 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5688 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5689 #ifdef CONFIG_X86_64
5690 "mov %%r8, %c[r8](%[svm]) \n\t"
5691 "mov %%r9, %c[r9](%[svm]) \n\t"
5692 "mov %%r10, %c[r10](%[svm]) \n\t"
5693 "mov %%r11, %c[r11](%[svm]) \n\t"
5694 "mov %%r12, %c[r12](%[svm]) \n\t"
5695 "mov %%r13, %c[r13](%[svm]) \n\t"
5696 "mov %%r14, %c[r14](%[svm]) \n\t"
5697 "mov %%r15, %c[r15](%[svm]) \n\t"
5699 * Clear host registers marked as clobbered to prevent
5702 "xor %%r8d, %%r8d \n\t"
5703 "xor %%r9d, %%r9d \n\t"
5704 "xor %%r10d, %%r10d \n\t"
5705 "xor %%r11d, %%r11d \n\t"
5706 "xor %%r12d, %%r12d \n\t"
5707 "xor %%r13d, %%r13d \n\t"
5708 "xor %%r14d, %%r14d \n\t"
5709 "xor %%r15d, %%r15d \n\t"
5711 "xor %%ebx, %%ebx \n\t"
5712 "xor %%ecx, %%ecx \n\t"
5713 "xor %%edx, %%edx \n\t"
5714 "xor %%esi, %%esi \n\t"
5715 "xor %%edi, %%edi \n\t"
5719 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5720 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5721 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5722 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5723 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5724 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5725 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5726 #ifdef CONFIG_X86_64
5727 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5728 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5729 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5730 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5731 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5732 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5733 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5734 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5737 #ifdef CONFIG_X86_64
5738 , "rbx", "rcx", "rdx", "rsi", "rdi"
5739 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5741 , "ebx", "ecx", "edx", "esi", "edi"
5745 /* Eliminate branch target predictions from guest mode */
5748 #ifdef CONFIG_X86_64
5749 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5751 loadsegment(fs, svm->host.fs);
5752 #ifndef CONFIG_X86_32_LAZY_GS
5753 loadsegment(gs, svm->host.gs);
5758 * We do not use IBRS in the kernel. If this vCPU has used the
5759 * SPEC_CTRL MSR it may have left it on; save the value and
5760 * turn it off. This is much more efficient than blindly adding
5761 * it to the atomic save/restore list. Especially as the former
5762 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5764 * For non-nested case:
5765 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5769 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5772 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5773 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5777 local_irq_disable();
5779 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5781 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5782 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5783 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5784 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5786 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5787 kvm_before_interrupt(&svm->vcpu);
5789 kvm_put_guest_xcr0(vcpu);
5792 /* Any pending NMI will happen here */
5794 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5795 kvm_after_interrupt(&svm->vcpu);
5797 sync_cr8_to_lapic(vcpu);
5801 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5803 /* if exit due to PF check for async PF */
5804 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5805 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5808 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5809 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5813 * We need to handle MC intercepts here before the vcpu has a chance to
5814 * change the physical cpu
5816 if (unlikely(svm->vmcb->control.exit_code ==
5817 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5818 svm_handle_mce(svm);
5820 mark_all_clean(svm->vmcb);
5822 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5824 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5826 struct vcpu_svm *svm = to_svm(vcpu);
5828 svm->vmcb->save.cr3 = __sme_set(root);
5829 mark_dirty(svm->vmcb, VMCB_CR);
5832 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5834 struct vcpu_svm *svm = to_svm(vcpu);
5836 svm->vmcb->control.nested_cr3 = __sme_set(root);
5837 mark_dirty(svm->vmcb, VMCB_NPT);
5839 /* Also sync guest cr3 here in case we live migrate */
5840 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5841 mark_dirty(svm->vmcb, VMCB_CR);
5844 static int is_disabled(void)
5848 rdmsrl(MSR_VM_CR, vm_cr);
5849 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5856 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5859 * Patch in the VMMCALL instruction:
5861 hypercall[0] = 0x0f;
5862 hypercall[1] = 0x01;
5863 hypercall[2] = 0xd9;
5866 static int __init svm_check_processor_compat(void)
5871 static bool svm_cpu_has_accelerated_tpr(void)
5876 static bool svm_has_emulated_msr(int index)
5879 case MSR_IA32_MCG_EXT_CTL:
5880 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
5889 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5894 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5896 struct vcpu_svm *svm = to_svm(vcpu);
5898 /* Update nrips enabled cache */
5899 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5901 if (!kvm_vcpu_apicv_active(vcpu))
5904 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5907 #define F(x) bit(X86_FEATURE_##x)
5909 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5914 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5918 entry->ecx |= (1 << 2); /* Set SVM bit */
5921 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5922 boot_cpu_has(X86_FEATURE_AMD_SSBD))
5923 entry->ebx |= F(VIRT_SSBD);
5926 entry->eax = 1; /* SVM revision 1 */
5927 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5928 ASID emulation to nested SVM */
5929 entry->ecx = 0; /* Reserved */
5930 entry->edx = 0; /* Per default do not support any
5931 additional features */
5933 /* Support next_rip if host supports it */
5934 if (boot_cpu_has(X86_FEATURE_NRIPS))
5935 entry->edx |= F(NRIPS);
5937 /* Support NPT for the guest if enabled */
5939 entry->edx |= F(NPT);
5943 /* Support memory encryption cpuid if host supports it */
5944 if (boot_cpu_has(X86_FEATURE_SEV))
5945 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5946 &entry->ecx, &entry->edx);
5951 static int svm_get_lpage_level(void)
5953 return PT_PDPE_LEVEL;
5956 static bool svm_rdtscp_supported(void)
5958 return boot_cpu_has(X86_FEATURE_RDTSCP);
5961 static bool svm_invpcid_supported(void)
5966 static bool svm_mpx_supported(void)
5971 static bool svm_xsaves_supported(void)
5976 static bool svm_umip_emulated(void)
5981 static bool svm_pt_supported(void)
5986 static bool svm_has_wbinvd_exit(void)
5991 #define PRE_EX(exit) { .exit_code = (exit), \
5992 .stage = X86_ICPT_PRE_EXCEPT, }
5993 #define POST_EX(exit) { .exit_code = (exit), \
5994 .stage = X86_ICPT_POST_EXCEPT, }
5995 #define POST_MEM(exit) { .exit_code = (exit), \
5996 .stage = X86_ICPT_POST_MEMACCESS, }
5998 static const struct __x86_intercept {
6000 enum x86_intercept_stage stage;
6001 } x86_intercept_map[] = {
6002 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6003 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6004 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6005 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6006 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6007 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6008 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6009 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6010 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6011 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6012 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6013 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6014 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6015 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6016 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6017 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6018 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6019 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6020 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6021 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6022 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6023 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6024 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6025 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6026 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6027 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6028 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6029 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6030 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6031 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6032 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6033 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6034 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6035 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6036 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6037 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6038 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6039 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6040 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6041 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6042 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6043 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6044 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6045 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6046 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6047 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6048 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
6055 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6056 struct x86_instruction_info *info,
6057 enum x86_intercept_stage stage)
6059 struct vcpu_svm *svm = to_svm(vcpu);
6060 int vmexit, ret = X86EMUL_CONTINUE;
6061 struct __x86_intercept icpt_info;
6062 struct vmcb *vmcb = svm->vmcb;
6064 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6067 icpt_info = x86_intercept_map[info->intercept];
6069 if (stage != icpt_info.stage)
6072 switch (icpt_info.exit_code) {
6073 case SVM_EXIT_READ_CR0:
6074 if (info->intercept == x86_intercept_cr_read)
6075 icpt_info.exit_code += info->modrm_reg;
6077 case SVM_EXIT_WRITE_CR0: {
6078 unsigned long cr0, val;
6081 if (info->intercept == x86_intercept_cr_write)
6082 icpt_info.exit_code += info->modrm_reg;
6084 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6085 info->intercept == x86_intercept_clts)
6088 intercept = svm->nested.intercept;
6090 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6093 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6094 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6096 if (info->intercept == x86_intercept_lmsw) {
6099 /* lmsw can't clear PE - catch this here */
6100 if (cr0 & X86_CR0_PE)
6105 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6109 case SVM_EXIT_READ_DR0:
6110 case SVM_EXIT_WRITE_DR0:
6111 icpt_info.exit_code += info->modrm_reg;
6114 if (info->intercept == x86_intercept_wrmsr)
6115 vmcb->control.exit_info_1 = 1;
6117 vmcb->control.exit_info_1 = 0;
6119 case SVM_EXIT_PAUSE:
6121 * We get this for NOP only, but pause
6122 * is rep not, check this here
6124 if (info->rep_prefix != REPE_PREFIX)
6127 case SVM_EXIT_IOIO: {
6131 if (info->intercept == x86_intercept_in ||
6132 info->intercept == x86_intercept_ins) {
6133 exit_info = ((info->src_val & 0xffff) << 16) |
6135 bytes = info->dst_bytes;
6137 exit_info = (info->dst_val & 0xffff) << 16;
6138 bytes = info->src_bytes;
6141 if (info->intercept == x86_intercept_outs ||
6142 info->intercept == x86_intercept_ins)
6143 exit_info |= SVM_IOIO_STR_MASK;
6145 if (info->rep_prefix)
6146 exit_info |= SVM_IOIO_REP_MASK;
6148 bytes = min(bytes, 4u);
6150 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6152 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6154 vmcb->control.exit_info_1 = exit_info;
6155 vmcb->control.exit_info_2 = info->next_rip;
6163 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6164 if (static_cpu_has(X86_FEATURE_NRIPS))
6165 vmcb->control.next_rip = info->next_rip;
6166 vmcb->control.exit_code = icpt_info.exit_code;
6167 vmexit = nested_svm_exit_handled(svm);
6169 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6176 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6181 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6183 if (pause_filter_thresh)
6184 shrink_ple_window(vcpu);
6187 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6189 if (avic_handle_apic_id_update(vcpu) != 0)
6191 avic_handle_dfr_update(vcpu);
6192 avic_handle_ldr_update(vcpu);
6195 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6197 /* [63:9] are reserved. */
6198 vcpu->arch.mcg_cap &= 0x1ff;
6201 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6203 struct vcpu_svm *svm = to_svm(vcpu);
6205 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6209 if (is_guest_mode(&svm->vcpu) &&
6210 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6211 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6212 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6213 svm->nested.exit_required = true;
6220 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6222 struct vcpu_svm *svm = to_svm(vcpu);
6225 if (is_guest_mode(vcpu)) {
6226 /* FED8h - SVM Guest */
6227 put_smstate(u64, smstate, 0x7ed8, 1);
6228 /* FEE0h - SVM Guest VMCB Physical Address */
6229 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6231 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6232 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6233 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6235 ret = nested_svm_vmexit(svm);
6242 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6244 struct vcpu_svm *svm = to_svm(vcpu);
6245 struct vmcb *nested_vmcb;
6246 struct kvm_host_map map;
6250 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6251 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6254 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6256 nested_vmcb = map.hva;
6257 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6262 static int enable_smi_window(struct kvm_vcpu *vcpu)
6264 struct vcpu_svm *svm = to_svm(vcpu);
6266 if (!gif_set(svm)) {
6267 if (vgif_enabled(svm))
6268 set_intercept(svm, INTERCEPT_STGI);
6269 /* STGI will cause a vm exit */
6275 static int sev_asid_new(void)
6280 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6282 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6283 if (pos >= max_sev_asid)
6286 set_bit(pos, sev_asid_bitmap);
6290 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6292 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6296 if (unlikely(sev->active))
6299 asid = sev_asid_new();
6303 ret = sev_platform_init(&argp->error);
6309 INIT_LIST_HEAD(&sev->regions_list);
6314 __sev_asid_free(asid);
6318 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6320 struct sev_data_activate *data;
6321 int asid = sev_get_asid(kvm);
6324 wbinvd_on_all_cpus();
6326 ret = sev_guest_df_flush(error);
6330 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6334 /* activate ASID on the given handle */
6335 data->handle = handle;
6337 ret = sev_guest_activate(data, error);
6343 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6352 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6358 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6360 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6362 return __sev_issue_cmd(sev->fd, id, data, error);
6365 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6367 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6368 struct sev_data_launch_start *start;
6369 struct kvm_sev_launch_start params;
6370 void *dh_blob, *session_blob;
6371 int *error = &argp->error;
6374 if (!sev_guest(kvm))
6377 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6380 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6385 if (params.dh_uaddr) {
6386 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6387 if (IS_ERR(dh_blob)) {
6388 ret = PTR_ERR(dh_blob);
6392 start->dh_cert_address = __sme_set(__pa(dh_blob));
6393 start->dh_cert_len = params.dh_len;
6396 session_blob = NULL;
6397 if (params.session_uaddr) {
6398 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6399 if (IS_ERR(session_blob)) {
6400 ret = PTR_ERR(session_blob);
6404 start->session_address = __sme_set(__pa(session_blob));
6405 start->session_len = params.session_len;
6408 start->handle = params.handle;
6409 start->policy = params.policy;
6411 /* create memory encryption context */
6412 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6414 goto e_free_session;
6416 /* Bind ASID to this guest */
6417 ret = sev_bind_asid(kvm, start->handle, error);
6419 goto e_free_session;
6421 /* return handle to userspace */
6422 params.handle = start->handle;
6423 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6424 sev_unbind_asid(kvm, start->handle);
6426 goto e_free_session;
6429 sev->handle = start->handle;
6430 sev->fd = argp->sev_fd;
6433 kfree(session_blob);
6441 static unsigned long get_num_contig_pages(unsigned long idx,
6442 struct page **inpages, unsigned long npages)
6444 unsigned long paddr, next_paddr;
6445 unsigned long i = idx + 1, pages = 1;
6447 /* find the number of contiguous pages starting from idx */
6448 paddr = __sme_page_pa(inpages[idx]);
6449 while (i < npages) {
6450 next_paddr = __sme_page_pa(inpages[i++]);
6451 if ((paddr + PAGE_SIZE) == next_paddr) {
6462 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6464 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6465 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6466 struct kvm_sev_launch_update_data params;
6467 struct sev_data_launch_update_data *data;
6468 struct page **inpages;
6471 if (!sev_guest(kvm))
6474 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6477 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6481 vaddr = params.uaddr;
6483 vaddr_end = vaddr + size;
6485 /* Lock the user memory. */
6486 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6493 * The LAUNCH_UPDATE command will perform in-place encryption of the
6494 * memory content (i.e it will write the same memory region with C=1).
6495 * It's possible that the cache may contain the data with C=0, i.e.,
6496 * unencrypted so invalidate it first.
6498 sev_clflush_pages(inpages, npages);
6500 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6504 * If the user buffer is not page-aligned, calculate the offset
6507 offset = vaddr & (PAGE_SIZE - 1);
6509 /* Calculate the number of pages that can be encrypted in one go. */
6510 pages = get_num_contig_pages(i, inpages, npages);
6512 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6514 data->handle = sev->handle;
6516 data->address = __sme_page_pa(inpages[i]) + offset;
6517 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6522 next_vaddr = vaddr + len;
6526 /* content of memory is updated, mark pages dirty */
6527 for (i = 0; i < npages; i++) {
6528 set_page_dirty_lock(inpages[i]);
6529 mark_page_accessed(inpages[i]);
6531 /* unlock the user pages */
6532 sev_unpin_memory(kvm, inpages, npages);
6538 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6540 void __user *measure = (void __user *)(uintptr_t)argp->data;
6541 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6542 struct sev_data_launch_measure *data;
6543 struct kvm_sev_launch_measure params;
6544 void __user *p = NULL;
6548 if (!sev_guest(kvm))
6551 if (copy_from_user(¶ms, measure, sizeof(params)))
6554 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6558 /* User wants to query the blob length */
6562 p = (void __user *)(uintptr_t)params.uaddr;
6564 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6570 blob = kmalloc(params.len, GFP_KERNEL);
6574 data->address = __psp_pa(blob);
6575 data->len = params.len;
6579 data->handle = sev->handle;
6580 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6583 * If we query the session length, FW responded with expected data.
6592 if (copy_to_user(p, blob, params.len))
6597 params.len = data->len;
6598 if (copy_to_user(measure, ¶ms, sizeof(params)))
6607 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6609 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6610 struct sev_data_launch_finish *data;
6613 if (!sev_guest(kvm))
6616 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6620 data->handle = sev->handle;
6621 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6627 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6629 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6630 struct kvm_sev_guest_status params;
6631 struct sev_data_guest_status *data;
6634 if (!sev_guest(kvm))
6637 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6641 data->handle = sev->handle;
6642 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6646 params.policy = data->policy;
6647 params.state = data->state;
6648 params.handle = data->handle;
6650 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6657 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6658 unsigned long dst, int size,
6659 int *error, bool enc)
6661 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6662 struct sev_data_dbg *data;
6665 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6669 data->handle = sev->handle;
6670 data->dst_addr = dst;
6671 data->src_addr = src;
6674 ret = sev_issue_cmd(kvm,
6675 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6681 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6682 unsigned long dst_paddr, int sz, int *err)
6687 * Its safe to read more than we are asked, caller should ensure that
6688 * destination has enough space.
6690 src_paddr = round_down(src_paddr, 16);
6691 offset = src_paddr & 15;
6692 sz = round_up(sz + offset, 16);
6694 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6697 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6698 unsigned long __user dst_uaddr,
6699 unsigned long dst_paddr,
6702 struct page *tpage = NULL;
6705 /* if inputs are not 16-byte then use intermediate buffer */
6706 if (!IS_ALIGNED(dst_paddr, 16) ||
6707 !IS_ALIGNED(paddr, 16) ||
6708 !IS_ALIGNED(size, 16)) {
6709 tpage = (void *)alloc_page(GFP_KERNEL);
6713 dst_paddr = __sme_page_pa(tpage);
6716 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6721 offset = paddr & 15;
6722 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6723 page_address(tpage) + offset, size))
6734 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6735 unsigned long __user vaddr,
6736 unsigned long dst_paddr,
6737 unsigned long __user dst_vaddr,
6738 int size, int *error)
6740 struct page *src_tpage = NULL;
6741 struct page *dst_tpage = NULL;
6742 int ret, len = size;
6744 /* If source buffer is not aligned then use an intermediate buffer */
6745 if (!IS_ALIGNED(vaddr, 16)) {
6746 src_tpage = alloc_page(GFP_KERNEL);
6750 if (copy_from_user(page_address(src_tpage),
6751 (void __user *)(uintptr_t)vaddr, size)) {
6752 __free_page(src_tpage);
6756 paddr = __sme_page_pa(src_tpage);
6760 * If destination buffer or length is not aligned then do read-modify-write:
6761 * - decrypt destination in an intermediate buffer
6762 * - copy the source buffer in an intermediate buffer
6763 * - use the intermediate buffer as source buffer
6765 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6768 dst_tpage = alloc_page(GFP_KERNEL);
6774 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6775 __sme_page_pa(dst_tpage), size, error);
6780 * If source is kernel buffer then use memcpy() otherwise
6783 dst_offset = dst_paddr & 15;
6786 memcpy(page_address(dst_tpage) + dst_offset,
6787 page_address(src_tpage), size);
6789 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6790 (void __user *)(uintptr_t)vaddr, size)) {
6796 paddr = __sme_page_pa(dst_tpage);
6797 dst_paddr = round_down(dst_paddr, 16);
6798 len = round_up(size, 16);
6801 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6805 __free_page(src_tpage);
6807 __free_page(dst_tpage);
6811 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6813 unsigned long vaddr, vaddr_end, next_vaddr;
6814 unsigned long dst_vaddr;
6815 struct page **src_p, **dst_p;
6816 struct kvm_sev_dbg debug;
6821 if (!sev_guest(kvm))
6824 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6827 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6829 if (!debug.dst_uaddr)
6832 vaddr = debug.src_uaddr;
6834 vaddr_end = vaddr + size;
6835 dst_vaddr = debug.dst_uaddr;
6837 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6838 int len, s_off, d_off;
6840 /* lock userspace source and destination page */
6841 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6845 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6847 sev_unpin_memory(kvm, src_p, n);
6852 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6853 * memory content (i.e it will write the same memory region with C=1).
6854 * It's possible that the cache may contain the data with C=0, i.e.,
6855 * unencrypted so invalidate it first.
6857 sev_clflush_pages(src_p, 1);
6858 sev_clflush_pages(dst_p, 1);
6861 * Since user buffer may not be page aligned, calculate the
6862 * offset within the page.
6864 s_off = vaddr & ~PAGE_MASK;
6865 d_off = dst_vaddr & ~PAGE_MASK;
6866 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6869 ret = __sev_dbg_decrypt_user(kvm,
6870 __sme_page_pa(src_p[0]) + s_off,
6872 __sme_page_pa(dst_p[0]) + d_off,
6875 ret = __sev_dbg_encrypt_user(kvm,
6876 __sme_page_pa(src_p[0]) + s_off,
6878 __sme_page_pa(dst_p[0]) + d_off,
6882 sev_unpin_memory(kvm, src_p, n);
6883 sev_unpin_memory(kvm, dst_p, n);
6888 next_vaddr = vaddr + len;
6889 dst_vaddr = dst_vaddr + len;
6896 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6898 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6899 struct sev_data_launch_secret *data;
6900 struct kvm_sev_launch_secret params;
6901 struct page **pages;
6906 if (!sev_guest(kvm))
6909 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6912 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6917 * The secret must be copied into contiguous memory region, lets verify
6918 * that userspace memory pages are contiguous before we issue command.
6920 if (get_num_contig_pages(0, pages, n) != n) {
6922 goto e_unpin_memory;
6926 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6928 goto e_unpin_memory;
6930 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6931 data->guest_address = __sme_page_pa(pages[0]) + offset;
6932 data->guest_len = params.guest_len;
6934 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6936 ret = PTR_ERR(blob);
6940 data->trans_address = __psp_pa(blob);
6941 data->trans_len = params.trans_len;
6943 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6948 data->hdr_address = __psp_pa(hdr);
6949 data->hdr_len = params.hdr_len;
6951 data->handle = sev->handle;
6952 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6961 sev_unpin_memory(kvm, pages, n);
6965 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6967 struct kvm_sev_cmd sev_cmd;
6970 if (!svm_sev_enabled())
6973 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6976 mutex_lock(&kvm->lock);
6978 switch (sev_cmd.id) {
6980 r = sev_guest_init(kvm, &sev_cmd);
6982 case KVM_SEV_LAUNCH_START:
6983 r = sev_launch_start(kvm, &sev_cmd);
6985 case KVM_SEV_LAUNCH_UPDATE_DATA:
6986 r = sev_launch_update_data(kvm, &sev_cmd);
6988 case KVM_SEV_LAUNCH_MEASURE:
6989 r = sev_launch_measure(kvm, &sev_cmd);
6991 case KVM_SEV_LAUNCH_FINISH:
6992 r = sev_launch_finish(kvm, &sev_cmd);
6994 case KVM_SEV_GUEST_STATUS:
6995 r = sev_guest_status(kvm, &sev_cmd);
6997 case KVM_SEV_DBG_DECRYPT:
6998 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7000 case KVM_SEV_DBG_ENCRYPT:
7001 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7003 case KVM_SEV_LAUNCH_SECRET:
7004 r = sev_launch_secret(kvm, &sev_cmd);
7011 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7015 mutex_unlock(&kvm->lock);
7019 static int svm_register_enc_region(struct kvm *kvm,
7020 struct kvm_enc_region *range)
7022 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7023 struct enc_region *region;
7026 if (!sev_guest(kvm))
7029 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7032 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7036 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7037 if (!region->pages) {
7043 * The guest may change the memory encryption attribute from C=0 -> C=1
7044 * or vice versa for this memory range. Lets make sure caches are
7045 * flushed to ensure that guest data gets written into memory with
7048 sev_clflush_pages(region->pages, region->npages);
7050 region->uaddr = range->addr;
7051 region->size = range->size;
7053 mutex_lock(&kvm->lock);
7054 list_add_tail(®ion->list, &sev->regions_list);
7055 mutex_unlock(&kvm->lock);
7064 static struct enc_region *
7065 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7067 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7068 struct list_head *head = &sev->regions_list;
7069 struct enc_region *i;
7071 list_for_each_entry(i, head, list) {
7072 if (i->uaddr == range->addr &&
7073 i->size == range->size)
7081 static int svm_unregister_enc_region(struct kvm *kvm,
7082 struct kvm_enc_region *range)
7084 struct enc_region *region;
7087 mutex_lock(&kvm->lock);
7089 if (!sev_guest(kvm)) {
7094 region = find_enc_region(kvm, range);
7100 __unregister_enc_region_locked(kvm, region);
7102 mutex_unlock(&kvm->lock);
7106 mutex_unlock(&kvm->lock);
7110 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7112 unsigned long cr4 = kvm_read_cr4(vcpu);
7113 bool smep = cr4 & X86_CR4_SMEP;
7114 bool smap = cr4 & X86_CR4_SMAP;
7115 bool is_user = svm_get_cpl(vcpu) == 3;
7118 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7121 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7122 * possible that CPU microcode implementing DecodeAssist will fail
7123 * to read bytes of instruction which caused #NPF. In this case,
7124 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7125 * return 0 instead of the correct guest instruction bytes.
7127 * This happens because CPU microcode reading instruction bytes
7128 * uses a special opcode which attempts to read data using CPL=0
7129 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7130 * fault, it gives up and returns no instruction bytes.
7133 * We reach here in case CPU supports DecodeAssist, raised #NPF and
7134 * returned 0 in GuestIntrBytes field of the VMCB.
7135 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7136 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7137 * in case vCPU CPL==3 (Because otherwise guest would have triggered
7138 * a SMEP fault instead of #NPF).
7139 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7140 * As most guests enable SMAP if they have also enabled SMEP, use above
7141 * logic in order to attempt minimize false-positive of detecting errata
7142 * while still preserving all cases semantic correctness.
7145 * To determine what instruction the guest was executing, the hypervisor
7146 * will have to decode the instruction at the instruction pointer.
7148 * In non SEV guest, hypervisor will be able to read the guest
7149 * memory to decode the instruction pointer when insn_len is zero
7150 * so we return true to indicate that decoding is possible.
7152 * But in the SEV guest, the guest memory is encrypted with the
7153 * guest specific key and hypervisor will not be able to decode the
7154 * instruction pointer so we will not able to workaround it. Lets
7155 * print the error and request to kill the guest.
7157 if (smap && (!smep || is_user)) {
7158 if (!sev_guest(vcpu->kvm))
7161 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7162 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7168 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7170 struct vcpu_svm *svm = to_svm(vcpu);
7173 * TODO: Last condition latch INIT signals on vCPU when
7174 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7175 * To properly emulate the INIT intercept, SVM should implement
7176 * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7177 * there if an INIT signal is pending.
7179 return !gif_set(svm) ||
7180 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7183 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7184 .cpu_has_kvm_support = has_svm,
7185 .disabled_by_bios = is_disabled,
7186 .hardware_setup = svm_hardware_setup,
7187 .hardware_unsetup = svm_hardware_unsetup,
7188 .check_processor_compatibility = svm_check_processor_compat,
7189 .hardware_enable = svm_hardware_enable,
7190 .hardware_disable = svm_hardware_disable,
7191 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7192 .has_emulated_msr = svm_has_emulated_msr,
7194 .vcpu_create = svm_create_vcpu,
7195 .vcpu_free = svm_free_vcpu,
7196 .vcpu_reset = svm_vcpu_reset,
7198 .vm_alloc = svm_vm_alloc,
7199 .vm_free = svm_vm_free,
7200 .vm_init = avic_vm_init,
7201 .vm_destroy = svm_vm_destroy,
7203 .prepare_guest_switch = svm_prepare_guest_switch,
7204 .vcpu_load = svm_vcpu_load,
7205 .vcpu_put = svm_vcpu_put,
7206 .vcpu_blocking = svm_vcpu_blocking,
7207 .vcpu_unblocking = svm_vcpu_unblocking,
7209 .update_bp_intercept = update_bp_intercept,
7210 .get_msr_feature = svm_get_msr_feature,
7211 .get_msr = svm_get_msr,
7212 .set_msr = svm_set_msr,
7213 .get_segment_base = svm_get_segment_base,
7214 .get_segment = svm_get_segment,
7215 .set_segment = svm_set_segment,
7216 .get_cpl = svm_get_cpl,
7217 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7218 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7219 .decache_cr3 = svm_decache_cr3,
7220 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7221 .set_cr0 = svm_set_cr0,
7222 .set_cr3 = svm_set_cr3,
7223 .set_cr4 = svm_set_cr4,
7224 .set_efer = svm_set_efer,
7225 .get_idt = svm_get_idt,
7226 .set_idt = svm_set_idt,
7227 .get_gdt = svm_get_gdt,
7228 .set_gdt = svm_set_gdt,
7229 .get_dr6 = svm_get_dr6,
7230 .set_dr6 = svm_set_dr6,
7231 .set_dr7 = svm_set_dr7,
7232 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7233 .cache_reg = svm_cache_reg,
7234 .get_rflags = svm_get_rflags,
7235 .set_rflags = svm_set_rflags,
7237 .tlb_flush = svm_flush_tlb,
7238 .tlb_flush_gva = svm_flush_tlb_gva,
7240 .run = svm_vcpu_run,
7241 .handle_exit = handle_exit,
7242 .skip_emulated_instruction = skip_emulated_instruction,
7243 .set_interrupt_shadow = svm_set_interrupt_shadow,
7244 .get_interrupt_shadow = svm_get_interrupt_shadow,
7245 .patch_hypercall = svm_patch_hypercall,
7246 .set_irq = svm_set_irq,
7247 .set_nmi = svm_inject_nmi,
7248 .queue_exception = svm_queue_exception,
7249 .cancel_injection = svm_cancel_injection,
7250 .interrupt_allowed = svm_interrupt_allowed,
7251 .nmi_allowed = svm_nmi_allowed,
7252 .get_nmi_mask = svm_get_nmi_mask,
7253 .set_nmi_mask = svm_set_nmi_mask,
7254 .enable_nmi_window = enable_nmi_window,
7255 .enable_irq_window = enable_irq_window,
7256 .update_cr8_intercept = update_cr8_intercept,
7257 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7258 .get_enable_apicv = svm_get_enable_apicv,
7259 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7260 .load_eoi_exitmap = svm_load_eoi_exitmap,
7261 .hwapic_irr_update = svm_hwapic_irr_update,
7262 .hwapic_isr_update = svm_hwapic_isr_update,
7263 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7264 .apicv_post_state_restore = avic_post_state_restore,
7266 .set_tss_addr = svm_set_tss_addr,
7267 .set_identity_map_addr = svm_set_identity_map_addr,
7268 .get_tdp_level = get_npt_level,
7269 .get_mt_mask = svm_get_mt_mask,
7271 .get_exit_info = svm_get_exit_info,
7273 .get_lpage_level = svm_get_lpage_level,
7275 .cpuid_update = svm_cpuid_update,
7277 .rdtscp_supported = svm_rdtscp_supported,
7278 .invpcid_supported = svm_invpcid_supported,
7279 .mpx_supported = svm_mpx_supported,
7280 .xsaves_supported = svm_xsaves_supported,
7281 .umip_emulated = svm_umip_emulated,
7282 .pt_supported = svm_pt_supported,
7284 .set_supported_cpuid = svm_set_supported_cpuid,
7286 .has_wbinvd_exit = svm_has_wbinvd_exit,
7288 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7289 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7291 .set_tdp_cr3 = set_tdp_cr3,
7293 .check_intercept = svm_check_intercept,
7294 .handle_exit_irqoff = svm_handle_exit_irqoff,
7296 .request_immediate_exit = __kvm_request_immediate_exit,
7298 .sched_in = svm_sched_in,
7300 .pmu_ops = &amd_pmu_ops,
7301 .deliver_posted_interrupt = svm_deliver_avic_intr,
7302 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7303 .update_pi_irte = svm_update_pi_irte,
7304 .setup_mce = svm_setup_mce,
7306 .smi_allowed = svm_smi_allowed,
7307 .pre_enter_smm = svm_pre_enter_smm,
7308 .pre_leave_smm = svm_pre_leave_smm,
7309 .enable_smi_window = enable_smi_window,
7311 .mem_enc_op = svm_mem_enc_op,
7312 .mem_enc_reg_region = svm_register_enc_region,
7313 .mem_enc_unreg_region = svm_unregister_enc_region,
7315 .nested_enable_evmcs = NULL,
7316 .nested_get_evmcs_version = NULL,
7318 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7320 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7323 static int __init svm_init(void)
7325 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7326 __alignof__(struct vcpu_svm), THIS_MODULE);
7329 static void __exit svm_exit(void)
7334 module_init(svm_init)
7335 module_exit(svm_exit)