2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM),
66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly;
123 static const u32 host_save_user_msrs[] = {
125 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
128 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info {
135 bool active; /* SEV enabled guest */
136 unsigned int asid; /* ASID used for this guest */
137 unsigned int handle; /* SEV firmware handle */
138 int fd; /* SEV device fd */
139 unsigned long pages_locked; /* Number of pages locked */
140 struct list_head regions_list; /* List of registered regions */
146 /* Struct members for AVIC */
149 struct page *avic_logical_id_table_page;
150 struct page *avic_physical_id_table_page;
151 struct hlist_node hnode;
153 struct kvm_sev_info sev_info;
158 struct nested_state {
164 /* These are the merged vectors */
167 /* gpa pointers to the real vectors */
171 /* A VMEXIT is required but not yet emulated */
174 /* cache for intercepts of the guest */
177 u32 intercept_exceptions;
180 /* Nested Paging related state */
184 #define MSRPM_OFFSETS 16
185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
188 * Set osvw_len to higher value when updated Revision Guides
189 * are published and we know what the new status bits are
191 static uint64_t osvw_len = 4, osvw_status;
194 struct kvm_vcpu vcpu;
196 unsigned long vmcb_pa;
197 struct svm_cpu_data *svm_data;
198 uint64_t asid_generation;
199 uint64_t sysenter_esp;
200 uint64_t sysenter_eip;
207 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
217 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
218 * translated into the appropriate L2_CFG bits on the host to
219 * perform speculative control.
227 struct nested_state nested;
230 u64 nmi_singlestep_guest_rflags;
232 unsigned int3_injected;
233 unsigned long int3_rip;
235 /* cached guest cpuid flags for faster access */
236 bool nrips_enabled : 1;
239 struct page *avic_backing_page;
240 u64 *avic_physical_id_cache;
241 bool avic_is_running;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list;
250 spinlock_t ir_list_lock;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir {
260 struct list_head node; /* Used by SVM for per-vcpu ir_list */
261 void *data; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
273 #define TSC_RATIO_DEFAULT 0x0100000000ULL
275 #define MSR_INVALID 0xffffffffU
277 static const struct svm_direct_access_msrs {
278 u32 index; /* Index of the MSR */
279 bool always; /* True if intercept is always on */
280 } direct_access_msrs[] = {
281 { .index = MSR_STAR, .always = true },
282 { .index = MSR_IA32_SYSENTER_CS, .always = true },
284 { .index = MSR_GS_BASE, .always = true },
285 { .index = MSR_FS_BASE, .always = true },
286 { .index = MSR_KERNEL_GS_BASE, .always = true },
287 { .index = MSR_LSTAR, .always = true },
288 { .index = MSR_CSTAR, .always = true },
289 { .index = MSR_SYSCALL_MASK, .always = true },
291 { .index = MSR_IA32_SPEC_CTRL, .always = false },
292 { .index = MSR_IA32_PRED_CMD, .always = false },
293 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
294 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
295 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
296 { .index = MSR_IA32_LASTINTTOIP, .always = false },
297 { .index = MSR_INVALID, .always = false },
300 /* enable NPT for AMD64 and X86 with PAE */
301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
302 static bool npt_enabled = true;
304 static bool npt_enabled;
308 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
309 * pause_filter_count: On processors that support Pause filtering(indicated
310 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
311 * count value. On VMRUN this value is loaded into an internal counter.
312 * Each time a pause instruction is executed, this counter is decremented
313 * until it reaches zero at which time a #VMEXIT is generated if pause
314 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
315 * Intercept Filtering for more details.
316 * This also indicate if ple logic enabled.
318 * pause_filter_thresh: In addition, some processor families support advanced
319 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
320 * the amount of time a guest is allowed to execute in a pause loop.
321 * In this mode, a 16-bit pause filter threshold field is added in the
322 * VMCB. The threshold value is a cycle count that is used to reset the
323 * pause counter. As with simple pause filtering, VMRUN loads the pause
324 * count value from VMCB into an internal counter. Then, on each pause
325 * instruction the hardware checks the elapsed number of cycles since
326 * the most recent pause instruction against the pause filter threshold.
327 * If the elapsed cycle count is greater than the pause filter threshold,
328 * then the internal pause count is reloaded from the VMCB and execution
329 * continues. If the elapsed cycle count is less than the pause filter
330 * threshold, then the internal pause count is decremented. If the count
331 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
332 * triggered. If advanced pause filtering is supported and pause filter
333 * threshold field is set to zero, the filter will operate in the simpler,
337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
338 module_param(pause_filter_thresh, ushort, 0444);
340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
341 module_param(pause_filter_count, ushort, 0444);
343 /* Default doubles per-vcpu window every exit. */
344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
345 module_param(pause_filter_count_grow, ushort, 0444);
347 /* Default resets per-vcpu window every exit to pause_filter_count. */
348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
349 module_param(pause_filter_count_shrink, ushort, 0444);
351 /* Default is to compute the maximum so we can never overflow. */
352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
353 module_param(pause_filter_count_max, ushort, 0444);
355 /* allow nested paging (virtualized MMU) for all guests */
356 static int npt = true;
357 module_param(npt, int, S_IRUGO);
359 /* allow nested virtualization in KVM/SVM */
360 static int nested = true;
361 module_param(nested, int, S_IRUGO);
363 /* enable / disable AVIC */
365 #ifdef CONFIG_X86_LOCAL_APIC
366 module_param(avic, int, S_IRUGO);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls = true;
371 module_param(vls, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif = true;
375 module_param(vgif, int, 0444);
377 /* enable/disable SEV support */
378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
379 module_param(sev, int, 0444);
381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
385 static void svm_complete_interrupts(struct vcpu_svm *svm);
387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
388 static int nested_svm_intercept(struct vcpu_svm *svm);
389 static int nested_svm_vmexit(struct vcpu_svm *svm);
390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
391 bool has_error_code, u32 error_code);
394 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
395 pause filter count */
396 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
397 VMCB_ASID, /* ASID */
398 VMCB_INTR, /* int_ctl, int_vector */
399 VMCB_NPT, /* npt_en, nCR3, gPAT */
400 VMCB_CR, /* CR0, CR3, CR4, EFER */
401 VMCB_DR, /* DR6, DR7 */
402 VMCB_DT, /* GDT, IDT */
403 VMCB_SEG, /* CS, DS, SS, ES, CPL */
404 VMCB_CR2, /* CR2 only */
405 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
406 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
407 * AVIC PHYSICAL_TABLE pointer,
408 * AVIC LOGICAL_TABLE pointer
413 /* TPR and CR2 are always written before VMRUN */
414 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
416 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
418 static unsigned int max_sev_asid;
419 static unsigned int min_sev_asid;
420 static unsigned long *sev_asid_bitmap;
421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
424 struct list_head list;
425 unsigned long npages;
432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
434 return container_of(kvm, struct kvm_svm, kvm);
437 static inline bool svm_sev_enabled(void)
439 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
442 static inline bool sev_guest(struct kvm *kvm)
444 #ifdef CONFIG_KVM_AMD_SEV
445 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
453 static inline int sev_get_asid(struct kvm *kvm)
455 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
460 static inline void mark_all_dirty(struct vmcb *vmcb)
462 vmcb->control.clean = 0;
465 static inline void mark_all_clean(struct vmcb *vmcb)
467 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
468 & ~VMCB_ALWAYS_DIRTY_MASK;
471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
473 vmcb->control.clean &= ~(1 << bit);
476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
478 return container_of(vcpu, struct vcpu_svm, vcpu);
481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
483 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
484 mark_dirty(svm->vmcb, VMCB_AVIC);
487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
489 struct vcpu_svm *svm = to_svm(vcpu);
490 u64 *entry = svm->avic_physical_id_cache;
495 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
498 static void recalc_intercepts(struct vcpu_svm *svm)
500 struct vmcb_control_area *c, *h;
501 struct nested_state *g;
503 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
505 if (!is_guest_mode(&svm->vcpu))
508 c = &svm->vmcb->control;
509 h = &svm->nested.hsave->control;
512 c->intercept_cr = h->intercept_cr | g->intercept_cr;
513 c->intercept_dr = h->intercept_dr | g->intercept_dr;
514 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
515 c->intercept = h->intercept | g->intercept;
518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
520 if (is_guest_mode(&svm->vcpu))
521 return svm->nested.hsave;
526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
528 struct vmcb *vmcb = get_host_vmcb(svm);
530 vmcb->control.intercept_cr |= (1U << bit);
532 recalc_intercepts(svm);
535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
537 struct vmcb *vmcb = get_host_vmcb(svm);
539 vmcb->control.intercept_cr &= ~(1U << bit);
541 recalc_intercepts(svm);
544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
546 struct vmcb *vmcb = get_host_vmcb(svm);
548 return vmcb->control.intercept_cr & (1U << bit);
551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
553 struct vmcb *vmcb = get_host_vmcb(svm);
555 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
556 | (1 << INTERCEPT_DR1_READ)
557 | (1 << INTERCEPT_DR2_READ)
558 | (1 << INTERCEPT_DR3_READ)
559 | (1 << INTERCEPT_DR4_READ)
560 | (1 << INTERCEPT_DR5_READ)
561 | (1 << INTERCEPT_DR6_READ)
562 | (1 << INTERCEPT_DR7_READ)
563 | (1 << INTERCEPT_DR0_WRITE)
564 | (1 << INTERCEPT_DR1_WRITE)
565 | (1 << INTERCEPT_DR2_WRITE)
566 | (1 << INTERCEPT_DR3_WRITE)
567 | (1 << INTERCEPT_DR4_WRITE)
568 | (1 << INTERCEPT_DR5_WRITE)
569 | (1 << INTERCEPT_DR6_WRITE)
570 | (1 << INTERCEPT_DR7_WRITE);
572 recalc_intercepts(svm);
575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
577 struct vmcb *vmcb = get_host_vmcb(svm);
579 vmcb->control.intercept_dr = 0;
581 recalc_intercepts(svm);
584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
586 struct vmcb *vmcb = get_host_vmcb(svm);
588 vmcb->control.intercept_exceptions |= (1U << bit);
590 recalc_intercepts(svm);
593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
595 struct vmcb *vmcb = get_host_vmcb(svm);
597 vmcb->control.intercept_exceptions &= ~(1U << bit);
599 recalc_intercepts(svm);
602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
604 struct vmcb *vmcb = get_host_vmcb(svm);
606 vmcb->control.intercept |= (1ULL << bit);
608 recalc_intercepts(svm);
611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
613 struct vmcb *vmcb = get_host_vmcb(svm);
615 vmcb->control.intercept &= ~(1ULL << bit);
617 recalc_intercepts(svm);
620 static inline bool vgif_enabled(struct vcpu_svm *svm)
622 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
625 static inline void enable_gif(struct vcpu_svm *svm)
627 if (vgif_enabled(svm))
628 svm->vmcb->control.int_ctl |= V_GIF_MASK;
630 svm->vcpu.arch.hflags |= HF_GIF_MASK;
633 static inline void disable_gif(struct vcpu_svm *svm)
635 if (vgif_enabled(svm))
636 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
638 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
641 static inline bool gif_set(struct vcpu_svm *svm)
643 if (vgif_enabled(svm))
644 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
646 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
649 static unsigned long iopm_base;
651 struct kvm_ldttss_desc {
654 unsigned base1:8, type:5, dpl:2, p:1;
655 unsigned limit1:4, zero0:3, g:1, base2:8;
658 } __attribute__((packed));
660 struct svm_cpu_data {
667 struct kvm_ldttss_desc *tss_desc;
669 struct page *save_area;
670 struct vmcb *current_vmcb;
672 /* index = sev_asid, value = vmcb pointer */
673 struct vmcb **sev_vmcbs;
676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
678 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
680 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
681 #define MSRS_RANGE_SIZE 2048
682 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
684 static u32 svm_msrpm_offset(u32 msr)
689 for (i = 0; i < NUM_MSR_MAPS; i++) {
690 if (msr < msrpm_ranges[i] ||
691 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
694 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
695 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
697 /* Now we have the u8 offset - but need the u32 offset */
701 /* MSR not in any range */
705 #define MAX_INST_SIZE 15
707 static inline void clgi(void)
709 asm volatile (__ex(SVM_CLGI));
712 static inline void stgi(void)
714 asm volatile (__ex(SVM_STGI));
717 static inline void invlpga(unsigned long addr, u32 asid)
719 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
722 static int get_npt_level(struct kvm_vcpu *vcpu)
725 return PT64_ROOT_4LEVEL;
727 return PT32E_ROOT_LEVEL;
731 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
733 vcpu->arch.efer = efer;
734 if (!npt_enabled && !(efer & EFER_LMA))
737 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
738 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
741 static int is_external_interrupt(u32 info)
743 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
744 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
747 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
749 struct vcpu_svm *svm = to_svm(vcpu);
752 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
753 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
757 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
759 struct vcpu_svm *svm = to_svm(vcpu);
762 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
764 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
768 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
770 struct vcpu_svm *svm = to_svm(vcpu);
772 if (svm->vmcb->control.next_rip != 0) {
773 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
774 svm->next_rip = svm->vmcb->control.next_rip;
777 if (!svm->next_rip) {
778 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
780 printk(KERN_DEBUG "%s: NOP\n", __func__);
783 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
784 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
785 __func__, kvm_rip_read(vcpu), svm->next_rip);
787 kvm_rip_write(vcpu, svm->next_rip);
788 svm_set_interrupt_shadow(vcpu, 0);
791 static void svm_queue_exception(struct kvm_vcpu *vcpu)
793 struct vcpu_svm *svm = to_svm(vcpu);
794 unsigned nr = vcpu->arch.exception.nr;
795 bool has_error_code = vcpu->arch.exception.has_error_code;
796 bool reinject = vcpu->arch.exception.injected;
797 u32 error_code = vcpu->arch.exception.error_code;
800 * If we are within a nested VM we'd better #VMEXIT and let the guest
801 * handle the exception
804 nested_svm_check_exception(svm, nr, has_error_code, error_code))
807 kvm_deliver_exception_payload(&svm->vcpu);
809 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
810 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
813 * For guest debugging where we have to reinject #BP if some
814 * INT3 is guest-owned:
815 * Emulate nRIP by moving RIP forward. Will fail if injection
816 * raises a fault that is not intercepted. Still better than
817 * failing in all cases.
819 skip_emulated_instruction(&svm->vcpu);
820 rip = kvm_rip_read(&svm->vcpu);
821 svm->int3_rip = rip + svm->vmcb->save.cs.base;
822 svm->int3_injected = rip - old_rip;
825 svm->vmcb->control.event_inj = nr
827 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
828 | SVM_EVTINJ_TYPE_EXEPT;
829 svm->vmcb->control.event_inj_err = error_code;
832 static void svm_init_erratum_383(void)
838 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
841 /* Use _safe variants to not break nested virtualization */
842 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
848 low = lower_32_bits(val);
849 high = upper_32_bits(val);
851 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
853 erratum_383_found = true;
856 static void svm_init_osvw(struct kvm_vcpu *vcpu)
859 * Guests should see errata 400 and 415 as fixed (assuming that
860 * HLT and IO instructions are intercepted).
862 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
863 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
866 * By increasing VCPU's osvw.length to 3 we are telling the guest that
867 * all osvw.status bits inside that length, including bit 0 (which is
868 * reserved for erratum 298), are valid. However, if host processor's
869 * osvw_len is 0 then osvw_status[0] carries no information. We need to
870 * be conservative here and therefore we tell the guest that erratum 298
871 * is present (because we really don't know).
873 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
874 vcpu->arch.osvw.status |= 1;
877 static int has_svm(void)
881 if (!cpu_has_svm(&msg)) {
882 printk(KERN_INFO "has_svm: %s\n", msg);
889 static void svm_hardware_disable(void)
891 /* Make sure we clean up behind us */
892 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
893 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
897 amd_pmu_disable_virt();
900 static int svm_hardware_enable(void)
903 struct svm_cpu_data *sd;
905 struct desc_struct *gdt;
906 int me = raw_smp_processor_id();
908 rdmsrl(MSR_EFER, efer);
909 if (efer & EFER_SVME)
913 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
916 sd = per_cpu(svm_data, me);
918 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
922 sd->asid_generation = 1;
923 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
924 sd->next_asid = sd->max_asid + 1;
925 sd->min_asid = max_sev_asid + 1;
927 gdt = get_current_gdt_rw();
928 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
930 wrmsrl(MSR_EFER, efer | EFER_SVME);
932 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
934 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
935 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
936 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
943 * Note that it is possible to have a system with mixed processor
944 * revisions and therefore different OSVW bits. If bits are not the same
945 * on different processors then choose the worst case (i.e. if erratum
946 * is present on one processor and not on another then assume that the
947 * erratum is present everywhere).
949 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
950 uint64_t len, status = 0;
953 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
955 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
959 osvw_status = osvw_len = 0;
963 osvw_status |= status;
964 osvw_status &= (1ULL << osvw_len) - 1;
967 osvw_status = osvw_len = 0;
969 svm_init_erratum_383();
971 amd_pmu_enable_virt();
976 static void svm_cpu_uninit(int cpu)
978 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
983 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
984 kfree(sd->sev_vmcbs);
985 __free_page(sd->save_area);
989 static int svm_cpu_init(int cpu)
991 struct svm_cpu_data *sd;
994 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
999 sd->save_area = alloc_page(GFP_KERNEL);
1003 if (svm_sev_enabled()) {
1005 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1012 per_cpu(svm_data, cpu) = sd;
1022 static bool valid_msr_intercept(u32 index)
1026 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1027 if (direct_access_msrs[i].index == index)
1033 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1040 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1041 to_svm(vcpu)->msrpm;
1043 offset = svm_msrpm_offset(msr);
1044 bit_write = 2 * (msr & 0x0f) + 1;
1045 tmp = msrpm[offset];
1047 BUG_ON(offset == MSR_INVALID);
1049 return !!test_bit(bit_write, &tmp);
1052 static void set_msr_interception(u32 *msrpm, unsigned msr,
1053 int read, int write)
1055 u8 bit_read, bit_write;
1060 * If this warning triggers extend the direct_access_msrs list at the
1061 * beginning of the file
1063 WARN_ON(!valid_msr_intercept(msr));
1065 offset = svm_msrpm_offset(msr);
1066 bit_read = 2 * (msr & 0x0f);
1067 bit_write = 2 * (msr & 0x0f) + 1;
1068 tmp = msrpm[offset];
1070 BUG_ON(offset == MSR_INVALID);
1072 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1073 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1075 msrpm[offset] = tmp;
1078 static void svm_vcpu_init_msrpm(u32 *msrpm)
1082 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1084 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1085 if (!direct_access_msrs[i].always)
1088 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1092 static void add_msr_offset(u32 offset)
1096 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1098 /* Offset already in list? */
1099 if (msrpm_offsets[i] == offset)
1102 /* Slot used by another offset? */
1103 if (msrpm_offsets[i] != MSR_INVALID)
1106 /* Add offset to list */
1107 msrpm_offsets[i] = offset;
1113 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1114 * increase MSRPM_OFFSETS in this case.
1119 static void init_msrpm_offsets(void)
1123 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1125 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1128 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1129 BUG_ON(offset == MSR_INVALID);
1131 add_msr_offset(offset);
1135 static void svm_enable_lbrv(struct vcpu_svm *svm)
1137 u32 *msrpm = svm->msrpm;
1139 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1140 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1141 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1142 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1143 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1146 static void svm_disable_lbrv(struct vcpu_svm *svm)
1148 u32 *msrpm = svm->msrpm;
1150 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1151 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1152 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1153 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1154 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1157 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1159 svm->nmi_singlestep = false;
1161 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1162 /* Clear our flags if they were not set by the guest */
1163 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1164 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1165 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1166 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1171 * This hash table is used to map VM_ID to a struct kvm_svm,
1172 * when handling AMD IOMMU GALOG notification to schedule in
1173 * a particular vCPU.
1175 #define SVM_VM_DATA_HASH_BITS 8
1176 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1177 static u32 next_vm_id = 0;
1178 static bool next_vm_id_wrapped = 0;
1179 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1182 * This function is called from IOMMU driver to notify
1183 * SVM to schedule in a particular vCPU of a particular VM.
1185 static int avic_ga_log_notifier(u32 ga_tag)
1187 unsigned long flags;
1188 struct kvm_svm *kvm_svm;
1189 struct kvm_vcpu *vcpu = NULL;
1190 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1191 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1193 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1195 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1196 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1197 if (kvm_svm->avic_vm_id != vm_id)
1199 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1202 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1205 * At this point, the IOMMU should have already set the pending
1206 * bit in the vAPIC backing page. So, we just need to schedule
1210 kvm_vcpu_wake_up(vcpu);
1215 static __init int sev_hardware_setup(void)
1217 struct sev_user_data_status *status;
1220 /* Maximum number of encrypted guests supported simultaneously */
1221 max_sev_asid = cpuid_ecx(0x8000001F);
1226 /* Minimum ASID value that should be used for SEV guest */
1227 min_sev_asid = cpuid_edx(0x8000001F);
1229 /* Initialize SEV ASID bitmap */
1230 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1231 if (!sev_asid_bitmap)
1234 status = kmalloc(sizeof(*status), GFP_KERNEL);
1239 * Check SEV platform status.
1241 * PLATFORM_STATUS can be called in any state, if we failed to query
1242 * the PLATFORM status then either PSP firmware does not support SEV
1243 * feature or SEV firmware is dead.
1245 rc = sev_platform_status(status, NULL);
1249 pr_info("SEV supported\n");
1256 static void grow_ple_window(struct kvm_vcpu *vcpu)
1258 struct vcpu_svm *svm = to_svm(vcpu);
1259 struct vmcb_control_area *control = &svm->vmcb->control;
1260 int old = control->pause_filter_count;
1262 control->pause_filter_count = __grow_ple_window(old,
1264 pause_filter_count_grow,
1265 pause_filter_count_max);
1267 if (control->pause_filter_count != old)
1268 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1270 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1271 control->pause_filter_count, old);
1274 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1276 struct vcpu_svm *svm = to_svm(vcpu);
1277 struct vmcb_control_area *control = &svm->vmcb->control;
1278 int old = control->pause_filter_count;
1280 control->pause_filter_count =
1281 __shrink_ple_window(old,
1283 pause_filter_count_shrink,
1284 pause_filter_count);
1285 if (control->pause_filter_count != old)
1286 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1288 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1289 control->pause_filter_count, old);
1292 static __init int svm_hardware_setup(void)
1295 struct page *iopm_pages;
1299 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1304 iopm_va = page_address(iopm_pages);
1305 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1306 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1308 init_msrpm_offsets();
1310 if (boot_cpu_has(X86_FEATURE_NX))
1311 kvm_enable_efer_bits(EFER_NX);
1313 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1314 kvm_enable_efer_bits(EFER_FFXSR);
1316 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1317 kvm_has_tsc_control = true;
1318 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1319 kvm_tsc_scaling_ratio_frac_bits = 32;
1322 /* Check for pause filtering support */
1323 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1324 pause_filter_count = 0;
1325 pause_filter_thresh = 0;
1326 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1327 pause_filter_thresh = 0;
1331 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1332 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1336 if (boot_cpu_has(X86_FEATURE_SEV) &&
1337 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1338 r = sev_hardware_setup();
1346 for_each_possible_cpu(cpu) {
1347 r = svm_cpu_init(cpu);
1352 if (!boot_cpu_has(X86_FEATURE_NPT))
1353 npt_enabled = false;
1355 if (npt_enabled && !npt) {
1356 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1357 npt_enabled = false;
1361 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1368 !boot_cpu_has(X86_FEATURE_AVIC) ||
1369 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1372 pr_info("AVIC enabled\n");
1374 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1380 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1381 !IS_ENABLED(CONFIG_X86_64)) {
1384 pr_info("Virtual VMLOAD VMSAVE supported\n");
1389 if (!boot_cpu_has(X86_FEATURE_VGIF))
1392 pr_info("Virtual GIF supported\n");
1398 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1403 static __exit void svm_hardware_unsetup(void)
1407 if (svm_sev_enabled())
1408 bitmap_free(sev_asid_bitmap);
1410 for_each_possible_cpu(cpu)
1411 svm_cpu_uninit(cpu);
1413 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1417 static void init_seg(struct vmcb_seg *seg)
1420 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1421 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1422 seg->limit = 0xffff;
1426 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1429 seg->attrib = SVM_SELECTOR_P_MASK | type;
1430 seg->limit = 0xffff;
1434 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1436 struct vcpu_svm *svm = to_svm(vcpu);
1438 if (is_guest_mode(vcpu))
1439 return svm->nested.hsave->control.tsc_offset;
1441 return vcpu->arch.tsc_offset;
1444 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1446 struct vcpu_svm *svm = to_svm(vcpu);
1447 u64 g_tsc_offset = 0;
1449 if (is_guest_mode(vcpu)) {
1450 /* Write L1's TSC offset. */
1451 g_tsc_offset = svm->vmcb->control.tsc_offset -
1452 svm->nested.hsave->control.tsc_offset;
1453 svm->nested.hsave->control.tsc_offset = offset;
1456 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1457 svm->vmcb->control.tsc_offset - g_tsc_offset,
1460 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1462 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1463 return svm->vmcb->control.tsc_offset;
1466 static void avic_init_vmcb(struct vcpu_svm *svm)
1468 struct vmcb *vmcb = svm->vmcb;
1469 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1470 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1471 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1472 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1474 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1475 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1476 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1477 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1478 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1481 static void init_vmcb(struct vcpu_svm *svm)
1483 struct vmcb_control_area *control = &svm->vmcb->control;
1484 struct vmcb_save_area *save = &svm->vmcb->save;
1486 svm->vcpu.arch.hflags = 0;
1488 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1489 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1490 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1491 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1492 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1493 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1494 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1495 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1497 set_dr_intercepts(svm);
1499 set_exception_intercept(svm, PF_VECTOR);
1500 set_exception_intercept(svm, UD_VECTOR);
1501 set_exception_intercept(svm, MC_VECTOR);
1502 set_exception_intercept(svm, AC_VECTOR);
1503 set_exception_intercept(svm, DB_VECTOR);
1505 * Guest access to VMware backdoor ports could legitimately
1506 * trigger #GP because of TSS I/O permission bitmap.
1507 * We intercept those #GP and allow access to them anyway
1510 if (enable_vmware_backdoor)
1511 set_exception_intercept(svm, GP_VECTOR);
1513 set_intercept(svm, INTERCEPT_INTR);
1514 set_intercept(svm, INTERCEPT_NMI);
1515 set_intercept(svm, INTERCEPT_SMI);
1516 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1517 set_intercept(svm, INTERCEPT_RDPMC);
1518 set_intercept(svm, INTERCEPT_CPUID);
1519 set_intercept(svm, INTERCEPT_INVD);
1520 set_intercept(svm, INTERCEPT_INVLPG);
1521 set_intercept(svm, INTERCEPT_INVLPGA);
1522 set_intercept(svm, INTERCEPT_IOIO_PROT);
1523 set_intercept(svm, INTERCEPT_MSR_PROT);
1524 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1525 set_intercept(svm, INTERCEPT_SHUTDOWN);
1526 set_intercept(svm, INTERCEPT_VMRUN);
1527 set_intercept(svm, INTERCEPT_VMMCALL);
1528 set_intercept(svm, INTERCEPT_VMLOAD);
1529 set_intercept(svm, INTERCEPT_VMSAVE);
1530 set_intercept(svm, INTERCEPT_STGI);
1531 set_intercept(svm, INTERCEPT_CLGI);
1532 set_intercept(svm, INTERCEPT_SKINIT);
1533 set_intercept(svm, INTERCEPT_WBINVD);
1534 set_intercept(svm, INTERCEPT_XSETBV);
1535 set_intercept(svm, INTERCEPT_RSM);
1537 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1538 set_intercept(svm, INTERCEPT_MONITOR);
1539 set_intercept(svm, INTERCEPT_MWAIT);
1542 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1543 set_intercept(svm, INTERCEPT_HLT);
1545 control->iopm_base_pa = __sme_set(iopm_base);
1546 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1547 control->int_ctl = V_INTR_MASKING_MASK;
1549 init_seg(&save->es);
1550 init_seg(&save->ss);
1551 init_seg(&save->ds);
1552 init_seg(&save->fs);
1553 init_seg(&save->gs);
1555 save->cs.selector = 0xf000;
1556 save->cs.base = 0xffff0000;
1557 /* Executable/Readable Code Segment */
1558 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1559 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1560 save->cs.limit = 0xffff;
1562 save->gdtr.limit = 0xffff;
1563 save->idtr.limit = 0xffff;
1565 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1566 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1568 svm_set_efer(&svm->vcpu, 0);
1569 save->dr6 = 0xffff0ff0;
1570 kvm_set_rflags(&svm->vcpu, 2);
1571 save->rip = 0x0000fff0;
1572 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1575 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1576 * It also updates the guest-visible cr0 value.
1578 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1579 kvm_mmu_reset_context(&svm->vcpu);
1581 save->cr4 = X86_CR4_PAE;
1585 /* Setup VMCB for Nested Paging */
1586 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1587 clr_intercept(svm, INTERCEPT_INVLPG);
1588 clr_exception_intercept(svm, PF_VECTOR);
1589 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1590 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1591 save->g_pat = svm->vcpu.arch.pat;
1595 svm->asid_generation = 0;
1597 svm->nested.vmcb = 0;
1598 svm->vcpu.arch.hflags = 0;
1600 if (pause_filter_count) {
1601 control->pause_filter_count = pause_filter_count;
1602 if (pause_filter_thresh)
1603 control->pause_filter_thresh = pause_filter_thresh;
1604 set_intercept(svm, INTERCEPT_PAUSE);
1606 clr_intercept(svm, INTERCEPT_PAUSE);
1609 if (kvm_vcpu_apicv_active(&svm->vcpu))
1610 avic_init_vmcb(svm);
1613 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1614 * in VMCB and clear intercepts to avoid #VMEXIT.
1617 clr_intercept(svm, INTERCEPT_VMLOAD);
1618 clr_intercept(svm, INTERCEPT_VMSAVE);
1619 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1623 clr_intercept(svm, INTERCEPT_STGI);
1624 clr_intercept(svm, INTERCEPT_CLGI);
1625 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1628 if (sev_guest(svm->vcpu.kvm)) {
1629 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1630 clr_exception_intercept(svm, UD_VECTOR);
1633 mark_all_dirty(svm->vmcb);
1639 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1642 u64 *avic_physical_id_table;
1643 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1645 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1648 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1650 return &avic_physical_id_table[index];
1655 * AVIC hardware walks the nested page table to check permissions,
1656 * but does not use the SPA address specified in the leaf page
1657 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1658 * field of the VMCB. Therefore, we set up the
1659 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1661 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1663 struct kvm *kvm = vcpu->kvm;
1666 mutex_lock(&kvm->slots_lock);
1667 if (kvm->arch.apic_access_page_done)
1670 ret = __x86_set_memory_region(kvm,
1671 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1672 APIC_DEFAULT_PHYS_BASE,
1677 kvm->arch.apic_access_page_done = true;
1679 mutex_unlock(&kvm->slots_lock);
1683 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1686 u64 *entry, new_entry;
1687 int id = vcpu->vcpu_id;
1688 struct vcpu_svm *svm = to_svm(vcpu);
1690 ret = avic_init_access_page(vcpu);
1694 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1697 if (!svm->vcpu.arch.apic->regs)
1700 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1702 /* Setting AVIC backing page address in the phy APIC ID table */
1703 entry = avic_get_physical_id_entry(vcpu, id);
1707 new_entry = READ_ONCE(*entry);
1708 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1709 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1710 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1711 WRITE_ONCE(*entry, new_entry);
1713 svm->avic_physical_id_cache = entry;
1718 static void __sev_asid_free(int asid)
1720 struct svm_cpu_data *sd;
1724 clear_bit(pos, sev_asid_bitmap);
1726 for_each_possible_cpu(cpu) {
1727 sd = per_cpu(svm_data, cpu);
1728 sd->sev_vmcbs[pos] = NULL;
1732 static void sev_asid_free(struct kvm *kvm)
1734 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1736 __sev_asid_free(sev->asid);
1739 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1741 struct sev_data_decommission *decommission;
1742 struct sev_data_deactivate *data;
1747 data = kzalloc(sizeof(*data), GFP_KERNEL);
1751 /* deactivate handle */
1752 data->handle = handle;
1753 sev_guest_deactivate(data, NULL);
1755 wbinvd_on_all_cpus();
1756 sev_guest_df_flush(NULL);
1759 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1763 /* decommission handle */
1764 decommission->handle = handle;
1765 sev_guest_decommission(decommission, NULL);
1767 kfree(decommission);
1770 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1771 unsigned long ulen, unsigned long *n,
1774 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1775 unsigned long npages, npinned, size;
1776 unsigned long locked, lock_limit;
1777 struct page **pages;
1778 unsigned long first, last;
1780 if (ulen == 0 || uaddr + ulen < uaddr)
1783 /* Calculate number of pages. */
1784 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1785 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1786 npages = (last - first + 1);
1788 locked = sev->pages_locked + npages;
1789 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1790 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1791 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1795 /* Avoid using vmalloc for smaller buffers. */
1796 size = npages * sizeof(struct page *);
1797 if (size > PAGE_SIZE)
1798 pages = vmalloc(size);
1800 pages = kmalloc(size, GFP_KERNEL);
1805 /* Pin the user virtual address. */
1806 npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1807 if (npinned != npages) {
1808 pr_err("SEV: Failure locking %lu pages.\n", npages);
1813 sev->pages_locked = locked;
1819 release_pages(pages, npinned);
1825 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1826 unsigned long npages)
1828 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1830 release_pages(pages, npages);
1832 sev->pages_locked -= npages;
1835 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1837 uint8_t *page_virtual;
1840 if (npages == 0 || pages == NULL)
1843 for (i = 0; i < npages; i++) {
1844 page_virtual = kmap_atomic(pages[i]);
1845 clflush_cache_range(page_virtual, PAGE_SIZE);
1846 kunmap_atomic(page_virtual);
1850 static void __unregister_enc_region_locked(struct kvm *kvm,
1851 struct enc_region *region)
1854 * The guest may change the memory encryption attribute from C=0 -> C=1
1855 * or vice versa for this memory range. Lets make sure caches are
1856 * flushed to ensure that guest data gets written into memory with
1859 sev_clflush_pages(region->pages, region->npages);
1861 sev_unpin_memory(kvm, region->pages, region->npages);
1862 list_del(®ion->list);
1866 static struct kvm *svm_vm_alloc(void)
1868 struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1869 return &kvm_svm->kvm;
1872 static void svm_vm_free(struct kvm *kvm)
1874 vfree(to_kvm_svm(kvm));
1877 static void sev_vm_destroy(struct kvm *kvm)
1879 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1880 struct list_head *head = &sev->regions_list;
1881 struct list_head *pos, *q;
1883 if (!sev_guest(kvm))
1886 mutex_lock(&kvm->lock);
1889 * if userspace was terminated before unregistering the memory regions
1890 * then lets unpin all the registered memory.
1892 if (!list_empty(head)) {
1893 list_for_each_safe(pos, q, head) {
1894 __unregister_enc_region_locked(kvm,
1895 list_entry(pos, struct enc_region, list));
1899 mutex_unlock(&kvm->lock);
1901 sev_unbind_asid(kvm, sev->handle);
1905 static void avic_vm_destroy(struct kvm *kvm)
1907 unsigned long flags;
1908 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1913 if (kvm_svm->avic_logical_id_table_page)
1914 __free_page(kvm_svm->avic_logical_id_table_page);
1915 if (kvm_svm->avic_physical_id_table_page)
1916 __free_page(kvm_svm->avic_physical_id_table_page);
1918 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1919 hash_del(&kvm_svm->hnode);
1920 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1923 static void svm_vm_destroy(struct kvm *kvm)
1925 avic_vm_destroy(kvm);
1926 sev_vm_destroy(kvm);
1929 static int avic_vm_init(struct kvm *kvm)
1931 unsigned long flags;
1933 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1935 struct page *p_page;
1936 struct page *l_page;
1942 /* Allocating physical APIC ID table (4KB) */
1943 p_page = alloc_page(GFP_KERNEL);
1947 kvm_svm->avic_physical_id_table_page = p_page;
1948 clear_page(page_address(p_page));
1950 /* Allocating logical APIC ID table (4KB) */
1951 l_page = alloc_page(GFP_KERNEL);
1955 kvm_svm->avic_logical_id_table_page = l_page;
1956 clear_page(page_address(l_page));
1958 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1960 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1961 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1962 next_vm_id_wrapped = 1;
1965 /* Is it still in use? Only possible if wrapped at least once */
1966 if (next_vm_id_wrapped) {
1967 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1968 if (k2->avic_vm_id == vm_id)
1972 kvm_svm->avic_vm_id = vm_id;
1973 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1974 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1979 avic_vm_destroy(kvm);
1984 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1987 unsigned long flags;
1988 struct amd_svm_iommu_ir *ir;
1989 struct vcpu_svm *svm = to_svm(vcpu);
1991 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1995 * Here, we go through the per-vcpu ir_list to update all existing
1996 * interrupt remapping table entry targeting this vcpu.
1998 spin_lock_irqsave(&svm->ir_list_lock, flags);
2000 if (list_empty(&svm->ir_list))
2003 list_for_each_entry(ir, &svm->ir_list, node) {
2004 ret = amd_iommu_update_ga(cpu, r, ir->data);
2009 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2013 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2016 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2017 int h_physical_id = kvm_cpu_get_apicid(cpu);
2018 struct vcpu_svm *svm = to_svm(vcpu);
2020 if (!kvm_vcpu_apicv_active(vcpu))
2023 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2026 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2027 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2029 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2030 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2032 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2033 if (svm->avic_is_running)
2034 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2036 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2037 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2038 svm->avic_is_running);
2041 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2044 struct vcpu_svm *svm = to_svm(vcpu);
2046 if (!kvm_vcpu_apicv_active(vcpu))
2049 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2050 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2051 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2053 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2054 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2058 * This function is called during VCPU halt/unhalt.
2060 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2062 struct vcpu_svm *svm = to_svm(vcpu);
2064 svm->avic_is_running = is_run;
2066 avic_vcpu_load(vcpu, vcpu->cpu);
2068 avic_vcpu_put(vcpu);
2071 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2073 struct vcpu_svm *svm = to_svm(vcpu);
2077 vcpu->arch.microcode_version = 0x01000065;
2079 svm->virt_spec_ctrl = 0;
2082 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2083 MSR_IA32_APICBASE_ENABLE;
2084 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2085 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2089 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2090 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2092 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2093 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2096 static int avic_init_vcpu(struct vcpu_svm *svm)
2100 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2103 ret = avic_init_backing_page(&svm->vcpu);
2107 INIT_LIST_HEAD(&svm->ir_list);
2108 spin_lock_init(&svm->ir_list_lock);
2113 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2115 struct vcpu_svm *svm;
2117 struct page *msrpm_pages;
2118 struct page *hsave_page;
2119 struct page *nested_msrpm_pages;
2122 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2128 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2133 page = alloc_page(GFP_KERNEL);
2137 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2141 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2142 if (!nested_msrpm_pages)
2145 hsave_page = alloc_page(GFP_KERNEL);
2149 err = avic_init_vcpu(svm);
2153 /* We initialize this flag to true to make sure that the is_running
2154 * bit would be set the first time the vcpu is loaded.
2156 svm->avic_is_running = true;
2158 svm->nested.hsave = page_address(hsave_page);
2160 svm->msrpm = page_address(msrpm_pages);
2161 svm_vcpu_init_msrpm(svm->msrpm);
2163 svm->nested.msrpm = page_address(nested_msrpm_pages);
2164 svm_vcpu_init_msrpm(svm->nested.msrpm);
2166 svm->vmcb = page_address(page);
2167 clear_page(svm->vmcb);
2168 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2169 svm->asid_generation = 0;
2172 svm_init_osvw(&svm->vcpu);
2177 __free_page(hsave_page);
2179 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2181 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2185 kvm_vcpu_uninit(&svm->vcpu);
2187 kmem_cache_free(kvm_vcpu_cache, svm);
2189 return ERR_PTR(err);
2192 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2196 for_each_online_cpu(i)
2197 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2200 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2202 struct vcpu_svm *svm = to_svm(vcpu);
2205 * The vmcb page can be recycled, causing a false negative in
2206 * svm_vcpu_load(). So, ensure that no logical CPU has this
2207 * vmcb page recorded as its current vmcb.
2209 svm_clear_current_vmcb(svm->vmcb);
2211 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2212 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2213 __free_page(virt_to_page(svm->nested.hsave));
2214 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2215 kvm_vcpu_uninit(vcpu);
2216 kmem_cache_free(kvm_vcpu_cache, svm);
2219 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2221 struct vcpu_svm *svm = to_svm(vcpu);
2222 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2225 if (unlikely(cpu != vcpu->cpu)) {
2226 svm->asid_generation = 0;
2227 mark_all_dirty(svm->vmcb);
2230 #ifdef CONFIG_X86_64
2231 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2233 savesegment(fs, svm->host.fs);
2234 savesegment(gs, svm->host.gs);
2235 svm->host.ldt = kvm_read_ldt();
2237 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2238 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2240 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2241 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2242 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2243 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2244 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2247 /* This assumes that the kernel never uses MSR_TSC_AUX */
2248 if (static_cpu_has(X86_FEATURE_RDTSCP))
2249 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2251 if (sd->current_vmcb != svm->vmcb) {
2252 sd->current_vmcb = svm->vmcb;
2253 indirect_branch_prediction_barrier();
2255 avic_vcpu_load(vcpu, cpu);
2258 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2260 struct vcpu_svm *svm = to_svm(vcpu);
2263 avic_vcpu_put(vcpu);
2265 ++vcpu->stat.host_state_reload;
2266 kvm_load_ldt(svm->host.ldt);
2267 #ifdef CONFIG_X86_64
2268 loadsegment(fs, svm->host.fs);
2269 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2270 load_gs_index(svm->host.gs);
2272 #ifdef CONFIG_X86_32_LAZY_GS
2273 loadsegment(gs, svm->host.gs);
2276 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2277 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2280 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2282 avic_set_running(vcpu, false);
2285 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2287 avic_set_running(vcpu, true);
2290 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2292 struct vcpu_svm *svm = to_svm(vcpu);
2293 unsigned long rflags = svm->vmcb->save.rflags;
2295 if (svm->nmi_singlestep) {
2296 /* Hide our flags if they were not set by the guest */
2297 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2298 rflags &= ~X86_EFLAGS_TF;
2299 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2300 rflags &= ~X86_EFLAGS_RF;
2305 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2307 if (to_svm(vcpu)->nmi_singlestep)
2308 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2311 * Any change of EFLAGS.VM is accompanied by a reload of SS
2312 * (caused by either a task switch or an inter-privilege IRET),
2313 * so we do not need to update the CPL here.
2315 to_svm(vcpu)->vmcb->save.rflags = rflags;
2318 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2321 case VCPU_EXREG_PDPTR:
2322 BUG_ON(!npt_enabled);
2323 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2330 static void svm_set_vintr(struct vcpu_svm *svm)
2332 set_intercept(svm, INTERCEPT_VINTR);
2335 static void svm_clear_vintr(struct vcpu_svm *svm)
2337 clr_intercept(svm, INTERCEPT_VINTR);
2340 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2342 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2345 case VCPU_SREG_CS: return &save->cs;
2346 case VCPU_SREG_DS: return &save->ds;
2347 case VCPU_SREG_ES: return &save->es;
2348 case VCPU_SREG_FS: return &save->fs;
2349 case VCPU_SREG_GS: return &save->gs;
2350 case VCPU_SREG_SS: return &save->ss;
2351 case VCPU_SREG_TR: return &save->tr;
2352 case VCPU_SREG_LDTR: return &save->ldtr;
2358 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2360 struct vmcb_seg *s = svm_seg(vcpu, seg);
2365 static void svm_get_segment(struct kvm_vcpu *vcpu,
2366 struct kvm_segment *var, int seg)
2368 struct vmcb_seg *s = svm_seg(vcpu, seg);
2370 var->base = s->base;
2371 var->limit = s->limit;
2372 var->selector = s->selector;
2373 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2374 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2375 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2376 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2377 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2378 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2379 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2382 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2383 * However, the SVM spec states that the G bit is not observed by the
2384 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2385 * So let's synthesize a legal G bit for all segments, this helps
2386 * running KVM nested. It also helps cross-vendor migration, because
2387 * Intel's vmentry has a check on the 'G' bit.
2389 var->g = s->limit > 0xfffff;
2392 * AMD's VMCB does not have an explicit unusable field, so emulate it
2393 * for cross vendor migration purposes by "not present"
2395 var->unusable = !var->present;
2400 * Work around a bug where the busy flag in the tr selector
2410 * The accessed bit must always be set in the segment
2411 * descriptor cache, although it can be cleared in the
2412 * descriptor, the cached bit always remains at 1. Since
2413 * Intel has a check on this, set it here to support
2414 * cross-vendor migration.
2421 * On AMD CPUs sometimes the DB bit in the segment
2422 * descriptor is left as 1, although the whole segment has
2423 * been made unusable. Clear it here to pass an Intel VMX
2424 * entry check when cross vendor migrating.
2428 /* This is symmetric with svm_set_segment() */
2429 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2434 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2436 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2441 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2443 struct vcpu_svm *svm = to_svm(vcpu);
2445 dt->size = svm->vmcb->save.idtr.limit;
2446 dt->address = svm->vmcb->save.idtr.base;
2449 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2451 struct vcpu_svm *svm = to_svm(vcpu);
2453 svm->vmcb->save.idtr.limit = dt->size;
2454 svm->vmcb->save.idtr.base = dt->address ;
2455 mark_dirty(svm->vmcb, VMCB_DT);
2458 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2460 struct vcpu_svm *svm = to_svm(vcpu);
2462 dt->size = svm->vmcb->save.gdtr.limit;
2463 dt->address = svm->vmcb->save.gdtr.base;
2466 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2468 struct vcpu_svm *svm = to_svm(vcpu);
2470 svm->vmcb->save.gdtr.limit = dt->size;
2471 svm->vmcb->save.gdtr.base = dt->address ;
2472 mark_dirty(svm->vmcb, VMCB_DT);
2475 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2479 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2483 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2487 static void update_cr0_intercept(struct vcpu_svm *svm)
2489 ulong gcr0 = svm->vcpu.arch.cr0;
2490 u64 *hcr0 = &svm->vmcb->save.cr0;
2492 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2493 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2495 mark_dirty(svm->vmcb, VMCB_CR);
2497 if (gcr0 == *hcr0) {
2498 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2499 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2501 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2502 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2506 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2508 struct vcpu_svm *svm = to_svm(vcpu);
2510 #ifdef CONFIG_X86_64
2511 if (vcpu->arch.efer & EFER_LME) {
2512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2513 vcpu->arch.efer |= EFER_LMA;
2514 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2517 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2518 vcpu->arch.efer &= ~EFER_LMA;
2519 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2523 vcpu->arch.cr0 = cr0;
2526 cr0 |= X86_CR0_PG | X86_CR0_WP;
2529 * re-enable caching here because the QEMU bios
2530 * does not do it - this results in some delay at
2533 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2534 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2535 svm->vmcb->save.cr0 = cr0;
2536 mark_dirty(svm->vmcb, VMCB_CR);
2537 update_cr0_intercept(svm);
2540 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2542 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2543 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2545 if (cr4 & X86_CR4_VMXE)
2548 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2549 svm_flush_tlb(vcpu, true);
2551 vcpu->arch.cr4 = cr4;
2554 cr4 |= host_cr4_mce;
2555 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2556 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2560 static void svm_set_segment(struct kvm_vcpu *vcpu,
2561 struct kvm_segment *var, int seg)
2563 struct vcpu_svm *svm = to_svm(vcpu);
2564 struct vmcb_seg *s = svm_seg(vcpu, seg);
2566 s->base = var->base;
2567 s->limit = var->limit;
2568 s->selector = var->selector;
2569 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2570 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2571 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2572 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2573 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2574 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2575 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2576 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2579 * This is always accurate, except if SYSRET returned to a segment
2580 * with SS.DPL != 3. Intel does not have this quirk, and always
2581 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2582 * would entail passing the CPL to userspace and back.
2584 if (seg == VCPU_SREG_SS)
2585 /* This is symmetric with svm_get_segment() */
2586 svm->vmcb->save.cpl = (var->dpl & 3);
2588 mark_dirty(svm->vmcb, VMCB_SEG);
2591 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2593 struct vcpu_svm *svm = to_svm(vcpu);
2595 clr_exception_intercept(svm, BP_VECTOR);
2597 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2598 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2599 set_exception_intercept(svm, BP_VECTOR);
2601 vcpu->guest_debug = 0;
2604 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2606 if (sd->next_asid > sd->max_asid) {
2607 ++sd->asid_generation;
2608 sd->next_asid = sd->min_asid;
2609 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2612 svm->asid_generation = sd->asid_generation;
2613 svm->vmcb->control.asid = sd->next_asid++;
2615 mark_dirty(svm->vmcb, VMCB_ASID);
2618 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2620 return to_svm(vcpu)->vmcb->save.dr6;
2623 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2625 struct vcpu_svm *svm = to_svm(vcpu);
2627 svm->vmcb->save.dr6 = value;
2628 mark_dirty(svm->vmcb, VMCB_DR);
2631 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2633 struct vcpu_svm *svm = to_svm(vcpu);
2635 get_debugreg(vcpu->arch.db[0], 0);
2636 get_debugreg(vcpu->arch.db[1], 1);
2637 get_debugreg(vcpu->arch.db[2], 2);
2638 get_debugreg(vcpu->arch.db[3], 3);
2639 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2640 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2642 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2643 set_dr_intercepts(svm);
2646 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2648 struct vcpu_svm *svm = to_svm(vcpu);
2650 svm->vmcb->save.dr7 = value;
2651 mark_dirty(svm->vmcb, VMCB_DR);
2654 static int pf_interception(struct vcpu_svm *svm)
2656 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2657 u64 error_code = svm->vmcb->control.exit_info_1;
2659 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2660 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2661 svm->vmcb->control.insn_bytes : NULL,
2662 svm->vmcb->control.insn_len);
2665 static int npf_interception(struct vcpu_svm *svm)
2667 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2668 u64 error_code = svm->vmcb->control.exit_info_1;
2670 trace_kvm_page_fault(fault_address, error_code);
2671 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2672 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2673 svm->vmcb->control.insn_bytes : NULL,
2674 svm->vmcb->control.insn_len);
2677 static int db_interception(struct vcpu_svm *svm)
2679 struct kvm_run *kvm_run = svm->vcpu.run;
2681 if (!(svm->vcpu.guest_debug &
2682 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2683 !svm->nmi_singlestep) {
2684 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2688 if (svm->nmi_singlestep) {
2689 disable_nmi_singlestep(svm);
2692 if (svm->vcpu.guest_debug &
2693 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2694 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2695 kvm_run->debug.arch.pc =
2696 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2697 kvm_run->debug.arch.exception = DB_VECTOR;
2704 static int bp_interception(struct vcpu_svm *svm)
2706 struct kvm_run *kvm_run = svm->vcpu.run;
2708 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2709 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2710 kvm_run->debug.arch.exception = BP_VECTOR;
2714 static int ud_interception(struct vcpu_svm *svm)
2716 return handle_ud(&svm->vcpu);
2719 static int ac_interception(struct vcpu_svm *svm)
2721 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2725 static int gp_interception(struct vcpu_svm *svm)
2727 struct kvm_vcpu *vcpu = &svm->vcpu;
2728 u32 error_code = svm->vmcb->control.exit_info_1;
2731 WARN_ON_ONCE(!enable_vmware_backdoor);
2733 er = kvm_emulate_instruction(vcpu,
2734 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2735 if (er == EMULATE_USER_EXIT)
2737 else if (er != EMULATE_DONE)
2738 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2742 static bool is_erratum_383(void)
2747 if (!erratum_383_found)
2750 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2754 /* Bit 62 may or may not be set for this mce */
2755 value &= ~(1ULL << 62);
2757 if (value != 0xb600000000010015ULL)
2760 /* Clear MCi_STATUS registers */
2761 for (i = 0; i < 6; ++i)
2762 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2764 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2768 value &= ~(1ULL << 2);
2769 low = lower_32_bits(value);
2770 high = upper_32_bits(value);
2772 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2775 /* Flush tlb to evict multi-match entries */
2781 static void svm_handle_mce(struct vcpu_svm *svm)
2783 if (is_erratum_383()) {
2785 * Erratum 383 triggered. Guest state is corrupt so kill the
2788 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2790 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2796 * On an #MC intercept the MCE handler is not called automatically in
2797 * the host. So do it by hand here.
2801 /* not sure if we ever come back to this point */
2806 static int mc_interception(struct vcpu_svm *svm)
2811 static int shutdown_interception(struct vcpu_svm *svm)
2813 struct kvm_run *kvm_run = svm->vcpu.run;
2816 * VMCB is undefined after a SHUTDOWN intercept
2817 * so reinitialize it.
2819 clear_page(svm->vmcb);
2822 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2826 static int io_interception(struct vcpu_svm *svm)
2828 struct kvm_vcpu *vcpu = &svm->vcpu;
2829 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2830 int size, in, string;
2833 ++svm->vcpu.stat.io_exits;
2834 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2835 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2837 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2839 port = io_info >> 16;
2840 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2841 svm->next_rip = svm->vmcb->control.exit_info_2;
2843 return kvm_fast_pio(&svm->vcpu, size, port, in);
2846 static int nmi_interception(struct vcpu_svm *svm)
2851 static int intr_interception(struct vcpu_svm *svm)
2853 ++svm->vcpu.stat.irq_exits;
2857 static int nop_on_interception(struct vcpu_svm *svm)
2862 static int halt_interception(struct vcpu_svm *svm)
2864 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2865 return kvm_emulate_halt(&svm->vcpu);
2868 static int vmmcall_interception(struct vcpu_svm *svm)
2870 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2871 return kvm_emulate_hypercall(&svm->vcpu);
2874 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2876 struct vcpu_svm *svm = to_svm(vcpu);
2878 return svm->nested.nested_cr3;
2881 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2883 struct vcpu_svm *svm = to_svm(vcpu);
2884 u64 cr3 = svm->nested.nested_cr3;
2888 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2889 offset_in_page(cr3) + index * 8, 8);
2895 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2898 struct vcpu_svm *svm = to_svm(vcpu);
2900 svm->vmcb->control.nested_cr3 = __sme_set(root);
2901 mark_dirty(svm->vmcb, VMCB_NPT);
2904 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2905 struct x86_exception *fault)
2907 struct vcpu_svm *svm = to_svm(vcpu);
2909 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2911 * TODO: track the cause of the nested page fault, and
2912 * correctly fill in the high bits of exit_info_1.
2914 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2915 svm->vmcb->control.exit_code_hi = 0;
2916 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2917 svm->vmcb->control.exit_info_2 = fault->address;
2920 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2921 svm->vmcb->control.exit_info_1 |= fault->error_code;
2924 * The present bit is always zero for page structure faults on real
2927 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2928 svm->vmcb->control.exit_info_1 &= ~1;
2930 nested_svm_vmexit(svm);
2933 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2935 WARN_ON(mmu_is_nested(vcpu));
2936 kvm_init_shadow_mmu(vcpu);
2937 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
2938 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
2939 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
2940 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2941 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2942 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2943 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2946 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2948 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2951 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2953 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2954 !is_paging(&svm->vcpu)) {
2955 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2959 if (svm->vmcb->save.cpl) {
2960 kvm_inject_gp(&svm->vcpu, 0);
2967 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2968 bool has_error_code, u32 error_code)
2972 if (!is_guest_mode(&svm->vcpu))
2975 vmexit = nested_svm_intercept(svm);
2976 if (vmexit != NESTED_EXIT_DONE)
2979 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2980 svm->vmcb->control.exit_code_hi = 0;
2981 svm->vmcb->control.exit_info_1 = error_code;
2984 * EXITINFO2 is undefined for all exception intercepts other
2987 if (svm->vcpu.arch.exception.nested_apf)
2988 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2989 else if (svm->vcpu.arch.exception.has_payload)
2990 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
2992 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2994 svm->nested.exit_required = true;
2998 /* This function returns true if it is save to enable the irq window */
2999 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3001 if (!is_guest_mode(&svm->vcpu))
3004 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3007 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3011 * if vmexit was already requested (by intercepted exception
3012 * for instance) do not overwrite it with "external interrupt"
3015 if (svm->nested.exit_required)
3018 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3019 svm->vmcb->control.exit_info_1 = 0;
3020 svm->vmcb->control.exit_info_2 = 0;
3022 if (svm->nested.intercept & 1ULL) {
3024 * The #vmexit can't be emulated here directly because this
3025 * code path runs with irqs and preemption disabled. A
3026 * #vmexit emulation might sleep. Only signal request for
3029 svm->nested.exit_required = true;
3030 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3037 /* This function returns true if it is save to enable the nmi window */
3038 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3040 if (!is_guest_mode(&svm->vcpu))
3043 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3046 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3047 svm->nested.exit_required = true;
3052 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3058 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3059 if (is_error_page(page))
3067 kvm_inject_gp(&svm->vcpu, 0);
3072 static void nested_svm_unmap(struct page *page)
3075 kvm_release_page_dirty(page);
3078 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3080 unsigned port, size, iopm_len;
3085 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3086 return NESTED_EXIT_HOST;
3088 port = svm->vmcb->control.exit_info_1 >> 16;
3089 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3090 SVM_IOIO_SIZE_SHIFT;
3091 gpa = svm->nested.vmcb_iopm + (port / 8);
3092 start_bit = port % 8;
3093 iopm_len = (start_bit + size > 8) ? 2 : 1;
3094 mask = (0xf >> (4 - size)) << start_bit;
3097 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3098 return NESTED_EXIT_DONE;
3100 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3103 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3105 u32 offset, msr, value;
3108 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3109 return NESTED_EXIT_HOST;
3111 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3112 offset = svm_msrpm_offset(msr);
3113 write = svm->vmcb->control.exit_info_1 & 1;
3114 mask = 1 << ((2 * (msr & 0xf)) + write);
3116 if (offset == MSR_INVALID)
3117 return NESTED_EXIT_DONE;
3119 /* Offset is in 32 bit units but need in 8 bit units */
3122 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3123 return NESTED_EXIT_DONE;
3125 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3128 /* DB exceptions for our internal use must not cause vmexit */
3129 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3133 /* if we're not singlestepping, it's not ours */
3134 if (!svm->nmi_singlestep)
3135 return NESTED_EXIT_DONE;
3137 /* if it's not a singlestep exception, it's not ours */
3138 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3139 return NESTED_EXIT_DONE;
3140 if (!(dr6 & DR6_BS))
3141 return NESTED_EXIT_DONE;
3143 /* if the guest is singlestepping, it should get the vmexit */
3144 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3145 disable_nmi_singlestep(svm);
3146 return NESTED_EXIT_DONE;
3149 /* it's ours, the nested hypervisor must not see this one */
3150 return NESTED_EXIT_HOST;
3153 static int nested_svm_exit_special(struct vcpu_svm *svm)
3155 u32 exit_code = svm->vmcb->control.exit_code;
3157 switch (exit_code) {
3160 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3161 return NESTED_EXIT_HOST;
3163 /* For now we are always handling NPFs when using them */
3165 return NESTED_EXIT_HOST;
3167 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3168 /* When we're shadowing, trap PFs, but not async PF */
3169 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3170 return NESTED_EXIT_HOST;
3176 return NESTED_EXIT_CONTINUE;
3180 * If this function returns true, this #vmexit was already handled
3182 static int nested_svm_intercept(struct vcpu_svm *svm)
3184 u32 exit_code = svm->vmcb->control.exit_code;
3185 int vmexit = NESTED_EXIT_HOST;
3187 switch (exit_code) {
3189 vmexit = nested_svm_exit_handled_msr(svm);
3192 vmexit = nested_svm_intercept_ioio(svm);
3194 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3195 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3196 if (svm->nested.intercept_cr & bit)
3197 vmexit = NESTED_EXIT_DONE;
3200 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3201 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3202 if (svm->nested.intercept_dr & bit)
3203 vmexit = NESTED_EXIT_DONE;
3206 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3207 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3208 if (svm->nested.intercept_exceptions & excp_bits) {
3209 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3210 vmexit = nested_svm_intercept_db(svm);
3212 vmexit = NESTED_EXIT_DONE;
3214 /* async page fault always cause vmexit */
3215 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3216 svm->vcpu.arch.exception.nested_apf != 0)
3217 vmexit = NESTED_EXIT_DONE;
3220 case SVM_EXIT_ERR: {
3221 vmexit = NESTED_EXIT_DONE;
3225 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3226 if (svm->nested.intercept & exit_bits)
3227 vmexit = NESTED_EXIT_DONE;
3234 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3238 vmexit = nested_svm_intercept(svm);
3240 if (vmexit == NESTED_EXIT_DONE)
3241 nested_svm_vmexit(svm);
3246 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3248 struct vmcb_control_area *dst = &dst_vmcb->control;
3249 struct vmcb_control_area *from = &from_vmcb->control;
3251 dst->intercept_cr = from->intercept_cr;
3252 dst->intercept_dr = from->intercept_dr;
3253 dst->intercept_exceptions = from->intercept_exceptions;
3254 dst->intercept = from->intercept;
3255 dst->iopm_base_pa = from->iopm_base_pa;
3256 dst->msrpm_base_pa = from->msrpm_base_pa;
3257 dst->tsc_offset = from->tsc_offset;
3258 dst->asid = from->asid;
3259 dst->tlb_ctl = from->tlb_ctl;
3260 dst->int_ctl = from->int_ctl;
3261 dst->int_vector = from->int_vector;
3262 dst->int_state = from->int_state;
3263 dst->exit_code = from->exit_code;
3264 dst->exit_code_hi = from->exit_code_hi;
3265 dst->exit_info_1 = from->exit_info_1;
3266 dst->exit_info_2 = from->exit_info_2;
3267 dst->exit_int_info = from->exit_int_info;
3268 dst->exit_int_info_err = from->exit_int_info_err;
3269 dst->nested_ctl = from->nested_ctl;
3270 dst->event_inj = from->event_inj;
3271 dst->event_inj_err = from->event_inj_err;
3272 dst->nested_cr3 = from->nested_cr3;
3273 dst->virt_ext = from->virt_ext;
3276 static int nested_svm_vmexit(struct vcpu_svm *svm)
3278 struct vmcb *nested_vmcb;
3279 struct vmcb *hsave = svm->nested.hsave;
3280 struct vmcb *vmcb = svm->vmcb;
3283 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3284 vmcb->control.exit_info_1,
3285 vmcb->control.exit_info_2,
3286 vmcb->control.exit_int_info,
3287 vmcb->control.exit_int_info_err,
3290 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3294 /* Exit Guest-Mode */
3295 leave_guest_mode(&svm->vcpu);
3296 svm->nested.vmcb = 0;
3298 /* Give the current vmcb to the guest */
3301 nested_vmcb->save.es = vmcb->save.es;
3302 nested_vmcb->save.cs = vmcb->save.cs;
3303 nested_vmcb->save.ss = vmcb->save.ss;
3304 nested_vmcb->save.ds = vmcb->save.ds;
3305 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3306 nested_vmcb->save.idtr = vmcb->save.idtr;
3307 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3308 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3309 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3310 nested_vmcb->save.cr2 = vmcb->save.cr2;
3311 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3312 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3313 nested_vmcb->save.rip = vmcb->save.rip;
3314 nested_vmcb->save.rsp = vmcb->save.rsp;
3315 nested_vmcb->save.rax = vmcb->save.rax;
3316 nested_vmcb->save.dr7 = vmcb->save.dr7;
3317 nested_vmcb->save.dr6 = vmcb->save.dr6;
3318 nested_vmcb->save.cpl = vmcb->save.cpl;
3320 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3321 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3322 nested_vmcb->control.int_state = vmcb->control.int_state;
3323 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3324 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3325 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3326 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3327 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3328 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3330 if (svm->nrips_enabled)
3331 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3334 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3335 * to make sure that we do not lose injected events. So check event_inj
3336 * here and copy it to exit_int_info if it is valid.
3337 * Exit_int_info and event_inj can't be both valid because the case
3338 * below only happens on a VMRUN instruction intercept which has
3339 * no valid exit_int_info set.
3341 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3342 struct vmcb_control_area *nc = &nested_vmcb->control;
3344 nc->exit_int_info = vmcb->control.event_inj;
3345 nc->exit_int_info_err = vmcb->control.event_inj_err;
3348 nested_vmcb->control.tlb_ctl = 0;
3349 nested_vmcb->control.event_inj = 0;
3350 nested_vmcb->control.event_inj_err = 0;
3352 /* We always set V_INTR_MASKING and remember the old value in hflags */
3353 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3354 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3356 /* Restore the original control entries */
3357 copy_vmcb_control_area(vmcb, hsave);
3359 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3360 kvm_clear_exception_queue(&svm->vcpu);
3361 kvm_clear_interrupt_queue(&svm->vcpu);
3363 svm->nested.nested_cr3 = 0;
3365 /* Restore selected save entries */
3366 svm->vmcb->save.es = hsave->save.es;
3367 svm->vmcb->save.cs = hsave->save.cs;
3368 svm->vmcb->save.ss = hsave->save.ss;
3369 svm->vmcb->save.ds = hsave->save.ds;
3370 svm->vmcb->save.gdtr = hsave->save.gdtr;
3371 svm->vmcb->save.idtr = hsave->save.idtr;
3372 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3373 svm_set_efer(&svm->vcpu, hsave->save.efer);
3374 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3375 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3377 svm->vmcb->save.cr3 = hsave->save.cr3;
3378 svm->vcpu.arch.cr3 = hsave->save.cr3;
3380 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3382 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3383 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3384 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3385 svm->vmcb->save.dr7 = 0;
3386 svm->vmcb->save.cpl = 0;
3387 svm->vmcb->control.exit_int_info = 0;
3389 mark_all_dirty(svm->vmcb);
3391 nested_svm_unmap(page);
3393 nested_svm_uninit_mmu_context(&svm->vcpu);
3394 kvm_mmu_reset_context(&svm->vcpu);
3395 kvm_mmu_load(&svm->vcpu);
3400 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3403 * This function merges the msr permission bitmaps of kvm and the
3404 * nested vmcb. It is optimized in that it only merges the parts where
3405 * the kvm msr permission bitmap may contain zero bits
3409 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3412 for (i = 0; i < MSRPM_OFFSETS; i++) {
3416 if (msrpm_offsets[i] == 0xffffffff)
3419 p = msrpm_offsets[i];
3420 offset = svm->nested.vmcb_msrpm + (p * 4);
3422 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3425 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3428 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3433 static bool nested_vmcb_checks(struct vmcb *vmcb)
3435 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3438 if (vmcb->control.asid == 0)
3441 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3448 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3449 struct vmcb *nested_vmcb, struct page *page)
3451 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3452 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3454 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3456 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3457 kvm_mmu_unload(&svm->vcpu);
3458 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3459 nested_svm_init_mmu_context(&svm->vcpu);
3462 /* Load the nested guest state */
3463 svm->vmcb->save.es = nested_vmcb->save.es;
3464 svm->vmcb->save.cs = nested_vmcb->save.cs;
3465 svm->vmcb->save.ss = nested_vmcb->save.ss;
3466 svm->vmcb->save.ds = nested_vmcb->save.ds;
3467 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3468 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3469 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3470 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3471 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3472 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3474 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3475 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3477 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3479 /* Guest paging mode is active - reset mmu */
3480 kvm_mmu_reset_context(&svm->vcpu);
3482 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3483 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3484 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3485 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3487 /* In case we don't even reach vcpu_run, the fields are not updated */
3488 svm->vmcb->save.rax = nested_vmcb->save.rax;
3489 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3490 svm->vmcb->save.rip = nested_vmcb->save.rip;
3491 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3492 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3493 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3495 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3496 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3498 /* cache intercepts */
3499 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3500 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3501 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3502 svm->nested.intercept = nested_vmcb->control.intercept;
3504 svm_flush_tlb(&svm->vcpu, true);
3505 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3506 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3507 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3509 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3511 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3512 /* We only want the cr8 intercept bits of the guest */
3513 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3514 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3517 /* We don't want to see VMMCALLs from a nested guest */
3518 clr_intercept(svm, INTERCEPT_VMMCALL);
3520 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3521 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3523 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3524 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3525 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3526 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3527 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3529 nested_svm_unmap(page);
3531 /* Enter Guest-Mode */
3532 enter_guest_mode(&svm->vcpu);
3535 * Merge guest and host intercepts - must be called with vcpu in
3536 * guest-mode to take affect here
3538 recalc_intercepts(svm);
3540 svm->nested.vmcb = vmcb_gpa;
3544 mark_all_dirty(svm->vmcb);
3547 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3549 struct vmcb *nested_vmcb;
3550 struct vmcb *hsave = svm->nested.hsave;
3551 struct vmcb *vmcb = svm->vmcb;
3555 vmcb_gpa = svm->vmcb->save.rax;
3557 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3561 if (!nested_vmcb_checks(nested_vmcb)) {
3562 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3563 nested_vmcb->control.exit_code_hi = 0;
3564 nested_vmcb->control.exit_info_1 = 0;
3565 nested_vmcb->control.exit_info_2 = 0;
3567 nested_svm_unmap(page);
3572 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3573 nested_vmcb->save.rip,
3574 nested_vmcb->control.int_ctl,
3575 nested_vmcb->control.event_inj,
3576 nested_vmcb->control.nested_ctl);
3578 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3579 nested_vmcb->control.intercept_cr >> 16,
3580 nested_vmcb->control.intercept_exceptions,
3581 nested_vmcb->control.intercept);
3583 /* Clear internal status */
3584 kvm_clear_exception_queue(&svm->vcpu);
3585 kvm_clear_interrupt_queue(&svm->vcpu);
3588 * Save the old vmcb, so we don't need to pick what we save, but can
3589 * restore everything when a VMEXIT occurs
3591 hsave->save.es = vmcb->save.es;
3592 hsave->save.cs = vmcb->save.cs;
3593 hsave->save.ss = vmcb->save.ss;
3594 hsave->save.ds = vmcb->save.ds;
3595 hsave->save.gdtr = vmcb->save.gdtr;
3596 hsave->save.idtr = vmcb->save.idtr;
3597 hsave->save.efer = svm->vcpu.arch.efer;
3598 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3599 hsave->save.cr4 = svm->vcpu.arch.cr4;
3600 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3601 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3602 hsave->save.rsp = vmcb->save.rsp;
3603 hsave->save.rax = vmcb->save.rax;
3605 hsave->save.cr3 = vmcb->save.cr3;
3607 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3609 copy_vmcb_control_area(hsave, vmcb);
3611 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3616 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3618 to_vmcb->save.fs = from_vmcb->save.fs;
3619 to_vmcb->save.gs = from_vmcb->save.gs;
3620 to_vmcb->save.tr = from_vmcb->save.tr;
3621 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3622 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3623 to_vmcb->save.star = from_vmcb->save.star;
3624 to_vmcb->save.lstar = from_vmcb->save.lstar;
3625 to_vmcb->save.cstar = from_vmcb->save.cstar;
3626 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3627 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3628 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3629 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3632 static int vmload_interception(struct vcpu_svm *svm)
3634 struct vmcb *nested_vmcb;
3638 if (nested_svm_check_permissions(svm))
3641 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3645 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3646 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3648 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3649 nested_svm_unmap(page);
3654 static int vmsave_interception(struct vcpu_svm *svm)
3656 struct vmcb *nested_vmcb;
3660 if (nested_svm_check_permissions(svm))
3663 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3667 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3668 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3670 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3671 nested_svm_unmap(page);
3676 static int vmrun_interception(struct vcpu_svm *svm)
3678 if (nested_svm_check_permissions(svm))
3681 /* Save rip after vmrun instruction */
3682 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3684 if (!nested_svm_vmrun(svm))
3687 if (!nested_svm_vmrun_msrpm(svm))
3694 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3695 svm->vmcb->control.exit_code_hi = 0;
3696 svm->vmcb->control.exit_info_1 = 0;
3697 svm->vmcb->control.exit_info_2 = 0;
3699 nested_svm_vmexit(svm);
3704 static int stgi_interception(struct vcpu_svm *svm)
3708 if (nested_svm_check_permissions(svm))
3712 * If VGIF is enabled, the STGI intercept is only added to
3713 * detect the opening of the SMI/NMI window; remove it now.
3715 if (vgif_enabled(svm))
3716 clr_intercept(svm, INTERCEPT_STGI);
3718 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3719 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3720 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3727 static int clgi_interception(struct vcpu_svm *svm)
3731 if (nested_svm_check_permissions(svm))
3734 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3735 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3739 /* After a CLGI no interrupts should come */
3740 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3741 svm_clear_vintr(svm);
3742 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3743 mark_dirty(svm->vmcb, VMCB_INTR);
3749 static int invlpga_interception(struct vcpu_svm *svm)
3751 struct kvm_vcpu *vcpu = &svm->vcpu;
3753 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3754 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3756 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3757 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3759 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3760 return kvm_skip_emulated_instruction(&svm->vcpu);
3763 static int skinit_interception(struct vcpu_svm *svm)
3765 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3767 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3771 static int wbinvd_interception(struct vcpu_svm *svm)
3773 return kvm_emulate_wbinvd(&svm->vcpu);
3776 static int xsetbv_interception(struct vcpu_svm *svm)
3778 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3779 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3781 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3782 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3783 return kvm_skip_emulated_instruction(&svm->vcpu);
3789 static int task_switch_interception(struct vcpu_svm *svm)
3793 int int_type = svm->vmcb->control.exit_int_info &
3794 SVM_EXITINTINFO_TYPE_MASK;
3795 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3797 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3799 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3800 bool has_error_code = false;
3803 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3805 if (svm->vmcb->control.exit_info_2 &
3806 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3807 reason = TASK_SWITCH_IRET;
3808 else if (svm->vmcb->control.exit_info_2 &
3809 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3810 reason = TASK_SWITCH_JMP;
3812 reason = TASK_SWITCH_GATE;
3814 reason = TASK_SWITCH_CALL;
3816 if (reason == TASK_SWITCH_GATE) {
3818 case SVM_EXITINTINFO_TYPE_NMI:
3819 svm->vcpu.arch.nmi_injected = false;
3821 case SVM_EXITINTINFO_TYPE_EXEPT:
3822 if (svm->vmcb->control.exit_info_2 &
3823 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3824 has_error_code = true;
3826 (u32)svm->vmcb->control.exit_info_2;
3828 kvm_clear_exception_queue(&svm->vcpu);
3830 case SVM_EXITINTINFO_TYPE_INTR:
3831 kvm_clear_interrupt_queue(&svm->vcpu);
3838 if (reason != TASK_SWITCH_GATE ||
3839 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3840 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3841 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3842 skip_emulated_instruction(&svm->vcpu);
3844 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3847 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3848 has_error_code, error_code) == EMULATE_FAIL) {
3849 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3850 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3851 svm->vcpu.run->internal.ndata = 0;
3857 static int cpuid_interception(struct vcpu_svm *svm)
3859 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3860 return kvm_emulate_cpuid(&svm->vcpu);
3863 static int iret_interception(struct vcpu_svm *svm)
3865 ++svm->vcpu.stat.nmi_window_exits;
3866 clr_intercept(svm, INTERCEPT_IRET);
3867 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3868 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3869 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3873 static int invlpg_interception(struct vcpu_svm *svm)
3875 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3876 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3878 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3879 return kvm_skip_emulated_instruction(&svm->vcpu);
3882 static int emulate_on_interception(struct vcpu_svm *svm)
3884 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3887 static int rsm_interception(struct vcpu_svm *svm)
3889 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3890 rsm_ins_bytes, 2) == EMULATE_DONE;
3893 static int rdpmc_interception(struct vcpu_svm *svm)
3897 if (!static_cpu_has(X86_FEATURE_NRIPS))
3898 return emulate_on_interception(svm);
3900 err = kvm_rdpmc(&svm->vcpu);
3901 return kvm_complete_insn_gp(&svm->vcpu, err);
3904 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3907 unsigned long cr0 = svm->vcpu.arch.cr0;
3911 intercept = svm->nested.intercept;
3913 if (!is_guest_mode(&svm->vcpu) ||
3914 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3917 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3918 val &= ~SVM_CR0_SELECTIVE_MASK;
3921 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3922 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3928 #define CR_VALID (1ULL << 63)
3930 static int cr_interception(struct vcpu_svm *svm)
3936 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3937 return emulate_on_interception(svm);
3939 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3940 return emulate_on_interception(svm);
3942 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3943 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3944 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3946 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3949 if (cr >= 16) { /* mov to cr */
3951 val = kvm_register_read(&svm->vcpu, reg);
3954 if (!check_selective_cr0_intercepted(svm, val))
3955 err = kvm_set_cr0(&svm->vcpu, val);
3961 err = kvm_set_cr3(&svm->vcpu, val);
3964 err = kvm_set_cr4(&svm->vcpu, val);
3967 err = kvm_set_cr8(&svm->vcpu, val);
3970 WARN(1, "unhandled write to CR%d", cr);
3971 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3974 } else { /* mov from cr */
3977 val = kvm_read_cr0(&svm->vcpu);
3980 val = svm->vcpu.arch.cr2;
3983 val = kvm_read_cr3(&svm->vcpu);
3986 val = kvm_read_cr4(&svm->vcpu);
3989 val = kvm_get_cr8(&svm->vcpu);
3992 WARN(1, "unhandled read from CR%d", cr);
3993 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3996 kvm_register_write(&svm->vcpu, reg, val);
3998 return kvm_complete_insn_gp(&svm->vcpu, err);
4001 static int dr_interception(struct vcpu_svm *svm)
4006 if (svm->vcpu.guest_debug == 0) {
4008 * No more DR vmexits; force a reload of the debug registers
4009 * and reenter on this instruction. The next vmexit will
4010 * retrieve the full state of the debug registers.
4012 clr_dr_intercepts(svm);
4013 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4017 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4018 return emulate_on_interception(svm);
4020 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4021 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4023 if (dr >= 16) { /* mov to DRn */
4024 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4026 val = kvm_register_read(&svm->vcpu, reg);
4027 kvm_set_dr(&svm->vcpu, dr - 16, val);
4029 if (!kvm_require_dr(&svm->vcpu, dr))
4031 kvm_get_dr(&svm->vcpu, dr, &val);
4032 kvm_register_write(&svm->vcpu, reg, val);
4035 return kvm_skip_emulated_instruction(&svm->vcpu);
4038 static int cr8_write_interception(struct vcpu_svm *svm)
4040 struct kvm_run *kvm_run = svm->vcpu.run;
4043 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4044 /* instruction emulation calls kvm_set_cr8() */
4045 r = cr_interception(svm);
4046 if (lapic_in_kernel(&svm->vcpu))
4048 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4050 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4054 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4058 switch (msr->index) {
4059 case MSR_F10H_DECFG:
4060 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4061 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4070 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4072 struct vcpu_svm *svm = to_svm(vcpu);
4074 switch (msr_info->index) {
4076 msr_info->data = svm->vmcb->save.star;
4078 #ifdef CONFIG_X86_64
4080 msr_info->data = svm->vmcb->save.lstar;
4083 msr_info->data = svm->vmcb->save.cstar;
4085 case MSR_KERNEL_GS_BASE:
4086 msr_info->data = svm->vmcb->save.kernel_gs_base;
4088 case MSR_SYSCALL_MASK:
4089 msr_info->data = svm->vmcb->save.sfmask;
4092 case MSR_IA32_SYSENTER_CS:
4093 msr_info->data = svm->vmcb->save.sysenter_cs;
4095 case MSR_IA32_SYSENTER_EIP:
4096 msr_info->data = svm->sysenter_eip;
4098 case MSR_IA32_SYSENTER_ESP:
4099 msr_info->data = svm->sysenter_esp;
4102 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4104 msr_info->data = svm->tsc_aux;
4107 * Nobody will change the following 5 values in the VMCB so we can
4108 * safely return them on rdmsr. They will always be 0 until LBRV is
4111 case MSR_IA32_DEBUGCTLMSR:
4112 msr_info->data = svm->vmcb->save.dbgctl;
4114 case MSR_IA32_LASTBRANCHFROMIP:
4115 msr_info->data = svm->vmcb->save.br_from;
4117 case MSR_IA32_LASTBRANCHTOIP:
4118 msr_info->data = svm->vmcb->save.br_to;
4120 case MSR_IA32_LASTINTFROMIP:
4121 msr_info->data = svm->vmcb->save.last_excp_from;
4123 case MSR_IA32_LASTINTTOIP:
4124 msr_info->data = svm->vmcb->save.last_excp_to;
4126 case MSR_VM_HSAVE_PA:
4127 msr_info->data = svm->nested.hsave_msr;
4130 msr_info->data = svm->nested.vm_cr_msr;
4132 case MSR_IA32_SPEC_CTRL:
4133 if (!msr_info->host_initiated &&
4134 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4135 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4138 msr_info->data = svm->spec_ctrl;
4140 case MSR_AMD64_VIRT_SPEC_CTRL:
4141 if (!msr_info->host_initiated &&
4142 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4145 msr_info->data = svm->virt_spec_ctrl;
4147 case MSR_F15H_IC_CFG: {
4151 family = guest_cpuid_family(vcpu);
4152 model = guest_cpuid_model(vcpu);
4154 if (family < 0 || model < 0)
4155 return kvm_get_msr_common(vcpu, msr_info);
4159 if (family == 0x15 &&
4160 (model >= 0x2 && model < 0x20))
4161 msr_info->data = 0x1E;
4164 case MSR_F10H_DECFG:
4165 msr_info->data = svm->msr_decfg;
4168 return kvm_get_msr_common(vcpu, msr_info);
4173 static int rdmsr_interception(struct vcpu_svm *svm)
4175 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4176 struct msr_data msr_info;
4178 msr_info.index = ecx;
4179 msr_info.host_initiated = false;
4180 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4181 trace_kvm_msr_read_ex(ecx);
4182 kvm_inject_gp(&svm->vcpu, 0);
4185 trace_kvm_msr_read(ecx, msr_info.data);
4187 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4188 msr_info.data & 0xffffffff);
4189 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4190 msr_info.data >> 32);
4191 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4192 return kvm_skip_emulated_instruction(&svm->vcpu);
4196 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4198 struct vcpu_svm *svm = to_svm(vcpu);
4199 int svm_dis, chg_mask;
4201 if (data & ~SVM_VM_CR_VALID_MASK)
4204 chg_mask = SVM_VM_CR_VALID_MASK;
4206 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4207 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4209 svm->nested.vm_cr_msr &= ~chg_mask;
4210 svm->nested.vm_cr_msr |= (data & chg_mask);
4212 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4214 /* check for svm_disable while efer.svme is set */
4215 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4221 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4223 struct vcpu_svm *svm = to_svm(vcpu);
4225 u32 ecx = msr->index;
4226 u64 data = msr->data;
4228 case MSR_IA32_CR_PAT:
4229 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4231 vcpu->arch.pat = data;
4232 svm->vmcb->save.g_pat = data;
4233 mark_dirty(svm->vmcb, VMCB_NPT);
4235 case MSR_IA32_SPEC_CTRL:
4236 if (!msr->host_initiated &&
4237 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4238 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4241 /* The STIBP bit doesn't fault even if it's not advertised */
4242 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4245 svm->spec_ctrl = data;
4252 * When it's written (to non-zero) for the first time, pass
4256 * The handling of the MSR bitmap for L2 guests is done in
4257 * nested_svm_vmrun_msrpm.
4258 * We update the L1 MSR bit as well since it will end up
4259 * touching the MSR anyway now.
4261 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4263 case MSR_IA32_PRED_CMD:
4264 if (!msr->host_initiated &&
4265 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4268 if (data & ~PRED_CMD_IBPB)
4274 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4275 if (is_guest_mode(vcpu))
4277 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4279 case MSR_AMD64_VIRT_SPEC_CTRL:
4280 if (!msr->host_initiated &&
4281 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4284 if (data & ~SPEC_CTRL_SSBD)
4287 svm->virt_spec_ctrl = data;
4290 svm->vmcb->save.star = data;
4292 #ifdef CONFIG_X86_64
4294 svm->vmcb->save.lstar = data;
4297 svm->vmcb->save.cstar = data;
4299 case MSR_KERNEL_GS_BASE:
4300 svm->vmcb->save.kernel_gs_base = data;
4302 case MSR_SYSCALL_MASK:
4303 svm->vmcb->save.sfmask = data;
4306 case MSR_IA32_SYSENTER_CS:
4307 svm->vmcb->save.sysenter_cs = data;
4309 case MSR_IA32_SYSENTER_EIP:
4310 svm->sysenter_eip = data;
4311 svm->vmcb->save.sysenter_eip = data;
4313 case MSR_IA32_SYSENTER_ESP:
4314 svm->sysenter_esp = data;
4315 svm->vmcb->save.sysenter_esp = data;
4318 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4322 * This is rare, so we update the MSR here instead of using
4323 * direct_access_msrs. Doing that would require a rdmsr in
4326 svm->tsc_aux = data;
4327 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4329 case MSR_IA32_DEBUGCTLMSR:
4330 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4331 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4335 if (data & DEBUGCTL_RESERVED_BITS)
4338 svm->vmcb->save.dbgctl = data;
4339 mark_dirty(svm->vmcb, VMCB_LBR);
4340 if (data & (1ULL<<0))
4341 svm_enable_lbrv(svm);
4343 svm_disable_lbrv(svm);
4345 case MSR_VM_HSAVE_PA:
4346 svm->nested.hsave_msr = data;
4349 return svm_set_vm_cr(vcpu, data);
4351 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4353 case MSR_F10H_DECFG: {
4354 struct kvm_msr_entry msr_entry;
4356 msr_entry.index = msr->index;
4357 if (svm_get_msr_feature(&msr_entry))
4360 /* Check the supported bits */
4361 if (data & ~msr_entry.data)
4364 /* Don't allow the guest to change a bit, #GP */
4365 if (!msr->host_initiated && (data ^ msr_entry.data))
4368 svm->msr_decfg = data;
4371 case MSR_IA32_APICBASE:
4372 if (kvm_vcpu_apicv_active(vcpu))
4373 avic_update_vapic_bar(to_svm(vcpu), data);
4374 /* Follow through */
4376 return kvm_set_msr_common(vcpu, msr);
4381 static int wrmsr_interception(struct vcpu_svm *svm)
4383 struct msr_data msr;
4384 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4385 u64 data = kvm_read_edx_eax(&svm->vcpu);
4389 msr.host_initiated = false;
4391 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4392 if (kvm_set_msr(&svm->vcpu, &msr)) {
4393 trace_kvm_msr_write_ex(ecx, data);
4394 kvm_inject_gp(&svm->vcpu, 0);
4397 trace_kvm_msr_write(ecx, data);
4398 return kvm_skip_emulated_instruction(&svm->vcpu);
4402 static int msr_interception(struct vcpu_svm *svm)
4404 if (svm->vmcb->control.exit_info_1)
4405 return wrmsr_interception(svm);
4407 return rdmsr_interception(svm);
4410 static int interrupt_window_interception(struct vcpu_svm *svm)
4412 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4413 svm_clear_vintr(svm);
4414 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4415 mark_dirty(svm->vmcb, VMCB_INTR);
4416 ++svm->vcpu.stat.irq_window_exits;
4420 static int pause_interception(struct vcpu_svm *svm)
4422 struct kvm_vcpu *vcpu = &svm->vcpu;
4423 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4425 if (pause_filter_thresh)
4426 grow_ple_window(vcpu);
4428 kvm_vcpu_on_spin(vcpu, in_kernel);
4432 static int nop_interception(struct vcpu_svm *svm)
4434 return kvm_skip_emulated_instruction(&(svm->vcpu));
4437 static int monitor_interception(struct vcpu_svm *svm)
4439 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4440 return nop_interception(svm);
4443 static int mwait_interception(struct vcpu_svm *svm)
4445 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4446 return nop_interception(svm);
4449 enum avic_ipi_failure_cause {
4450 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4451 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4452 AVIC_IPI_FAILURE_INVALID_TARGET,
4453 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4456 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4458 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4459 u32 icrl = svm->vmcb->control.exit_info_1;
4460 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4461 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4462 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4464 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4467 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4469 * AVIC hardware handles the generation of
4470 * IPIs when the specified Message Type is Fixed
4471 * (also known as fixed delivery mode) and
4472 * the Trigger Mode is edge-triggered. The hardware
4473 * also supports self and broadcast delivery modes
4474 * specified via the Destination Shorthand(DSH)
4475 * field of the ICRL. Logical and physical APIC ID
4476 * formats are supported. All other IPI types cause
4477 * a #VMEXIT, which needs to emulated.
4479 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4480 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4482 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4484 struct kvm_vcpu *vcpu;
4485 struct kvm *kvm = svm->vcpu.kvm;
4486 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4489 * At this point, we expect that the AVIC HW has already
4490 * set the appropriate IRR bits on the valid target
4491 * vcpus. So, we just need to kick the appropriate vcpu.
4493 kvm_for_each_vcpu(i, vcpu, kvm) {
4494 bool m = kvm_apic_match_dest(vcpu, apic,
4495 icrl & KVM_APIC_SHORT_MASK,
4496 GET_APIC_DEST_FIELD(icrh),
4497 icrl & KVM_APIC_DEST_MASK);
4499 if (m && !avic_vcpu_is_running(vcpu))
4500 kvm_vcpu_wake_up(vcpu);
4504 case AVIC_IPI_FAILURE_INVALID_TARGET:
4506 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4507 WARN_ONCE(1, "Invalid backing page\n");
4510 pr_err("Unknown IPI interception\n");
4516 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4518 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4520 u32 *logical_apic_id_table;
4521 int dlid = GET_APIC_LOGICAL_ID(ldr);
4526 if (flat) { /* flat */
4527 index = ffs(dlid) - 1;
4530 } else { /* cluster */
4531 int cluster = (dlid & 0xf0) >> 4;
4532 int apic = ffs(dlid & 0x0f) - 1;
4534 if ((apic < 0) || (apic > 7) ||
4537 index = (cluster << 2) + apic;
4540 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4542 return &logical_apic_id_table[index];
4545 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4549 u32 *entry, new_entry;
4551 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4552 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4556 new_entry = READ_ONCE(*entry);
4557 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4558 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4560 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4562 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4563 WRITE_ONCE(*entry, new_entry);
4568 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4571 struct vcpu_svm *svm = to_svm(vcpu);
4572 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4577 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4578 if (ret && svm->ldr_reg) {
4579 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4587 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4590 struct vcpu_svm *svm = to_svm(vcpu);
4591 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4592 u32 id = (apic_id_reg >> 24) & 0xff;
4594 if (vcpu->vcpu_id == id)
4597 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4598 new = avic_get_physical_id_entry(vcpu, id);
4602 /* We need to move physical_id_entry to new offset */
4605 to_svm(vcpu)->avic_physical_id_cache = new;
4608 * Also update the guest physical APIC ID in the logical
4609 * APIC ID table entry if already setup the LDR.
4612 avic_handle_ldr_update(vcpu);
4617 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4619 struct vcpu_svm *svm = to_svm(vcpu);
4620 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4621 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4622 u32 mod = (dfr >> 28) & 0xf;
4625 * We assume that all local APICs are using the same type.
4626 * If this changes, we need to flush the AVIC logical
4629 if (kvm_svm->ldr_mode == mod)
4632 clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4633 kvm_svm->ldr_mode = mod;
4636 avic_handle_ldr_update(vcpu);
4640 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4642 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4643 u32 offset = svm->vmcb->control.exit_info_1 &
4644 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4648 if (avic_handle_apic_id_update(&svm->vcpu))
4652 if (avic_handle_ldr_update(&svm->vcpu))
4656 avic_handle_dfr_update(&svm->vcpu);
4662 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4667 static bool is_avic_unaccelerated_access_trap(u32 offset)
4696 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4699 u32 offset = svm->vmcb->control.exit_info_1 &
4700 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4701 u32 vector = svm->vmcb->control.exit_info_2 &
4702 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4703 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4704 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4705 bool trap = is_avic_unaccelerated_access_trap(offset);
4707 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4708 trap, write, vector);
4711 WARN_ONCE(!write, "svm: Handling trap read.\n");
4712 ret = avic_unaccel_trap_write(svm);
4714 /* Handling Fault */
4715 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4721 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4722 [SVM_EXIT_READ_CR0] = cr_interception,
4723 [SVM_EXIT_READ_CR3] = cr_interception,
4724 [SVM_EXIT_READ_CR4] = cr_interception,
4725 [SVM_EXIT_READ_CR8] = cr_interception,
4726 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4727 [SVM_EXIT_WRITE_CR0] = cr_interception,
4728 [SVM_EXIT_WRITE_CR3] = cr_interception,
4729 [SVM_EXIT_WRITE_CR4] = cr_interception,
4730 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4731 [SVM_EXIT_READ_DR0] = dr_interception,
4732 [SVM_EXIT_READ_DR1] = dr_interception,
4733 [SVM_EXIT_READ_DR2] = dr_interception,
4734 [SVM_EXIT_READ_DR3] = dr_interception,
4735 [SVM_EXIT_READ_DR4] = dr_interception,
4736 [SVM_EXIT_READ_DR5] = dr_interception,
4737 [SVM_EXIT_READ_DR6] = dr_interception,
4738 [SVM_EXIT_READ_DR7] = dr_interception,
4739 [SVM_EXIT_WRITE_DR0] = dr_interception,
4740 [SVM_EXIT_WRITE_DR1] = dr_interception,
4741 [SVM_EXIT_WRITE_DR2] = dr_interception,
4742 [SVM_EXIT_WRITE_DR3] = dr_interception,
4743 [SVM_EXIT_WRITE_DR4] = dr_interception,
4744 [SVM_EXIT_WRITE_DR5] = dr_interception,
4745 [SVM_EXIT_WRITE_DR6] = dr_interception,
4746 [SVM_EXIT_WRITE_DR7] = dr_interception,
4747 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4748 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4749 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4750 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4751 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4752 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4753 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4754 [SVM_EXIT_INTR] = intr_interception,
4755 [SVM_EXIT_NMI] = nmi_interception,
4756 [SVM_EXIT_SMI] = nop_on_interception,
4757 [SVM_EXIT_INIT] = nop_on_interception,
4758 [SVM_EXIT_VINTR] = interrupt_window_interception,
4759 [SVM_EXIT_RDPMC] = rdpmc_interception,
4760 [SVM_EXIT_CPUID] = cpuid_interception,
4761 [SVM_EXIT_IRET] = iret_interception,
4762 [SVM_EXIT_INVD] = emulate_on_interception,
4763 [SVM_EXIT_PAUSE] = pause_interception,
4764 [SVM_EXIT_HLT] = halt_interception,
4765 [SVM_EXIT_INVLPG] = invlpg_interception,
4766 [SVM_EXIT_INVLPGA] = invlpga_interception,
4767 [SVM_EXIT_IOIO] = io_interception,
4768 [SVM_EXIT_MSR] = msr_interception,
4769 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4770 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4771 [SVM_EXIT_VMRUN] = vmrun_interception,
4772 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4773 [SVM_EXIT_VMLOAD] = vmload_interception,
4774 [SVM_EXIT_VMSAVE] = vmsave_interception,
4775 [SVM_EXIT_STGI] = stgi_interception,
4776 [SVM_EXIT_CLGI] = clgi_interception,
4777 [SVM_EXIT_SKINIT] = skinit_interception,
4778 [SVM_EXIT_WBINVD] = wbinvd_interception,
4779 [SVM_EXIT_MONITOR] = monitor_interception,
4780 [SVM_EXIT_MWAIT] = mwait_interception,
4781 [SVM_EXIT_XSETBV] = xsetbv_interception,
4782 [SVM_EXIT_NPF] = npf_interception,
4783 [SVM_EXIT_RSM] = rsm_interception,
4784 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4785 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4788 static void dump_vmcb(struct kvm_vcpu *vcpu)
4790 struct vcpu_svm *svm = to_svm(vcpu);
4791 struct vmcb_control_area *control = &svm->vmcb->control;
4792 struct vmcb_save_area *save = &svm->vmcb->save;
4794 pr_err("VMCB Control Area:\n");
4795 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4796 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4797 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4798 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4799 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4800 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4801 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4802 pr_err("%-20s%d\n", "pause filter threshold:",
4803 control->pause_filter_thresh);
4804 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4805 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4806 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4807 pr_err("%-20s%d\n", "asid:", control->asid);
4808 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4809 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4810 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4811 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4812 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4813 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4814 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4815 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4816 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4817 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4818 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4819 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4820 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4821 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4822 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4823 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4824 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4825 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4826 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4827 pr_err("VMCB State Save Area:\n");
4828 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4830 save->es.selector, save->es.attrib,
4831 save->es.limit, save->es.base);
4832 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4834 save->cs.selector, save->cs.attrib,
4835 save->cs.limit, save->cs.base);
4836 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4838 save->ss.selector, save->ss.attrib,
4839 save->ss.limit, save->ss.base);
4840 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4842 save->ds.selector, save->ds.attrib,
4843 save->ds.limit, save->ds.base);
4844 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4846 save->fs.selector, save->fs.attrib,
4847 save->fs.limit, save->fs.base);
4848 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4850 save->gs.selector, save->gs.attrib,
4851 save->gs.limit, save->gs.base);
4852 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4854 save->gdtr.selector, save->gdtr.attrib,
4855 save->gdtr.limit, save->gdtr.base);
4856 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4858 save->ldtr.selector, save->ldtr.attrib,
4859 save->ldtr.limit, save->ldtr.base);
4860 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4862 save->idtr.selector, save->idtr.attrib,
4863 save->idtr.limit, save->idtr.base);
4864 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4866 save->tr.selector, save->tr.attrib,
4867 save->tr.limit, save->tr.base);
4868 pr_err("cpl: %d efer: %016llx\n",
4869 save->cpl, save->efer);
4870 pr_err("%-15s %016llx %-13s %016llx\n",
4871 "cr0:", save->cr0, "cr2:", save->cr2);
4872 pr_err("%-15s %016llx %-13s %016llx\n",
4873 "cr3:", save->cr3, "cr4:", save->cr4);
4874 pr_err("%-15s %016llx %-13s %016llx\n",
4875 "dr6:", save->dr6, "dr7:", save->dr7);
4876 pr_err("%-15s %016llx %-13s %016llx\n",
4877 "rip:", save->rip, "rflags:", save->rflags);
4878 pr_err("%-15s %016llx %-13s %016llx\n",
4879 "rsp:", save->rsp, "rax:", save->rax);
4880 pr_err("%-15s %016llx %-13s %016llx\n",
4881 "star:", save->star, "lstar:", save->lstar);
4882 pr_err("%-15s %016llx %-13s %016llx\n",
4883 "cstar:", save->cstar, "sfmask:", save->sfmask);
4884 pr_err("%-15s %016llx %-13s %016llx\n",
4885 "kernel_gs_base:", save->kernel_gs_base,
4886 "sysenter_cs:", save->sysenter_cs);
4887 pr_err("%-15s %016llx %-13s %016llx\n",
4888 "sysenter_esp:", save->sysenter_esp,
4889 "sysenter_eip:", save->sysenter_eip);
4890 pr_err("%-15s %016llx %-13s %016llx\n",
4891 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4892 pr_err("%-15s %016llx %-13s %016llx\n",
4893 "br_from:", save->br_from, "br_to:", save->br_to);
4894 pr_err("%-15s %016llx %-13s %016llx\n",
4895 "excp_from:", save->last_excp_from,
4896 "excp_to:", save->last_excp_to);
4899 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4901 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4903 *info1 = control->exit_info_1;
4904 *info2 = control->exit_info_2;
4907 static int handle_exit(struct kvm_vcpu *vcpu)
4909 struct vcpu_svm *svm = to_svm(vcpu);
4910 struct kvm_run *kvm_run = vcpu->run;
4911 u32 exit_code = svm->vmcb->control.exit_code;
4913 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4915 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4916 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4918 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4920 if (unlikely(svm->nested.exit_required)) {
4921 nested_svm_vmexit(svm);
4922 svm->nested.exit_required = false;
4927 if (is_guest_mode(vcpu)) {
4930 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4931 svm->vmcb->control.exit_info_1,
4932 svm->vmcb->control.exit_info_2,
4933 svm->vmcb->control.exit_int_info,
4934 svm->vmcb->control.exit_int_info_err,
4937 vmexit = nested_svm_exit_special(svm);
4939 if (vmexit == NESTED_EXIT_CONTINUE)
4940 vmexit = nested_svm_exit_handled(svm);
4942 if (vmexit == NESTED_EXIT_DONE)
4946 svm_complete_interrupts(svm);
4948 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4949 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4950 kvm_run->fail_entry.hardware_entry_failure_reason
4951 = svm->vmcb->control.exit_code;
4952 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4957 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4958 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4959 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4960 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4961 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4963 __func__, svm->vmcb->control.exit_int_info,
4966 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4967 || !svm_exit_handlers[exit_code]) {
4968 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4969 kvm_queue_exception(vcpu, UD_VECTOR);
4973 return svm_exit_handlers[exit_code](svm);
4976 static void reload_tss(struct kvm_vcpu *vcpu)
4978 int cpu = raw_smp_processor_id();
4980 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4981 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4985 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4987 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4988 int asid = sev_get_asid(svm->vcpu.kvm);
4990 /* Assign the asid allocated with this SEV guest */
4991 svm->vmcb->control.asid = asid;
4996 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4997 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4999 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5000 svm->last_cpu == cpu)
5003 svm->last_cpu = cpu;
5004 sd->sev_vmcbs[asid] = svm->vmcb;
5005 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5006 mark_dirty(svm->vmcb, VMCB_ASID);
5009 static void pre_svm_run(struct vcpu_svm *svm)
5011 int cpu = raw_smp_processor_id();
5013 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5015 if (sev_guest(svm->vcpu.kvm))
5016 return pre_sev_run(svm, cpu);
5018 /* FIXME: handle wraparound of asid_generation */
5019 if (svm->asid_generation != sd->asid_generation)
5023 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5025 struct vcpu_svm *svm = to_svm(vcpu);
5027 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5028 vcpu->arch.hflags |= HF_NMI_MASK;
5029 set_intercept(svm, INTERCEPT_IRET);
5030 ++vcpu->stat.nmi_injections;
5033 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5035 struct vmcb_control_area *control;
5037 /* The following fields are ignored when AVIC is enabled */
5038 control = &svm->vmcb->control;
5039 control->int_vector = irq;
5040 control->int_ctl &= ~V_INTR_PRIO_MASK;
5041 control->int_ctl |= V_IRQ_MASK |
5042 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5043 mark_dirty(svm->vmcb, VMCB_INTR);
5046 static void svm_set_irq(struct kvm_vcpu *vcpu)
5048 struct vcpu_svm *svm = to_svm(vcpu);
5050 BUG_ON(!(gif_set(svm)));
5052 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5053 ++vcpu->stat.irq_injections;
5055 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5056 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5059 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5061 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5064 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5066 struct vcpu_svm *svm = to_svm(vcpu);
5068 if (svm_nested_virtualize_tpr(vcpu) ||
5069 kvm_vcpu_apicv_active(vcpu))
5072 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5078 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5081 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5086 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5088 return avic && irqchip_split(vcpu->kvm);
5091 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5095 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5099 /* Note: Currently only used by Hyper-V. */
5100 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5102 struct vcpu_svm *svm = to_svm(vcpu);
5103 struct vmcb *vmcb = svm->vmcb;
5105 if (!kvm_vcpu_apicv_active(&svm->vcpu))
5108 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5109 mark_dirty(vmcb, VMCB_INTR);
5112 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5117 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5119 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5120 smp_mb__after_atomic();
5122 if (avic_vcpu_is_running(vcpu))
5123 wrmsrl(SVM_AVIC_DOORBELL,
5124 kvm_cpu_get_apicid(vcpu->cpu));
5126 kvm_vcpu_wake_up(vcpu);
5129 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5131 unsigned long flags;
5132 struct amd_svm_iommu_ir *cur;
5134 spin_lock_irqsave(&svm->ir_list_lock, flags);
5135 list_for_each_entry(cur, &svm->ir_list, node) {
5136 if (cur->data != pi->ir_data)
5138 list_del(&cur->node);
5142 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5145 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5148 unsigned long flags;
5149 struct amd_svm_iommu_ir *ir;
5152 * In some cases, the existing irte is updaed and re-set,
5153 * so we need to check here if it's already been * added
5156 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5157 struct kvm *kvm = svm->vcpu.kvm;
5158 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5159 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5160 struct vcpu_svm *prev_svm;
5167 prev_svm = to_svm(prev_vcpu);
5168 svm_ir_list_del(prev_svm, pi);
5172 * Allocating new amd_iommu_pi_data, which will get
5173 * add to the per-vcpu ir_list.
5175 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5180 ir->data = pi->ir_data;
5182 spin_lock_irqsave(&svm->ir_list_lock, flags);
5183 list_add(&ir->node, &svm->ir_list);
5184 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5191 * The HW cannot support posting multicast/broadcast
5192 * interrupts to a vCPU. So, we still use legacy interrupt
5193 * remapping for these kind of interrupts.
5195 * For lowest-priority interrupts, we only support
5196 * those with single CPU as the destination, e.g. user
5197 * configures the interrupts via /proc/irq or uses
5198 * irqbalance to make the interrupts single-CPU.
5201 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5202 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5204 struct kvm_lapic_irq irq;
5205 struct kvm_vcpu *vcpu = NULL;
5207 kvm_set_msi_irq(kvm, e, &irq);
5209 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5210 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5211 __func__, irq.vector);
5215 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5217 *svm = to_svm(vcpu);
5218 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5219 vcpu_info->vector = irq.vector;
5225 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5228 * @host_irq: host irq of the interrupt
5229 * @guest_irq: gsi of the interrupt
5230 * @set: set or unset PI
5231 * returns 0 on success, < 0 on failure
5233 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5234 uint32_t guest_irq, bool set)
5236 struct kvm_kernel_irq_routing_entry *e;
5237 struct kvm_irq_routing_table *irq_rt;
5238 int idx, ret = -EINVAL;
5240 if (!kvm_arch_has_assigned_device(kvm) ||
5241 !irq_remapping_cap(IRQ_POSTING_CAP))
5244 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5245 __func__, host_irq, guest_irq, set);
5247 idx = srcu_read_lock(&kvm->irq_srcu);
5248 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5249 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5251 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5252 struct vcpu_data vcpu_info;
5253 struct vcpu_svm *svm = NULL;
5255 if (e->type != KVM_IRQ_ROUTING_MSI)
5259 * Here, we setup with legacy mode in the following cases:
5260 * 1. When cannot target interrupt to a specific vcpu.
5261 * 2. Unsetting posted interrupt.
5262 * 3. APIC virtialization is disabled for the vcpu.
5264 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5265 kvm_vcpu_apicv_active(&svm->vcpu)) {
5266 struct amd_iommu_pi_data pi;
5268 /* Try to enable guest_mode in IRTE */
5269 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5271 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5273 pi.is_guest_mode = true;
5274 pi.vcpu_data = &vcpu_info;
5275 ret = irq_set_vcpu_affinity(host_irq, &pi);
5278 * Here, we successfully setting up vcpu affinity in
5279 * IOMMU guest mode. Now, we need to store the posted
5280 * interrupt information in a per-vcpu ir_list so that
5281 * we can reference to them directly when we update vcpu
5282 * scheduling information in IOMMU irte.
5284 if (!ret && pi.is_guest_mode)
5285 svm_ir_list_add(svm, &pi);
5287 /* Use legacy mode in IRTE */
5288 struct amd_iommu_pi_data pi;
5291 * Here, pi is used to:
5292 * - Tell IOMMU to use legacy mode for this interrupt.
5293 * - Retrieve ga_tag of prior interrupt remapping data.
5295 pi.is_guest_mode = false;
5296 ret = irq_set_vcpu_affinity(host_irq, &pi);
5299 * Check if the posted interrupt was previously
5300 * setup with the guest_mode by checking if the ga_tag
5301 * was cached. If so, we need to clean up the per-vcpu
5304 if (!ret && pi.prev_ga_tag) {
5305 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5306 struct kvm_vcpu *vcpu;
5308 vcpu = kvm_get_vcpu_by_id(kvm, id);
5310 svm_ir_list_del(to_svm(vcpu), &pi);
5315 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5316 e->gsi, vcpu_info.vector,
5317 vcpu_info.pi_desc_addr, set);
5321 pr_err("%s: failed to update PI IRTE\n", __func__);
5328 srcu_read_unlock(&kvm->irq_srcu, idx);
5332 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5334 struct vcpu_svm *svm = to_svm(vcpu);
5335 struct vmcb *vmcb = svm->vmcb;
5337 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5338 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5339 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5344 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5346 struct vcpu_svm *svm = to_svm(vcpu);
5348 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5351 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5353 struct vcpu_svm *svm = to_svm(vcpu);
5356 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5357 set_intercept(svm, INTERCEPT_IRET);
5359 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5360 clr_intercept(svm, INTERCEPT_IRET);
5364 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5366 struct vcpu_svm *svm = to_svm(vcpu);
5367 struct vmcb *vmcb = svm->vmcb;
5370 if (!gif_set(svm) ||
5371 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5374 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5376 if (is_guest_mode(vcpu))
5377 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5382 static void enable_irq_window(struct kvm_vcpu *vcpu)
5384 struct vcpu_svm *svm = to_svm(vcpu);
5386 if (kvm_vcpu_apicv_active(vcpu))
5390 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5391 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5392 * get that intercept, this function will be called again though and
5393 * we'll get the vintr intercept. However, if the vGIF feature is
5394 * enabled, the STGI interception will not occur. Enable the irq
5395 * window under the assumption that the hardware will set the GIF.
5397 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5399 svm_inject_irq(svm, 0x0);
5403 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5405 struct vcpu_svm *svm = to_svm(vcpu);
5407 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5409 return; /* IRET will cause a vm exit */
5411 if (!gif_set(svm)) {
5412 if (vgif_enabled(svm))
5413 set_intercept(svm, INTERCEPT_STGI);
5414 return; /* STGI will cause a vm exit */
5417 if (svm->nested.exit_required)
5418 return; /* we're not going to run the guest yet */
5421 * Something prevents NMI from been injected. Single step over possible
5422 * problem (IRET or exception injection or interrupt shadow)
5424 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5425 svm->nmi_singlestep = true;
5426 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5429 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5434 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5439 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5441 struct vcpu_svm *svm = to_svm(vcpu);
5443 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5444 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5446 svm->asid_generation--;
5449 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5451 struct vcpu_svm *svm = to_svm(vcpu);
5453 invlpga(gva, svm->vmcb->control.asid);
5456 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5460 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5462 struct vcpu_svm *svm = to_svm(vcpu);
5464 if (svm_nested_virtualize_tpr(vcpu))
5467 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5468 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5469 kvm_set_cr8(vcpu, cr8);
5473 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5475 struct vcpu_svm *svm = to_svm(vcpu);
5478 if (svm_nested_virtualize_tpr(vcpu) ||
5479 kvm_vcpu_apicv_active(vcpu))
5482 cr8 = kvm_get_cr8(vcpu);
5483 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5484 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5487 static void svm_complete_interrupts(struct vcpu_svm *svm)
5491 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5492 unsigned int3_injected = svm->int3_injected;
5494 svm->int3_injected = 0;
5497 * If we've made progress since setting HF_IRET_MASK, we've
5498 * executed an IRET and can allow NMI injection.
5500 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5501 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5502 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5503 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5506 svm->vcpu.arch.nmi_injected = false;
5507 kvm_clear_exception_queue(&svm->vcpu);
5508 kvm_clear_interrupt_queue(&svm->vcpu);
5510 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5513 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5515 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5516 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5519 case SVM_EXITINTINFO_TYPE_NMI:
5520 svm->vcpu.arch.nmi_injected = true;
5522 case SVM_EXITINTINFO_TYPE_EXEPT:
5524 * In case of software exceptions, do not reinject the vector,
5525 * but re-execute the instruction instead. Rewind RIP first
5526 * if we emulated INT3 before.
5528 if (kvm_exception_is_soft(vector)) {
5529 if (vector == BP_VECTOR && int3_injected &&
5530 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5531 kvm_rip_write(&svm->vcpu,
5532 kvm_rip_read(&svm->vcpu) -
5536 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5537 u32 err = svm->vmcb->control.exit_int_info_err;
5538 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5541 kvm_requeue_exception(&svm->vcpu, vector);
5543 case SVM_EXITINTINFO_TYPE_INTR:
5544 kvm_queue_interrupt(&svm->vcpu, vector, false);
5551 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5553 struct vcpu_svm *svm = to_svm(vcpu);
5554 struct vmcb_control_area *control = &svm->vmcb->control;
5556 control->exit_int_info = control->event_inj;
5557 control->exit_int_info_err = control->event_inj_err;
5558 control->event_inj = 0;
5559 svm_complete_interrupts(svm);
5562 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5564 struct vcpu_svm *svm = to_svm(vcpu);
5566 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5567 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5568 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5571 * A vmexit emulation is required before the vcpu can be executed
5574 if (unlikely(svm->nested.exit_required))
5578 * Disable singlestep if we're injecting an interrupt/exception.
5579 * We don't want our modified rflags to be pushed on the stack where
5580 * we might not be able to easily reset them if we disabled NMI
5583 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5585 * Event injection happens before external interrupts cause a
5586 * vmexit and interrupts are disabled here, so smp_send_reschedule
5587 * is enough to force an immediate vmexit.
5589 disable_nmi_singlestep(svm);
5590 smp_send_reschedule(vcpu->cpu);
5595 sync_lapic_to_cr8(vcpu);
5597 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5602 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5603 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5604 * is no need to worry about the conditional branch over the wrmsr
5605 * being speculatively taken.
5607 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5612 "push %%" _ASM_BP "; \n\t"
5613 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5614 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5615 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5616 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5617 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5618 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5619 #ifdef CONFIG_X86_64
5620 "mov %c[r8](%[svm]), %%r8 \n\t"
5621 "mov %c[r9](%[svm]), %%r9 \n\t"
5622 "mov %c[r10](%[svm]), %%r10 \n\t"
5623 "mov %c[r11](%[svm]), %%r11 \n\t"
5624 "mov %c[r12](%[svm]), %%r12 \n\t"
5625 "mov %c[r13](%[svm]), %%r13 \n\t"
5626 "mov %c[r14](%[svm]), %%r14 \n\t"
5627 "mov %c[r15](%[svm]), %%r15 \n\t"
5630 /* Enter guest mode */
5631 "push %%" _ASM_AX " \n\t"
5632 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5633 __ex(SVM_VMLOAD) "\n\t"
5634 __ex(SVM_VMRUN) "\n\t"
5635 __ex(SVM_VMSAVE) "\n\t"
5636 "pop %%" _ASM_AX " \n\t"
5638 /* Save guest registers, load host registers */
5639 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5640 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5641 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5642 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5643 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5644 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5645 #ifdef CONFIG_X86_64
5646 "mov %%r8, %c[r8](%[svm]) \n\t"
5647 "mov %%r9, %c[r9](%[svm]) \n\t"
5648 "mov %%r10, %c[r10](%[svm]) \n\t"
5649 "mov %%r11, %c[r11](%[svm]) \n\t"
5650 "mov %%r12, %c[r12](%[svm]) \n\t"
5651 "mov %%r13, %c[r13](%[svm]) \n\t"
5652 "mov %%r14, %c[r14](%[svm]) \n\t"
5653 "mov %%r15, %c[r15](%[svm]) \n\t"
5655 * Clear host registers marked as clobbered to prevent
5658 "xor %%r8d, %%r8d \n\t"
5659 "xor %%r9d, %%r9d \n\t"
5660 "xor %%r10d, %%r10d \n\t"
5661 "xor %%r11d, %%r11d \n\t"
5662 "xor %%r12d, %%r12d \n\t"
5663 "xor %%r13d, %%r13d \n\t"
5664 "xor %%r14d, %%r14d \n\t"
5665 "xor %%r15d, %%r15d \n\t"
5667 "xor %%ebx, %%ebx \n\t"
5668 "xor %%ecx, %%ecx \n\t"
5669 "xor %%edx, %%edx \n\t"
5670 "xor %%esi, %%esi \n\t"
5671 "xor %%edi, %%edi \n\t"
5675 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5676 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5677 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5678 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5679 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5680 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5681 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5682 #ifdef CONFIG_X86_64
5683 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5684 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5685 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5686 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5687 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5688 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5689 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5690 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5693 #ifdef CONFIG_X86_64
5694 , "rbx", "rcx", "rdx", "rsi", "rdi"
5695 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5697 , "ebx", "ecx", "edx", "esi", "edi"
5701 /* Eliminate branch target predictions from guest mode */
5704 #ifdef CONFIG_X86_64
5705 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5707 loadsegment(fs, svm->host.fs);
5708 #ifndef CONFIG_X86_32_LAZY_GS
5709 loadsegment(gs, svm->host.gs);
5714 * We do not use IBRS in the kernel. If this vCPU has used the
5715 * SPEC_CTRL MSR it may have left it on; save the value and
5716 * turn it off. This is much more efficient than blindly adding
5717 * it to the atomic save/restore list. Especially as the former
5718 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5720 * For non-nested case:
5721 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5725 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5728 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5729 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5733 local_irq_disable();
5735 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5737 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5738 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5739 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5740 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5742 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5743 kvm_before_interrupt(&svm->vcpu);
5747 /* Any pending NMI will happen here */
5749 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5750 kvm_after_interrupt(&svm->vcpu);
5752 sync_cr8_to_lapic(vcpu);
5756 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5758 /* if exit due to PF check for async PF */
5759 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5760 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5763 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5764 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5768 * We need to handle MC intercepts here before the vcpu has a chance to
5769 * change the physical cpu
5771 if (unlikely(svm->vmcb->control.exit_code ==
5772 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5773 svm_handle_mce(svm);
5775 mark_all_clean(svm->vmcb);
5777 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5779 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5781 struct vcpu_svm *svm = to_svm(vcpu);
5783 svm->vmcb->save.cr3 = __sme_set(root);
5784 mark_dirty(svm->vmcb, VMCB_CR);
5787 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5789 struct vcpu_svm *svm = to_svm(vcpu);
5791 svm->vmcb->control.nested_cr3 = __sme_set(root);
5792 mark_dirty(svm->vmcb, VMCB_NPT);
5794 /* Also sync guest cr3 here in case we live migrate */
5795 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5796 mark_dirty(svm->vmcb, VMCB_CR);
5799 static int is_disabled(void)
5803 rdmsrl(MSR_VM_CR, vm_cr);
5804 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5811 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5814 * Patch in the VMMCALL instruction:
5816 hypercall[0] = 0x0f;
5817 hypercall[1] = 0x01;
5818 hypercall[2] = 0xd9;
5821 static void svm_check_processor_compat(void *rtn)
5826 static bool svm_cpu_has_accelerated_tpr(void)
5831 static bool svm_has_emulated_msr(int index)
5836 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5841 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5843 struct vcpu_svm *svm = to_svm(vcpu);
5845 /* Update nrips enabled cache */
5846 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5848 if (!kvm_vcpu_apicv_active(vcpu))
5851 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5854 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5859 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5863 entry->ecx |= (1 << 2); /* Set SVM bit */
5866 entry->eax = 1; /* SVM revision 1 */
5867 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5868 ASID emulation to nested SVM */
5869 entry->ecx = 0; /* Reserved */
5870 entry->edx = 0; /* Per default do not support any
5871 additional features */
5873 /* Support next_rip if host supports it */
5874 if (boot_cpu_has(X86_FEATURE_NRIPS))
5875 entry->edx |= SVM_FEATURE_NRIP;
5877 /* Support NPT for the guest if enabled */
5879 entry->edx |= SVM_FEATURE_NPT;
5883 /* Support memory encryption cpuid if host supports it */
5884 if (boot_cpu_has(X86_FEATURE_SEV))
5885 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5886 &entry->ecx, &entry->edx);
5891 static int svm_get_lpage_level(void)
5893 return PT_PDPE_LEVEL;
5896 static bool svm_rdtscp_supported(void)
5898 return boot_cpu_has(X86_FEATURE_RDTSCP);
5901 static bool svm_invpcid_supported(void)
5906 static bool svm_mpx_supported(void)
5911 static bool svm_xsaves_supported(void)
5916 static bool svm_umip_emulated(void)
5921 static bool svm_has_wbinvd_exit(void)
5926 #define PRE_EX(exit) { .exit_code = (exit), \
5927 .stage = X86_ICPT_PRE_EXCEPT, }
5928 #define POST_EX(exit) { .exit_code = (exit), \
5929 .stage = X86_ICPT_POST_EXCEPT, }
5930 #define POST_MEM(exit) { .exit_code = (exit), \
5931 .stage = X86_ICPT_POST_MEMACCESS, }
5933 static const struct __x86_intercept {
5935 enum x86_intercept_stage stage;
5936 } x86_intercept_map[] = {
5937 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5938 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5939 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5940 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5941 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5942 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5943 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5944 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5945 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5946 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5947 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5948 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5949 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5950 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5951 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5952 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5953 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5954 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5955 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5956 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5957 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5958 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5959 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5960 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5961 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5962 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5963 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5964 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5965 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5966 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5967 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5968 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5969 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5970 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5971 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5972 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5973 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5974 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5975 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5976 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5977 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5978 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5979 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5980 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5981 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5982 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5989 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5990 struct x86_instruction_info *info,
5991 enum x86_intercept_stage stage)
5993 struct vcpu_svm *svm = to_svm(vcpu);
5994 int vmexit, ret = X86EMUL_CONTINUE;
5995 struct __x86_intercept icpt_info;
5996 struct vmcb *vmcb = svm->vmcb;
5998 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6001 icpt_info = x86_intercept_map[info->intercept];
6003 if (stage != icpt_info.stage)
6006 switch (icpt_info.exit_code) {
6007 case SVM_EXIT_READ_CR0:
6008 if (info->intercept == x86_intercept_cr_read)
6009 icpt_info.exit_code += info->modrm_reg;
6011 case SVM_EXIT_WRITE_CR0: {
6012 unsigned long cr0, val;
6015 if (info->intercept == x86_intercept_cr_write)
6016 icpt_info.exit_code += info->modrm_reg;
6018 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6019 info->intercept == x86_intercept_clts)
6022 intercept = svm->nested.intercept;
6024 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6027 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6028 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6030 if (info->intercept == x86_intercept_lmsw) {
6033 /* lmsw can't clear PE - catch this here */
6034 if (cr0 & X86_CR0_PE)
6039 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6043 case SVM_EXIT_READ_DR0:
6044 case SVM_EXIT_WRITE_DR0:
6045 icpt_info.exit_code += info->modrm_reg;
6048 if (info->intercept == x86_intercept_wrmsr)
6049 vmcb->control.exit_info_1 = 1;
6051 vmcb->control.exit_info_1 = 0;
6053 case SVM_EXIT_PAUSE:
6055 * We get this for NOP only, but pause
6056 * is rep not, check this here
6058 if (info->rep_prefix != REPE_PREFIX)
6061 case SVM_EXIT_IOIO: {
6065 if (info->intercept == x86_intercept_in ||
6066 info->intercept == x86_intercept_ins) {
6067 exit_info = ((info->src_val & 0xffff) << 16) |
6069 bytes = info->dst_bytes;
6071 exit_info = (info->dst_val & 0xffff) << 16;
6072 bytes = info->src_bytes;
6075 if (info->intercept == x86_intercept_outs ||
6076 info->intercept == x86_intercept_ins)
6077 exit_info |= SVM_IOIO_STR_MASK;
6079 if (info->rep_prefix)
6080 exit_info |= SVM_IOIO_REP_MASK;
6082 bytes = min(bytes, 4u);
6084 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6086 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6088 vmcb->control.exit_info_1 = exit_info;
6089 vmcb->control.exit_info_2 = info->next_rip;
6097 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6098 if (static_cpu_has(X86_FEATURE_NRIPS))
6099 vmcb->control.next_rip = info->next_rip;
6100 vmcb->control.exit_code = icpt_info.exit_code;
6101 vmexit = nested_svm_exit_handled(svm);
6103 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6110 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6114 * We must have an instruction with interrupts enabled, so
6115 * the timer interrupt isn't delayed by the interrupt shadow.
6118 local_irq_disable();
6121 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6123 if (pause_filter_thresh)
6124 shrink_ple_window(vcpu);
6127 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6129 if (avic_handle_apic_id_update(vcpu) != 0)
6131 if (avic_handle_dfr_update(vcpu) != 0)
6133 avic_handle_ldr_update(vcpu);
6136 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6138 /* [63:9] are reserved. */
6139 vcpu->arch.mcg_cap &= 0x1ff;
6142 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6144 struct vcpu_svm *svm = to_svm(vcpu);
6146 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6150 if (is_guest_mode(&svm->vcpu) &&
6151 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6152 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6153 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6154 svm->nested.exit_required = true;
6161 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6163 struct vcpu_svm *svm = to_svm(vcpu);
6166 if (is_guest_mode(vcpu)) {
6167 /* FED8h - SVM Guest */
6168 put_smstate(u64, smstate, 0x7ed8, 1);
6169 /* FEE0h - SVM Guest VMCB Physical Address */
6170 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6172 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6173 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6174 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6176 ret = nested_svm_vmexit(svm);
6183 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6185 struct vcpu_svm *svm = to_svm(vcpu);
6186 struct vmcb *nested_vmcb;
6194 ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6195 sizeof(svm_state_save));
6199 if (svm_state_save.guest) {
6200 vcpu->arch.hflags &= ~HF_SMM_MASK;
6201 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6203 enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6206 vcpu->arch.hflags |= HF_SMM_MASK;
6211 static int enable_smi_window(struct kvm_vcpu *vcpu)
6213 struct vcpu_svm *svm = to_svm(vcpu);
6215 if (!gif_set(svm)) {
6216 if (vgif_enabled(svm))
6217 set_intercept(svm, INTERCEPT_STGI);
6218 /* STGI will cause a vm exit */
6224 static int sev_asid_new(void)
6229 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6231 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6232 if (pos >= max_sev_asid)
6235 set_bit(pos, sev_asid_bitmap);
6239 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6241 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6245 asid = sev_asid_new();
6249 ret = sev_platform_init(&argp->error);
6255 INIT_LIST_HEAD(&sev->regions_list);
6260 __sev_asid_free(asid);
6264 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6266 struct sev_data_activate *data;
6267 int asid = sev_get_asid(kvm);
6270 wbinvd_on_all_cpus();
6272 ret = sev_guest_df_flush(error);
6276 data = kzalloc(sizeof(*data), GFP_KERNEL);
6280 /* activate ASID on the given handle */
6281 data->handle = handle;
6283 ret = sev_guest_activate(data, error);
6289 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6298 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6304 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6306 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6308 return __sev_issue_cmd(sev->fd, id, data, error);
6311 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6313 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6314 struct sev_data_launch_start *start;
6315 struct kvm_sev_launch_start params;
6316 void *dh_blob, *session_blob;
6317 int *error = &argp->error;
6320 if (!sev_guest(kvm))
6323 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6326 start = kzalloc(sizeof(*start), GFP_KERNEL);
6331 if (params.dh_uaddr) {
6332 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6333 if (IS_ERR(dh_blob)) {
6334 ret = PTR_ERR(dh_blob);
6338 start->dh_cert_address = __sme_set(__pa(dh_blob));
6339 start->dh_cert_len = params.dh_len;
6342 session_blob = NULL;
6343 if (params.session_uaddr) {
6344 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6345 if (IS_ERR(session_blob)) {
6346 ret = PTR_ERR(session_blob);
6350 start->session_address = __sme_set(__pa(session_blob));
6351 start->session_len = params.session_len;
6354 start->handle = params.handle;
6355 start->policy = params.policy;
6357 /* create memory encryption context */
6358 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6360 goto e_free_session;
6362 /* Bind ASID to this guest */
6363 ret = sev_bind_asid(kvm, start->handle, error);
6365 goto e_free_session;
6367 /* return handle to userspace */
6368 params.handle = start->handle;
6369 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6370 sev_unbind_asid(kvm, start->handle);
6372 goto e_free_session;
6375 sev->handle = start->handle;
6376 sev->fd = argp->sev_fd;
6379 kfree(session_blob);
6387 static int get_num_contig_pages(int idx, struct page **inpages,
6388 unsigned long npages)
6390 unsigned long paddr, next_paddr;
6391 int i = idx + 1, pages = 1;
6393 /* find the number of contiguous pages starting from idx */
6394 paddr = __sme_page_pa(inpages[idx]);
6395 while (i < npages) {
6396 next_paddr = __sme_page_pa(inpages[i++]);
6397 if ((paddr + PAGE_SIZE) == next_paddr) {
6408 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6410 unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6411 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6412 struct kvm_sev_launch_update_data params;
6413 struct sev_data_launch_update_data *data;
6414 struct page **inpages;
6417 if (!sev_guest(kvm))
6420 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6423 data = kzalloc(sizeof(*data), GFP_KERNEL);
6427 vaddr = params.uaddr;
6429 vaddr_end = vaddr + size;
6431 /* Lock the user memory. */
6432 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6439 * The LAUNCH_UPDATE command will perform in-place encryption of the
6440 * memory content (i.e it will write the same memory region with C=1).
6441 * It's possible that the cache may contain the data with C=0, i.e.,
6442 * unencrypted so invalidate it first.
6444 sev_clflush_pages(inpages, npages);
6446 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6450 * If the user buffer is not page-aligned, calculate the offset
6453 offset = vaddr & (PAGE_SIZE - 1);
6455 /* Calculate the number of pages that can be encrypted in one go. */
6456 pages = get_num_contig_pages(i, inpages, npages);
6458 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6460 data->handle = sev->handle;
6462 data->address = __sme_page_pa(inpages[i]) + offset;
6463 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6468 next_vaddr = vaddr + len;
6472 /* content of memory is updated, mark pages dirty */
6473 for (i = 0; i < npages; i++) {
6474 set_page_dirty_lock(inpages[i]);
6475 mark_page_accessed(inpages[i]);
6477 /* unlock the user pages */
6478 sev_unpin_memory(kvm, inpages, npages);
6484 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6486 void __user *measure = (void __user *)(uintptr_t)argp->data;
6487 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6488 struct sev_data_launch_measure *data;
6489 struct kvm_sev_launch_measure params;
6490 void __user *p = NULL;
6494 if (!sev_guest(kvm))
6497 if (copy_from_user(¶ms, measure, sizeof(params)))
6500 data = kzalloc(sizeof(*data), GFP_KERNEL);
6504 /* User wants to query the blob length */
6508 p = (void __user *)(uintptr_t)params.uaddr;
6510 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6516 blob = kmalloc(params.len, GFP_KERNEL);
6520 data->address = __psp_pa(blob);
6521 data->len = params.len;
6525 data->handle = sev->handle;
6526 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6529 * If we query the session length, FW responded with expected data.
6538 if (copy_to_user(p, blob, params.len))
6543 params.len = data->len;
6544 if (copy_to_user(measure, ¶ms, sizeof(params)))
6553 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6555 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6556 struct sev_data_launch_finish *data;
6559 if (!sev_guest(kvm))
6562 data = kzalloc(sizeof(*data), GFP_KERNEL);
6566 data->handle = sev->handle;
6567 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6573 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6575 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6576 struct kvm_sev_guest_status params;
6577 struct sev_data_guest_status *data;
6580 if (!sev_guest(kvm))
6583 data = kzalloc(sizeof(*data), GFP_KERNEL);
6587 data->handle = sev->handle;
6588 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6592 params.policy = data->policy;
6593 params.state = data->state;
6594 params.handle = data->handle;
6596 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6603 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6604 unsigned long dst, int size,
6605 int *error, bool enc)
6607 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6608 struct sev_data_dbg *data;
6611 data = kzalloc(sizeof(*data), GFP_KERNEL);
6615 data->handle = sev->handle;
6616 data->dst_addr = dst;
6617 data->src_addr = src;
6620 ret = sev_issue_cmd(kvm,
6621 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6627 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6628 unsigned long dst_paddr, int sz, int *err)
6633 * Its safe to read more than we are asked, caller should ensure that
6634 * destination has enough space.
6636 src_paddr = round_down(src_paddr, 16);
6637 offset = src_paddr & 15;
6638 sz = round_up(sz + offset, 16);
6640 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6643 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6644 unsigned long __user dst_uaddr,
6645 unsigned long dst_paddr,
6648 struct page *tpage = NULL;
6651 /* if inputs are not 16-byte then use intermediate buffer */
6652 if (!IS_ALIGNED(dst_paddr, 16) ||
6653 !IS_ALIGNED(paddr, 16) ||
6654 !IS_ALIGNED(size, 16)) {
6655 tpage = (void *)alloc_page(GFP_KERNEL);
6659 dst_paddr = __sme_page_pa(tpage);
6662 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6667 offset = paddr & 15;
6668 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6669 page_address(tpage) + offset, size))
6680 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6681 unsigned long __user vaddr,
6682 unsigned long dst_paddr,
6683 unsigned long __user dst_vaddr,
6684 int size, int *error)
6686 struct page *src_tpage = NULL;
6687 struct page *dst_tpage = NULL;
6688 int ret, len = size;
6690 /* If source buffer is not aligned then use an intermediate buffer */
6691 if (!IS_ALIGNED(vaddr, 16)) {
6692 src_tpage = alloc_page(GFP_KERNEL);
6696 if (copy_from_user(page_address(src_tpage),
6697 (void __user *)(uintptr_t)vaddr, size)) {
6698 __free_page(src_tpage);
6702 paddr = __sme_page_pa(src_tpage);
6706 * If destination buffer or length is not aligned then do read-modify-write:
6707 * - decrypt destination in an intermediate buffer
6708 * - copy the source buffer in an intermediate buffer
6709 * - use the intermediate buffer as source buffer
6711 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6714 dst_tpage = alloc_page(GFP_KERNEL);
6720 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6721 __sme_page_pa(dst_tpage), size, error);
6726 * If source is kernel buffer then use memcpy() otherwise
6729 dst_offset = dst_paddr & 15;
6732 memcpy(page_address(dst_tpage) + dst_offset,
6733 page_address(src_tpage), size);
6735 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6736 (void __user *)(uintptr_t)vaddr, size)) {
6742 paddr = __sme_page_pa(dst_tpage);
6743 dst_paddr = round_down(dst_paddr, 16);
6744 len = round_up(size, 16);
6747 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6751 __free_page(src_tpage);
6753 __free_page(dst_tpage);
6757 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6759 unsigned long vaddr, vaddr_end, next_vaddr;
6760 unsigned long dst_vaddr;
6761 struct page **src_p, **dst_p;
6762 struct kvm_sev_dbg debug;
6766 if (!sev_guest(kvm))
6769 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6772 vaddr = debug.src_uaddr;
6774 vaddr_end = vaddr + size;
6775 dst_vaddr = debug.dst_uaddr;
6777 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6778 int len, s_off, d_off;
6780 /* lock userspace source and destination page */
6781 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6785 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6787 sev_unpin_memory(kvm, src_p, n);
6792 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6793 * memory content (i.e it will write the same memory region with C=1).
6794 * It's possible that the cache may contain the data with C=0, i.e.,
6795 * unencrypted so invalidate it first.
6797 sev_clflush_pages(src_p, 1);
6798 sev_clflush_pages(dst_p, 1);
6801 * Since user buffer may not be page aligned, calculate the
6802 * offset within the page.
6804 s_off = vaddr & ~PAGE_MASK;
6805 d_off = dst_vaddr & ~PAGE_MASK;
6806 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6809 ret = __sev_dbg_decrypt_user(kvm,
6810 __sme_page_pa(src_p[0]) + s_off,
6812 __sme_page_pa(dst_p[0]) + d_off,
6815 ret = __sev_dbg_encrypt_user(kvm,
6816 __sme_page_pa(src_p[0]) + s_off,
6818 __sme_page_pa(dst_p[0]) + d_off,
6822 sev_unpin_memory(kvm, src_p, 1);
6823 sev_unpin_memory(kvm, dst_p, 1);
6828 next_vaddr = vaddr + len;
6829 dst_vaddr = dst_vaddr + len;
6836 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6838 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6839 struct sev_data_launch_secret *data;
6840 struct kvm_sev_launch_secret params;
6841 struct page **pages;
6846 if (!sev_guest(kvm))
6849 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6852 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6857 * The secret must be copied into contiguous memory region, lets verify
6858 * that userspace memory pages are contiguous before we issue command.
6860 if (get_num_contig_pages(0, pages, n) != n) {
6862 goto e_unpin_memory;
6866 data = kzalloc(sizeof(*data), GFP_KERNEL);
6868 goto e_unpin_memory;
6870 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6871 data->guest_address = __sme_page_pa(pages[0]) + offset;
6872 data->guest_len = params.guest_len;
6874 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6876 ret = PTR_ERR(blob);
6880 data->trans_address = __psp_pa(blob);
6881 data->trans_len = params.trans_len;
6883 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6888 data->hdr_address = __psp_pa(hdr);
6889 data->hdr_len = params.hdr_len;
6891 data->handle = sev->handle;
6892 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6901 sev_unpin_memory(kvm, pages, n);
6905 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6907 struct kvm_sev_cmd sev_cmd;
6910 if (!svm_sev_enabled())
6913 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6916 mutex_lock(&kvm->lock);
6918 switch (sev_cmd.id) {
6920 r = sev_guest_init(kvm, &sev_cmd);
6922 case KVM_SEV_LAUNCH_START:
6923 r = sev_launch_start(kvm, &sev_cmd);
6925 case KVM_SEV_LAUNCH_UPDATE_DATA:
6926 r = sev_launch_update_data(kvm, &sev_cmd);
6928 case KVM_SEV_LAUNCH_MEASURE:
6929 r = sev_launch_measure(kvm, &sev_cmd);
6931 case KVM_SEV_LAUNCH_FINISH:
6932 r = sev_launch_finish(kvm, &sev_cmd);
6934 case KVM_SEV_GUEST_STATUS:
6935 r = sev_guest_status(kvm, &sev_cmd);
6937 case KVM_SEV_DBG_DECRYPT:
6938 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6940 case KVM_SEV_DBG_ENCRYPT:
6941 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6943 case KVM_SEV_LAUNCH_SECRET:
6944 r = sev_launch_secret(kvm, &sev_cmd);
6951 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6955 mutex_unlock(&kvm->lock);
6959 static int svm_register_enc_region(struct kvm *kvm,
6960 struct kvm_enc_region *range)
6962 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6963 struct enc_region *region;
6966 if (!sev_guest(kvm))
6969 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6972 region = kzalloc(sizeof(*region), GFP_KERNEL);
6976 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
6977 if (!region->pages) {
6983 * The guest may change the memory encryption attribute from C=0 -> C=1
6984 * or vice versa for this memory range. Lets make sure caches are
6985 * flushed to ensure that guest data gets written into memory with
6988 sev_clflush_pages(region->pages, region->npages);
6990 region->uaddr = range->addr;
6991 region->size = range->size;
6993 mutex_lock(&kvm->lock);
6994 list_add_tail(®ion->list, &sev->regions_list);
6995 mutex_unlock(&kvm->lock);
7004 static struct enc_region *
7005 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7007 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7008 struct list_head *head = &sev->regions_list;
7009 struct enc_region *i;
7011 list_for_each_entry(i, head, list) {
7012 if (i->uaddr == range->addr &&
7013 i->size == range->size)
7021 static int svm_unregister_enc_region(struct kvm *kvm,
7022 struct kvm_enc_region *range)
7024 struct enc_region *region;
7027 mutex_lock(&kvm->lock);
7029 if (!sev_guest(kvm)) {
7034 region = find_enc_region(kvm, range);
7040 __unregister_enc_region_locked(kvm, region);
7042 mutex_unlock(&kvm->lock);
7046 mutex_unlock(&kvm->lock);
7050 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7056 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7057 uint16_t *vmcs_version)
7059 /* Intel-only feature */
7063 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7064 .cpu_has_kvm_support = has_svm,
7065 .disabled_by_bios = is_disabled,
7066 .hardware_setup = svm_hardware_setup,
7067 .hardware_unsetup = svm_hardware_unsetup,
7068 .check_processor_compatibility = svm_check_processor_compat,
7069 .hardware_enable = svm_hardware_enable,
7070 .hardware_disable = svm_hardware_disable,
7071 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7072 .has_emulated_msr = svm_has_emulated_msr,
7074 .vcpu_create = svm_create_vcpu,
7075 .vcpu_free = svm_free_vcpu,
7076 .vcpu_reset = svm_vcpu_reset,
7078 .vm_alloc = svm_vm_alloc,
7079 .vm_free = svm_vm_free,
7080 .vm_init = avic_vm_init,
7081 .vm_destroy = svm_vm_destroy,
7083 .prepare_guest_switch = svm_prepare_guest_switch,
7084 .vcpu_load = svm_vcpu_load,
7085 .vcpu_put = svm_vcpu_put,
7086 .vcpu_blocking = svm_vcpu_blocking,
7087 .vcpu_unblocking = svm_vcpu_unblocking,
7089 .update_bp_intercept = update_bp_intercept,
7090 .get_msr_feature = svm_get_msr_feature,
7091 .get_msr = svm_get_msr,
7092 .set_msr = svm_set_msr,
7093 .get_segment_base = svm_get_segment_base,
7094 .get_segment = svm_get_segment,
7095 .set_segment = svm_set_segment,
7096 .get_cpl = svm_get_cpl,
7097 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7098 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7099 .decache_cr3 = svm_decache_cr3,
7100 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7101 .set_cr0 = svm_set_cr0,
7102 .set_cr3 = svm_set_cr3,
7103 .set_cr4 = svm_set_cr4,
7104 .set_efer = svm_set_efer,
7105 .get_idt = svm_get_idt,
7106 .set_idt = svm_set_idt,
7107 .get_gdt = svm_get_gdt,
7108 .set_gdt = svm_set_gdt,
7109 .get_dr6 = svm_get_dr6,
7110 .set_dr6 = svm_set_dr6,
7111 .set_dr7 = svm_set_dr7,
7112 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7113 .cache_reg = svm_cache_reg,
7114 .get_rflags = svm_get_rflags,
7115 .set_rflags = svm_set_rflags,
7117 .tlb_flush = svm_flush_tlb,
7118 .tlb_flush_gva = svm_flush_tlb_gva,
7120 .run = svm_vcpu_run,
7121 .handle_exit = handle_exit,
7122 .skip_emulated_instruction = skip_emulated_instruction,
7123 .set_interrupt_shadow = svm_set_interrupt_shadow,
7124 .get_interrupt_shadow = svm_get_interrupt_shadow,
7125 .patch_hypercall = svm_patch_hypercall,
7126 .set_irq = svm_set_irq,
7127 .set_nmi = svm_inject_nmi,
7128 .queue_exception = svm_queue_exception,
7129 .cancel_injection = svm_cancel_injection,
7130 .interrupt_allowed = svm_interrupt_allowed,
7131 .nmi_allowed = svm_nmi_allowed,
7132 .get_nmi_mask = svm_get_nmi_mask,
7133 .set_nmi_mask = svm_set_nmi_mask,
7134 .enable_nmi_window = enable_nmi_window,
7135 .enable_irq_window = enable_irq_window,
7136 .update_cr8_intercept = update_cr8_intercept,
7137 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7138 .get_enable_apicv = svm_get_enable_apicv,
7139 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7140 .load_eoi_exitmap = svm_load_eoi_exitmap,
7141 .hwapic_irr_update = svm_hwapic_irr_update,
7142 .hwapic_isr_update = svm_hwapic_isr_update,
7143 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7144 .apicv_post_state_restore = avic_post_state_restore,
7146 .set_tss_addr = svm_set_tss_addr,
7147 .set_identity_map_addr = svm_set_identity_map_addr,
7148 .get_tdp_level = get_npt_level,
7149 .get_mt_mask = svm_get_mt_mask,
7151 .get_exit_info = svm_get_exit_info,
7153 .get_lpage_level = svm_get_lpage_level,
7155 .cpuid_update = svm_cpuid_update,
7157 .rdtscp_supported = svm_rdtscp_supported,
7158 .invpcid_supported = svm_invpcid_supported,
7159 .mpx_supported = svm_mpx_supported,
7160 .xsaves_supported = svm_xsaves_supported,
7161 .umip_emulated = svm_umip_emulated,
7163 .set_supported_cpuid = svm_set_supported_cpuid,
7165 .has_wbinvd_exit = svm_has_wbinvd_exit,
7167 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7168 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7170 .set_tdp_cr3 = set_tdp_cr3,
7172 .check_intercept = svm_check_intercept,
7173 .handle_external_intr = svm_handle_external_intr,
7175 .request_immediate_exit = __kvm_request_immediate_exit,
7177 .sched_in = svm_sched_in,
7179 .pmu_ops = &amd_pmu_ops,
7180 .deliver_posted_interrupt = svm_deliver_avic_intr,
7181 .update_pi_irte = svm_update_pi_irte,
7182 .setup_mce = svm_setup_mce,
7184 .smi_allowed = svm_smi_allowed,
7185 .pre_enter_smm = svm_pre_enter_smm,
7186 .pre_leave_smm = svm_pre_leave_smm,
7187 .enable_smi_window = enable_smi_window,
7189 .mem_enc_op = svm_mem_enc_op,
7190 .mem_enc_reg_region = svm_register_enc_region,
7191 .mem_enc_unreg_region = svm_unregister_enc_region,
7193 .nested_enable_evmcs = nested_enable_evmcs,
7194 .nested_get_evmcs_version = nested_get_evmcs_version,
7197 static int __init svm_init(void)
7199 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7200 __alignof__(struct vcpu_svm), THIS_MODULE);
7203 static void __exit svm_exit(void)
7208 module_init(svm_init)
7209 module_exit(svm_exit)