1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
43 #include <asm/perf_event.h>
44 #include <asm/tlbflush.h>
46 #include <asm/debugreg.h>
47 #include <asm/kvm_para.h>
48 #include <asm/irq_remapping.h>
49 #include <asm/spec-ctrl.h>
51 #include <asm/virtext.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id svm_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_SVM),
63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
65 #define IOPM_ALLOC_ORDER 2
66 #define MSRPM_ALLOC_ORDER 1
68 #define SEG_TYPE_LDT 2
69 #define SEG_TYPE_BUSY_TSS16 3
71 #define SVM_FEATURE_LBRV (1 << 1)
72 #define SVM_FEATURE_SVML (1 << 2)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
79 #define SVM_AVIC_DOORBELL 0xc001011b
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
116 static bool erratum_383_found __read_mostly;
118 static const u32 host_save_user_msrs[] = {
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
129 struct kvm_sev_info {
130 bool active; /* SEV enabled guest */
131 unsigned int asid; /* ASID used for this guest */
132 unsigned int handle; /* SEV firmware handle */
133 int fd; /* SEV device fd */
134 unsigned long pages_locked; /* Number of pages locked */
135 struct list_head regions_list; /* List of registered regions */
141 /* Struct members for AVIC */
143 struct page *avic_logical_id_table_page;
144 struct page *avic_physical_id_table_page;
145 struct hlist_node hnode;
147 struct kvm_sev_info sev_info;
152 struct nested_state {
158 /* These are the merged vectors */
161 /* gpa pointers to the real vectors */
165 /* A VMEXIT is required but not yet emulated */
168 /* cache for intercepts of the guest */
171 u32 intercept_exceptions;
174 /* Nested Paging related state */
178 #define MSRPM_OFFSETS 16
179 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
182 * Set osvw_len to higher value when updated Revision Guides
183 * are published and we know what the new status bits are
185 static uint64_t osvw_len = 4, osvw_status;
188 struct kvm_vcpu vcpu;
190 unsigned long vmcb_pa;
191 struct svm_cpu_data *svm_data;
192 uint64_t asid_generation;
193 uint64_t sysenter_esp;
194 uint64_t sysenter_eip;
201 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
211 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
212 * translated into the appropriate L2_CFG bits on the host to
213 * perform speculative control.
221 struct nested_state nested;
224 u64 nmi_singlestep_guest_rflags;
226 unsigned int3_injected;
227 unsigned long int3_rip;
229 /* cached guest cpuid flags for faster access */
230 bool nrips_enabled : 1;
234 struct page *avic_backing_page;
235 u64 *avic_physical_id_cache;
236 bool avic_is_running;
239 * Per-vcpu list of struct amd_svm_iommu_ir:
240 * This is used mainly to store interrupt remapping information used
241 * when update the vcpu affinity. This avoids the need to scan for
242 * IRTE and try to match ga_tag in the IOMMU driver.
244 struct list_head ir_list;
245 spinlock_t ir_list_lock;
247 /* which host CPU was used for running this vcpu */
248 unsigned int last_cpu;
252 * This is a wrapper of struct amd_iommu_ir_data.
254 struct amd_svm_iommu_ir {
255 struct list_head node; /* Used by SVM for per-vcpu ir_list */
256 void *data; /* Storing pointer to struct amd_ir_data */
259 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
260 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
261 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
263 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
264 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
265 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
266 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
268 static DEFINE_PER_CPU(u64, current_tsc_ratio);
269 #define TSC_RATIO_DEFAULT 0x0100000000ULL
271 #define MSR_INVALID 0xffffffffU
273 static const struct svm_direct_access_msrs {
274 u32 index; /* Index of the MSR */
275 bool always; /* True if intercept is always on */
276 } direct_access_msrs[] = {
277 { .index = MSR_STAR, .always = true },
278 { .index = MSR_IA32_SYSENTER_CS, .always = true },
280 { .index = MSR_GS_BASE, .always = true },
281 { .index = MSR_FS_BASE, .always = true },
282 { .index = MSR_KERNEL_GS_BASE, .always = true },
283 { .index = MSR_LSTAR, .always = true },
284 { .index = MSR_CSTAR, .always = true },
285 { .index = MSR_SYSCALL_MASK, .always = true },
287 { .index = MSR_IA32_SPEC_CTRL, .always = false },
288 { .index = MSR_IA32_PRED_CMD, .always = false },
289 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
290 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
291 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
292 { .index = MSR_IA32_LASTINTTOIP, .always = false },
293 { .index = MSR_INVALID, .always = false },
296 /* enable NPT for AMD64 and X86 with PAE */
297 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
298 static bool npt_enabled = true;
300 static bool npt_enabled;
304 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
305 * pause_filter_count: On processors that support Pause filtering(indicated
306 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
307 * count value. On VMRUN this value is loaded into an internal counter.
308 * Each time a pause instruction is executed, this counter is decremented
309 * until it reaches zero at which time a #VMEXIT is generated if pause
310 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
311 * Intercept Filtering for more details.
312 * This also indicate if ple logic enabled.
314 * pause_filter_thresh: In addition, some processor families support advanced
315 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
316 * the amount of time a guest is allowed to execute in a pause loop.
317 * In this mode, a 16-bit pause filter threshold field is added in the
318 * VMCB. The threshold value is a cycle count that is used to reset the
319 * pause counter. As with simple pause filtering, VMRUN loads the pause
320 * count value from VMCB into an internal counter. Then, on each pause
321 * instruction the hardware checks the elapsed number of cycles since
322 * the most recent pause instruction against the pause filter threshold.
323 * If the elapsed cycle count is greater than the pause filter threshold,
324 * then the internal pause count is reloaded from the VMCB and execution
325 * continues. If the elapsed cycle count is less than the pause filter
326 * threshold, then the internal pause count is decremented. If the count
327 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
328 * triggered. If advanced pause filtering is supported and pause filter
329 * threshold field is set to zero, the filter will operate in the simpler,
333 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
334 module_param(pause_filter_thresh, ushort, 0444);
336 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
337 module_param(pause_filter_count, ushort, 0444);
339 /* Default doubles per-vcpu window every exit. */
340 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
341 module_param(pause_filter_count_grow, ushort, 0444);
343 /* Default resets per-vcpu window every exit to pause_filter_count. */
344 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
345 module_param(pause_filter_count_shrink, ushort, 0444);
347 /* Default is to compute the maximum so we can never overflow. */
348 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
349 module_param(pause_filter_count_max, ushort, 0444);
351 /* allow nested paging (virtualized MMU) for all guests */
352 static int npt = true;
353 module_param(npt, int, S_IRUGO);
355 /* allow nested virtualization in KVM/SVM */
356 static int nested = true;
357 module_param(nested, int, S_IRUGO);
359 /* enable / disable AVIC */
361 #ifdef CONFIG_X86_LOCAL_APIC
362 module_param(avic, int, S_IRUGO);
365 /* enable/disable Next RIP Save */
366 static int nrips = true;
367 module_param(nrips, int, 0444);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls = true;
371 module_param(vls, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif = true;
375 module_param(vgif, int, 0444);
377 /* enable/disable SEV support */
378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
379 module_param(sev, int, 0444);
381 static bool __read_mostly dump_invalid_vmcb = 0;
382 module_param(dump_invalid_vmcb, bool, 0644);
384 static u8 rsm_ins_bytes[] = "\x0f\xaa";
386 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
387 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
388 static void svm_complete_interrupts(struct vcpu_svm *svm);
390 static int nested_svm_exit_handled(struct vcpu_svm *svm);
391 static int nested_svm_intercept(struct vcpu_svm *svm);
392 static int nested_svm_vmexit(struct vcpu_svm *svm);
393 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
394 bool has_error_code, u32 error_code);
397 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
398 pause filter count */
399 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
400 VMCB_ASID, /* ASID */
401 VMCB_INTR, /* int_ctl, int_vector */
402 VMCB_NPT, /* npt_en, nCR3, gPAT */
403 VMCB_CR, /* CR0, CR3, CR4, EFER */
404 VMCB_DR, /* DR6, DR7 */
405 VMCB_DT, /* GDT, IDT */
406 VMCB_SEG, /* CS, DS, SS, ES, CPL */
407 VMCB_CR2, /* CR2 only */
408 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
409 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
410 * AVIC PHYSICAL_TABLE pointer,
411 * AVIC LOGICAL_TABLE pointer
416 /* TPR and CR2 are always written before VMRUN */
417 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
419 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
421 static DEFINE_MUTEX(sev_deactivate_lock);
422 static DEFINE_MUTEX(sev_bitmap_lock);
423 static unsigned int max_sev_asid;
424 static unsigned int min_sev_asid;
425 static unsigned long *sev_asid_bitmap;
426 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
429 struct list_head list;
430 unsigned long npages;
437 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
439 return container_of(kvm, struct kvm_svm, kvm);
442 static inline bool svm_sev_enabled(void)
444 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
447 static inline bool sev_guest(struct kvm *kvm)
449 #ifdef CONFIG_KVM_AMD_SEV
450 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
458 static inline int sev_get_asid(struct kvm *kvm)
460 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
465 static inline void mark_all_dirty(struct vmcb *vmcb)
467 vmcb->control.clean = 0;
470 static inline void mark_all_clean(struct vmcb *vmcb)
472 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
473 & ~VMCB_ALWAYS_DIRTY_MASK;
476 static inline void mark_dirty(struct vmcb *vmcb, int bit)
478 vmcb->control.clean &= ~(1 << bit);
481 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
483 return container_of(vcpu, struct vcpu_svm, vcpu);
486 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
488 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
489 mark_dirty(svm->vmcb, VMCB_AVIC);
492 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
494 struct vcpu_svm *svm = to_svm(vcpu);
495 u64 *entry = svm->avic_physical_id_cache;
500 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
503 static void recalc_intercepts(struct vcpu_svm *svm)
505 struct vmcb_control_area *c, *h;
506 struct nested_state *g;
508 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
510 if (!is_guest_mode(&svm->vcpu))
513 c = &svm->vmcb->control;
514 h = &svm->nested.hsave->control;
517 c->intercept_cr = h->intercept_cr | g->intercept_cr;
518 c->intercept_dr = h->intercept_dr | g->intercept_dr;
519 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
520 c->intercept = h->intercept | g->intercept;
523 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
525 if (is_guest_mode(&svm->vcpu))
526 return svm->nested.hsave;
531 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
533 struct vmcb *vmcb = get_host_vmcb(svm);
535 vmcb->control.intercept_cr |= (1U << bit);
537 recalc_intercepts(svm);
540 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
542 struct vmcb *vmcb = get_host_vmcb(svm);
544 vmcb->control.intercept_cr &= ~(1U << bit);
546 recalc_intercepts(svm);
549 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
551 struct vmcb *vmcb = get_host_vmcb(svm);
553 return vmcb->control.intercept_cr & (1U << bit);
556 static inline void set_dr_intercepts(struct vcpu_svm *svm)
558 struct vmcb *vmcb = get_host_vmcb(svm);
560 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
561 | (1 << INTERCEPT_DR1_READ)
562 | (1 << INTERCEPT_DR2_READ)
563 | (1 << INTERCEPT_DR3_READ)
564 | (1 << INTERCEPT_DR4_READ)
565 | (1 << INTERCEPT_DR5_READ)
566 | (1 << INTERCEPT_DR6_READ)
567 | (1 << INTERCEPT_DR7_READ)
568 | (1 << INTERCEPT_DR0_WRITE)
569 | (1 << INTERCEPT_DR1_WRITE)
570 | (1 << INTERCEPT_DR2_WRITE)
571 | (1 << INTERCEPT_DR3_WRITE)
572 | (1 << INTERCEPT_DR4_WRITE)
573 | (1 << INTERCEPT_DR5_WRITE)
574 | (1 << INTERCEPT_DR6_WRITE)
575 | (1 << INTERCEPT_DR7_WRITE);
577 recalc_intercepts(svm);
580 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
582 struct vmcb *vmcb = get_host_vmcb(svm);
584 vmcb->control.intercept_dr = 0;
586 recalc_intercepts(svm);
589 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
591 struct vmcb *vmcb = get_host_vmcb(svm);
593 vmcb->control.intercept_exceptions |= (1U << bit);
595 recalc_intercepts(svm);
598 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
600 struct vmcb *vmcb = get_host_vmcb(svm);
602 vmcb->control.intercept_exceptions &= ~(1U << bit);
604 recalc_intercepts(svm);
607 static inline void set_intercept(struct vcpu_svm *svm, int bit)
609 struct vmcb *vmcb = get_host_vmcb(svm);
611 vmcb->control.intercept |= (1ULL << bit);
613 recalc_intercepts(svm);
616 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
618 struct vmcb *vmcb = get_host_vmcb(svm);
620 vmcb->control.intercept &= ~(1ULL << bit);
622 recalc_intercepts(svm);
625 static inline bool vgif_enabled(struct vcpu_svm *svm)
627 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
630 static inline void enable_gif(struct vcpu_svm *svm)
632 if (vgif_enabled(svm))
633 svm->vmcb->control.int_ctl |= V_GIF_MASK;
635 svm->vcpu.arch.hflags |= HF_GIF_MASK;
638 static inline void disable_gif(struct vcpu_svm *svm)
640 if (vgif_enabled(svm))
641 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
643 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
646 static inline bool gif_set(struct vcpu_svm *svm)
648 if (vgif_enabled(svm))
649 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
651 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
654 static unsigned long iopm_base;
656 struct kvm_ldttss_desc {
659 unsigned base1:8, type:5, dpl:2, p:1;
660 unsigned limit1:4, zero0:3, g:1, base2:8;
663 } __attribute__((packed));
665 struct svm_cpu_data {
672 struct kvm_ldttss_desc *tss_desc;
674 struct page *save_area;
675 struct vmcb *current_vmcb;
677 /* index = sev_asid, value = vmcb pointer */
678 struct vmcb **sev_vmcbs;
681 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
683 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
685 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
686 #define MSRS_RANGE_SIZE 2048
687 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
689 static u32 svm_msrpm_offset(u32 msr)
694 for (i = 0; i < NUM_MSR_MAPS; i++) {
695 if (msr < msrpm_ranges[i] ||
696 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
699 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
700 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
702 /* Now we have the u8 offset - but need the u32 offset */
706 /* MSR not in any range */
710 #define MAX_INST_SIZE 15
712 static inline void clgi(void)
714 asm volatile (__ex("clgi"));
717 static inline void stgi(void)
719 asm volatile (__ex("stgi"));
722 static inline void invlpga(unsigned long addr, u32 asid)
724 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
727 static int get_npt_level(struct kvm_vcpu *vcpu)
730 return PT64_ROOT_4LEVEL;
732 return PT32E_ROOT_LEVEL;
736 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
738 vcpu->arch.efer = efer;
739 if (!npt_enabled && !(efer & EFER_LMA))
742 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
743 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
746 static int is_external_interrupt(u32 info)
748 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
749 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
752 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
754 struct vcpu_svm *svm = to_svm(vcpu);
757 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
758 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
762 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
764 struct vcpu_svm *svm = to_svm(vcpu);
767 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
769 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
773 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
775 struct vcpu_svm *svm = to_svm(vcpu);
777 if (nrips && svm->vmcb->control.next_rip != 0) {
778 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
779 svm->next_rip = svm->vmcb->control.next_rip;
782 if (!svm->next_rip) {
783 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
786 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
787 pr_err("%s: ip 0x%lx next 0x%llx\n",
788 __func__, kvm_rip_read(vcpu), svm->next_rip);
789 kvm_rip_write(vcpu, svm->next_rip);
791 svm_set_interrupt_shadow(vcpu, 0);
796 static void svm_queue_exception(struct kvm_vcpu *vcpu)
798 struct vcpu_svm *svm = to_svm(vcpu);
799 unsigned nr = vcpu->arch.exception.nr;
800 bool has_error_code = vcpu->arch.exception.has_error_code;
801 bool reinject = vcpu->arch.exception.injected;
802 u32 error_code = vcpu->arch.exception.error_code;
805 * If we are within a nested VM we'd better #VMEXIT and let the guest
806 * handle the exception
809 nested_svm_check_exception(svm, nr, has_error_code, error_code))
812 kvm_deliver_exception_payload(&svm->vcpu);
814 if (nr == BP_VECTOR && !nrips) {
815 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
818 * For guest debugging where we have to reinject #BP if some
819 * INT3 is guest-owned:
820 * Emulate nRIP by moving RIP forward. Will fail if injection
821 * raises a fault that is not intercepted. Still better than
822 * failing in all cases.
824 (void)skip_emulated_instruction(&svm->vcpu);
825 rip = kvm_rip_read(&svm->vcpu);
826 svm->int3_rip = rip + svm->vmcb->save.cs.base;
827 svm->int3_injected = rip - old_rip;
830 svm->vmcb->control.event_inj = nr
832 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
833 | SVM_EVTINJ_TYPE_EXEPT;
834 svm->vmcb->control.event_inj_err = error_code;
837 static void svm_init_erratum_383(void)
843 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
846 /* Use _safe variants to not break nested virtualization */
847 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
853 low = lower_32_bits(val);
854 high = upper_32_bits(val);
856 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
858 erratum_383_found = true;
861 static void svm_init_osvw(struct kvm_vcpu *vcpu)
864 * Guests should see errata 400 and 415 as fixed (assuming that
865 * HLT and IO instructions are intercepted).
867 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
868 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
871 * By increasing VCPU's osvw.length to 3 we are telling the guest that
872 * all osvw.status bits inside that length, including bit 0 (which is
873 * reserved for erratum 298), are valid. However, if host processor's
874 * osvw_len is 0 then osvw_status[0] carries no information. We need to
875 * be conservative here and therefore we tell the guest that erratum 298
876 * is present (because we really don't know).
878 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
879 vcpu->arch.osvw.status |= 1;
882 static int has_svm(void)
886 if (!cpu_has_svm(&msg)) {
887 printk(KERN_INFO "has_svm: %s\n", msg);
894 static void svm_hardware_disable(void)
896 /* Make sure we clean up behind us */
897 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
898 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
902 amd_pmu_disable_virt();
905 static int svm_hardware_enable(void)
908 struct svm_cpu_data *sd;
910 struct desc_struct *gdt;
911 int me = raw_smp_processor_id();
913 rdmsrl(MSR_EFER, efer);
914 if (efer & EFER_SVME)
918 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
921 sd = per_cpu(svm_data, me);
923 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
927 sd->asid_generation = 1;
928 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
929 sd->next_asid = sd->max_asid + 1;
930 sd->min_asid = max_sev_asid + 1;
932 gdt = get_current_gdt_rw();
933 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
935 wrmsrl(MSR_EFER, efer | EFER_SVME);
937 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
939 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
940 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
941 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
948 * Note that it is possible to have a system with mixed processor
949 * revisions and therefore different OSVW bits. If bits are not the same
950 * on different processors then choose the worst case (i.e. if erratum
951 * is present on one processor and not on another then assume that the
952 * erratum is present everywhere).
954 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
955 uint64_t len, status = 0;
958 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
960 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
964 osvw_status = osvw_len = 0;
968 osvw_status |= status;
969 osvw_status &= (1ULL << osvw_len) - 1;
972 osvw_status = osvw_len = 0;
974 svm_init_erratum_383();
976 amd_pmu_enable_virt();
981 static void svm_cpu_uninit(int cpu)
983 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
988 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
989 kfree(sd->sev_vmcbs);
990 __free_page(sd->save_area);
994 static int svm_cpu_init(int cpu)
996 struct svm_cpu_data *sd;
999 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1004 sd->save_area = alloc_page(GFP_KERNEL);
1008 if (svm_sev_enabled()) {
1010 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1017 per_cpu(svm_data, cpu) = sd;
1027 static bool valid_msr_intercept(u32 index)
1031 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1032 if (direct_access_msrs[i].index == index)
1038 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1045 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1046 to_svm(vcpu)->msrpm;
1048 offset = svm_msrpm_offset(msr);
1049 bit_write = 2 * (msr & 0x0f) + 1;
1050 tmp = msrpm[offset];
1052 BUG_ON(offset == MSR_INVALID);
1054 return !!test_bit(bit_write, &tmp);
1057 static void set_msr_interception(u32 *msrpm, unsigned msr,
1058 int read, int write)
1060 u8 bit_read, bit_write;
1065 * If this warning triggers extend the direct_access_msrs list at the
1066 * beginning of the file
1068 WARN_ON(!valid_msr_intercept(msr));
1070 offset = svm_msrpm_offset(msr);
1071 bit_read = 2 * (msr & 0x0f);
1072 bit_write = 2 * (msr & 0x0f) + 1;
1073 tmp = msrpm[offset];
1075 BUG_ON(offset == MSR_INVALID);
1077 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1078 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1080 msrpm[offset] = tmp;
1083 static void svm_vcpu_init_msrpm(u32 *msrpm)
1087 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1089 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1090 if (!direct_access_msrs[i].always)
1093 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1097 static void add_msr_offset(u32 offset)
1101 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1103 /* Offset already in list? */
1104 if (msrpm_offsets[i] == offset)
1107 /* Slot used by another offset? */
1108 if (msrpm_offsets[i] != MSR_INVALID)
1111 /* Add offset to list */
1112 msrpm_offsets[i] = offset;
1118 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1119 * increase MSRPM_OFFSETS in this case.
1124 static void init_msrpm_offsets(void)
1128 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1130 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1133 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1134 BUG_ON(offset == MSR_INVALID);
1136 add_msr_offset(offset);
1140 static void svm_enable_lbrv(struct vcpu_svm *svm)
1142 u32 *msrpm = svm->msrpm;
1144 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1145 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1146 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1147 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1148 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1151 static void svm_disable_lbrv(struct vcpu_svm *svm)
1153 u32 *msrpm = svm->msrpm;
1155 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1156 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1157 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1158 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1159 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1162 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1164 svm->nmi_singlestep = false;
1166 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1167 /* Clear our flags if they were not set by the guest */
1168 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1169 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1170 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1171 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1176 * This hash table is used to map VM_ID to a struct kvm_svm,
1177 * when handling AMD IOMMU GALOG notification to schedule in
1178 * a particular vCPU.
1180 #define SVM_VM_DATA_HASH_BITS 8
1181 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1182 static u32 next_vm_id = 0;
1183 static bool next_vm_id_wrapped = 0;
1184 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1187 * This function is called from IOMMU driver to notify
1188 * SVM to schedule in a particular vCPU of a particular VM.
1190 static int avic_ga_log_notifier(u32 ga_tag)
1192 unsigned long flags;
1193 struct kvm_svm *kvm_svm;
1194 struct kvm_vcpu *vcpu = NULL;
1195 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1196 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1198 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1200 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1201 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1202 if (kvm_svm->avic_vm_id != vm_id)
1204 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1207 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1210 * At this point, the IOMMU should have already set the pending
1211 * bit in the vAPIC backing page. So, we just need to schedule
1215 kvm_vcpu_wake_up(vcpu);
1220 static __init int sev_hardware_setup(void)
1222 struct sev_user_data_status *status;
1225 /* Maximum number of encrypted guests supported simultaneously */
1226 max_sev_asid = cpuid_ecx(0x8000001F);
1231 /* Minimum ASID value that should be used for SEV guest */
1232 min_sev_asid = cpuid_edx(0x8000001F);
1234 /* Initialize SEV ASID bitmap */
1235 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1236 if (!sev_asid_bitmap)
1239 status = kmalloc(sizeof(*status), GFP_KERNEL);
1244 * Check SEV platform status.
1246 * PLATFORM_STATUS can be called in any state, if we failed to query
1247 * the PLATFORM status then either PSP firmware does not support SEV
1248 * feature or SEV firmware is dead.
1250 rc = sev_platform_status(status, NULL);
1254 pr_info("SEV supported\n");
1261 static void grow_ple_window(struct kvm_vcpu *vcpu)
1263 struct vcpu_svm *svm = to_svm(vcpu);
1264 struct vmcb_control_area *control = &svm->vmcb->control;
1265 int old = control->pause_filter_count;
1267 control->pause_filter_count = __grow_ple_window(old,
1269 pause_filter_count_grow,
1270 pause_filter_count_max);
1272 if (control->pause_filter_count != old) {
1273 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1274 trace_kvm_ple_window_update(vcpu->vcpu_id,
1275 control->pause_filter_count, old);
1279 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1281 struct vcpu_svm *svm = to_svm(vcpu);
1282 struct vmcb_control_area *control = &svm->vmcb->control;
1283 int old = control->pause_filter_count;
1285 control->pause_filter_count =
1286 __shrink_ple_window(old,
1288 pause_filter_count_shrink,
1289 pause_filter_count);
1290 if (control->pause_filter_count != old) {
1291 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1292 trace_kvm_ple_window_update(vcpu->vcpu_id,
1293 control->pause_filter_count, old);
1297 static __init int svm_hardware_setup(void)
1300 struct page *iopm_pages;
1304 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1309 iopm_va = page_address(iopm_pages);
1310 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1311 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1313 init_msrpm_offsets();
1315 if (boot_cpu_has(X86_FEATURE_NX))
1316 kvm_enable_efer_bits(EFER_NX);
1318 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1319 kvm_enable_efer_bits(EFER_FFXSR);
1321 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1322 kvm_has_tsc_control = true;
1323 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1324 kvm_tsc_scaling_ratio_frac_bits = 32;
1327 /* Check for pause filtering support */
1328 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1329 pause_filter_count = 0;
1330 pause_filter_thresh = 0;
1331 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1332 pause_filter_thresh = 0;
1336 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1337 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1341 if (boot_cpu_has(X86_FEATURE_SEV) &&
1342 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1343 r = sev_hardware_setup();
1351 for_each_possible_cpu(cpu) {
1352 r = svm_cpu_init(cpu);
1357 if (!boot_cpu_has(X86_FEATURE_NPT))
1358 npt_enabled = false;
1360 if (npt_enabled && !npt) {
1361 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1362 npt_enabled = false;
1366 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1372 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1378 !boot_cpu_has(X86_FEATURE_AVIC) ||
1379 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1382 pr_info("AVIC enabled\n");
1384 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1390 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1391 !IS_ENABLED(CONFIG_X86_64)) {
1394 pr_info("Virtual VMLOAD VMSAVE supported\n");
1399 if (!boot_cpu_has(X86_FEATURE_VGIF))
1402 pr_info("Virtual GIF supported\n");
1408 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1413 static __exit void svm_hardware_unsetup(void)
1417 if (svm_sev_enabled())
1418 bitmap_free(sev_asid_bitmap);
1420 for_each_possible_cpu(cpu)
1421 svm_cpu_uninit(cpu);
1423 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1427 static void init_seg(struct vmcb_seg *seg)
1430 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1431 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1432 seg->limit = 0xffff;
1436 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1439 seg->attrib = SVM_SELECTOR_P_MASK | type;
1440 seg->limit = 0xffff;
1444 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1446 struct vcpu_svm *svm = to_svm(vcpu);
1448 if (is_guest_mode(vcpu))
1449 return svm->nested.hsave->control.tsc_offset;
1451 return vcpu->arch.tsc_offset;
1454 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1456 struct vcpu_svm *svm = to_svm(vcpu);
1457 u64 g_tsc_offset = 0;
1459 if (is_guest_mode(vcpu)) {
1460 /* Write L1's TSC offset. */
1461 g_tsc_offset = svm->vmcb->control.tsc_offset -
1462 svm->nested.hsave->control.tsc_offset;
1463 svm->nested.hsave->control.tsc_offset = offset;
1466 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1467 svm->vmcb->control.tsc_offset - g_tsc_offset,
1470 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1472 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1473 return svm->vmcb->control.tsc_offset;
1476 static void avic_init_vmcb(struct vcpu_svm *svm)
1478 struct vmcb *vmcb = svm->vmcb;
1479 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1480 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1481 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1482 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1484 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1485 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1486 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1487 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1488 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1491 static void init_vmcb(struct vcpu_svm *svm)
1493 struct vmcb_control_area *control = &svm->vmcb->control;
1494 struct vmcb_save_area *save = &svm->vmcb->save;
1496 svm->vcpu.arch.hflags = 0;
1498 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1499 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1500 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1501 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1502 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1503 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1504 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1505 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1507 set_dr_intercepts(svm);
1509 set_exception_intercept(svm, PF_VECTOR);
1510 set_exception_intercept(svm, UD_VECTOR);
1511 set_exception_intercept(svm, MC_VECTOR);
1512 set_exception_intercept(svm, AC_VECTOR);
1513 set_exception_intercept(svm, DB_VECTOR);
1515 * Guest access to VMware backdoor ports could legitimately
1516 * trigger #GP because of TSS I/O permission bitmap.
1517 * We intercept those #GP and allow access to them anyway
1520 if (enable_vmware_backdoor)
1521 set_exception_intercept(svm, GP_VECTOR);
1523 set_intercept(svm, INTERCEPT_INTR);
1524 set_intercept(svm, INTERCEPT_NMI);
1525 set_intercept(svm, INTERCEPT_SMI);
1526 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1527 set_intercept(svm, INTERCEPT_RDPMC);
1528 set_intercept(svm, INTERCEPT_CPUID);
1529 set_intercept(svm, INTERCEPT_INVD);
1530 set_intercept(svm, INTERCEPT_INVLPG);
1531 set_intercept(svm, INTERCEPT_INVLPGA);
1532 set_intercept(svm, INTERCEPT_IOIO_PROT);
1533 set_intercept(svm, INTERCEPT_MSR_PROT);
1534 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1535 set_intercept(svm, INTERCEPT_SHUTDOWN);
1536 set_intercept(svm, INTERCEPT_VMRUN);
1537 set_intercept(svm, INTERCEPT_VMMCALL);
1538 set_intercept(svm, INTERCEPT_VMLOAD);
1539 set_intercept(svm, INTERCEPT_VMSAVE);
1540 set_intercept(svm, INTERCEPT_STGI);
1541 set_intercept(svm, INTERCEPT_CLGI);
1542 set_intercept(svm, INTERCEPT_SKINIT);
1543 set_intercept(svm, INTERCEPT_WBINVD);
1544 set_intercept(svm, INTERCEPT_XSETBV);
1545 set_intercept(svm, INTERCEPT_RDPRU);
1546 set_intercept(svm, INTERCEPT_RSM);
1548 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1549 set_intercept(svm, INTERCEPT_MONITOR);
1550 set_intercept(svm, INTERCEPT_MWAIT);
1553 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1554 set_intercept(svm, INTERCEPT_HLT);
1556 control->iopm_base_pa = __sme_set(iopm_base);
1557 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1558 control->int_ctl = V_INTR_MASKING_MASK;
1560 init_seg(&save->es);
1561 init_seg(&save->ss);
1562 init_seg(&save->ds);
1563 init_seg(&save->fs);
1564 init_seg(&save->gs);
1566 save->cs.selector = 0xf000;
1567 save->cs.base = 0xffff0000;
1568 /* Executable/Readable Code Segment */
1569 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1570 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1571 save->cs.limit = 0xffff;
1573 save->gdtr.limit = 0xffff;
1574 save->idtr.limit = 0xffff;
1576 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1577 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1579 svm_set_efer(&svm->vcpu, 0);
1580 save->dr6 = 0xffff0ff0;
1581 kvm_set_rflags(&svm->vcpu, 2);
1582 save->rip = 0x0000fff0;
1583 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1586 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1587 * It also updates the guest-visible cr0 value.
1589 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1590 kvm_mmu_reset_context(&svm->vcpu);
1592 save->cr4 = X86_CR4_PAE;
1596 /* Setup VMCB for Nested Paging */
1597 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1598 clr_intercept(svm, INTERCEPT_INVLPG);
1599 clr_exception_intercept(svm, PF_VECTOR);
1600 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1601 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1602 save->g_pat = svm->vcpu.arch.pat;
1606 svm->asid_generation = 0;
1608 svm->nested.vmcb = 0;
1609 svm->vcpu.arch.hflags = 0;
1611 if (pause_filter_count) {
1612 control->pause_filter_count = pause_filter_count;
1613 if (pause_filter_thresh)
1614 control->pause_filter_thresh = pause_filter_thresh;
1615 set_intercept(svm, INTERCEPT_PAUSE);
1617 clr_intercept(svm, INTERCEPT_PAUSE);
1620 if (kvm_vcpu_apicv_active(&svm->vcpu))
1621 avic_init_vmcb(svm);
1624 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1625 * in VMCB and clear intercepts to avoid #VMEXIT.
1628 clr_intercept(svm, INTERCEPT_VMLOAD);
1629 clr_intercept(svm, INTERCEPT_VMSAVE);
1630 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1634 clr_intercept(svm, INTERCEPT_STGI);
1635 clr_intercept(svm, INTERCEPT_CLGI);
1636 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1639 if (sev_guest(svm->vcpu.kvm)) {
1640 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1641 clr_exception_intercept(svm, UD_VECTOR);
1644 mark_all_dirty(svm->vmcb);
1650 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1653 u64 *avic_physical_id_table;
1654 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1656 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1659 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1661 return &avic_physical_id_table[index];
1666 * AVIC hardware walks the nested page table to check permissions,
1667 * but does not use the SPA address specified in the leaf page
1668 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1669 * field of the VMCB. Therefore, we set up the
1670 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1672 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1674 struct kvm *kvm = vcpu->kvm;
1677 mutex_lock(&kvm->slots_lock);
1678 if (kvm->arch.apic_access_page_done)
1681 ret = __x86_set_memory_region(kvm,
1682 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1683 APIC_DEFAULT_PHYS_BASE,
1688 kvm->arch.apic_access_page_done = true;
1690 mutex_unlock(&kvm->slots_lock);
1694 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1697 u64 *entry, new_entry;
1698 int id = vcpu->vcpu_id;
1699 struct vcpu_svm *svm = to_svm(vcpu);
1701 ret = avic_init_access_page(vcpu);
1705 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1708 if (!svm->vcpu.arch.apic->regs)
1711 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1713 /* Setting AVIC backing page address in the phy APIC ID table */
1714 entry = avic_get_physical_id_entry(vcpu, id);
1718 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1719 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1720 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1721 WRITE_ONCE(*entry, new_entry);
1723 svm->avic_physical_id_cache = entry;
1728 static void sev_asid_free(int asid)
1730 struct svm_cpu_data *sd;
1733 mutex_lock(&sev_bitmap_lock);
1736 __clear_bit(pos, sev_asid_bitmap);
1738 for_each_possible_cpu(cpu) {
1739 sd = per_cpu(svm_data, cpu);
1740 sd->sev_vmcbs[pos] = NULL;
1743 mutex_unlock(&sev_bitmap_lock);
1746 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1748 struct sev_data_decommission *decommission;
1749 struct sev_data_deactivate *data;
1754 data = kzalloc(sizeof(*data), GFP_KERNEL);
1758 /* deactivate handle */
1759 data->handle = handle;
1762 * Guard against a parallel DEACTIVATE command before the DF_FLUSH
1763 * command has completed.
1765 mutex_lock(&sev_deactivate_lock);
1767 sev_guest_deactivate(data, NULL);
1769 wbinvd_on_all_cpus();
1770 sev_guest_df_flush(NULL);
1772 mutex_unlock(&sev_deactivate_lock);
1776 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1780 /* decommission handle */
1781 decommission->handle = handle;
1782 sev_guest_decommission(decommission, NULL);
1784 kfree(decommission);
1787 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1788 unsigned long ulen, unsigned long *n,
1791 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1792 unsigned long npages, npinned, size;
1793 unsigned long locked, lock_limit;
1794 struct page **pages;
1795 unsigned long first, last;
1797 if (ulen == 0 || uaddr + ulen < uaddr)
1800 /* Calculate number of pages. */
1801 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1802 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1803 npages = (last - first + 1);
1805 locked = sev->pages_locked + npages;
1806 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1807 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1808 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1812 /* Avoid using vmalloc for smaller buffers. */
1813 size = npages * sizeof(struct page *);
1814 if (size > PAGE_SIZE)
1815 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1818 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1823 /* Pin the user virtual address. */
1824 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1825 if (npinned != npages) {
1826 pr_err("SEV: Failure locking %lu pages.\n", npages);
1831 sev->pages_locked = locked;
1837 release_pages(pages, npinned);
1843 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1844 unsigned long npages)
1846 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1848 release_pages(pages, npages);
1850 sev->pages_locked -= npages;
1853 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1855 uint8_t *page_virtual;
1858 if (npages == 0 || pages == NULL)
1861 for (i = 0; i < npages; i++) {
1862 page_virtual = kmap_atomic(pages[i]);
1863 clflush_cache_range(page_virtual, PAGE_SIZE);
1864 kunmap_atomic(page_virtual);
1868 static void __unregister_enc_region_locked(struct kvm *kvm,
1869 struct enc_region *region)
1872 * The guest may change the memory encryption attribute from C=0 -> C=1
1873 * or vice versa for this memory range. Lets make sure caches are
1874 * flushed to ensure that guest data gets written into memory with
1877 sev_clflush_pages(region->pages, region->npages);
1879 sev_unpin_memory(kvm, region->pages, region->npages);
1880 list_del(®ion->list);
1884 static struct kvm *svm_vm_alloc(void)
1886 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1887 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1889 return &kvm_svm->kvm;
1892 static void svm_vm_free(struct kvm *kvm)
1894 vfree(to_kvm_svm(kvm));
1897 static void sev_vm_destroy(struct kvm *kvm)
1899 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1900 struct list_head *head = &sev->regions_list;
1901 struct list_head *pos, *q;
1903 if (!sev_guest(kvm))
1906 mutex_lock(&kvm->lock);
1909 * if userspace was terminated before unregistering the memory regions
1910 * then lets unpin all the registered memory.
1912 if (!list_empty(head)) {
1913 list_for_each_safe(pos, q, head) {
1914 __unregister_enc_region_locked(kvm,
1915 list_entry(pos, struct enc_region, list));
1919 mutex_unlock(&kvm->lock);
1921 sev_unbind_asid(kvm, sev->handle);
1922 sev_asid_free(sev->asid);
1925 static void avic_vm_destroy(struct kvm *kvm)
1927 unsigned long flags;
1928 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1933 if (kvm_svm->avic_logical_id_table_page)
1934 __free_page(kvm_svm->avic_logical_id_table_page);
1935 if (kvm_svm->avic_physical_id_table_page)
1936 __free_page(kvm_svm->avic_physical_id_table_page);
1938 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1939 hash_del(&kvm_svm->hnode);
1940 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1943 static void svm_vm_destroy(struct kvm *kvm)
1945 avic_vm_destroy(kvm);
1946 sev_vm_destroy(kvm);
1949 static int avic_vm_init(struct kvm *kvm)
1951 unsigned long flags;
1953 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1955 struct page *p_page;
1956 struct page *l_page;
1962 /* Allocating physical APIC ID table (4KB) */
1963 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1967 kvm_svm->avic_physical_id_table_page = p_page;
1968 clear_page(page_address(p_page));
1970 /* Allocating logical APIC ID table (4KB) */
1971 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1975 kvm_svm->avic_logical_id_table_page = l_page;
1976 clear_page(page_address(l_page));
1978 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1980 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1981 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1982 next_vm_id_wrapped = 1;
1985 /* Is it still in use? Only possible if wrapped at least once */
1986 if (next_vm_id_wrapped) {
1987 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1988 if (k2->avic_vm_id == vm_id)
1992 kvm_svm->avic_vm_id = vm_id;
1993 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1994 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1999 avic_vm_destroy(kvm);
2004 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2007 unsigned long flags;
2008 struct amd_svm_iommu_ir *ir;
2009 struct vcpu_svm *svm = to_svm(vcpu);
2011 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2015 * Here, we go through the per-vcpu ir_list to update all existing
2016 * interrupt remapping table entry targeting this vcpu.
2018 spin_lock_irqsave(&svm->ir_list_lock, flags);
2020 if (list_empty(&svm->ir_list))
2023 list_for_each_entry(ir, &svm->ir_list, node) {
2024 ret = amd_iommu_update_ga(cpu, r, ir->data);
2029 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2033 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2036 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2037 int h_physical_id = kvm_cpu_get_apicid(cpu);
2038 struct vcpu_svm *svm = to_svm(vcpu);
2040 if (!kvm_vcpu_apicv_active(vcpu))
2044 * Since the host physical APIC id is 8 bits,
2045 * we can support host APIC ID upto 255.
2047 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2050 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2051 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2053 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2054 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2056 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2057 if (svm->avic_is_running)
2058 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2060 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2061 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2062 svm->avic_is_running);
2065 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2068 struct vcpu_svm *svm = to_svm(vcpu);
2070 if (!kvm_vcpu_apicv_active(vcpu))
2073 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2074 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2075 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2077 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2078 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2082 * This function is called during VCPU halt/unhalt.
2084 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2086 struct vcpu_svm *svm = to_svm(vcpu);
2088 svm->avic_is_running = is_run;
2090 avic_vcpu_load(vcpu, vcpu->cpu);
2092 avic_vcpu_put(vcpu);
2095 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2097 struct vcpu_svm *svm = to_svm(vcpu);
2101 vcpu->arch.microcode_version = 0x01000065;
2103 svm->virt_spec_ctrl = 0;
2106 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2107 MSR_IA32_APICBASE_ENABLE;
2108 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2109 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2113 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2114 kvm_rdx_write(vcpu, eax);
2116 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2117 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2120 static int avic_init_vcpu(struct vcpu_svm *svm)
2124 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2127 ret = avic_init_backing_page(&svm->vcpu);
2131 INIT_LIST_HEAD(&svm->ir_list);
2132 spin_lock_init(&svm->ir_list_lock);
2133 svm->dfr_reg = APIC_DFR_FLAT;
2138 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2140 struct vcpu_svm *svm;
2142 struct page *msrpm_pages;
2143 struct page *hsave_page;
2144 struct page *nested_msrpm_pages;
2147 BUILD_BUG_ON_MSG(offsetof(struct vcpu_svm, vcpu) != 0,
2148 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
2150 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2156 svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
2157 GFP_KERNEL_ACCOUNT);
2158 if (!svm->vcpu.arch.user_fpu) {
2159 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
2161 goto free_partial_svm;
2164 svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2165 GFP_KERNEL_ACCOUNT);
2166 if (!svm->vcpu.arch.guest_fpu) {
2167 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2172 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2177 page = alloc_page(GFP_KERNEL_ACCOUNT);
2181 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2185 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2186 if (!nested_msrpm_pages)
2189 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2193 err = avic_init_vcpu(svm);
2197 /* We initialize this flag to true to make sure that the is_running
2198 * bit would be set the first time the vcpu is loaded.
2200 svm->avic_is_running = true;
2202 svm->nested.hsave = page_address(hsave_page);
2204 svm->msrpm = page_address(msrpm_pages);
2205 svm_vcpu_init_msrpm(svm->msrpm);
2207 svm->nested.msrpm = page_address(nested_msrpm_pages);
2208 svm_vcpu_init_msrpm(svm->nested.msrpm);
2210 svm->vmcb = page_address(page);
2211 clear_page(svm->vmcb);
2212 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2213 svm->asid_generation = 0;
2216 svm_init_osvw(&svm->vcpu);
2221 __free_page(hsave_page);
2223 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2225 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2229 kvm_vcpu_uninit(&svm->vcpu);
2231 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2233 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2235 kmem_cache_free(kvm_vcpu_cache, svm);
2237 return ERR_PTR(err);
2240 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2244 for_each_online_cpu(i)
2245 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2248 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2250 struct vcpu_svm *svm = to_svm(vcpu);
2253 * The vmcb page can be recycled, causing a false negative in
2254 * svm_vcpu_load(). So, ensure that no logical CPU has this
2255 * vmcb page recorded as its current vmcb.
2257 svm_clear_current_vmcb(svm->vmcb);
2259 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2260 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2261 __free_page(virt_to_page(svm->nested.hsave));
2262 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2263 kvm_vcpu_uninit(vcpu);
2264 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu);
2265 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2266 kmem_cache_free(kvm_vcpu_cache, svm);
2269 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2271 struct vcpu_svm *svm = to_svm(vcpu);
2272 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2275 if (unlikely(cpu != vcpu->cpu)) {
2276 svm->asid_generation = 0;
2277 mark_all_dirty(svm->vmcb);
2280 #ifdef CONFIG_X86_64
2281 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2283 savesegment(fs, svm->host.fs);
2284 savesegment(gs, svm->host.gs);
2285 svm->host.ldt = kvm_read_ldt();
2287 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2288 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2290 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2291 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2292 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2293 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2294 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2297 /* This assumes that the kernel never uses MSR_TSC_AUX */
2298 if (static_cpu_has(X86_FEATURE_RDTSCP))
2299 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2301 if (sd->current_vmcb != svm->vmcb) {
2302 sd->current_vmcb = svm->vmcb;
2303 indirect_branch_prediction_barrier();
2305 avic_vcpu_load(vcpu, cpu);
2308 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2310 struct vcpu_svm *svm = to_svm(vcpu);
2313 avic_vcpu_put(vcpu);
2315 ++vcpu->stat.host_state_reload;
2316 kvm_load_ldt(svm->host.ldt);
2317 #ifdef CONFIG_X86_64
2318 loadsegment(fs, svm->host.fs);
2319 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2320 load_gs_index(svm->host.gs);
2322 #ifdef CONFIG_X86_32_LAZY_GS
2323 loadsegment(gs, svm->host.gs);
2326 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2327 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2330 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2332 avic_set_running(vcpu, false);
2335 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2337 avic_set_running(vcpu, true);
2340 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2342 struct vcpu_svm *svm = to_svm(vcpu);
2343 unsigned long rflags = svm->vmcb->save.rflags;
2345 if (svm->nmi_singlestep) {
2346 /* Hide our flags if they were not set by the guest */
2347 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2348 rflags &= ~X86_EFLAGS_TF;
2349 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2350 rflags &= ~X86_EFLAGS_RF;
2355 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2357 if (to_svm(vcpu)->nmi_singlestep)
2358 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2361 * Any change of EFLAGS.VM is accompanied by a reload of SS
2362 * (caused by either a task switch or an inter-privilege IRET),
2363 * so we do not need to update the CPL here.
2365 to_svm(vcpu)->vmcb->save.rflags = rflags;
2368 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2371 case VCPU_EXREG_PDPTR:
2372 BUG_ON(!npt_enabled);
2373 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2380 static void svm_set_vintr(struct vcpu_svm *svm)
2382 set_intercept(svm, INTERCEPT_VINTR);
2385 static void svm_clear_vintr(struct vcpu_svm *svm)
2387 clr_intercept(svm, INTERCEPT_VINTR);
2390 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2392 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2395 case VCPU_SREG_CS: return &save->cs;
2396 case VCPU_SREG_DS: return &save->ds;
2397 case VCPU_SREG_ES: return &save->es;
2398 case VCPU_SREG_FS: return &save->fs;
2399 case VCPU_SREG_GS: return &save->gs;
2400 case VCPU_SREG_SS: return &save->ss;
2401 case VCPU_SREG_TR: return &save->tr;
2402 case VCPU_SREG_LDTR: return &save->ldtr;
2408 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2410 struct vmcb_seg *s = svm_seg(vcpu, seg);
2415 static void svm_get_segment(struct kvm_vcpu *vcpu,
2416 struct kvm_segment *var, int seg)
2418 struct vmcb_seg *s = svm_seg(vcpu, seg);
2420 var->base = s->base;
2421 var->limit = s->limit;
2422 var->selector = s->selector;
2423 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2424 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2425 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2426 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2427 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2428 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2429 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2432 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2433 * However, the SVM spec states that the G bit is not observed by the
2434 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2435 * So let's synthesize a legal G bit for all segments, this helps
2436 * running KVM nested. It also helps cross-vendor migration, because
2437 * Intel's vmentry has a check on the 'G' bit.
2439 var->g = s->limit > 0xfffff;
2442 * AMD's VMCB does not have an explicit unusable field, so emulate it
2443 * for cross vendor migration purposes by "not present"
2445 var->unusable = !var->present;
2450 * Work around a bug where the busy flag in the tr selector
2460 * The accessed bit must always be set in the segment
2461 * descriptor cache, although it can be cleared in the
2462 * descriptor, the cached bit always remains at 1. Since
2463 * Intel has a check on this, set it here to support
2464 * cross-vendor migration.
2471 * On AMD CPUs sometimes the DB bit in the segment
2472 * descriptor is left as 1, although the whole segment has
2473 * been made unusable. Clear it here to pass an Intel VMX
2474 * entry check when cross vendor migrating.
2478 /* This is symmetric with svm_set_segment() */
2479 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2484 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2486 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2491 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2493 struct vcpu_svm *svm = to_svm(vcpu);
2495 dt->size = svm->vmcb->save.idtr.limit;
2496 dt->address = svm->vmcb->save.idtr.base;
2499 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2501 struct vcpu_svm *svm = to_svm(vcpu);
2503 svm->vmcb->save.idtr.limit = dt->size;
2504 svm->vmcb->save.idtr.base = dt->address ;
2505 mark_dirty(svm->vmcb, VMCB_DT);
2508 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2510 struct vcpu_svm *svm = to_svm(vcpu);
2512 dt->size = svm->vmcb->save.gdtr.limit;
2513 dt->address = svm->vmcb->save.gdtr.base;
2516 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2518 struct vcpu_svm *svm = to_svm(vcpu);
2520 svm->vmcb->save.gdtr.limit = dt->size;
2521 svm->vmcb->save.gdtr.base = dt->address ;
2522 mark_dirty(svm->vmcb, VMCB_DT);
2525 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2529 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2533 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2537 static void update_cr0_intercept(struct vcpu_svm *svm)
2539 ulong gcr0 = svm->vcpu.arch.cr0;
2540 u64 *hcr0 = &svm->vmcb->save.cr0;
2542 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2543 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2545 mark_dirty(svm->vmcb, VMCB_CR);
2547 if (gcr0 == *hcr0) {
2548 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2549 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2551 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2552 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2556 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2558 struct vcpu_svm *svm = to_svm(vcpu);
2560 #ifdef CONFIG_X86_64
2561 if (vcpu->arch.efer & EFER_LME) {
2562 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2563 vcpu->arch.efer |= EFER_LMA;
2564 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2567 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2568 vcpu->arch.efer &= ~EFER_LMA;
2569 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2573 vcpu->arch.cr0 = cr0;
2576 cr0 |= X86_CR0_PG | X86_CR0_WP;
2579 * re-enable caching here because the QEMU bios
2580 * does not do it - this results in some delay at
2583 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2584 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2585 svm->vmcb->save.cr0 = cr0;
2586 mark_dirty(svm->vmcb, VMCB_CR);
2587 update_cr0_intercept(svm);
2590 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2592 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2593 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2595 if (cr4 & X86_CR4_VMXE)
2598 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2599 svm_flush_tlb(vcpu, true);
2601 vcpu->arch.cr4 = cr4;
2604 cr4 |= host_cr4_mce;
2605 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2606 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2610 static void svm_set_segment(struct kvm_vcpu *vcpu,
2611 struct kvm_segment *var, int seg)
2613 struct vcpu_svm *svm = to_svm(vcpu);
2614 struct vmcb_seg *s = svm_seg(vcpu, seg);
2616 s->base = var->base;
2617 s->limit = var->limit;
2618 s->selector = var->selector;
2619 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2620 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2621 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2622 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2623 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2624 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2625 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2626 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2629 * This is always accurate, except if SYSRET returned to a segment
2630 * with SS.DPL != 3. Intel does not have this quirk, and always
2631 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2632 * would entail passing the CPL to userspace and back.
2634 if (seg == VCPU_SREG_SS)
2635 /* This is symmetric with svm_get_segment() */
2636 svm->vmcb->save.cpl = (var->dpl & 3);
2638 mark_dirty(svm->vmcb, VMCB_SEG);
2641 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2643 struct vcpu_svm *svm = to_svm(vcpu);
2645 clr_exception_intercept(svm, BP_VECTOR);
2647 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2648 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2649 set_exception_intercept(svm, BP_VECTOR);
2651 vcpu->guest_debug = 0;
2654 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2656 if (sd->next_asid > sd->max_asid) {
2657 ++sd->asid_generation;
2658 sd->next_asid = sd->min_asid;
2659 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2662 svm->asid_generation = sd->asid_generation;
2663 svm->vmcb->control.asid = sd->next_asid++;
2665 mark_dirty(svm->vmcb, VMCB_ASID);
2668 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2670 return to_svm(vcpu)->vmcb->save.dr6;
2673 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2675 struct vcpu_svm *svm = to_svm(vcpu);
2677 svm->vmcb->save.dr6 = value;
2678 mark_dirty(svm->vmcb, VMCB_DR);
2681 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2683 struct vcpu_svm *svm = to_svm(vcpu);
2685 get_debugreg(vcpu->arch.db[0], 0);
2686 get_debugreg(vcpu->arch.db[1], 1);
2687 get_debugreg(vcpu->arch.db[2], 2);
2688 get_debugreg(vcpu->arch.db[3], 3);
2689 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2690 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2692 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2693 set_dr_intercepts(svm);
2696 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2698 struct vcpu_svm *svm = to_svm(vcpu);
2700 svm->vmcb->save.dr7 = value;
2701 mark_dirty(svm->vmcb, VMCB_DR);
2704 static int pf_interception(struct vcpu_svm *svm)
2706 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2707 u64 error_code = svm->vmcb->control.exit_info_1;
2709 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2710 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2711 svm->vmcb->control.insn_bytes : NULL,
2712 svm->vmcb->control.insn_len);
2715 static int npf_interception(struct vcpu_svm *svm)
2717 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2718 u64 error_code = svm->vmcb->control.exit_info_1;
2720 trace_kvm_page_fault(fault_address, error_code);
2721 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2722 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2723 svm->vmcb->control.insn_bytes : NULL,
2724 svm->vmcb->control.insn_len);
2727 static int db_interception(struct vcpu_svm *svm)
2729 struct kvm_run *kvm_run = svm->vcpu.run;
2730 struct kvm_vcpu *vcpu = &svm->vcpu;
2732 if (!(svm->vcpu.guest_debug &
2733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2734 !svm->nmi_singlestep) {
2735 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2739 if (svm->nmi_singlestep) {
2740 disable_nmi_singlestep(svm);
2741 /* Make sure we check for pending NMIs upon entry */
2742 kvm_make_request(KVM_REQ_EVENT, vcpu);
2745 if (svm->vcpu.guest_debug &
2746 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2747 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2748 kvm_run->debug.arch.pc =
2749 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2750 kvm_run->debug.arch.exception = DB_VECTOR;
2757 static int bp_interception(struct vcpu_svm *svm)
2759 struct kvm_run *kvm_run = svm->vcpu.run;
2761 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2762 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2763 kvm_run->debug.arch.exception = BP_VECTOR;
2767 static int ud_interception(struct vcpu_svm *svm)
2769 return handle_ud(&svm->vcpu);
2772 static int ac_interception(struct vcpu_svm *svm)
2774 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2778 static int gp_interception(struct vcpu_svm *svm)
2780 struct kvm_vcpu *vcpu = &svm->vcpu;
2781 u32 error_code = svm->vmcb->control.exit_info_1;
2783 WARN_ON_ONCE(!enable_vmware_backdoor);
2786 * VMware backdoor emulation on #GP interception only handles IN{S},
2787 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2790 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2793 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
2796 static bool is_erratum_383(void)
2801 if (!erratum_383_found)
2804 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2808 /* Bit 62 may or may not be set for this mce */
2809 value &= ~(1ULL << 62);
2811 if (value != 0xb600000000010015ULL)
2814 /* Clear MCi_STATUS registers */
2815 for (i = 0; i < 6; ++i)
2816 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2818 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2822 value &= ~(1ULL << 2);
2823 low = lower_32_bits(value);
2824 high = upper_32_bits(value);
2826 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2829 /* Flush tlb to evict multi-match entries */
2835 static void svm_handle_mce(struct vcpu_svm *svm)
2837 if (is_erratum_383()) {
2839 * Erratum 383 triggered. Guest state is corrupt so kill the
2842 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2844 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2850 * On an #MC intercept the MCE handler is not called automatically in
2851 * the host. So do it by hand here.
2855 /* not sure if we ever come back to this point */
2860 static int mc_interception(struct vcpu_svm *svm)
2865 static int shutdown_interception(struct vcpu_svm *svm)
2867 struct kvm_run *kvm_run = svm->vcpu.run;
2870 * VMCB is undefined after a SHUTDOWN intercept
2871 * so reinitialize it.
2873 clear_page(svm->vmcb);
2876 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2880 static int io_interception(struct vcpu_svm *svm)
2882 struct kvm_vcpu *vcpu = &svm->vcpu;
2883 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2884 int size, in, string;
2887 ++svm->vcpu.stat.io_exits;
2888 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2889 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2891 return kvm_emulate_instruction(vcpu, 0);
2893 port = io_info >> 16;
2894 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2895 svm->next_rip = svm->vmcb->control.exit_info_2;
2897 return kvm_fast_pio(&svm->vcpu, size, port, in);
2900 static int nmi_interception(struct vcpu_svm *svm)
2905 static int intr_interception(struct vcpu_svm *svm)
2907 ++svm->vcpu.stat.irq_exits;
2911 static int nop_on_interception(struct vcpu_svm *svm)
2916 static int halt_interception(struct vcpu_svm *svm)
2918 return kvm_emulate_halt(&svm->vcpu);
2921 static int vmmcall_interception(struct vcpu_svm *svm)
2923 return kvm_emulate_hypercall(&svm->vcpu);
2926 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2928 struct vcpu_svm *svm = to_svm(vcpu);
2930 return svm->nested.nested_cr3;
2933 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2935 struct vcpu_svm *svm = to_svm(vcpu);
2936 u64 cr3 = svm->nested.nested_cr3;
2940 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2941 offset_in_page(cr3) + index * 8, 8);
2947 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2950 struct vcpu_svm *svm = to_svm(vcpu);
2952 svm->vmcb->control.nested_cr3 = __sme_set(root);
2953 mark_dirty(svm->vmcb, VMCB_NPT);
2956 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2957 struct x86_exception *fault)
2959 struct vcpu_svm *svm = to_svm(vcpu);
2961 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2963 * TODO: track the cause of the nested page fault, and
2964 * correctly fill in the high bits of exit_info_1.
2966 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2967 svm->vmcb->control.exit_code_hi = 0;
2968 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2969 svm->vmcb->control.exit_info_2 = fault->address;
2972 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2973 svm->vmcb->control.exit_info_1 |= fault->error_code;
2976 * The present bit is always zero for page structure faults on real
2979 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2980 svm->vmcb->control.exit_info_1 &= ~1;
2982 nested_svm_vmexit(svm);
2985 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2987 WARN_ON(mmu_is_nested(vcpu));
2989 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2990 kvm_init_shadow_mmu(vcpu);
2991 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
2992 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
2993 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
2994 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2995 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2996 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2997 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3000 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3002 vcpu->arch.mmu = &vcpu->arch.root_mmu;
3003 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3006 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3008 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3009 !is_paging(&svm->vcpu)) {
3010 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3014 if (svm->vmcb->save.cpl) {
3015 kvm_inject_gp(&svm->vcpu, 0);
3022 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3023 bool has_error_code, u32 error_code)
3027 if (!is_guest_mode(&svm->vcpu))
3030 vmexit = nested_svm_intercept(svm);
3031 if (vmexit != NESTED_EXIT_DONE)
3034 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3035 svm->vmcb->control.exit_code_hi = 0;
3036 svm->vmcb->control.exit_info_1 = error_code;
3039 * EXITINFO2 is undefined for all exception intercepts other
3042 if (svm->vcpu.arch.exception.nested_apf)
3043 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3044 else if (svm->vcpu.arch.exception.has_payload)
3045 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3047 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3049 svm->nested.exit_required = true;
3053 /* This function returns true if it is save to enable the irq window */
3054 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3056 if (!is_guest_mode(&svm->vcpu))
3059 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3062 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3066 * if vmexit was already requested (by intercepted exception
3067 * for instance) do not overwrite it with "external interrupt"
3070 if (svm->nested.exit_required)
3073 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3074 svm->vmcb->control.exit_info_1 = 0;
3075 svm->vmcb->control.exit_info_2 = 0;
3077 if (svm->nested.intercept & 1ULL) {
3079 * The #vmexit can't be emulated here directly because this
3080 * code path runs with irqs and preemption disabled. A
3081 * #vmexit emulation might sleep. Only signal request for
3084 svm->nested.exit_required = true;
3085 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3092 /* This function returns true if it is save to enable the nmi window */
3093 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3095 if (!is_guest_mode(&svm->vcpu))
3098 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3101 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3102 svm->nested.exit_required = true;
3107 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3109 unsigned port, size, iopm_len;
3114 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3115 return NESTED_EXIT_HOST;
3117 port = svm->vmcb->control.exit_info_1 >> 16;
3118 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3119 SVM_IOIO_SIZE_SHIFT;
3120 gpa = svm->nested.vmcb_iopm + (port / 8);
3121 start_bit = port % 8;
3122 iopm_len = (start_bit + size > 8) ? 2 : 1;
3123 mask = (0xf >> (4 - size)) << start_bit;
3126 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3127 return NESTED_EXIT_DONE;
3129 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3132 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3134 u32 offset, msr, value;
3137 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3138 return NESTED_EXIT_HOST;
3140 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3141 offset = svm_msrpm_offset(msr);
3142 write = svm->vmcb->control.exit_info_1 & 1;
3143 mask = 1 << ((2 * (msr & 0xf)) + write);
3145 if (offset == MSR_INVALID)
3146 return NESTED_EXIT_DONE;
3148 /* Offset is in 32 bit units but need in 8 bit units */
3151 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3152 return NESTED_EXIT_DONE;
3154 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3157 /* DB exceptions for our internal use must not cause vmexit */
3158 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3162 /* if we're not singlestepping, it's not ours */
3163 if (!svm->nmi_singlestep)
3164 return NESTED_EXIT_DONE;
3166 /* if it's not a singlestep exception, it's not ours */
3167 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3168 return NESTED_EXIT_DONE;
3169 if (!(dr6 & DR6_BS))
3170 return NESTED_EXIT_DONE;
3172 /* if the guest is singlestepping, it should get the vmexit */
3173 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3174 disable_nmi_singlestep(svm);
3175 return NESTED_EXIT_DONE;
3178 /* it's ours, the nested hypervisor must not see this one */
3179 return NESTED_EXIT_HOST;
3182 static int nested_svm_exit_special(struct vcpu_svm *svm)
3184 u32 exit_code = svm->vmcb->control.exit_code;
3186 switch (exit_code) {
3189 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3190 return NESTED_EXIT_HOST;
3192 /* For now we are always handling NPFs when using them */
3194 return NESTED_EXIT_HOST;
3196 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3197 /* When we're shadowing, trap PFs, but not async PF */
3198 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3199 return NESTED_EXIT_HOST;
3205 return NESTED_EXIT_CONTINUE;
3209 * If this function returns true, this #vmexit was already handled
3211 static int nested_svm_intercept(struct vcpu_svm *svm)
3213 u32 exit_code = svm->vmcb->control.exit_code;
3214 int vmexit = NESTED_EXIT_HOST;
3216 switch (exit_code) {
3218 vmexit = nested_svm_exit_handled_msr(svm);
3221 vmexit = nested_svm_intercept_ioio(svm);
3223 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3224 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3225 if (svm->nested.intercept_cr & bit)
3226 vmexit = NESTED_EXIT_DONE;
3229 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3230 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3231 if (svm->nested.intercept_dr & bit)
3232 vmexit = NESTED_EXIT_DONE;
3235 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3236 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3237 if (svm->nested.intercept_exceptions & excp_bits) {
3238 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3239 vmexit = nested_svm_intercept_db(svm);
3241 vmexit = NESTED_EXIT_DONE;
3243 /* async page fault always cause vmexit */
3244 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3245 svm->vcpu.arch.exception.nested_apf != 0)
3246 vmexit = NESTED_EXIT_DONE;
3249 case SVM_EXIT_ERR: {
3250 vmexit = NESTED_EXIT_DONE;
3254 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3255 if (svm->nested.intercept & exit_bits)
3256 vmexit = NESTED_EXIT_DONE;
3263 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3267 vmexit = nested_svm_intercept(svm);
3269 if (vmexit == NESTED_EXIT_DONE)
3270 nested_svm_vmexit(svm);
3275 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3277 struct vmcb_control_area *dst = &dst_vmcb->control;
3278 struct vmcb_control_area *from = &from_vmcb->control;
3280 dst->intercept_cr = from->intercept_cr;
3281 dst->intercept_dr = from->intercept_dr;
3282 dst->intercept_exceptions = from->intercept_exceptions;
3283 dst->intercept = from->intercept;
3284 dst->iopm_base_pa = from->iopm_base_pa;
3285 dst->msrpm_base_pa = from->msrpm_base_pa;
3286 dst->tsc_offset = from->tsc_offset;
3287 dst->asid = from->asid;
3288 dst->tlb_ctl = from->tlb_ctl;
3289 dst->int_ctl = from->int_ctl;
3290 dst->int_vector = from->int_vector;
3291 dst->int_state = from->int_state;
3292 dst->exit_code = from->exit_code;
3293 dst->exit_code_hi = from->exit_code_hi;
3294 dst->exit_info_1 = from->exit_info_1;
3295 dst->exit_info_2 = from->exit_info_2;
3296 dst->exit_int_info = from->exit_int_info;
3297 dst->exit_int_info_err = from->exit_int_info_err;
3298 dst->nested_ctl = from->nested_ctl;
3299 dst->event_inj = from->event_inj;
3300 dst->event_inj_err = from->event_inj_err;
3301 dst->nested_cr3 = from->nested_cr3;
3302 dst->virt_ext = from->virt_ext;
3303 dst->pause_filter_count = from->pause_filter_count;
3304 dst->pause_filter_thresh = from->pause_filter_thresh;
3307 static int nested_svm_vmexit(struct vcpu_svm *svm)
3310 struct vmcb *nested_vmcb;
3311 struct vmcb *hsave = svm->nested.hsave;
3312 struct vmcb *vmcb = svm->vmcb;
3313 struct kvm_host_map map;
3315 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3316 vmcb->control.exit_info_1,
3317 vmcb->control.exit_info_2,
3318 vmcb->control.exit_int_info,
3319 vmcb->control.exit_int_info_err,
3322 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3325 kvm_inject_gp(&svm->vcpu, 0);
3329 nested_vmcb = map.hva;
3331 /* Exit Guest-Mode */
3332 leave_guest_mode(&svm->vcpu);
3333 svm->nested.vmcb = 0;
3335 /* Give the current vmcb to the guest */
3338 nested_vmcb->save.es = vmcb->save.es;
3339 nested_vmcb->save.cs = vmcb->save.cs;
3340 nested_vmcb->save.ss = vmcb->save.ss;
3341 nested_vmcb->save.ds = vmcb->save.ds;
3342 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3343 nested_vmcb->save.idtr = vmcb->save.idtr;
3344 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3345 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3346 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3347 nested_vmcb->save.cr2 = vmcb->save.cr2;
3348 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3349 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3350 nested_vmcb->save.rip = vmcb->save.rip;
3351 nested_vmcb->save.rsp = vmcb->save.rsp;
3352 nested_vmcb->save.rax = vmcb->save.rax;
3353 nested_vmcb->save.dr7 = vmcb->save.dr7;
3354 nested_vmcb->save.dr6 = vmcb->save.dr6;
3355 nested_vmcb->save.cpl = vmcb->save.cpl;
3357 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3358 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3359 nested_vmcb->control.int_state = vmcb->control.int_state;
3360 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3361 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3362 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3363 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3364 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3365 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3367 if (svm->nrips_enabled)
3368 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3371 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3372 * to make sure that we do not lose injected events. So check event_inj
3373 * here and copy it to exit_int_info if it is valid.
3374 * Exit_int_info and event_inj can't be both valid because the case
3375 * below only happens on a VMRUN instruction intercept which has
3376 * no valid exit_int_info set.
3378 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3379 struct vmcb_control_area *nc = &nested_vmcb->control;
3381 nc->exit_int_info = vmcb->control.event_inj;
3382 nc->exit_int_info_err = vmcb->control.event_inj_err;
3385 nested_vmcb->control.tlb_ctl = 0;
3386 nested_vmcb->control.event_inj = 0;
3387 nested_vmcb->control.event_inj_err = 0;
3389 nested_vmcb->control.pause_filter_count =
3390 svm->vmcb->control.pause_filter_count;
3391 nested_vmcb->control.pause_filter_thresh =
3392 svm->vmcb->control.pause_filter_thresh;
3394 /* We always set V_INTR_MASKING and remember the old value in hflags */
3395 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3396 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3398 /* Restore the original control entries */
3399 copy_vmcb_control_area(vmcb, hsave);
3401 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3402 kvm_clear_exception_queue(&svm->vcpu);
3403 kvm_clear_interrupt_queue(&svm->vcpu);
3405 svm->nested.nested_cr3 = 0;
3407 /* Restore selected save entries */
3408 svm->vmcb->save.es = hsave->save.es;
3409 svm->vmcb->save.cs = hsave->save.cs;
3410 svm->vmcb->save.ss = hsave->save.ss;
3411 svm->vmcb->save.ds = hsave->save.ds;
3412 svm->vmcb->save.gdtr = hsave->save.gdtr;
3413 svm->vmcb->save.idtr = hsave->save.idtr;
3414 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3415 svm_set_efer(&svm->vcpu, hsave->save.efer);
3416 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3417 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3419 svm->vmcb->save.cr3 = hsave->save.cr3;
3420 svm->vcpu.arch.cr3 = hsave->save.cr3;
3422 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3424 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3425 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3426 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3427 svm->vmcb->save.dr7 = 0;
3428 svm->vmcb->save.cpl = 0;
3429 svm->vmcb->control.exit_int_info = 0;
3431 mark_all_dirty(svm->vmcb);
3433 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3435 nested_svm_uninit_mmu_context(&svm->vcpu);
3436 kvm_mmu_reset_context(&svm->vcpu);
3437 kvm_mmu_load(&svm->vcpu);
3440 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3441 * doesn't end up in L1.
3443 svm->vcpu.arch.nmi_injected = false;
3444 kvm_clear_exception_queue(&svm->vcpu);
3445 kvm_clear_interrupt_queue(&svm->vcpu);
3450 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3453 * This function merges the msr permission bitmaps of kvm and the
3454 * nested vmcb. It is optimized in that it only merges the parts where
3455 * the kvm msr permission bitmap may contain zero bits
3459 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3462 for (i = 0; i < MSRPM_OFFSETS; i++) {
3466 if (msrpm_offsets[i] == 0xffffffff)
3469 p = msrpm_offsets[i];
3470 offset = svm->nested.vmcb_msrpm + (p * 4);
3472 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3475 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3478 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3483 static bool nested_vmcb_checks(struct vmcb *vmcb)
3485 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3488 if (vmcb->control.asid == 0)
3491 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3498 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3499 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3501 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3502 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3504 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3506 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3507 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3508 nested_svm_init_mmu_context(&svm->vcpu);
3511 /* Load the nested guest state */
3512 svm->vmcb->save.es = nested_vmcb->save.es;
3513 svm->vmcb->save.cs = nested_vmcb->save.cs;
3514 svm->vmcb->save.ss = nested_vmcb->save.ss;
3515 svm->vmcb->save.ds = nested_vmcb->save.ds;
3516 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3517 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3518 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3519 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3520 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3521 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3523 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3524 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3526 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3528 /* Guest paging mode is active - reset mmu */
3529 kvm_mmu_reset_context(&svm->vcpu);
3531 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3532 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3533 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3534 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3536 /* In case we don't even reach vcpu_run, the fields are not updated */
3537 svm->vmcb->save.rax = nested_vmcb->save.rax;
3538 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3539 svm->vmcb->save.rip = nested_vmcb->save.rip;
3540 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3541 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3542 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3544 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3545 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3547 /* cache intercepts */
3548 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3549 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3550 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3551 svm->nested.intercept = nested_vmcb->control.intercept;
3553 svm_flush_tlb(&svm->vcpu, true);
3554 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3555 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3556 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3558 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3560 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3561 /* We only want the cr8 intercept bits of the guest */
3562 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3563 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3566 /* We don't want to see VMMCALLs from a nested guest */
3567 clr_intercept(svm, INTERCEPT_VMMCALL);
3569 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3570 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3572 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3573 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3574 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3575 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3576 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3578 svm->vmcb->control.pause_filter_count =
3579 nested_vmcb->control.pause_filter_count;
3580 svm->vmcb->control.pause_filter_thresh =
3581 nested_vmcb->control.pause_filter_thresh;
3583 kvm_vcpu_unmap(&svm->vcpu, map, true);
3585 /* Enter Guest-Mode */
3586 enter_guest_mode(&svm->vcpu);
3589 * Merge guest and host intercepts - must be called with vcpu in
3590 * guest-mode to take affect here
3592 recalc_intercepts(svm);
3594 svm->nested.vmcb = vmcb_gpa;
3598 mark_all_dirty(svm->vmcb);
3601 static int nested_svm_vmrun(struct vcpu_svm *svm)
3604 struct vmcb *nested_vmcb;
3605 struct vmcb *hsave = svm->nested.hsave;
3606 struct vmcb *vmcb = svm->vmcb;
3607 struct kvm_host_map map;
3610 vmcb_gpa = svm->vmcb->save.rax;
3612 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3613 if (ret == -EINVAL) {
3614 kvm_inject_gp(&svm->vcpu, 0);
3617 return kvm_skip_emulated_instruction(&svm->vcpu);
3620 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3622 nested_vmcb = map.hva;
3624 if (!nested_vmcb_checks(nested_vmcb)) {
3625 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3626 nested_vmcb->control.exit_code_hi = 0;
3627 nested_vmcb->control.exit_info_1 = 0;
3628 nested_vmcb->control.exit_info_2 = 0;
3630 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3635 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3636 nested_vmcb->save.rip,
3637 nested_vmcb->control.int_ctl,
3638 nested_vmcb->control.event_inj,
3639 nested_vmcb->control.nested_ctl);
3641 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3642 nested_vmcb->control.intercept_cr >> 16,
3643 nested_vmcb->control.intercept_exceptions,
3644 nested_vmcb->control.intercept);
3646 /* Clear internal status */
3647 kvm_clear_exception_queue(&svm->vcpu);
3648 kvm_clear_interrupt_queue(&svm->vcpu);
3651 * Save the old vmcb, so we don't need to pick what we save, but can
3652 * restore everything when a VMEXIT occurs
3654 hsave->save.es = vmcb->save.es;
3655 hsave->save.cs = vmcb->save.cs;
3656 hsave->save.ss = vmcb->save.ss;
3657 hsave->save.ds = vmcb->save.ds;
3658 hsave->save.gdtr = vmcb->save.gdtr;
3659 hsave->save.idtr = vmcb->save.idtr;
3660 hsave->save.efer = svm->vcpu.arch.efer;
3661 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3662 hsave->save.cr4 = svm->vcpu.arch.cr4;
3663 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3664 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3665 hsave->save.rsp = vmcb->save.rsp;
3666 hsave->save.rax = vmcb->save.rax;
3668 hsave->save.cr3 = vmcb->save.cr3;
3670 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3672 copy_vmcb_control_area(hsave, vmcb);
3674 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3676 if (!nested_svm_vmrun_msrpm(svm)) {
3677 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3678 svm->vmcb->control.exit_code_hi = 0;
3679 svm->vmcb->control.exit_info_1 = 0;
3680 svm->vmcb->control.exit_info_2 = 0;
3682 nested_svm_vmexit(svm);
3688 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3690 to_vmcb->save.fs = from_vmcb->save.fs;
3691 to_vmcb->save.gs = from_vmcb->save.gs;
3692 to_vmcb->save.tr = from_vmcb->save.tr;
3693 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3694 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3695 to_vmcb->save.star = from_vmcb->save.star;
3696 to_vmcb->save.lstar = from_vmcb->save.lstar;
3697 to_vmcb->save.cstar = from_vmcb->save.cstar;
3698 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3699 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3700 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3701 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3704 static int vmload_interception(struct vcpu_svm *svm)
3706 struct vmcb *nested_vmcb;
3707 struct kvm_host_map map;
3710 if (nested_svm_check_permissions(svm))
3713 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3716 kvm_inject_gp(&svm->vcpu, 0);
3720 nested_vmcb = map.hva;
3722 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3724 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3725 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3730 static int vmsave_interception(struct vcpu_svm *svm)
3732 struct vmcb *nested_vmcb;
3733 struct kvm_host_map map;
3736 if (nested_svm_check_permissions(svm))
3739 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3742 kvm_inject_gp(&svm->vcpu, 0);
3746 nested_vmcb = map.hva;
3748 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3750 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3751 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3756 static int vmrun_interception(struct vcpu_svm *svm)
3758 if (nested_svm_check_permissions(svm))
3761 return nested_svm_vmrun(svm);
3764 static int stgi_interception(struct vcpu_svm *svm)
3768 if (nested_svm_check_permissions(svm))
3772 * If VGIF is enabled, the STGI intercept is only added to
3773 * detect the opening of the SMI/NMI window; remove it now.
3775 if (vgif_enabled(svm))
3776 clr_intercept(svm, INTERCEPT_STGI);
3778 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3779 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3786 static int clgi_interception(struct vcpu_svm *svm)
3790 if (nested_svm_check_permissions(svm))
3793 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3797 /* After a CLGI no interrupts should come */
3798 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3799 svm_clear_vintr(svm);
3800 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3801 mark_dirty(svm->vmcb, VMCB_INTR);
3807 static int invlpga_interception(struct vcpu_svm *svm)
3809 struct kvm_vcpu *vcpu = &svm->vcpu;
3811 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3812 kvm_rax_read(&svm->vcpu));
3814 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3815 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3817 return kvm_skip_emulated_instruction(&svm->vcpu);
3820 static int skinit_interception(struct vcpu_svm *svm)
3822 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3824 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3828 static int wbinvd_interception(struct vcpu_svm *svm)
3830 return kvm_emulate_wbinvd(&svm->vcpu);
3833 static int xsetbv_interception(struct vcpu_svm *svm)
3835 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3836 u32 index = kvm_rcx_read(&svm->vcpu);
3838 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3839 return kvm_skip_emulated_instruction(&svm->vcpu);
3845 static int rdpru_interception(struct vcpu_svm *svm)
3847 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3851 static int task_switch_interception(struct vcpu_svm *svm)
3855 int int_type = svm->vmcb->control.exit_int_info &
3856 SVM_EXITINTINFO_TYPE_MASK;
3857 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3859 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3861 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3862 bool has_error_code = false;
3865 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3867 if (svm->vmcb->control.exit_info_2 &
3868 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3869 reason = TASK_SWITCH_IRET;
3870 else if (svm->vmcb->control.exit_info_2 &
3871 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3872 reason = TASK_SWITCH_JMP;
3874 reason = TASK_SWITCH_GATE;
3876 reason = TASK_SWITCH_CALL;
3878 if (reason == TASK_SWITCH_GATE) {
3880 case SVM_EXITINTINFO_TYPE_NMI:
3881 svm->vcpu.arch.nmi_injected = false;
3883 case SVM_EXITINTINFO_TYPE_EXEPT:
3884 if (svm->vmcb->control.exit_info_2 &
3885 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3886 has_error_code = true;
3888 (u32)svm->vmcb->control.exit_info_2;
3890 kvm_clear_exception_queue(&svm->vcpu);
3892 case SVM_EXITINTINFO_TYPE_INTR:
3893 kvm_clear_interrupt_queue(&svm->vcpu);
3900 if (reason != TASK_SWITCH_GATE ||
3901 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3902 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3903 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3904 if (!skip_emulated_instruction(&svm->vcpu))
3908 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3911 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3912 has_error_code, error_code);
3915 static int cpuid_interception(struct vcpu_svm *svm)
3917 return kvm_emulate_cpuid(&svm->vcpu);
3920 static int iret_interception(struct vcpu_svm *svm)
3922 ++svm->vcpu.stat.nmi_window_exits;
3923 clr_intercept(svm, INTERCEPT_IRET);
3924 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3925 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3926 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3930 static int invlpg_interception(struct vcpu_svm *svm)
3932 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3933 return kvm_emulate_instruction(&svm->vcpu, 0);
3935 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3936 return kvm_skip_emulated_instruction(&svm->vcpu);
3939 static int emulate_on_interception(struct vcpu_svm *svm)
3941 return kvm_emulate_instruction(&svm->vcpu, 0);
3944 static int rsm_interception(struct vcpu_svm *svm)
3946 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
3949 static int rdpmc_interception(struct vcpu_svm *svm)
3954 return emulate_on_interception(svm);
3956 err = kvm_rdpmc(&svm->vcpu);
3957 return kvm_complete_insn_gp(&svm->vcpu, err);
3960 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3963 unsigned long cr0 = svm->vcpu.arch.cr0;
3967 intercept = svm->nested.intercept;
3969 if (!is_guest_mode(&svm->vcpu) ||
3970 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3973 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3974 val &= ~SVM_CR0_SELECTIVE_MASK;
3977 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3978 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3984 #define CR_VALID (1ULL << 63)
3986 static int cr_interception(struct vcpu_svm *svm)
3992 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3993 return emulate_on_interception(svm);
3995 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3996 return emulate_on_interception(svm);
3998 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3999 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4000 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4002 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4005 if (cr >= 16) { /* mov to cr */
4007 val = kvm_register_read(&svm->vcpu, reg);
4010 if (!check_selective_cr0_intercepted(svm, val))
4011 err = kvm_set_cr0(&svm->vcpu, val);
4017 err = kvm_set_cr3(&svm->vcpu, val);
4020 err = kvm_set_cr4(&svm->vcpu, val);
4023 err = kvm_set_cr8(&svm->vcpu, val);
4026 WARN(1, "unhandled write to CR%d", cr);
4027 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4030 } else { /* mov from cr */
4033 val = kvm_read_cr0(&svm->vcpu);
4036 val = svm->vcpu.arch.cr2;
4039 val = kvm_read_cr3(&svm->vcpu);
4042 val = kvm_read_cr4(&svm->vcpu);
4045 val = kvm_get_cr8(&svm->vcpu);
4048 WARN(1, "unhandled read from CR%d", cr);
4049 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4052 kvm_register_write(&svm->vcpu, reg, val);
4054 return kvm_complete_insn_gp(&svm->vcpu, err);
4057 static int dr_interception(struct vcpu_svm *svm)
4062 if (svm->vcpu.guest_debug == 0) {
4064 * No more DR vmexits; force a reload of the debug registers
4065 * and reenter on this instruction. The next vmexit will
4066 * retrieve the full state of the debug registers.
4068 clr_dr_intercepts(svm);
4069 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4073 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4074 return emulate_on_interception(svm);
4076 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4077 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4079 if (dr >= 16) { /* mov to DRn */
4080 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4082 val = kvm_register_read(&svm->vcpu, reg);
4083 kvm_set_dr(&svm->vcpu, dr - 16, val);
4085 if (!kvm_require_dr(&svm->vcpu, dr))
4087 kvm_get_dr(&svm->vcpu, dr, &val);
4088 kvm_register_write(&svm->vcpu, reg, val);
4091 return kvm_skip_emulated_instruction(&svm->vcpu);
4094 static int cr8_write_interception(struct vcpu_svm *svm)
4096 struct kvm_run *kvm_run = svm->vcpu.run;
4099 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4100 /* instruction emulation calls kvm_set_cr8() */
4101 r = cr_interception(svm);
4102 if (lapic_in_kernel(&svm->vcpu))
4104 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4106 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4110 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4114 switch (msr->index) {
4115 case MSR_F10H_DECFG:
4116 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4117 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4126 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4128 struct vcpu_svm *svm = to_svm(vcpu);
4130 switch (msr_info->index) {
4132 msr_info->data = svm->vmcb->save.star;
4134 #ifdef CONFIG_X86_64
4136 msr_info->data = svm->vmcb->save.lstar;
4139 msr_info->data = svm->vmcb->save.cstar;
4141 case MSR_KERNEL_GS_BASE:
4142 msr_info->data = svm->vmcb->save.kernel_gs_base;
4144 case MSR_SYSCALL_MASK:
4145 msr_info->data = svm->vmcb->save.sfmask;
4148 case MSR_IA32_SYSENTER_CS:
4149 msr_info->data = svm->vmcb->save.sysenter_cs;
4151 case MSR_IA32_SYSENTER_EIP:
4152 msr_info->data = svm->sysenter_eip;
4154 case MSR_IA32_SYSENTER_ESP:
4155 msr_info->data = svm->sysenter_esp;
4158 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4160 msr_info->data = svm->tsc_aux;
4163 * Nobody will change the following 5 values in the VMCB so we can
4164 * safely return them on rdmsr. They will always be 0 until LBRV is
4167 case MSR_IA32_DEBUGCTLMSR:
4168 msr_info->data = svm->vmcb->save.dbgctl;
4170 case MSR_IA32_LASTBRANCHFROMIP:
4171 msr_info->data = svm->vmcb->save.br_from;
4173 case MSR_IA32_LASTBRANCHTOIP:
4174 msr_info->data = svm->vmcb->save.br_to;
4176 case MSR_IA32_LASTINTFROMIP:
4177 msr_info->data = svm->vmcb->save.last_excp_from;
4179 case MSR_IA32_LASTINTTOIP:
4180 msr_info->data = svm->vmcb->save.last_excp_to;
4182 case MSR_VM_HSAVE_PA:
4183 msr_info->data = svm->nested.hsave_msr;
4186 msr_info->data = svm->nested.vm_cr_msr;
4188 case MSR_IA32_SPEC_CTRL:
4189 if (!msr_info->host_initiated &&
4190 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4191 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4194 msr_info->data = svm->spec_ctrl;
4196 case MSR_AMD64_VIRT_SPEC_CTRL:
4197 if (!msr_info->host_initiated &&
4198 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4201 msr_info->data = svm->virt_spec_ctrl;
4203 case MSR_F15H_IC_CFG: {
4207 family = guest_cpuid_family(vcpu);
4208 model = guest_cpuid_model(vcpu);
4210 if (family < 0 || model < 0)
4211 return kvm_get_msr_common(vcpu, msr_info);
4215 if (family == 0x15 &&
4216 (model >= 0x2 && model < 0x20))
4217 msr_info->data = 0x1E;
4220 case MSR_F10H_DECFG:
4221 msr_info->data = svm->msr_decfg;
4224 return kvm_get_msr_common(vcpu, msr_info);
4229 static int rdmsr_interception(struct vcpu_svm *svm)
4231 return kvm_emulate_rdmsr(&svm->vcpu);
4234 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4236 struct vcpu_svm *svm = to_svm(vcpu);
4237 int svm_dis, chg_mask;
4239 if (data & ~SVM_VM_CR_VALID_MASK)
4242 chg_mask = SVM_VM_CR_VALID_MASK;
4244 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4245 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4247 svm->nested.vm_cr_msr &= ~chg_mask;
4248 svm->nested.vm_cr_msr |= (data & chg_mask);
4250 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4252 /* check for svm_disable while efer.svme is set */
4253 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4259 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4261 struct vcpu_svm *svm = to_svm(vcpu);
4263 u32 ecx = msr->index;
4264 u64 data = msr->data;
4266 case MSR_IA32_CR_PAT:
4267 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4269 vcpu->arch.pat = data;
4270 svm->vmcb->save.g_pat = data;
4271 mark_dirty(svm->vmcb, VMCB_NPT);
4273 case MSR_IA32_SPEC_CTRL:
4274 if (!msr->host_initiated &&
4275 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4276 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4279 /* The STIBP bit doesn't fault even if it's not advertised */
4280 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4283 svm->spec_ctrl = data;
4290 * When it's written (to non-zero) for the first time, pass
4294 * The handling of the MSR bitmap for L2 guests is done in
4295 * nested_svm_vmrun_msrpm.
4296 * We update the L1 MSR bit as well since it will end up
4297 * touching the MSR anyway now.
4299 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4301 case MSR_IA32_PRED_CMD:
4302 if (!msr->host_initiated &&
4303 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4306 if (data & ~PRED_CMD_IBPB)
4312 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4313 if (is_guest_mode(vcpu))
4315 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4317 case MSR_AMD64_VIRT_SPEC_CTRL:
4318 if (!msr->host_initiated &&
4319 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4322 if (data & ~SPEC_CTRL_SSBD)
4325 svm->virt_spec_ctrl = data;
4328 svm->vmcb->save.star = data;
4330 #ifdef CONFIG_X86_64
4332 svm->vmcb->save.lstar = data;
4335 svm->vmcb->save.cstar = data;
4337 case MSR_KERNEL_GS_BASE:
4338 svm->vmcb->save.kernel_gs_base = data;
4340 case MSR_SYSCALL_MASK:
4341 svm->vmcb->save.sfmask = data;
4344 case MSR_IA32_SYSENTER_CS:
4345 svm->vmcb->save.sysenter_cs = data;
4347 case MSR_IA32_SYSENTER_EIP:
4348 svm->sysenter_eip = data;
4349 svm->vmcb->save.sysenter_eip = data;
4351 case MSR_IA32_SYSENTER_ESP:
4352 svm->sysenter_esp = data;
4353 svm->vmcb->save.sysenter_esp = data;
4356 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4360 * This is rare, so we update the MSR here instead of using
4361 * direct_access_msrs. Doing that would require a rdmsr in
4364 svm->tsc_aux = data;
4365 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4367 case MSR_IA32_DEBUGCTLMSR:
4368 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4369 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4373 if (data & DEBUGCTL_RESERVED_BITS)
4376 svm->vmcb->save.dbgctl = data;
4377 mark_dirty(svm->vmcb, VMCB_LBR);
4378 if (data & (1ULL<<0))
4379 svm_enable_lbrv(svm);
4381 svm_disable_lbrv(svm);
4383 case MSR_VM_HSAVE_PA:
4384 svm->nested.hsave_msr = data;
4387 return svm_set_vm_cr(vcpu, data);
4389 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4391 case MSR_F10H_DECFG: {
4392 struct kvm_msr_entry msr_entry;
4394 msr_entry.index = msr->index;
4395 if (svm_get_msr_feature(&msr_entry))
4398 /* Check the supported bits */
4399 if (data & ~msr_entry.data)
4402 /* Don't allow the guest to change a bit, #GP */
4403 if (!msr->host_initiated && (data ^ msr_entry.data))
4406 svm->msr_decfg = data;
4409 case MSR_IA32_APICBASE:
4410 if (kvm_vcpu_apicv_active(vcpu))
4411 avic_update_vapic_bar(to_svm(vcpu), data);
4414 return kvm_set_msr_common(vcpu, msr);
4419 static int wrmsr_interception(struct vcpu_svm *svm)
4421 return kvm_emulate_wrmsr(&svm->vcpu);
4424 static int msr_interception(struct vcpu_svm *svm)
4426 if (svm->vmcb->control.exit_info_1)
4427 return wrmsr_interception(svm);
4429 return rdmsr_interception(svm);
4432 static int interrupt_window_interception(struct vcpu_svm *svm)
4434 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4435 svm_clear_vintr(svm);
4436 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4437 mark_dirty(svm->vmcb, VMCB_INTR);
4438 ++svm->vcpu.stat.irq_window_exits;
4442 static int pause_interception(struct vcpu_svm *svm)
4444 struct kvm_vcpu *vcpu = &svm->vcpu;
4445 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4447 if (pause_filter_thresh)
4448 grow_ple_window(vcpu);
4450 kvm_vcpu_on_spin(vcpu, in_kernel);
4454 static int nop_interception(struct vcpu_svm *svm)
4456 return kvm_skip_emulated_instruction(&(svm->vcpu));
4459 static int monitor_interception(struct vcpu_svm *svm)
4461 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4462 return nop_interception(svm);
4465 static int mwait_interception(struct vcpu_svm *svm)
4467 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4468 return nop_interception(svm);
4471 enum avic_ipi_failure_cause {
4472 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4473 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4474 AVIC_IPI_FAILURE_INVALID_TARGET,
4475 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4478 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4480 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4481 u32 icrl = svm->vmcb->control.exit_info_1;
4482 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4483 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4484 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4486 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4489 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4491 * AVIC hardware handles the generation of
4492 * IPIs when the specified Message Type is Fixed
4493 * (also known as fixed delivery mode) and
4494 * the Trigger Mode is edge-triggered. The hardware
4495 * also supports self and broadcast delivery modes
4496 * specified via the Destination Shorthand(DSH)
4497 * field of the ICRL. Logical and physical APIC ID
4498 * formats are supported. All other IPI types cause
4499 * a #VMEXIT, which needs to emulated.
4501 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4502 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4504 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4506 struct kvm_vcpu *vcpu;
4507 struct kvm *kvm = svm->vcpu.kvm;
4508 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4511 * At this point, we expect that the AVIC HW has already
4512 * set the appropriate IRR bits on the valid target
4513 * vcpus. So, we just need to kick the appropriate vcpu.
4515 kvm_for_each_vcpu(i, vcpu, kvm) {
4516 bool m = kvm_apic_match_dest(vcpu, apic,
4517 icrl & KVM_APIC_SHORT_MASK,
4518 GET_APIC_DEST_FIELD(icrh),
4519 icrl & KVM_APIC_DEST_MASK);
4521 if (m && !avic_vcpu_is_running(vcpu))
4522 kvm_vcpu_wake_up(vcpu);
4526 case AVIC_IPI_FAILURE_INVALID_TARGET:
4527 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4528 index, svm->vcpu.vcpu_id, icrh, icrl);
4530 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4531 WARN_ONCE(1, "Invalid backing page\n");
4534 pr_err("Unknown IPI interception\n");
4540 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4542 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4544 u32 *logical_apic_id_table;
4545 int dlid = GET_APIC_LOGICAL_ID(ldr);
4550 if (flat) { /* flat */
4551 index = ffs(dlid) - 1;
4554 } else { /* cluster */
4555 int cluster = (dlid & 0xf0) >> 4;
4556 int apic = ffs(dlid & 0x0f) - 1;
4558 if ((apic < 0) || (apic > 7) ||
4561 index = (cluster << 2) + apic;
4564 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4566 return &logical_apic_id_table[index];
4569 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4572 u32 *entry, new_entry;
4574 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4575 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4579 new_entry = READ_ONCE(*entry);
4580 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4581 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4582 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4583 WRITE_ONCE(*entry, new_entry);
4588 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4590 struct vcpu_svm *svm = to_svm(vcpu);
4591 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4592 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4595 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4598 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4601 struct vcpu_svm *svm = to_svm(vcpu);
4602 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4604 if (ldr == svm->ldr_reg)
4607 avic_invalidate_logical_id_entry(vcpu);
4610 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4618 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4621 struct vcpu_svm *svm = to_svm(vcpu);
4622 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4623 u32 id = (apic_id_reg >> 24) & 0xff;
4625 if (vcpu->vcpu_id == id)
4628 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4629 new = avic_get_physical_id_entry(vcpu, id);
4633 /* We need to move physical_id_entry to new offset */
4636 to_svm(vcpu)->avic_physical_id_cache = new;
4639 * Also update the guest physical APIC ID in the logical
4640 * APIC ID table entry if already setup the LDR.
4643 avic_handle_ldr_update(vcpu);
4648 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4650 struct vcpu_svm *svm = to_svm(vcpu);
4651 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4653 if (svm->dfr_reg == dfr)
4656 avic_invalidate_logical_id_entry(vcpu);
4660 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4662 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4663 u32 offset = svm->vmcb->control.exit_info_1 &
4664 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4668 if (avic_handle_apic_id_update(&svm->vcpu))
4672 if (avic_handle_ldr_update(&svm->vcpu))
4676 avic_handle_dfr_update(&svm->vcpu);
4682 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4687 static bool is_avic_unaccelerated_access_trap(u32 offset)
4716 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4719 u32 offset = svm->vmcb->control.exit_info_1 &
4720 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4721 u32 vector = svm->vmcb->control.exit_info_2 &
4722 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4723 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4724 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4725 bool trap = is_avic_unaccelerated_access_trap(offset);
4727 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4728 trap, write, vector);
4731 WARN_ONCE(!write, "svm: Handling trap read.\n");
4732 ret = avic_unaccel_trap_write(svm);
4734 /* Handling Fault */
4735 ret = kvm_emulate_instruction(&svm->vcpu, 0);
4741 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4742 [SVM_EXIT_READ_CR0] = cr_interception,
4743 [SVM_EXIT_READ_CR3] = cr_interception,
4744 [SVM_EXIT_READ_CR4] = cr_interception,
4745 [SVM_EXIT_READ_CR8] = cr_interception,
4746 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4747 [SVM_EXIT_WRITE_CR0] = cr_interception,
4748 [SVM_EXIT_WRITE_CR3] = cr_interception,
4749 [SVM_EXIT_WRITE_CR4] = cr_interception,
4750 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4751 [SVM_EXIT_READ_DR0] = dr_interception,
4752 [SVM_EXIT_READ_DR1] = dr_interception,
4753 [SVM_EXIT_READ_DR2] = dr_interception,
4754 [SVM_EXIT_READ_DR3] = dr_interception,
4755 [SVM_EXIT_READ_DR4] = dr_interception,
4756 [SVM_EXIT_READ_DR5] = dr_interception,
4757 [SVM_EXIT_READ_DR6] = dr_interception,
4758 [SVM_EXIT_READ_DR7] = dr_interception,
4759 [SVM_EXIT_WRITE_DR0] = dr_interception,
4760 [SVM_EXIT_WRITE_DR1] = dr_interception,
4761 [SVM_EXIT_WRITE_DR2] = dr_interception,
4762 [SVM_EXIT_WRITE_DR3] = dr_interception,
4763 [SVM_EXIT_WRITE_DR4] = dr_interception,
4764 [SVM_EXIT_WRITE_DR5] = dr_interception,
4765 [SVM_EXIT_WRITE_DR6] = dr_interception,
4766 [SVM_EXIT_WRITE_DR7] = dr_interception,
4767 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4768 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4769 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4770 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4771 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4772 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4773 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4774 [SVM_EXIT_INTR] = intr_interception,
4775 [SVM_EXIT_NMI] = nmi_interception,
4776 [SVM_EXIT_SMI] = nop_on_interception,
4777 [SVM_EXIT_INIT] = nop_on_interception,
4778 [SVM_EXIT_VINTR] = interrupt_window_interception,
4779 [SVM_EXIT_RDPMC] = rdpmc_interception,
4780 [SVM_EXIT_CPUID] = cpuid_interception,
4781 [SVM_EXIT_IRET] = iret_interception,
4782 [SVM_EXIT_INVD] = emulate_on_interception,
4783 [SVM_EXIT_PAUSE] = pause_interception,
4784 [SVM_EXIT_HLT] = halt_interception,
4785 [SVM_EXIT_INVLPG] = invlpg_interception,
4786 [SVM_EXIT_INVLPGA] = invlpga_interception,
4787 [SVM_EXIT_IOIO] = io_interception,
4788 [SVM_EXIT_MSR] = msr_interception,
4789 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4790 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4791 [SVM_EXIT_VMRUN] = vmrun_interception,
4792 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4793 [SVM_EXIT_VMLOAD] = vmload_interception,
4794 [SVM_EXIT_VMSAVE] = vmsave_interception,
4795 [SVM_EXIT_STGI] = stgi_interception,
4796 [SVM_EXIT_CLGI] = clgi_interception,
4797 [SVM_EXIT_SKINIT] = skinit_interception,
4798 [SVM_EXIT_WBINVD] = wbinvd_interception,
4799 [SVM_EXIT_MONITOR] = monitor_interception,
4800 [SVM_EXIT_MWAIT] = mwait_interception,
4801 [SVM_EXIT_XSETBV] = xsetbv_interception,
4802 [SVM_EXIT_RDPRU] = rdpru_interception,
4803 [SVM_EXIT_NPF] = npf_interception,
4804 [SVM_EXIT_RSM] = rsm_interception,
4805 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4806 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4809 static void dump_vmcb(struct kvm_vcpu *vcpu)
4811 struct vcpu_svm *svm = to_svm(vcpu);
4812 struct vmcb_control_area *control = &svm->vmcb->control;
4813 struct vmcb_save_area *save = &svm->vmcb->save;
4815 if (!dump_invalid_vmcb) {
4816 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4820 pr_err("VMCB Control Area:\n");
4821 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4822 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4823 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4824 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4825 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4826 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4827 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4828 pr_err("%-20s%d\n", "pause filter threshold:",
4829 control->pause_filter_thresh);
4830 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4831 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4832 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4833 pr_err("%-20s%d\n", "asid:", control->asid);
4834 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4835 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4836 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4837 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4838 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4839 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4840 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4841 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4842 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4843 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4844 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4845 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4846 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4847 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4848 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4849 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4850 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4851 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4852 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4853 pr_err("VMCB State Save Area:\n");
4854 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4856 save->es.selector, save->es.attrib,
4857 save->es.limit, save->es.base);
4858 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4860 save->cs.selector, save->cs.attrib,
4861 save->cs.limit, save->cs.base);
4862 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4864 save->ss.selector, save->ss.attrib,
4865 save->ss.limit, save->ss.base);
4866 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4868 save->ds.selector, save->ds.attrib,
4869 save->ds.limit, save->ds.base);
4870 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4872 save->fs.selector, save->fs.attrib,
4873 save->fs.limit, save->fs.base);
4874 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4876 save->gs.selector, save->gs.attrib,
4877 save->gs.limit, save->gs.base);
4878 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4880 save->gdtr.selector, save->gdtr.attrib,
4881 save->gdtr.limit, save->gdtr.base);
4882 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4884 save->ldtr.selector, save->ldtr.attrib,
4885 save->ldtr.limit, save->ldtr.base);
4886 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4888 save->idtr.selector, save->idtr.attrib,
4889 save->idtr.limit, save->idtr.base);
4890 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4892 save->tr.selector, save->tr.attrib,
4893 save->tr.limit, save->tr.base);
4894 pr_err("cpl: %d efer: %016llx\n",
4895 save->cpl, save->efer);
4896 pr_err("%-15s %016llx %-13s %016llx\n",
4897 "cr0:", save->cr0, "cr2:", save->cr2);
4898 pr_err("%-15s %016llx %-13s %016llx\n",
4899 "cr3:", save->cr3, "cr4:", save->cr4);
4900 pr_err("%-15s %016llx %-13s %016llx\n",
4901 "dr6:", save->dr6, "dr7:", save->dr7);
4902 pr_err("%-15s %016llx %-13s %016llx\n",
4903 "rip:", save->rip, "rflags:", save->rflags);
4904 pr_err("%-15s %016llx %-13s %016llx\n",
4905 "rsp:", save->rsp, "rax:", save->rax);
4906 pr_err("%-15s %016llx %-13s %016llx\n",
4907 "star:", save->star, "lstar:", save->lstar);
4908 pr_err("%-15s %016llx %-13s %016llx\n",
4909 "cstar:", save->cstar, "sfmask:", save->sfmask);
4910 pr_err("%-15s %016llx %-13s %016llx\n",
4911 "kernel_gs_base:", save->kernel_gs_base,
4912 "sysenter_cs:", save->sysenter_cs);
4913 pr_err("%-15s %016llx %-13s %016llx\n",
4914 "sysenter_esp:", save->sysenter_esp,
4915 "sysenter_eip:", save->sysenter_eip);
4916 pr_err("%-15s %016llx %-13s %016llx\n",
4917 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4918 pr_err("%-15s %016llx %-13s %016llx\n",
4919 "br_from:", save->br_from, "br_to:", save->br_to);
4920 pr_err("%-15s %016llx %-13s %016llx\n",
4921 "excp_from:", save->last_excp_from,
4922 "excp_to:", save->last_excp_to);
4925 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4927 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4929 *info1 = control->exit_info_1;
4930 *info2 = control->exit_info_2;
4933 static int handle_exit(struct kvm_vcpu *vcpu)
4935 struct vcpu_svm *svm = to_svm(vcpu);
4936 struct kvm_run *kvm_run = vcpu->run;
4937 u32 exit_code = svm->vmcb->control.exit_code;
4939 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4941 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4942 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4944 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4946 if (unlikely(svm->nested.exit_required)) {
4947 nested_svm_vmexit(svm);
4948 svm->nested.exit_required = false;
4953 if (is_guest_mode(vcpu)) {
4956 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4957 svm->vmcb->control.exit_info_1,
4958 svm->vmcb->control.exit_info_2,
4959 svm->vmcb->control.exit_int_info,
4960 svm->vmcb->control.exit_int_info_err,
4963 vmexit = nested_svm_exit_special(svm);
4965 if (vmexit == NESTED_EXIT_CONTINUE)
4966 vmexit = nested_svm_exit_handled(svm);
4968 if (vmexit == NESTED_EXIT_DONE)
4972 svm_complete_interrupts(svm);
4974 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4975 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4976 kvm_run->fail_entry.hardware_entry_failure_reason
4977 = svm->vmcb->control.exit_code;
4982 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4983 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4984 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4985 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4986 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4988 __func__, svm->vmcb->control.exit_int_info,
4991 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4992 || !svm_exit_handlers[exit_code]) {
4993 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
4995 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4996 vcpu->run->internal.suberror =
4997 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
4998 vcpu->run->internal.ndata = 1;
4999 vcpu->run->internal.data[0] = exit_code;
5003 return svm_exit_handlers[exit_code](svm);
5006 static void reload_tss(struct kvm_vcpu *vcpu)
5008 int cpu = raw_smp_processor_id();
5010 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5011 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5015 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5017 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5018 int asid = sev_get_asid(svm->vcpu.kvm);
5020 /* Assign the asid allocated with this SEV guest */
5021 svm->vmcb->control.asid = asid;
5026 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5027 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5029 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5030 svm->last_cpu == cpu)
5033 svm->last_cpu = cpu;
5034 sd->sev_vmcbs[asid] = svm->vmcb;
5035 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5036 mark_dirty(svm->vmcb, VMCB_ASID);
5039 static void pre_svm_run(struct vcpu_svm *svm)
5041 int cpu = raw_smp_processor_id();
5043 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5045 if (sev_guest(svm->vcpu.kvm))
5046 return pre_sev_run(svm, cpu);
5048 /* FIXME: handle wraparound of asid_generation */
5049 if (svm->asid_generation != sd->asid_generation)
5053 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5055 struct vcpu_svm *svm = to_svm(vcpu);
5057 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5058 vcpu->arch.hflags |= HF_NMI_MASK;
5059 set_intercept(svm, INTERCEPT_IRET);
5060 ++vcpu->stat.nmi_injections;
5063 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5065 struct vmcb_control_area *control;
5067 /* The following fields are ignored when AVIC is enabled */
5068 control = &svm->vmcb->control;
5069 control->int_vector = irq;
5070 control->int_ctl &= ~V_INTR_PRIO_MASK;
5071 control->int_ctl |= V_IRQ_MASK |
5072 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5073 mark_dirty(svm->vmcb, VMCB_INTR);
5076 static void svm_set_irq(struct kvm_vcpu *vcpu)
5078 struct vcpu_svm *svm = to_svm(vcpu);
5080 BUG_ON(!(gif_set(svm)));
5082 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5083 ++vcpu->stat.irq_injections;
5085 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5086 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5089 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5091 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5094 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5096 struct vcpu_svm *svm = to_svm(vcpu);
5098 if (svm_nested_virtualize_tpr(vcpu) ||
5099 kvm_vcpu_apicv_active(vcpu))
5102 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5108 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5111 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5116 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5118 return avic && irqchip_split(vcpu->kvm);
5121 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5125 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5129 /* Note: Currently only used by Hyper-V. */
5130 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5132 struct vcpu_svm *svm = to_svm(vcpu);
5133 struct vmcb *vmcb = svm->vmcb;
5135 if (kvm_vcpu_apicv_active(vcpu))
5136 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5138 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5139 mark_dirty(vmcb, VMCB_AVIC);
5142 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5147 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5149 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5150 smp_mb__after_atomic();
5152 if (avic_vcpu_is_running(vcpu)) {
5153 int cpuid = vcpu->cpu;
5155 if (cpuid != get_cpu())
5156 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5159 kvm_vcpu_wake_up(vcpu);
5162 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5167 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5169 unsigned long flags;
5170 struct amd_svm_iommu_ir *cur;
5172 spin_lock_irqsave(&svm->ir_list_lock, flags);
5173 list_for_each_entry(cur, &svm->ir_list, node) {
5174 if (cur->data != pi->ir_data)
5176 list_del(&cur->node);
5180 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5183 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5186 unsigned long flags;
5187 struct amd_svm_iommu_ir *ir;
5190 * In some cases, the existing irte is updaed and re-set,
5191 * so we need to check here if it's already been * added
5194 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5195 struct kvm *kvm = svm->vcpu.kvm;
5196 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5197 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5198 struct vcpu_svm *prev_svm;
5205 prev_svm = to_svm(prev_vcpu);
5206 svm_ir_list_del(prev_svm, pi);
5210 * Allocating new amd_iommu_pi_data, which will get
5211 * add to the per-vcpu ir_list.
5213 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5218 ir->data = pi->ir_data;
5220 spin_lock_irqsave(&svm->ir_list_lock, flags);
5221 list_add(&ir->node, &svm->ir_list);
5222 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5229 * The HW cannot support posting multicast/broadcast
5230 * interrupts to a vCPU. So, we still use legacy interrupt
5231 * remapping for these kind of interrupts.
5233 * For lowest-priority interrupts, we only support
5234 * those with single CPU as the destination, e.g. user
5235 * configures the interrupts via /proc/irq or uses
5236 * irqbalance to make the interrupts single-CPU.
5239 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5240 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5242 struct kvm_lapic_irq irq;
5243 struct kvm_vcpu *vcpu = NULL;
5245 kvm_set_msi_irq(kvm, e, &irq);
5247 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5248 !kvm_irq_is_postable(&irq)) {
5249 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5250 __func__, irq.vector);
5254 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5256 *svm = to_svm(vcpu);
5257 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5258 vcpu_info->vector = irq.vector;
5264 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5267 * @host_irq: host irq of the interrupt
5268 * @guest_irq: gsi of the interrupt
5269 * @set: set or unset PI
5270 * returns 0 on success, < 0 on failure
5272 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5273 uint32_t guest_irq, bool set)
5275 struct kvm_kernel_irq_routing_entry *e;
5276 struct kvm_irq_routing_table *irq_rt;
5277 int idx, ret = -EINVAL;
5279 if (!kvm_arch_has_assigned_device(kvm) ||
5280 !irq_remapping_cap(IRQ_POSTING_CAP))
5283 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5284 __func__, host_irq, guest_irq, set);
5286 idx = srcu_read_lock(&kvm->irq_srcu);
5287 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5288 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5290 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5291 struct vcpu_data vcpu_info;
5292 struct vcpu_svm *svm = NULL;
5294 if (e->type != KVM_IRQ_ROUTING_MSI)
5298 * Here, we setup with legacy mode in the following cases:
5299 * 1. When cannot target interrupt to a specific vcpu.
5300 * 2. Unsetting posted interrupt.
5301 * 3. APIC virtialization is disabled for the vcpu.
5302 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5304 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5305 kvm_vcpu_apicv_active(&svm->vcpu)) {
5306 struct amd_iommu_pi_data pi;
5308 /* Try to enable guest_mode in IRTE */
5309 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5311 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5313 pi.is_guest_mode = true;
5314 pi.vcpu_data = &vcpu_info;
5315 ret = irq_set_vcpu_affinity(host_irq, &pi);
5318 * Here, we successfully setting up vcpu affinity in
5319 * IOMMU guest mode. Now, we need to store the posted
5320 * interrupt information in a per-vcpu ir_list so that
5321 * we can reference to them directly when we update vcpu
5322 * scheduling information in IOMMU irte.
5324 if (!ret && pi.is_guest_mode)
5325 svm_ir_list_add(svm, &pi);
5327 /* Use legacy mode in IRTE */
5328 struct amd_iommu_pi_data pi;
5331 * Here, pi is used to:
5332 * - Tell IOMMU to use legacy mode for this interrupt.
5333 * - Retrieve ga_tag of prior interrupt remapping data.
5335 pi.is_guest_mode = false;
5336 ret = irq_set_vcpu_affinity(host_irq, &pi);
5339 * Check if the posted interrupt was previously
5340 * setup with the guest_mode by checking if the ga_tag
5341 * was cached. If so, we need to clean up the per-vcpu
5344 if (!ret && pi.prev_ga_tag) {
5345 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5346 struct kvm_vcpu *vcpu;
5348 vcpu = kvm_get_vcpu_by_id(kvm, id);
5350 svm_ir_list_del(to_svm(vcpu), &pi);
5355 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5356 e->gsi, vcpu_info.vector,
5357 vcpu_info.pi_desc_addr, set);
5361 pr_err("%s: failed to update PI IRTE\n", __func__);
5368 srcu_read_unlock(&kvm->irq_srcu, idx);
5372 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5374 struct vcpu_svm *svm = to_svm(vcpu);
5375 struct vmcb *vmcb = svm->vmcb;
5377 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5378 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5379 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5384 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5386 struct vcpu_svm *svm = to_svm(vcpu);
5388 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5391 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5393 struct vcpu_svm *svm = to_svm(vcpu);
5396 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5397 set_intercept(svm, INTERCEPT_IRET);
5399 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5400 clr_intercept(svm, INTERCEPT_IRET);
5404 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5406 struct vcpu_svm *svm = to_svm(vcpu);
5407 struct vmcb *vmcb = svm->vmcb;
5410 if (!gif_set(svm) ||
5411 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5414 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5416 if (is_guest_mode(vcpu))
5417 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5422 static void enable_irq_window(struct kvm_vcpu *vcpu)
5424 struct vcpu_svm *svm = to_svm(vcpu);
5426 if (kvm_vcpu_apicv_active(vcpu))
5430 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5431 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5432 * get that intercept, this function will be called again though and
5433 * we'll get the vintr intercept. However, if the vGIF feature is
5434 * enabled, the STGI interception will not occur. Enable the irq
5435 * window under the assumption that the hardware will set the GIF.
5437 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5439 svm_inject_irq(svm, 0x0);
5443 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5445 struct vcpu_svm *svm = to_svm(vcpu);
5447 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5449 return; /* IRET will cause a vm exit */
5451 if (!gif_set(svm)) {
5452 if (vgif_enabled(svm))
5453 set_intercept(svm, INTERCEPT_STGI);
5454 return; /* STGI will cause a vm exit */
5457 if (svm->nested.exit_required)
5458 return; /* we're not going to run the guest yet */
5461 * Something prevents NMI from been injected. Single step over possible
5462 * problem (IRET or exception injection or interrupt shadow)
5464 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5465 svm->nmi_singlestep = true;
5466 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5469 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5474 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5479 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5481 struct vcpu_svm *svm = to_svm(vcpu);
5483 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5484 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5486 svm->asid_generation--;
5489 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5491 struct vcpu_svm *svm = to_svm(vcpu);
5493 invlpga(gva, svm->vmcb->control.asid);
5496 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5500 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5502 struct vcpu_svm *svm = to_svm(vcpu);
5504 if (svm_nested_virtualize_tpr(vcpu))
5507 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5508 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5509 kvm_set_cr8(vcpu, cr8);
5513 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5515 struct vcpu_svm *svm = to_svm(vcpu);
5518 if (svm_nested_virtualize_tpr(vcpu) ||
5519 kvm_vcpu_apicv_active(vcpu))
5522 cr8 = kvm_get_cr8(vcpu);
5523 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5524 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5527 static void svm_complete_interrupts(struct vcpu_svm *svm)
5531 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5532 unsigned int3_injected = svm->int3_injected;
5534 svm->int3_injected = 0;
5537 * If we've made progress since setting HF_IRET_MASK, we've
5538 * executed an IRET and can allow NMI injection.
5540 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5541 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5542 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5543 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5546 svm->vcpu.arch.nmi_injected = false;
5547 kvm_clear_exception_queue(&svm->vcpu);
5548 kvm_clear_interrupt_queue(&svm->vcpu);
5550 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5553 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5555 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5556 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5559 case SVM_EXITINTINFO_TYPE_NMI:
5560 svm->vcpu.arch.nmi_injected = true;
5562 case SVM_EXITINTINFO_TYPE_EXEPT:
5564 * In case of software exceptions, do not reinject the vector,
5565 * but re-execute the instruction instead. Rewind RIP first
5566 * if we emulated INT3 before.
5568 if (kvm_exception_is_soft(vector)) {
5569 if (vector == BP_VECTOR && int3_injected &&
5570 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5571 kvm_rip_write(&svm->vcpu,
5572 kvm_rip_read(&svm->vcpu) -
5576 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5577 u32 err = svm->vmcb->control.exit_int_info_err;
5578 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5581 kvm_requeue_exception(&svm->vcpu, vector);
5583 case SVM_EXITINTINFO_TYPE_INTR:
5584 kvm_queue_interrupt(&svm->vcpu, vector, false);
5591 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5593 struct vcpu_svm *svm = to_svm(vcpu);
5594 struct vmcb_control_area *control = &svm->vmcb->control;
5596 control->exit_int_info = control->event_inj;
5597 control->exit_int_info_err = control->event_inj_err;
5598 control->event_inj = 0;
5599 svm_complete_interrupts(svm);
5602 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5604 struct vcpu_svm *svm = to_svm(vcpu);
5606 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5607 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5608 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5611 * A vmexit emulation is required before the vcpu can be executed
5614 if (unlikely(svm->nested.exit_required))
5618 * Disable singlestep if we're injecting an interrupt/exception.
5619 * We don't want our modified rflags to be pushed on the stack where
5620 * we might not be able to easily reset them if we disabled NMI
5623 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5625 * Event injection happens before external interrupts cause a
5626 * vmexit and interrupts are disabled here, so smp_send_reschedule
5627 * is enough to force an immediate vmexit.
5629 disable_nmi_singlestep(svm);
5630 smp_send_reschedule(vcpu->cpu);
5635 sync_lapic_to_cr8(vcpu);
5637 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5640 kvm_load_guest_xcr0(vcpu);
5642 if (lapic_in_kernel(vcpu) &&
5643 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5644 kvm_wait_lapic_expire(vcpu);
5647 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5648 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5649 * is no need to worry about the conditional branch over the wrmsr
5650 * being speculatively taken.
5652 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5657 "push %%" _ASM_BP "; \n\t"
5658 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5659 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5660 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5661 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5662 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5663 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5664 #ifdef CONFIG_X86_64
5665 "mov %c[r8](%[svm]), %%r8 \n\t"
5666 "mov %c[r9](%[svm]), %%r9 \n\t"
5667 "mov %c[r10](%[svm]), %%r10 \n\t"
5668 "mov %c[r11](%[svm]), %%r11 \n\t"
5669 "mov %c[r12](%[svm]), %%r12 \n\t"
5670 "mov %c[r13](%[svm]), %%r13 \n\t"
5671 "mov %c[r14](%[svm]), %%r14 \n\t"
5672 "mov %c[r15](%[svm]), %%r15 \n\t"
5675 /* Enter guest mode */
5676 "push %%" _ASM_AX " \n\t"
5677 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5678 __ex("vmload %%" _ASM_AX) "\n\t"
5679 __ex("vmrun %%" _ASM_AX) "\n\t"
5680 __ex("vmsave %%" _ASM_AX) "\n\t"
5681 "pop %%" _ASM_AX " \n\t"
5683 /* Save guest registers, load host registers */
5684 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5685 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5686 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5687 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5688 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5689 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5690 #ifdef CONFIG_X86_64
5691 "mov %%r8, %c[r8](%[svm]) \n\t"
5692 "mov %%r9, %c[r9](%[svm]) \n\t"
5693 "mov %%r10, %c[r10](%[svm]) \n\t"
5694 "mov %%r11, %c[r11](%[svm]) \n\t"
5695 "mov %%r12, %c[r12](%[svm]) \n\t"
5696 "mov %%r13, %c[r13](%[svm]) \n\t"
5697 "mov %%r14, %c[r14](%[svm]) \n\t"
5698 "mov %%r15, %c[r15](%[svm]) \n\t"
5700 * Clear host registers marked as clobbered to prevent
5703 "xor %%r8d, %%r8d \n\t"
5704 "xor %%r9d, %%r9d \n\t"
5705 "xor %%r10d, %%r10d \n\t"
5706 "xor %%r11d, %%r11d \n\t"
5707 "xor %%r12d, %%r12d \n\t"
5708 "xor %%r13d, %%r13d \n\t"
5709 "xor %%r14d, %%r14d \n\t"
5710 "xor %%r15d, %%r15d \n\t"
5712 "xor %%ebx, %%ebx \n\t"
5713 "xor %%ecx, %%ecx \n\t"
5714 "xor %%edx, %%edx \n\t"
5715 "xor %%esi, %%esi \n\t"
5716 "xor %%edi, %%edi \n\t"
5720 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5721 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5722 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5723 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5724 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5725 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5726 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5727 #ifdef CONFIG_X86_64
5728 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5729 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5730 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5731 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5732 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5733 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5734 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5735 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5738 #ifdef CONFIG_X86_64
5739 , "rbx", "rcx", "rdx", "rsi", "rdi"
5740 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5742 , "ebx", "ecx", "edx", "esi", "edi"
5746 /* Eliminate branch target predictions from guest mode */
5749 #ifdef CONFIG_X86_64
5750 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5752 loadsegment(fs, svm->host.fs);
5753 #ifndef CONFIG_X86_32_LAZY_GS
5754 loadsegment(gs, svm->host.gs);
5759 * We do not use IBRS in the kernel. If this vCPU has used the
5760 * SPEC_CTRL MSR it may have left it on; save the value and
5761 * turn it off. This is much more efficient than blindly adding
5762 * it to the atomic save/restore list. Especially as the former
5763 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5765 * For non-nested case:
5766 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5770 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5773 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5774 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5778 local_irq_disable();
5780 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5782 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5783 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5784 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5785 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5787 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5788 kvm_before_interrupt(&svm->vcpu);
5790 kvm_put_guest_xcr0(vcpu);
5793 /* Any pending NMI will happen here */
5795 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5796 kvm_after_interrupt(&svm->vcpu);
5798 sync_cr8_to_lapic(vcpu);
5802 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5804 /* if exit due to PF check for async PF */
5805 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5806 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5809 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5810 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5814 * We need to handle MC intercepts here before the vcpu has a chance to
5815 * change the physical cpu
5817 if (unlikely(svm->vmcb->control.exit_code ==
5818 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5819 svm_handle_mce(svm);
5821 mark_all_clean(svm->vmcb);
5823 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5825 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5827 struct vcpu_svm *svm = to_svm(vcpu);
5829 svm->vmcb->save.cr3 = __sme_set(root);
5830 mark_dirty(svm->vmcb, VMCB_CR);
5833 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5835 struct vcpu_svm *svm = to_svm(vcpu);
5837 svm->vmcb->control.nested_cr3 = __sme_set(root);
5838 mark_dirty(svm->vmcb, VMCB_NPT);
5840 /* Also sync guest cr3 here in case we live migrate */
5841 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5842 mark_dirty(svm->vmcb, VMCB_CR);
5845 static int is_disabled(void)
5849 rdmsrl(MSR_VM_CR, vm_cr);
5850 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5857 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5860 * Patch in the VMMCALL instruction:
5862 hypercall[0] = 0x0f;
5863 hypercall[1] = 0x01;
5864 hypercall[2] = 0xd9;
5867 static int __init svm_check_processor_compat(void)
5872 static bool svm_cpu_has_accelerated_tpr(void)
5877 static bool svm_has_emulated_msr(int index)
5880 case MSR_IA32_MCG_EXT_CTL:
5881 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
5890 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5895 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5897 struct vcpu_svm *svm = to_svm(vcpu);
5899 /* Update nrips enabled cache */
5900 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5902 if (!kvm_vcpu_apicv_active(vcpu))
5905 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5908 #define F(x) bit(X86_FEATURE_##x)
5910 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5915 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5919 entry->ecx |= (1 << 2); /* Set SVM bit */
5922 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5923 boot_cpu_has(X86_FEATURE_AMD_SSBD))
5924 entry->ebx |= F(VIRT_SSBD);
5927 entry->eax = 1; /* SVM revision 1 */
5928 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5929 ASID emulation to nested SVM */
5930 entry->ecx = 0; /* Reserved */
5931 entry->edx = 0; /* Per default do not support any
5932 additional features */
5934 /* Support next_rip if host supports it */
5935 if (boot_cpu_has(X86_FEATURE_NRIPS))
5936 entry->edx |= F(NRIPS);
5938 /* Support NPT for the guest if enabled */
5940 entry->edx |= F(NPT);
5944 /* Support memory encryption cpuid if host supports it */
5945 if (boot_cpu_has(X86_FEATURE_SEV))
5946 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5947 &entry->ecx, &entry->edx);
5952 static int svm_get_lpage_level(void)
5954 return PT_PDPE_LEVEL;
5957 static bool svm_rdtscp_supported(void)
5959 return boot_cpu_has(X86_FEATURE_RDTSCP);
5962 static bool svm_invpcid_supported(void)
5967 static bool svm_mpx_supported(void)
5972 static bool svm_xsaves_supported(void)
5977 static bool svm_umip_emulated(void)
5982 static bool svm_pt_supported(void)
5987 static bool svm_has_wbinvd_exit(void)
5992 #define PRE_EX(exit) { .exit_code = (exit), \
5993 .stage = X86_ICPT_PRE_EXCEPT, }
5994 #define POST_EX(exit) { .exit_code = (exit), \
5995 .stage = X86_ICPT_POST_EXCEPT, }
5996 #define POST_MEM(exit) { .exit_code = (exit), \
5997 .stage = X86_ICPT_POST_MEMACCESS, }
5999 static const struct __x86_intercept {
6001 enum x86_intercept_stage stage;
6002 } x86_intercept_map[] = {
6003 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6004 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6005 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6006 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6007 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6008 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6009 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6010 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6011 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6012 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6013 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6014 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6015 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6016 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6017 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6018 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6019 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6020 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6021 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6022 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6023 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6024 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6025 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6026 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6027 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6028 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6029 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6030 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6031 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6032 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6033 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6034 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6035 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6036 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6037 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6038 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6039 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6040 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6041 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6042 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6043 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6044 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6045 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6046 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6047 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6048 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6049 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
6056 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6057 struct x86_instruction_info *info,
6058 enum x86_intercept_stage stage)
6060 struct vcpu_svm *svm = to_svm(vcpu);
6061 int vmexit, ret = X86EMUL_CONTINUE;
6062 struct __x86_intercept icpt_info;
6063 struct vmcb *vmcb = svm->vmcb;
6065 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6068 icpt_info = x86_intercept_map[info->intercept];
6070 if (stage != icpt_info.stage)
6073 switch (icpt_info.exit_code) {
6074 case SVM_EXIT_READ_CR0:
6075 if (info->intercept == x86_intercept_cr_read)
6076 icpt_info.exit_code += info->modrm_reg;
6078 case SVM_EXIT_WRITE_CR0: {
6079 unsigned long cr0, val;
6082 if (info->intercept == x86_intercept_cr_write)
6083 icpt_info.exit_code += info->modrm_reg;
6085 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6086 info->intercept == x86_intercept_clts)
6089 intercept = svm->nested.intercept;
6091 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6094 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6095 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6097 if (info->intercept == x86_intercept_lmsw) {
6100 /* lmsw can't clear PE - catch this here */
6101 if (cr0 & X86_CR0_PE)
6106 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6110 case SVM_EXIT_READ_DR0:
6111 case SVM_EXIT_WRITE_DR0:
6112 icpt_info.exit_code += info->modrm_reg;
6115 if (info->intercept == x86_intercept_wrmsr)
6116 vmcb->control.exit_info_1 = 1;
6118 vmcb->control.exit_info_1 = 0;
6120 case SVM_EXIT_PAUSE:
6122 * We get this for NOP only, but pause
6123 * is rep not, check this here
6125 if (info->rep_prefix != REPE_PREFIX)
6128 case SVM_EXIT_IOIO: {
6132 if (info->intercept == x86_intercept_in ||
6133 info->intercept == x86_intercept_ins) {
6134 exit_info = ((info->src_val & 0xffff) << 16) |
6136 bytes = info->dst_bytes;
6138 exit_info = (info->dst_val & 0xffff) << 16;
6139 bytes = info->src_bytes;
6142 if (info->intercept == x86_intercept_outs ||
6143 info->intercept == x86_intercept_ins)
6144 exit_info |= SVM_IOIO_STR_MASK;
6146 if (info->rep_prefix)
6147 exit_info |= SVM_IOIO_REP_MASK;
6149 bytes = min(bytes, 4u);
6151 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6153 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6155 vmcb->control.exit_info_1 = exit_info;
6156 vmcb->control.exit_info_2 = info->next_rip;
6164 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6165 if (static_cpu_has(X86_FEATURE_NRIPS))
6166 vmcb->control.next_rip = info->next_rip;
6167 vmcb->control.exit_code = icpt_info.exit_code;
6168 vmexit = nested_svm_exit_handled(svm);
6170 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6177 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6182 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6184 if (pause_filter_thresh)
6185 shrink_ple_window(vcpu);
6188 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6190 if (avic_handle_apic_id_update(vcpu) != 0)
6192 avic_handle_dfr_update(vcpu);
6193 avic_handle_ldr_update(vcpu);
6196 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6198 /* [63:9] are reserved. */
6199 vcpu->arch.mcg_cap &= 0x1ff;
6202 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6204 struct vcpu_svm *svm = to_svm(vcpu);
6206 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6210 if (is_guest_mode(&svm->vcpu) &&
6211 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6212 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6213 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6214 svm->nested.exit_required = true;
6221 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6223 struct vcpu_svm *svm = to_svm(vcpu);
6226 if (is_guest_mode(vcpu)) {
6227 /* FED8h - SVM Guest */
6228 put_smstate(u64, smstate, 0x7ed8, 1);
6229 /* FEE0h - SVM Guest VMCB Physical Address */
6230 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6232 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6233 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6234 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6236 ret = nested_svm_vmexit(svm);
6243 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6245 struct vcpu_svm *svm = to_svm(vcpu);
6246 struct vmcb *nested_vmcb;
6247 struct kvm_host_map map;
6251 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6252 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6255 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6257 nested_vmcb = map.hva;
6258 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6263 static int enable_smi_window(struct kvm_vcpu *vcpu)
6265 struct vcpu_svm *svm = to_svm(vcpu);
6267 if (!gif_set(svm)) {
6268 if (vgif_enabled(svm))
6269 set_intercept(svm, INTERCEPT_STGI);
6270 /* STGI will cause a vm exit */
6276 static int sev_asid_new(void)
6280 mutex_lock(&sev_bitmap_lock);
6283 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6285 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6286 if (pos >= max_sev_asid) {
6287 mutex_unlock(&sev_bitmap_lock);
6291 __set_bit(pos, sev_asid_bitmap);
6293 mutex_unlock(&sev_bitmap_lock);
6298 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6300 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6304 if (unlikely(sev->active))
6307 asid = sev_asid_new();
6311 ret = sev_platform_init(&argp->error);
6317 INIT_LIST_HEAD(&sev->regions_list);
6322 sev_asid_free(asid);
6326 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6328 struct sev_data_activate *data;
6329 int asid = sev_get_asid(kvm);
6333 * Guard against a DEACTIVATE command before the DF_FLUSH command
6336 mutex_lock(&sev_deactivate_lock);
6338 wbinvd_on_all_cpus();
6340 ret = sev_guest_df_flush(error);
6342 mutex_unlock(&sev_deactivate_lock);
6347 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6351 /* activate ASID on the given handle */
6352 data->handle = handle;
6354 ret = sev_guest_activate(data, error);
6360 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6369 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6375 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6377 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6379 return __sev_issue_cmd(sev->fd, id, data, error);
6382 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6384 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6385 struct sev_data_launch_start *start;
6386 struct kvm_sev_launch_start params;
6387 void *dh_blob, *session_blob;
6388 int *error = &argp->error;
6391 if (!sev_guest(kvm))
6394 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6397 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6402 if (params.dh_uaddr) {
6403 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6404 if (IS_ERR(dh_blob)) {
6405 ret = PTR_ERR(dh_blob);
6409 start->dh_cert_address = __sme_set(__pa(dh_blob));
6410 start->dh_cert_len = params.dh_len;
6413 session_blob = NULL;
6414 if (params.session_uaddr) {
6415 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6416 if (IS_ERR(session_blob)) {
6417 ret = PTR_ERR(session_blob);
6421 start->session_address = __sme_set(__pa(session_blob));
6422 start->session_len = params.session_len;
6425 start->handle = params.handle;
6426 start->policy = params.policy;
6428 /* create memory encryption context */
6429 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6431 goto e_free_session;
6433 /* Bind ASID to this guest */
6434 ret = sev_bind_asid(kvm, start->handle, error);
6436 goto e_free_session;
6438 /* return handle to userspace */
6439 params.handle = start->handle;
6440 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6441 sev_unbind_asid(kvm, start->handle);
6443 goto e_free_session;
6446 sev->handle = start->handle;
6447 sev->fd = argp->sev_fd;
6450 kfree(session_blob);
6458 static unsigned long get_num_contig_pages(unsigned long idx,
6459 struct page **inpages, unsigned long npages)
6461 unsigned long paddr, next_paddr;
6462 unsigned long i = idx + 1, pages = 1;
6464 /* find the number of contiguous pages starting from idx */
6465 paddr = __sme_page_pa(inpages[idx]);
6466 while (i < npages) {
6467 next_paddr = __sme_page_pa(inpages[i++]);
6468 if ((paddr + PAGE_SIZE) == next_paddr) {
6479 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6481 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6482 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6483 struct kvm_sev_launch_update_data params;
6484 struct sev_data_launch_update_data *data;
6485 struct page **inpages;
6488 if (!sev_guest(kvm))
6491 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6494 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6498 vaddr = params.uaddr;
6500 vaddr_end = vaddr + size;
6502 /* Lock the user memory. */
6503 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6510 * The LAUNCH_UPDATE command will perform in-place encryption of the
6511 * memory content (i.e it will write the same memory region with C=1).
6512 * It's possible that the cache may contain the data with C=0, i.e.,
6513 * unencrypted so invalidate it first.
6515 sev_clflush_pages(inpages, npages);
6517 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6521 * If the user buffer is not page-aligned, calculate the offset
6524 offset = vaddr & (PAGE_SIZE - 1);
6526 /* Calculate the number of pages that can be encrypted in one go. */
6527 pages = get_num_contig_pages(i, inpages, npages);
6529 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6531 data->handle = sev->handle;
6533 data->address = __sme_page_pa(inpages[i]) + offset;
6534 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6539 next_vaddr = vaddr + len;
6543 /* content of memory is updated, mark pages dirty */
6544 for (i = 0; i < npages; i++) {
6545 set_page_dirty_lock(inpages[i]);
6546 mark_page_accessed(inpages[i]);
6548 /* unlock the user pages */
6549 sev_unpin_memory(kvm, inpages, npages);
6555 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6557 void __user *measure = (void __user *)(uintptr_t)argp->data;
6558 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6559 struct sev_data_launch_measure *data;
6560 struct kvm_sev_launch_measure params;
6561 void __user *p = NULL;
6565 if (!sev_guest(kvm))
6568 if (copy_from_user(¶ms, measure, sizeof(params)))
6571 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6575 /* User wants to query the blob length */
6579 p = (void __user *)(uintptr_t)params.uaddr;
6581 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6587 blob = kmalloc(params.len, GFP_KERNEL);
6591 data->address = __psp_pa(blob);
6592 data->len = params.len;
6596 data->handle = sev->handle;
6597 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6600 * If we query the session length, FW responded with expected data.
6609 if (copy_to_user(p, blob, params.len))
6614 params.len = data->len;
6615 if (copy_to_user(measure, ¶ms, sizeof(params)))
6624 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6626 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6627 struct sev_data_launch_finish *data;
6630 if (!sev_guest(kvm))
6633 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6637 data->handle = sev->handle;
6638 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6644 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6646 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6647 struct kvm_sev_guest_status params;
6648 struct sev_data_guest_status *data;
6651 if (!sev_guest(kvm))
6654 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6658 data->handle = sev->handle;
6659 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6663 params.policy = data->policy;
6664 params.state = data->state;
6665 params.handle = data->handle;
6667 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6674 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6675 unsigned long dst, int size,
6676 int *error, bool enc)
6678 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6679 struct sev_data_dbg *data;
6682 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6686 data->handle = sev->handle;
6687 data->dst_addr = dst;
6688 data->src_addr = src;
6691 ret = sev_issue_cmd(kvm,
6692 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6698 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6699 unsigned long dst_paddr, int sz, int *err)
6704 * Its safe to read more than we are asked, caller should ensure that
6705 * destination has enough space.
6707 src_paddr = round_down(src_paddr, 16);
6708 offset = src_paddr & 15;
6709 sz = round_up(sz + offset, 16);
6711 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6714 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6715 unsigned long __user dst_uaddr,
6716 unsigned long dst_paddr,
6719 struct page *tpage = NULL;
6722 /* if inputs are not 16-byte then use intermediate buffer */
6723 if (!IS_ALIGNED(dst_paddr, 16) ||
6724 !IS_ALIGNED(paddr, 16) ||
6725 !IS_ALIGNED(size, 16)) {
6726 tpage = (void *)alloc_page(GFP_KERNEL);
6730 dst_paddr = __sme_page_pa(tpage);
6733 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6738 offset = paddr & 15;
6739 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6740 page_address(tpage) + offset, size))
6751 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6752 unsigned long __user vaddr,
6753 unsigned long dst_paddr,
6754 unsigned long __user dst_vaddr,
6755 int size, int *error)
6757 struct page *src_tpage = NULL;
6758 struct page *dst_tpage = NULL;
6759 int ret, len = size;
6761 /* If source buffer is not aligned then use an intermediate buffer */
6762 if (!IS_ALIGNED(vaddr, 16)) {
6763 src_tpage = alloc_page(GFP_KERNEL);
6767 if (copy_from_user(page_address(src_tpage),
6768 (void __user *)(uintptr_t)vaddr, size)) {
6769 __free_page(src_tpage);
6773 paddr = __sme_page_pa(src_tpage);
6777 * If destination buffer or length is not aligned then do read-modify-write:
6778 * - decrypt destination in an intermediate buffer
6779 * - copy the source buffer in an intermediate buffer
6780 * - use the intermediate buffer as source buffer
6782 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6785 dst_tpage = alloc_page(GFP_KERNEL);
6791 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6792 __sme_page_pa(dst_tpage), size, error);
6797 * If source is kernel buffer then use memcpy() otherwise
6800 dst_offset = dst_paddr & 15;
6803 memcpy(page_address(dst_tpage) + dst_offset,
6804 page_address(src_tpage), size);
6806 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6807 (void __user *)(uintptr_t)vaddr, size)) {
6813 paddr = __sme_page_pa(dst_tpage);
6814 dst_paddr = round_down(dst_paddr, 16);
6815 len = round_up(size, 16);
6818 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6822 __free_page(src_tpage);
6824 __free_page(dst_tpage);
6828 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6830 unsigned long vaddr, vaddr_end, next_vaddr;
6831 unsigned long dst_vaddr;
6832 struct page **src_p, **dst_p;
6833 struct kvm_sev_dbg debug;
6838 if (!sev_guest(kvm))
6841 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6844 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6846 if (!debug.dst_uaddr)
6849 vaddr = debug.src_uaddr;
6851 vaddr_end = vaddr + size;
6852 dst_vaddr = debug.dst_uaddr;
6854 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6855 int len, s_off, d_off;
6857 /* lock userspace source and destination page */
6858 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6862 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6864 sev_unpin_memory(kvm, src_p, n);
6869 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6870 * memory content (i.e it will write the same memory region with C=1).
6871 * It's possible that the cache may contain the data with C=0, i.e.,
6872 * unencrypted so invalidate it first.
6874 sev_clflush_pages(src_p, 1);
6875 sev_clflush_pages(dst_p, 1);
6878 * Since user buffer may not be page aligned, calculate the
6879 * offset within the page.
6881 s_off = vaddr & ~PAGE_MASK;
6882 d_off = dst_vaddr & ~PAGE_MASK;
6883 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6886 ret = __sev_dbg_decrypt_user(kvm,
6887 __sme_page_pa(src_p[0]) + s_off,
6889 __sme_page_pa(dst_p[0]) + d_off,
6892 ret = __sev_dbg_encrypt_user(kvm,
6893 __sme_page_pa(src_p[0]) + s_off,
6895 __sme_page_pa(dst_p[0]) + d_off,
6899 sev_unpin_memory(kvm, src_p, n);
6900 sev_unpin_memory(kvm, dst_p, n);
6905 next_vaddr = vaddr + len;
6906 dst_vaddr = dst_vaddr + len;
6913 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6915 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6916 struct sev_data_launch_secret *data;
6917 struct kvm_sev_launch_secret params;
6918 struct page **pages;
6923 if (!sev_guest(kvm))
6926 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6929 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6934 * The secret must be copied into contiguous memory region, lets verify
6935 * that userspace memory pages are contiguous before we issue command.
6937 if (get_num_contig_pages(0, pages, n) != n) {
6939 goto e_unpin_memory;
6943 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6945 goto e_unpin_memory;
6947 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6948 data->guest_address = __sme_page_pa(pages[0]) + offset;
6949 data->guest_len = params.guest_len;
6951 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6953 ret = PTR_ERR(blob);
6957 data->trans_address = __psp_pa(blob);
6958 data->trans_len = params.trans_len;
6960 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6965 data->hdr_address = __psp_pa(hdr);
6966 data->hdr_len = params.hdr_len;
6968 data->handle = sev->handle;
6969 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6978 sev_unpin_memory(kvm, pages, n);
6982 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6984 struct kvm_sev_cmd sev_cmd;
6987 if (!svm_sev_enabled())
6990 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6993 mutex_lock(&kvm->lock);
6995 switch (sev_cmd.id) {
6997 r = sev_guest_init(kvm, &sev_cmd);
6999 case KVM_SEV_LAUNCH_START:
7000 r = sev_launch_start(kvm, &sev_cmd);
7002 case KVM_SEV_LAUNCH_UPDATE_DATA:
7003 r = sev_launch_update_data(kvm, &sev_cmd);
7005 case KVM_SEV_LAUNCH_MEASURE:
7006 r = sev_launch_measure(kvm, &sev_cmd);
7008 case KVM_SEV_LAUNCH_FINISH:
7009 r = sev_launch_finish(kvm, &sev_cmd);
7011 case KVM_SEV_GUEST_STATUS:
7012 r = sev_guest_status(kvm, &sev_cmd);
7014 case KVM_SEV_DBG_DECRYPT:
7015 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7017 case KVM_SEV_DBG_ENCRYPT:
7018 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7020 case KVM_SEV_LAUNCH_SECRET:
7021 r = sev_launch_secret(kvm, &sev_cmd);
7028 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7032 mutex_unlock(&kvm->lock);
7036 static int svm_register_enc_region(struct kvm *kvm,
7037 struct kvm_enc_region *range)
7039 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7040 struct enc_region *region;
7043 if (!sev_guest(kvm))
7046 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7049 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7053 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7054 if (!region->pages) {
7060 * The guest may change the memory encryption attribute from C=0 -> C=1
7061 * or vice versa for this memory range. Lets make sure caches are
7062 * flushed to ensure that guest data gets written into memory with
7065 sev_clflush_pages(region->pages, region->npages);
7067 region->uaddr = range->addr;
7068 region->size = range->size;
7070 mutex_lock(&kvm->lock);
7071 list_add_tail(®ion->list, &sev->regions_list);
7072 mutex_unlock(&kvm->lock);
7081 static struct enc_region *
7082 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7084 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7085 struct list_head *head = &sev->regions_list;
7086 struct enc_region *i;
7088 list_for_each_entry(i, head, list) {
7089 if (i->uaddr == range->addr &&
7090 i->size == range->size)
7098 static int svm_unregister_enc_region(struct kvm *kvm,
7099 struct kvm_enc_region *range)
7101 struct enc_region *region;
7104 mutex_lock(&kvm->lock);
7106 if (!sev_guest(kvm)) {
7111 region = find_enc_region(kvm, range);
7117 __unregister_enc_region_locked(kvm, region);
7119 mutex_unlock(&kvm->lock);
7123 mutex_unlock(&kvm->lock);
7127 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7129 unsigned long cr4 = kvm_read_cr4(vcpu);
7130 bool smep = cr4 & X86_CR4_SMEP;
7131 bool smap = cr4 & X86_CR4_SMAP;
7132 bool is_user = svm_get_cpl(vcpu) == 3;
7135 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7138 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7139 * possible that CPU microcode implementing DecodeAssist will fail
7140 * to read bytes of instruction which caused #NPF. In this case,
7141 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7142 * return 0 instead of the correct guest instruction bytes.
7144 * This happens because CPU microcode reading instruction bytes
7145 * uses a special opcode which attempts to read data using CPL=0
7146 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7147 * fault, it gives up and returns no instruction bytes.
7150 * We reach here in case CPU supports DecodeAssist, raised #NPF and
7151 * returned 0 in GuestIntrBytes field of the VMCB.
7152 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7153 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7154 * in case vCPU CPL==3 (Because otherwise guest would have triggered
7155 * a SMEP fault instead of #NPF).
7156 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7157 * As most guests enable SMAP if they have also enabled SMEP, use above
7158 * logic in order to attempt minimize false-positive of detecting errata
7159 * while still preserving all cases semantic correctness.
7162 * To determine what instruction the guest was executing, the hypervisor
7163 * will have to decode the instruction at the instruction pointer.
7165 * In non SEV guest, hypervisor will be able to read the guest
7166 * memory to decode the instruction pointer when insn_len is zero
7167 * so we return true to indicate that decoding is possible.
7169 * But in the SEV guest, the guest memory is encrypted with the
7170 * guest specific key and hypervisor will not be able to decode the
7171 * instruction pointer so we will not able to workaround it. Lets
7172 * print the error and request to kill the guest.
7174 if (smap && (!smep || is_user)) {
7175 if (!sev_guest(vcpu->kvm))
7178 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7179 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7185 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7187 struct vcpu_svm *svm = to_svm(vcpu);
7190 * TODO: Last condition latch INIT signals on vCPU when
7191 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7192 * To properly emulate the INIT intercept, SVM should implement
7193 * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7194 * there if an INIT signal is pending.
7196 return !gif_set(svm) ||
7197 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7200 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7201 .cpu_has_kvm_support = has_svm,
7202 .disabled_by_bios = is_disabled,
7203 .hardware_setup = svm_hardware_setup,
7204 .hardware_unsetup = svm_hardware_unsetup,
7205 .check_processor_compatibility = svm_check_processor_compat,
7206 .hardware_enable = svm_hardware_enable,
7207 .hardware_disable = svm_hardware_disable,
7208 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7209 .has_emulated_msr = svm_has_emulated_msr,
7211 .vcpu_create = svm_create_vcpu,
7212 .vcpu_free = svm_free_vcpu,
7213 .vcpu_reset = svm_vcpu_reset,
7215 .vm_alloc = svm_vm_alloc,
7216 .vm_free = svm_vm_free,
7217 .vm_init = avic_vm_init,
7218 .vm_destroy = svm_vm_destroy,
7220 .prepare_guest_switch = svm_prepare_guest_switch,
7221 .vcpu_load = svm_vcpu_load,
7222 .vcpu_put = svm_vcpu_put,
7223 .vcpu_blocking = svm_vcpu_blocking,
7224 .vcpu_unblocking = svm_vcpu_unblocking,
7226 .update_bp_intercept = update_bp_intercept,
7227 .get_msr_feature = svm_get_msr_feature,
7228 .get_msr = svm_get_msr,
7229 .set_msr = svm_set_msr,
7230 .get_segment_base = svm_get_segment_base,
7231 .get_segment = svm_get_segment,
7232 .set_segment = svm_set_segment,
7233 .get_cpl = svm_get_cpl,
7234 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7235 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7236 .decache_cr3 = svm_decache_cr3,
7237 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7238 .set_cr0 = svm_set_cr0,
7239 .set_cr3 = svm_set_cr3,
7240 .set_cr4 = svm_set_cr4,
7241 .set_efer = svm_set_efer,
7242 .get_idt = svm_get_idt,
7243 .set_idt = svm_set_idt,
7244 .get_gdt = svm_get_gdt,
7245 .set_gdt = svm_set_gdt,
7246 .get_dr6 = svm_get_dr6,
7247 .set_dr6 = svm_set_dr6,
7248 .set_dr7 = svm_set_dr7,
7249 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7250 .cache_reg = svm_cache_reg,
7251 .get_rflags = svm_get_rflags,
7252 .set_rflags = svm_set_rflags,
7254 .tlb_flush = svm_flush_tlb,
7255 .tlb_flush_gva = svm_flush_tlb_gva,
7257 .run = svm_vcpu_run,
7258 .handle_exit = handle_exit,
7259 .skip_emulated_instruction = skip_emulated_instruction,
7260 .set_interrupt_shadow = svm_set_interrupt_shadow,
7261 .get_interrupt_shadow = svm_get_interrupt_shadow,
7262 .patch_hypercall = svm_patch_hypercall,
7263 .set_irq = svm_set_irq,
7264 .set_nmi = svm_inject_nmi,
7265 .queue_exception = svm_queue_exception,
7266 .cancel_injection = svm_cancel_injection,
7267 .interrupt_allowed = svm_interrupt_allowed,
7268 .nmi_allowed = svm_nmi_allowed,
7269 .get_nmi_mask = svm_get_nmi_mask,
7270 .set_nmi_mask = svm_set_nmi_mask,
7271 .enable_nmi_window = enable_nmi_window,
7272 .enable_irq_window = enable_irq_window,
7273 .update_cr8_intercept = update_cr8_intercept,
7274 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7275 .get_enable_apicv = svm_get_enable_apicv,
7276 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7277 .load_eoi_exitmap = svm_load_eoi_exitmap,
7278 .hwapic_irr_update = svm_hwapic_irr_update,
7279 .hwapic_isr_update = svm_hwapic_isr_update,
7280 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7281 .apicv_post_state_restore = avic_post_state_restore,
7283 .set_tss_addr = svm_set_tss_addr,
7284 .set_identity_map_addr = svm_set_identity_map_addr,
7285 .get_tdp_level = get_npt_level,
7286 .get_mt_mask = svm_get_mt_mask,
7288 .get_exit_info = svm_get_exit_info,
7290 .get_lpage_level = svm_get_lpage_level,
7292 .cpuid_update = svm_cpuid_update,
7294 .rdtscp_supported = svm_rdtscp_supported,
7295 .invpcid_supported = svm_invpcid_supported,
7296 .mpx_supported = svm_mpx_supported,
7297 .xsaves_supported = svm_xsaves_supported,
7298 .umip_emulated = svm_umip_emulated,
7299 .pt_supported = svm_pt_supported,
7301 .set_supported_cpuid = svm_set_supported_cpuid,
7303 .has_wbinvd_exit = svm_has_wbinvd_exit,
7305 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7306 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7308 .set_tdp_cr3 = set_tdp_cr3,
7310 .check_intercept = svm_check_intercept,
7311 .handle_exit_irqoff = svm_handle_exit_irqoff,
7313 .request_immediate_exit = __kvm_request_immediate_exit,
7315 .sched_in = svm_sched_in,
7317 .pmu_ops = &amd_pmu_ops,
7318 .deliver_posted_interrupt = svm_deliver_avic_intr,
7319 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7320 .update_pi_irte = svm_update_pi_irte,
7321 .setup_mce = svm_setup_mce,
7323 .smi_allowed = svm_smi_allowed,
7324 .pre_enter_smm = svm_pre_enter_smm,
7325 .pre_leave_smm = svm_pre_leave_smm,
7326 .enable_smi_window = enable_smi_window,
7328 .mem_enc_op = svm_mem_enc_op,
7329 .mem_enc_reg_region = svm_register_enc_region,
7330 .mem_enc_unreg_region = svm_unregister_enc_region,
7332 .nested_enable_evmcs = NULL,
7333 .nested_get_evmcs_version = NULL,
7335 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7337 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7340 static int __init svm_init(void)
7342 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7343 __alignof__(struct vcpu_svm), THIS_MODULE);
7346 static void __exit svm_exit(void)
7351 module_init(svm_init)
7352 module_exit(svm_exit)